From 87d240ffa9fe577507b2e7a575f482382ea8acfd Mon Sep 17 00:00:00 2001 From: Triss Date: Sat, 17 Jun 2023 18:55:20 +0200 Subject: [PATCH] fix a few bugs, make a very rudimentary assembler --- .gitignore | 2 + README.md | 4 +- analyze-asm.py | 2 +- defs.h | 1795 ++++++++++++++++++++++++++++++++++++++++ defs.inc | 2131 ++++++++++++++++++++++++------------------------ isa.inc | 244 ++++++ nasm.sh | 7 + text.asm | 135 +-- text.lst | 726 +++++++++++++++++ text.s | 1105 +++++++++++++++++++++++++ 10 files changed, 5019 insertions(+), 1132 deletions(-) create mode 100644 defs.h create mode 100644 isa.inc create mode 100755 nasm.sh create mode 100644 text.lst create mode 100644 text.s diff --git a/.gitignore b/.gitignore index a32b199..3dbc439 100644 --- a/.gitignore +++ b/.gitignore @@ -2,3 +2,5 @@ *.html *.zip *.tar.gz +orig-le.* +reasm.* diff --git a/README.md b/README.md index 3523818..9762d05 100644 --- a/README.md +++ b/README.md @@ -41,7 +41,9 @@ instruction set (as of now): wait wait for interrupt??? input abs, reg read from I/O space (absolute address) + input (reg), reg read from I/O space (register indirect) output reg, abs write to I/O space + output reg, (reg) write to I/O space outclr abs set I/O reg to 0? outset abs set I/O reg to 0xffff?? outbclr imm, abs clear bit of I/O reg @@ -93,7 +95,7 @@ instruction set encoding maybe: 0110 1100 0000 dddd jmp (d=reg) ^^^^ other ops? ? 0110 1101 ssss dddd ?? input (s=srcreg), d=dst hypothetical - 0110 1110 ssss dddd output s=src, (d=dstreg) + 0110 1110 dddd ssss output s=src, (d=dstreg) 0110 1111 ssss dddd lmd (s=srcreg), d=dst no store? 0111 0000 0000 0000 rts diff --git a/analyze-asm.py b/analyze-asm.py index ba43349..2cf65e6 100755 --- a/analyze-asm.py +++ b/analyze-asm.py @@ -129,7 +129,7 @@ def decode(insn): elif typ == 1: # input return "input (%s), %s" % (REGS[src], REGS[dreg]) elif typ == 2: # output - return "output %s, (%s)" % (REGS[src], REGS[dreg]) + return "output %s, (%s)" % (REGS[dreg], REGS[src]) elif typ == 3: # lmd return "lmd (%s), %s" % (REGS[src], REGS[dreg]) else: assert False diff --git a/defs.h b/defs.h new file mode 100644 index 0000000..047ba9f --- /dev/null +++ b/defs.h @@ -0,0 +1,1795 @@ +; vim: set ft=asm: + +.DEFINE CMD_OK 1 +.DEFINE CMD_ERR 2 + +.DEFINE MDMCONF_IQDUMP_FIRST_REG 43 ; ADCDIGCONF +.DEFINE MDMCONF_IQDUMP_LAST_REG 78 ; DEMSWQU0 + +;;; Length of configuration (number of .DATA words) +.DEFINE MDMCONF_IQDUMP_LENGTH 36 + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;;;; mce_commonlib.asm +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; -------------------------------------------------------------- +; MCEEVENT0 event register bit positions +; +.DEFINE MCEEVENT0_MDMAPI_WR 0 ; New command from CPE received in MDMAPI register +.DEFINE MCEEVENT0_TIMER_IRQ 1 ; Timer period expired in local timer +.DEFINE MCEEVENT0_CLKEN_4BAUD 2 ; Clock enable event at 4 times baud rate +.DEFINE MCEEVENT0_FIFO_ERR_UNDERFLOW 3 ; FIFO underflow error event +.DEFINE MCEEVENT0_FIFO_ERR_OVERFLOW 4 ; FIFO overflow error event +.DEFINE MCEEVENT0_RFECMD_IRQ 5 ; New command from RFE received in MCERCEV register +.DEFINE MCEEVENT0_COUNTER_IRQ 6 ; Counter value reached in local timer +.DEFINE MCEEVENT0_MDMFIFO_WR 7 ; A write to the MDMFIFO register from CPE +.DEFINE MCEEVENT0_CPEFWEVENT0 8 ; Firmware defined event from CPE +.DEFINE MCEEVENT0_CPEFWEVENT1 9 ; Firmware defined event from CPE +.DEFINE MCEEVENT0_BDEC_EN 10 ; BDEC output enable +.DEFINE MCEEVENT0_FRAC_EN 11 ; FRAC output enable +.DEFINE MCEEVENT0_DL_TX_DONE 12 ; SMI serdes data word transmit done +.DEFINE MCEEVENT0_CL_TX_DONE 13 ; SMI serdes command word transmit done +.DEFINE MCEEVENT0_DL_RX_IRQ 14 ; SMI serdes data word receive interrupt +.DEFINE MCEEVENT0_CL_RX_IRQ 15 ; SMI serdes command word receive interrupt +; -------------------------------------------------------------- +; MCEEVENT1 event register bit positions +; +.DEFINE MCEEVENT1_PREAMBLE_DONE 0 ; Preamble done interrupt from modulator +.DEFINE MCEEVENT1_CLKEN_BAUD 1 ; Baud indication +.DEFINE MCEEVENT1_FIFOWR_READY 2 ; It is legal to write to MDMFIFOWR register +.DEFINE MCEEVENT1_FIFORD_VALID 3 ; It is leval to read from MDMFIFORD register +.DEFINE MCEEVENT1_VITACC 4 ; Unused event +.DEFINE MCEEVENT1_MDMCMDPAR0_WR 5 ; A write to MDMCMDPAR0 register from CPE +.DEFINE MCEEVENT1_MDMCMDPAR1_WR 6 ; A write to MDMCMDPAR1 register from CPE +.DEFINE MCEEVENT1_CLKEN_BAUD_F 7 ; Flushed Baud Indication +.DEFINE MCEEVENT1_RAT_EVENT0 8 ; Radio timer event 0 +.DEFINE MCEEVENT1_RAT_EVENT1 9 ; Radio timer event 1 +.DEFINE MCEEVENT1_RAT_EVENT2 10 ; Radio timer event 2 +.DEFINE MCEEVENT1_RAT_EVENT3 11 ; Radio timer event 3 +.DEFINE MCEEVENT1_RAT_EVENT4 12 ; Radio timer event 4 +.DEFINE MCEEVENT1_RAT_EVENT5 13 ; Radio timer event 5 +.DEFINE MCEEVENT1_RAT_EVENT6 14 ; Radio timer event 6 +.DEFINE MCEEVENT1_RAT_EVENT7 15 ; Radio timer event 7 +; -------------------------------------------------------------- +; MCEEVENT2 event register bit positions +; +.DEFINE MCEEVENT2_C1BE_A_POS_PEAK 0 ; Correlator peak detect: corr A > thr A (occurs one sample after peak) +.DEFINE MCEEVENT2_C1BE_A_NEG_PEAK 1 ; Correlator peak detect: corr A < -thr A (occurs one sample after peak) +.DEFINE MCEEVENT2_C1BE_A_ANY_PEAK 2 ; Correlator peak detect: abs(corr A) > thr A (occurs one sample after peak) +.DEFINE MCEEVENT2_C1BE_B_POS_PEAK 3 ; Correlator peak detect: corr B > thr B (occurs one sample after peak) +.DEFINE MCEEVENT2_C1BE_B_NEG_PEAK 4 ; Correlator peak detect: corr B < -thr B (occurs one sample after peak) +.DEFINE MCEEVENT2_C1BE_B_ANY_PEAK 5 ; Correlator peak detect: abs(corr B) > thr B (occurs one sample after peak) +.DEFINE MCEEVENT2_C1BE_C_POS_PEAK 6 ; Correlator peak detect: corr C > thr C (occurs one sample after peak) +.DEFINE MCEEVENT2_C1BE_C_NEG_PEAK 7 ; Correlator peak detect: corr C < -thr C (occurs one sample after peak) +.DEFINE MCEEVENT2_C1BE_C_ANY_PEAK 8 ; Correlator peak detect: abs(corr C) > thr C (occurs one sample after peak) +.DEFINE MCEEVENT2_C1BE_CMB_POS_PEAK 9 ; Correlator peak detect: corr CMB > thr CMB (occurs one sample after peak) +.DEFINE MCEEVENT2_C1BE_CMB_NEG_PEAK 10 ; Correlator peak detect: corr CMB < -thr CMB (occurs one sample after peak) +.DEFINE MCEEVENT2_C1BE_CMB_ANY_PEAK 11 ; Correlator peak detect: abs(corr CMB) > thr CMB (occurs one sample after peak) +.DEFINE MCEEVENT2_C1BE_B_LOADED 12 ; Correlator B loaded (by auto-copy function) +.DEFINE MCEEVENT2_SWQU_SYNCED_IRQ 13 ; Sync word qualifier detected sync word +.DEFINE MCEEVENT2_MDMGPI0 14 ; Event from RFCore GPI 0 +.DEFINE MCEEVENT2_MDMGPI1 15 ; Event from RFCore GPI 1 +; -------------------------------------------------------------- +; MCEEVENT3 event register bit positions +; +.DEFINE MCEEVENT3_C1BE_D_POS_PEAK 0 ; Correlator peak detect: corr A > thr A (occurs one sample after peak) +.DEFINE MCEEVENT3_C1BE_D_NEG_PEAK 1 ; Correlator peak detect: corr A < -thr A (occurs one sample after peak) +.DEFINE MCEEVENT3_C1BE_D_ANY_PEAK 2 ; Correlator peak detect: abs(corr A) > thr A (occurs one sample after peak) +.DEFINE MCEEVENT3_C1BE_E_POS_PEAK 3 ; Correlator peak detect: corr B > thr B (occurs one sample after peak) +.DEFINE MCEEVENT3_C1BE_E_NEG_PEAK 4 ; Correlator peak detect: corr B < -thr B (occurs one sample after peak) +.DEFINE MCEEVENT3_C1BE_E_ANY_PEAK 5 ; Correlator peak detect: abs(corr B) > thr B (occurs one sample after peak) +.DEFINE MCEEVENT3_C1BE_F_POS_PEAK 6 ; Correlator peak detect: corr C > thr C (occurs one sample after peak) +.DEFINE MCEEVENT3_C1BE_F_NEG_PEAK 7 ; Correlator peak detect: corr C < -thr C (occurs one sample after peak) +.DEFINE MCEEVENT3_C1BE_F_ANY_PEAK 8 ; Correlator peak detect: abs(corr C) > thr C (occurs one sample after peak) +.DEFINE MCEEVENT3_C1BE_CMB_DE_POS_PEAK 9 ; Correlator peak detect: corr CMB > thr CMB (occurs one sample after peak) +.DEFINE MCEEVENT3_C1BE_CMB_DE_NEG_PEAK 10 ; Correlator peak detect: corr CMB < -thr CMB (occurs one sample after peak) +.DEFINE MCEEVENT3_C1BE_CMB_DE_ANY_PEAK 11 ; Correlator peak detect: abs(corr CMB) > thr CMB (occurs one sample after peak) +.DEFINE MCEEVENT3_C1BE_G_POS_PEAK 12 ; Correlator peak detect: corr G > thr G +.DEFINE MCEEVENT3_C1BE_G_NEG_PEAK 13 ; Correlator peak detect: corr G < -thr G +.DEFINE MCEEVENT3_C1BE_G_ANY_PEAK 14 ; Correlator peak detect: abs(corr G) > thr G +.DEFINE MCEEVENT3_SWQU_FALSE_SYNC_IRQ 15 ; Sync owrd qualifier false sync + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;;;; mdm_regs.asm +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; -------------------------------------------------------------- +; MDMENABLE +; +MDMENABLE .assign 0 +MDMENABLE_PDIF2 .assign 11 ; +MDMENABLE_PHASECORR .assign 10 ; +MDMENABLE_HILBDISC .assign 9 ; +MDMENABLE_FB2PLL .assign 8 ; +MDMENABLE_VITACC .assign 7 ; +MDMENABLE_ADCDIG .assign 6 ; +MDMENABLE_SMI .assign 5 ; +MDMENABLE_DEMODULATOR .assign 4 ; +MDMENABLE_MODULATOR .assign 3 ; +MDMENABLE_TIMEBASE .assign 2 ; +MDMENABLE_TXRXFIFO .assign 1 ; +MDMENABLE_mce .assign 0 ; +; -------------------------------------------------------------- +; MDMINIT +; +MDMINIT .assign 1 +MDMINIT_PDIF2 .assign 11 ; +MDMINIT_PHASECORR .assign 10 ; +MDMINIT_HILBDISC .assign 9 ; +MDMINIT_FB2PLL .assign 8 ; +MDMINIT_VITACC .assign 7 ; +MDMINIT_ADCDIG .assign 6 ; +MDMINIT_SMI .assign 5 ; +MDMINIT_DEMODULATOR .assign 4 ; +MDMINIT_MODULATOR .assign 3 ; +MDMINIT_TIMEBASE .assign 2 ; +MDMINIT_TXRXFIFO .assign 1 ; +MDMINIT_mce .assign 0 ; +; -------------------------------------------------------------- +; MDMPDREQ +; +MDMPDREQ .assign 2 +MDMPDREQ_mcePDREQ .assign 0 ; +; -------------------------------------------------------------- +; DEMENABLE0 +; +DEMENABLE0 .assign 3 +DEMENABLE0_FE23 .assign 15 ; +DEMENABLE0_FE13 .assign 14 ; +DEMENABLE0_FELP .assign 13 ; +DEMENABLE0_THRD .assign 12 ; +DEMENABLE0_FRAC .assign 11 ; +DEMENABLE0_FIDC .assign 10 ; +DEMENABLE0_CHFI .assign 9 ; +DEMENABLE0_BDEC .assign 8 ; +DEMENABLE0_IQMC .assign 7 ; +DEMENABLE0_MGE2 .assign 6 ; +DEMENABLE0_MGE1 .assign 5 ; +DEMENABLE0_RSVD .assign 4 ; +DEMENABLE0_CODC .assign 3 ; +DEMENABLE0_CMI4 .assign 2 ; +DEMENABLE0_CMIX .assign 1 ; +DEMENABLE0_HILB .assign 0 ; +; -------------------------------------------------------------- +; DEMENABLE1 +; +DEMENABLE1 .assign 4 +DEMENABLE1_VITE .assign 15 ; +DEMENABLE1_MLSE .assign 14 ; +DEMENABLE1_SOFD .assign 13 ; +DEMENABLE1_SWQU .assign 12 ; +DEMENABLE1_MAFC .assign 11 ; +DEMENABLE1_MAFI .assign 10 ; +DEMENABLE1_FIFE .assign 9 ; +DEMENABLE1_PDIF .assign 8 ; +DEMENABLE1_CA2P .assign 7 ; +DEMENABLE1_FECP .assign 6 ; +DEMENABLE1_FEC5 .assign 5 ; +DEMENABLE1_C1BE .assign 4 ; +DEMENABLE1_LQIE .assign 3 ; +DEMENABLE1_F4BA .assign 2 ; +DEMENABLE1_STIM .assign 1 ; +DEMENABLE1_DSBU .assign 0 ; +; -------------------------------------------------------------- +; DEMINIT0 +; +DEMINIT0 .assign 5 +DEMINIT0_FE23 .assign 15 ; +DEMINIT0_FE13 .assign 14 ; +DEMINIT0_FELP .assign 13 ; +DEMINIT0_THRD .assign 12 ; +DEMINIT0_FRAC .assign 11 ; +DEMINIT0_FIDC .assign 10 ; +DEMINIT0_CHFI .assign 9 ; +DEMINIT0_BDEC .assign 8 ; +DEMINIT0_IQMC .assign 7 ; +DEMINIT0_MGE2 .assign 6 ; +DEMINIT0_MGE1 .assign 5 ; +DEMINIT0_RSVD .assign 4 ; +DEMINIT0_CODC .assign 3 ; +DEMINIT0_CMI4 .assign 2 ; +DEMINIT0_CMIX .assign 1 ; +DEMINIT0_HILB .assign 0 ; +; -------------------------------------------------------------- +; DEMINIT1 +; +DEMINIT1 .assign 6 +DEMINIT1_VITE .assign 15 ; +DEMINIT1_MLSE .assign 14 ; +DEMINIT1_SOFD .assign 13 ; +DEMINIT1_SWQU .assign 12 ; +DEMINIT1_MAFC .assign 11 ; +DEMINIT1_MAFI .assign 10 ; +DEMINIT1_FIFE .assign 9 ; +DEMINIT1_PDIF .assign 8 ; +DEMINIT1_CA2P .assign 7 ; +DEMINIT1_FECP .assign 6 ; +DEMINIT1_FEC5 .assign 5 ; +DEMINIT1_C1BE .assign 4 ; +DEMINIT1_LQIE .assign 3 ; +DEMINIT1_F4BA .assign 2 ; +DEMINIT1_STIM .assign 1 ; +DEMINIT1_DSBU .assign 0 ; +; -------------------------------------------------------------- +; MCESTROBES0 +; +MCESTROBES0 .assign 7 +MCESTROBES0_EVENT5 .assign 12 ; +MCESTROBES0_EVENT4 .assign 11 ; +MCESTROBES0_ROMDUMP .assign 10 ; +MCESTROBES0_VITACCSTART .assign 9 ; +MCESTROBES0_MLSETERM .assign 8 ; +MCESTROBES0_EVENT3 .assign 7 ; +MCESTROBES0_EVENT2 .assign 6 ; +MCESTROBES0_EVENT1 .assign 5 ; +MCESTROBES0_EVENT0 .assign 4 ; +MCESTROBES0_MCETIMBALIGN .assign 3 ; +MCESTROBES0_DSBURESTART .assign 2 ; +MCESTROBES0_RSVD .assign 1 ; +MCESTROBES0_CMDDONE .assign 0 ; +; -------------------------------------------------------------- +; MCESTROBES1 +; +MCESTROBES1 .assign 8 +MCESTROBES1_C1BECOPYCMD2 .assign 15 ; +MCESTROBES1_C1BEPEAKGCMD .assign 14 ; +MCESTROBES1_C1BEPEAKDECMD .assign 13 ; +MCESTROBES1_C1BEPEAKFCMD .assign 12 ; +MCESTROBES1_C1BEPEAKECMD .assign 11 ; +MCESTROBES1_C1BEPEAKDCMD .assign 10 ; +MCESTROBES1_C1BEPEAKABCMD .assign 9 ; +MCESTROBES1_C1BEPEAKCCMD .assign 8 ; +MCESTROBES1_C1BEPEAKBCMD .assign 7 ; +MCESTROBES1_C1BEPEAKACMD .assign 6 ; +MCESTROBES1_C1BEADVANCECMD .assign 5 ; +MCESTROBES1_C1BESTALLCMD .assign 4 ; +MCESTROBES1_C1BEROTCMD .assign 2 ; +MCESTROBES1_C1BECOPYCMD .assign 1 ; +MCESTROBES1_RESERVED .assign 0 ; +; -------------------------------------------------------------- +; MCEEVENT0 +; +MCEEVENT0 .assign 9 +MCEEVENT0_CL_RX_IRQ .assign 15 ; +MCEEVENT0_DL_RX_IRQ .assign 14 ; +MCEEVENT0_CL_TX_DONE .assign 13 ; +MCEEVENT0_DL_TX_DONE .assign 12 ; +MCEEVENT0_FRAC_EN .assign 11 ; +MCEEVENT0_BDEC_EN .assign 10 ; +MCEEVENT0_CPEFWEVENT1 .assign 9 ; +MCEEVENT0_CPEFWEVENT0 .assign 8 ; +MCEEVENT0_MDMFIFO_WR .assign 7 ; +MCEEVENT0_COUNTER_IRQ .assign 6 ; +MCEEVENT0_RFECMD_IRQ .assign 5 ; +MCEEVENT0_FIFO_ERR_OVERFLOW .assign 4 ; +MCEEVENT0_FIFO_ERR_UNDERFLOW .assign 3 ; +MCEEVENT0_CLKEN_4BAUD .assign 2 ; +MCEEVENT0_TIMER_IRQ .assign 1 ; +MCEEVENT0_MDMAPI_WR .assign 0 ; +; -------------------------------------------------------------- +; MCEEVENT1 +; +MCEEVENT1 .assign 10 +MCEEVENT1_RAT_EVENT7 .assign 15 ; +MCEEVENT1_RAT_EVENT6 .assign 14 ; +MCEEVENT1_RAT_EVENT5 .assign 13 ; +MCEEVENT1_RAT_EVENT4 .assign 12 ; +MCEEVENT1_RAT_EVENT3 .assign 11 ; +MCEEVENT1_RAT_EVENT2 .assign 10 ; +MCEEVENT1_RAT_EVENT1 .assign 9 ; +MCEEVENT1_RAT_EVENT0 .assign 8 ; +MCEEVENT1_CLKEN_BAUD_F .assign 7 ; +MCEEVENT1_MDMCMDPAR1_WR .assign 6 ; +MCEEVENT1_MDMCMDPAR0_WR .assign 5 ; +MCEEVENT1_VITACC .assign 4 ; +MCEEVENT1_FIFORD_VALID .assign 3 ; +MCEEVENT1_FIFOWR_READY .assign 2 ; +MCEEVENT1_CLKEN_BAUD .assign 1 ; +MCEEVENT1_PREAMBLE_DONE .assign 0 ; +; -------------------------------------------------------------- +; MCEEVENT2 +; +MCEEVENT2 .assign 11 +MCEEVENT2_MDMGPI1 .assign 15 ; +MCEEVENT2_MDMGPI0 .assign 14 ; +MCEEVENT2_SWQU_SYNCED_IRQ .assign 13 ; +MCEEVENT2_C1BE_B_LOADED .assign 12 ; +MCEEVENT2_C1BE_CMB_ANY_PEAK .assign 11 ; +MCEEVENT2_C1BE_CMB_NEG_PEAK .assign 10 ; +MCEEVENT2_C1BE_CMB_POS_PEAK .assign 9 ; +MCEEVENT2_C1BE_C_ANY_PEAK .assign 8 ; +MCEEVENT2_C1BE_C_NEG_PEAK .assign 7 ; +MCEEVENT2_C1BE_C_POS_PEAK .assign 6 ; +MCEEVENT2_C1BE_B_ANY_PEAK .assign 5 ; +MCEEVENT2_C1BE_B_NEG_PEAK .assign 4 ; +MCEEVENT2_C1BE_B_POS_PEAK .assign 3 ; +MCEEVENT2_C1BE_A_ANY_PEAK .assign 2 ; +MCEEVENT2_C1BE_A_NEG_PEAK .assign 1 ; +MCEEVENT2_C1BE_A_POS_PEAK .assign 0 ; +; -------------------------------------------------------------- +; MCEEVENT3 +; +MCEEVENT3 .assign 12 +MCEEVENT3_SWQU_FALSE_SYNC_IRQ .assign 15 ; +MCEEVENT3_C1BE_G_ANY_PEAK .assign 14 ; +MCEEVENT3_C1BE_G_NEG_PEAK .assign 13 ; +MCEEVENT3_C1BE_G_POS_PEAK .assign 12 ; +MCEEVENT3_C1BE_CMB_DE_ANY_PEAK .assign 11 ; +MCEEVENT3_C1BE_CMB_DE_NEG_PEAK .assign 10 ; +MCEEVENT3_C1BE_CMB_DE_POS_PEAK .assign 9 ; +MCEEVENT3_C1BE_F_ANY_PEAK .assign 8 ; +MCEEVENT3_C1BE_F_NEG_PEAK .assign 7 ; +MCEEVENT3_C1BE_F_POS_PEAK .assign 6 ; +MCEEVENT3_C1BE_E_ANY_PEAK .assign 5 ; +MCEEVENT3_C1BE_E_NEG_PEAK .assign 4 ; +MCEEVENT3_C1BE_E_POS_PEAK .assign 3 ; +MCEEVENT3_C1BE_D_ANY_PEAK .assign 2 ; +MCEEVENT3_C1BE_D_NEG_PEAK .assign 1 ; +MCEEVENT3_C1BE_D_POS_PEAK .assign 0 ; +; -------------------------------------------------------------- +; MCEEVENTMSK0 +; +MCEEVENTMSK0 .assign 13 +MCEEVENTMSK0_CL_RX_IRQ .assign 15 ; +MCEEVENTMSK0_DL_RX_IRQ .assign 14 ; +MCEEVENTMSK0_CL_TX_DONE .assign 13 ; +MCEEVENTMSK0_DL_TX_DONE .assign 12 ; +MCEEVENTMSK0_FRAC_EN .assign 11 ; +MCEEVENTMSK0_BDEC_EN .assign 10 ; +MCEEVENTMSK0_CPEFWEVENT1 .assign 9 ; +MCEEVENTMSK0_CPEFWEVENT0 .assign 8 ; +MCEEVENTMSK0_MDMFIFO_WR .assign 7 ; +MCEEVENTMSK0_COUNTER_IRQ .assign 6 ; +MCEEVENTMSK0_RFECMD_IRQ .assign 5 ; +MCEEVENTMSK0_FIFO_ERR_OVERFLOW .assign 4 ; +MCEEVENTMSK0_FIFO_ERR_UNDERFLOW .assign 3 ; +MCEEVENTMSK0_CLKEN_4BAUD .assign 2 ; +MCEEVENTMSK0_TIMER_IRQ .assign 1 ; +MCEEVENTMSK0_MDMAPI_WR .assign 0 ; +; -------------------------------------------------------------- +; MCEEVENTMSK1 +; +MCEEVENTMSK1 .assign 14 +MCEEVENTMSK1_RAT_EVENT7 .assign 15 ; +MCEEVENTMSK1_RAT_EVENT6 .assign 14 ; +MCEEVENTMSK1_RAT_EVENT5 .assign 13 ; +MCEEVENTMSK1_RAT_EVENT4 .assign 12 ; +MCEEVENTMSK1_RAT_EVENT3 .assign 11 ; +MCEEVENTMSK1_RAT_EVENT2 .assign 10 ; +MCEEVENTMSK1_RAT_EVENT1 .assign 9 ; +MCEEVENTMSK1_RAT_EVENT0 .assign 8 ; +MCEEVENTMSK1_CLKEN_BAUD_F .assign 7 ; +MCEEVENTMSK1_MDMCMDPAR1_WR .assign 6 ; +MCEEVENTMSK1_MDMCMDPAR0_WR .assign 5 ; +MCEEVENTMSK1_VITACC .assign 4 ; +MCEEVENTMSK1_FIFORD_VALID .assign 3 ; +MCEEVENTMSK1_FIFOWR_READY .assign 2 ; +MCEEVENTMSK1_CLKEN_BAUD .assign 1 ; +MCEEVENTMSK1_PREAMBLE_DONE .assign 0 ; +; -------------------------------------------------------------- +; MCEEVENTMSK2 +; +MCEEVENTMSK2 .assign 15 +MCEEVENTMSK2_MDMGPI1 .assign 15 ; +MCEEVENTMSK2_MDMGPI0 .assign 14 ; +MCEEVENTMSK2_SWQU_SYNCED_IRQ .assign 13 ; +MCEEVENTMSK2_C1BE_B_LOADED .assign 12 ; +MCEEVENTMSK2_C1BE_CMB_ANY_PEAK .assign 11 ; +MCEEVENTMSK2_C1BE_CMB_NEG_PEAK .assign 10 ; +MCEEVENTMSK2_C1BE_CMB_POS_PEAK .assign 9 ; +MCEEVENTMSK2_C1BE_C_ANY_PEAK .assign 8 ; +MCEEVENTMSK2_C1BE_C_NEG_PEAK .assign 7 ; +MCEEVENTMSK2_C1BE_C_POS_PEAK .assign 6 ; +MCEEVENTMSK2_C1BE_B_ANY_PEAK .assign 5 ; +MCEEVENTMSK2_C1BE_B_NEG_PEAK .assign 4 ; +MCEEVENTMSK2_C1BE_B_POS_PEAK .assign 3 ; +MCEEVENTMSK2_C1BE_A_ANY_PEAK .assign 2 ; +MCEEVENTMSK2_C1BE_A_NEG_PEAK .assign 1 ; +MCEEVENTMSK2_C1BE_A_POS_PEAK .assign 0 ; +; -------------------------------------------------------------- +; MCEEVENTMSK3 +; +MCEEVENTMSK3 .assign 16 +MCEEVENTMSK3_SWQU_FALSE_SYNC_IRQ .assign 15 ; +MCEEVENTMSK3_C1BE_G_ANY_PEAK .assign 14 ; +MCEEVENTMSK3_C1BE_G_NEG_PEAK .assign 13 ; +MCEEVENTMSK3_C1BE_G_POS_PEAK .assign 12 ; +MCEEVENTMSK3_C1BE_CMB_DE_ANY_PEAK .assign 11 ; +MCEEVENTMSK3_C1BE_CMB_DE_NEG_PEAK .assign 10 ; +MCEEVENTMSK3_C1BE_CMB_DE_POS_PEAK .assign 9 ; +MCEEVENTMSK3_C1BE_F_ANY_PEAK .assign 8 ; +MCEEVENTMSK3_C1BE_F_NEG_PEAK .assign 7 ; +MCEEVENTMSK3_C1BE_F_POS_PEAK .assign 6 ; +MCEEVENTMSK3_C1BE_E_ANY_PEAK .assign 5 ; +MCEEVENTMSK3_C1BE_E_NEG_PEAK .assign 4 ; +MCEEVENTMSK3_C1BE_E_POS_PEAK .assign 3 ; +MCEEVENTMSK3_C1BE_D_ANY_PEAK .assign 2 ; +MCEEVENTMSK3_C1BE_D_NEG_PEAK .assign 1 ; +MCEEVENTMSK3_C1BE_D_POS_PEAK .assign 0 ; +; -------------------------------------------------------------- +; MCEEVENTCLR0 +; +MCEEVENTCLR0 .assign 17 +MCEEVENTCLR0_CL_RX_IRQ .assign 15 ; +MCEEVENTCLR0_DL_RX_IRQ .assign 14 ; +MCEEVENTCLR0_CL_TX_DONE .assign 13 ; +MCEEVENTCLR0_DL_TX_DONE .assign 12 ; +MCEEVENTCLR0_FRAC_EN .assign 11 ; +MCEEVENTCLR0_BDEC_EN .assign 10 ; +MCEEVENTCLR0_CPEFWEVENT1 .assign 9 ; +MCEEVENTCLR0_CPEFWEVENT0 .assign 8 ; +MCEEVENTCLR0_MDMFIFO_WR .assign 7 ; +MCEEVENTCLR0_COUNTER_IRQ .assign 6 ; +MCEEVENTCLR0_RFECMD_IRQ .assign 5 ; +MCEEVENTCLR0_FIFO_ERR_OVERFLOW .assign 4 ; +MCEEVENTCLR0_FIFO_ERR_UNDERFLOW .assign 3 ; +MCEEVENTCLR0_CLKEN_4BAUD .assign 2 ; +MCEEVENTCLR0_TIMER_IRQ .assign 1 ; +MCEEVENTCLR0_MDMAPI_WR .assign 0 ; +; -------------------------------------------------------------- +; MCEEVENTCLR1 +; +MCEEVENTCLR1 .assign 18 +MCEEVENTCLR1_RAT_EVENT7 .assign 15 ; +MCEEVENTCLR1_RAT_EVENT6 .assign 14 ; +MCEEVENTCLR1_RAT_EVENT5 .assign 13 ; +MCEEVENTCLR1_RAT_EVENT4 .assign 12 ; +MCEEVENTCLR1_RAT_EVENT3 .assign 11 ; +MCEEVENTCLR1_RAT_EVENT2 .assign 10 ; +MCEEVENTCLR1_RAT_EVENT1 .assign 9 ; +MCEEVENTCLR1_RAT_EVENT0 .assign 8 ; +MCEEVENTCLR1_CLKEN_BAUD_F .assign 7 ; +MCEEVENTCLR1_MDMCMDPAR1_WR .assign 6 ; +MCEEVENTCLR1_MDMCMDPAR0_WR .assign 5 ; +MCEEVENTCLR1_VITACC .assign 4 ; +MCEEVENTCLR1_FIFORD_VALID .assign 3 ; +MCEEVENTCLR1_FIFOWR_READY .assign 2 ; +MCEEVENTCLR1_CLKEN_BAUD .assign 1 ; +MCEEVENTCLR1_PREAMBLE_DONE .assign 0 ; +; -------------------------------------------------------------- +; MCEEVENTCLR2 +; +MCEEVENTCLR2 .assign 19 +MCEEVENTCLR2_MDMGPI1 .assign 15 ; +MCEEVENTCLR2_MDMGPI0 .assign 14 ; +MCEEVENTCLR2_SWQU_SYNCED_IRQ .assign 13 ; +MCEEVENTCLR2_C1BE_B_LOADED .assign 12 ; +MCEEVENTCLR2_C1BE_CMB_ANY_PEAK .assign 11 ; +MCEEVENTCLR2_C1BE_CMB_NEG_PEAK .assign 10 ; +MCEEVENTCLR2_C1BE_CMB_POS_PEAK .assign 9 ; +MCEEVENTCLR2_C1BE_C_ANY_PEAK .assign 8 ; +MCEEVENTCLR2_C1BE_C_NEG_PEAK .assign 7 ; +MCEEVENTCLR2_C1BE_C_POS_PEAK .assign 6 ; +MCEEVENTCLR2_C1BE_B_ANY_PEAK .assign 5 ; +MCEEVENTCLR2_C1BE_B_NEG_PEAK .assign 4 ; +MCEEVENTCLR2_C1BE_B_POS_PEAK .assign 3 ; +MCEEVENTCLR2_C1BE_A_ANY_PEAK .assign 2 ; +MCEEVENTCLR2_C1BE_A_NEG_PEAK .assign 1 ; +MCEEVENTCLR2_C1BE_A_POS_PEAK .assign 0 ; +; -------------------------------------------------------------- +; MCEEVENTCLR3 +; +MCEEVENTCLR3 .assign 20 +MCEEVENTCLR3_SWQU_FALSE_SYNC_IRQ .assign 15 ; +MCEEVENTCLR3_C1BE_G_ANY_PEAK .assign 14 ; +MCEEVENTCLR3_C1BE_G_NEG_PEAK .assign 13 ; +MCEEVENTCLR3_C1BE_G_POS_PEAK .assign 12 ; +MCEEVENTCLR3_C1BE_CMB_DE_ANY_PEAK .assign 11 ; +MCEEVENTCLR3_C1BE_CMB_DE_NEG_PEAK .assign 10 ; +MCEEVENTCLR3_C1BE_CMB_DE_POS_PEAK .assign 9 ; +MCEEVENTCLR3_C1BE_F_ANY_PEAK .assign 8 ; +MCEEVENTCLR3_C1BE_F_NEG_PEAK .assign 7 ; +MCEEVENTCLR3_C1BE_F_POS_PEAK .assign 6 ; +MCEEVENTCLR3_C1BE_E_ANY_PEAK .assign 5 ; +MCEEVENTCLR3_C1BE_E_NEG_PEAK .assign 4 ; +MCEEVENTCLR3_C1BE_E_POS_PEAK .assign 3 ; +MCEEVENTCLR3_C1BE_D_ANY_PEAK .assign 2 ; +MCEEVENTCLR3_C1BE_D_NEG_PEAK .assign 1 ; +MCEEVENTCLR3_C1BE_D_POS_PEAK .assign 0 ; +; -------------------------------------------------------------- +; MCEPROGRAMSRC +; +MCEPROGRAMSRC .assign 21 +MCEPROGRAMSRC_ROMBANK .assign 1 ; +MCEPROGRAMSRC_RAMROM .assign 0 ; +; -------------------------------------------------------------- +; MDMAPI +; +MDMAPI .assign 22 +MDMAPI_PROTOCOLID .assign 8 ; +MDMAPI_MDMCMD .assign 0 ; +; -------------------------------------------------------------- +; MDMCMDPAR0 +; +MDMCMDPAR0 .assign 23 +MDMCMDPAR0_PAR0 .assign 0 ; +; -------------------------------------------------------------- +; MDMCMDPAR1 +; +MDMCMDPAR1 .assign 24 +MDMCMDPAR1_PAR1 .assign 0 ; +; -------------------------------------------------------------- +; MDMCMDPAR2 +; +MDMCMDPAR2 .assign 25 +MDMCMDPAR2_PAR .assign 0 ; +; -------------------------------------------------------------- +; MDMRFCHANNEL +; +MDMRFCHANNEL .assign 26 +MDMRFCHANNEL_VALUE .assign 0 ; +; -------------------------------------------------------------- +; MDMSTATUS +; +MDMSTATUS .assign 27 +MDMSTATUS_VALUE .assign 0 ; +; -------------------------------------------------------------- +; MDMFIFOWR +; +MDMFIFOWR .assign 28 +MDMFIFOWR_PAYLOADIN .assign 0 ; +; -------------------------------------------------------------- +; MDMFIFORD +; +MDMFIFORD .assign 29 +MDMFIFORD_PAYLOADOUT .assign 0 ; +; -------------------------------------------------------------- +; MDMFIFOWRCTRL +; +MDMFIFOWRCTRL .assign 30 +MDMFIFOWRCTRL_FIFOWRPORT .assign 4 ; +MDMFIFOWRCTRL_WORDSZWR .assign 0 ; +; -------------------------------------------------------------- +; MDMFIFORDCTRL +; +MDMFIFORDCTRL .assign 31 +MDMFIFORDCTRL_FIFORDPORT .assign 4 ; +MDMFIFORDCTRL_WORDSZRD .assign 0 ; +; -------------------------------------------------------------- +; MDMFIFOCFG +; +MDMFIFOCFG .assign 32 +MDMFIFOCFG_AFULLTHR .assign 8 ; +MDMFIFOCFG_AEMPTYTHR .assign 0 ; +; -------------------------------------------------------------- +; MDMFIFOSTA +; +MDMFIFOSTA .assign 33 +MDMFIFOSTA_OVERFLOW .assign 5 ; +MDMFIFOSTA_ALMOSTFULL .assign 4 ; +MDMFIFOSTA_ALMOSTEMPTY .assign 3 ; +MDMFIFOSTA_UNDERFLOW .assign 2 ; +MDMFIFOSTA_RXVALID .assign 1 ; +MDMFIFOSTA_TXREADY .assign 0 ; +; -------------------------------------------------------------- +; CPEFWEVENT +; +CPEFWEVENT .assign 34 +CPEFWEVENT_EVENT3 .assign 3 ; +CPEFWEVENT_EVENT2 .assign 2 ; +CPEFWEVENT_EVENT1 .assign 1 ; +CPEFWEVENT_EVENT0 .assign 0 ; +; -------------------------------------------------------------- +; RFESEND +; +RFESEND .assign 35 +RFESEND_MCECMD .assign 0 ; +; -------------------------------------------------------------- +; RFERCEV +; +RFERCEV .assign 36 +RFERCEV_RFECMD .assign 0 ; +; -------------------------------------------------------------- +; SMICONF +; +SMICONF .assign 37 +SMICONF_SMIENABLE .assign 8 ; +SMICONF_PRESCALER .assign 4 ; +SMICONF_MLENGTH .assign 0 ; +; -------------------------------------------------------------- +; SMIDLOUTG +; +SMIDLOUTG .assign 38 +SMIDLOUTG_DL .assign 0 ; +; -------------------------------------------------------------- +; SMICLOUTG +; +SMICLOUTG .assign 39 +SMICLOUTG_CL .assign 0 ; +; -------------------------------------------------------------- +; SMIDLINC +; +SMIDLINC .assign 40 +SMIDLINC_DL .assign 0 ; +; -------------------------------------------------------------- +; SMICLINC +; +SMICLINC .assign 41 +SMICLINC_CL .assign 0 ; +; -------------------------------------------------------------- +; SMISTA +; +SMISTA .assign 42 +SMISTA_INCCLERROR .assign 1 ; +SMISTA_INCDLERROR .assign 0 ; +; -------------------------------------------------------------- +; ADCDIGCONF +; +ADCDIGCONF .assign 43 +ADCDIGCONF_QBRANCHEN .assign 1 ; +ADCDIGCONF_IBRANCHEN .assign 0 ; +; -------------------------------------------------------------- +; MODPRECTRL +; +MODPRECTRL .assign 44 +MODPRECTRL_REPS .assign 4 ; +MODPRECTRL_SIZE .assign 0 ; +; -------------------------------------------------------------- +; MODSYMMAP0 +; +MODSYMMAP0 .assign 45 +MODSYMMAP0_SYM3 .assign 12 ; +MODSYMMAP0_SYM2 .assign 8 ; +MODSYMMAP0_SYM1 .assign 4 ; +MODSYMMAP0_SYM0 .assign 0 ; +; -------------------------------------------------------------- +; MODSYMMAP1 +; +MODSYMMAP1 .assign 46 +MODSYMMAP1_SYM7 .assign 12 ; +MODSYMMAP1_SYM6 .assign 8 ; +MODSYMMAP1_SYM5 .assign 4 ; +MODSYMMAP1_SYM4 .assign 0 ; +; -------------------------------------------------------------- +; MODSOFTTX +; +MODSOFTTX .assign 47 +MODSOFTTX_SOFTSYMBOL .assign 0 ; +; -------------------------------------------------------------- +; MDMBAUD +; +MDMBAUD .assign 48 +MDMBAUD_RATEWORD .assign 0 ; +; -------------------------------------------------------------- +; MDMBAUDPRE +; +MDMBAUDPRE .assign 49 +MDMBAUDPRE_ALIGNVALUE .assign 13 ; +MDMBAUDPRE_EXTRATEWORD .assign 8 ; +MDMBAUDPRE_PRESCALER .assign 0 ; +; -------------------------------------------------------------- +; MODMAIN +; +MODMAIN .assign 50 +MODMAIN_SPREADFACTOR .assign 6 ; +MODMAIN_FECSELECT .assign 2 ; +MODMAIN_MODLEVELS .assign 0 ; +; -------------------------------------------------------------- +; DEMMISC0 +; +DEMMISC0 .assign 51 +DEMMISC0_CMI4FMIXSIGN .assign 12 ; +DEMMISC0_HILBREMOVEREAL .assign 11 ; +DEMMISC0_HILBEN .assign 10 ; +DEMMISC0_CMIXN .assign 0 ; +; -------------------------------------------------------------- +; DEMMISC1 +; +DEMMISC1 .assign 52 +DEMMISC1_MGE2SRCSEL .assign 2 ; +DEMMISC1_CHFIBW .assign 0 ; +; -------------------------------------------------------------- +; DEMMISC2 +; +DEMMISC2 .assign 53 +DEMMISC2_LQIPERIOD .assign 14 ; +DEMMISC2_MLSERUN .assign 13 ; +DEMMISC2_MAFCGAIN .assign 11 ; +DEMMISC2_STIMESTONLY .assign 10 ; +DEMMISC2_STIMTEAPERIOD .assign 7 ; +DEMMISC2_STIMTEAGAIN .assign 4 ; +DEMMISC2_PDIFLINPREDEN .assign 3 ; +DEMMISC2_PDIFDESPECKLEREN .assign 2 ; +DEMMISC2_PDIFIQCONJEN .assign 1 ; +DEMMISC2_PDIFLIMITRANGE .assign 0 ; +; -------------------------------------------------------------- +; DEMMISC3 +; +DEMMISC3 .assign 54 +DEMMISC3_BDE1DVGA .assign 10 ; +DEMMISC3_BDE2DVGA .assign 8 ; +DEMMISC3_BDE1NUMSTAGES .assign 5 ; +DEMMISC3_PDIFDECIM .assign 3 ; +DEMMISC3_BDECNUMSTAGES .assign 0 ; +; -------------------------------------------------------------- +; DEMIQMC0 +; +DEMIQMC0 .assign 55 +DEMIQMC0_GAINFACTOR .assign 8 ; +DEMIQMC0_PHASEFACTOR .assign 0 ; +; -------------------------------------------------------------- +; DEMDSBU +; +DEMDSBU .assign 56 +DEMDSBU_DSBUDELAY .assign 0 ; +; -------------------------------------------------------------- +; DEMDSBU2 +; +DEMDSBU2 .assign 57 +DEMDSBU2_DSBUAVGLENGTH .assign 0 ; +; -------------------------------------------------------------- +; DEMCODC0 +; +DEMCODC0 .assign 58 +DEMCODC0_ESTSEL .assign 11 ; +DEMCODC0_COMPSEL .assign 9 ; +DEMCODC0_IIRUSEINITIAL .assign 8 ; +DEMCODC0_IIRGAIN .assign 5 ; +DEMCODC0_IIREN .assign 4 ; +DEMCODC0_ACCCONTMODE .assign 3 ; +DEMCODC0_ACCPERIOD .assign 1 ; +DEMCODC0_ACCEN .assign 0 ; +; -------------------------------------------------------------- +; DEMFIDC0 +; +DEMFIDC0 .assign 59 +DEMFIDC0_COMPSEL .assign 4 ; +DEMFIDC0_ACCPERIOD .assign 2 ; +DEMFIDC0_ACCCONTMODE .assign 1 ; +DEMFIDC0_ACCEN .assign 0 ; +; -------------------------------------------------------------- +; DEMFEXB0 +; +DEMFEXB0 .assign 60 +DEMFEXB0_OUT2PASSTHROUGH .assign 13 ; +DEMFEXB0_OUT2SRCSEL .assign 11 ; +DEMFEXB0_OUT1PASSTHROUGH .assign 10 ; +DEMFEXB0_OUT1SRCSEL .assign 8 ; +DEMFEXB0_B4SRCSEL .assign 6 ; +DEMFEXB0_B3SRCSEL .assign 4 ; +DEMFEXB0_B2SRCSEL .assign 2 ; +DEMFEXB0_B1SRCSEL .assign 0 ; +; -------------------------------------------------------------- +; DEMDSXB0 +; +DEMDSXB0 .assign 61 +DEMDSXB0_OUT2PASSTHROUGH .assign 13 ; +DEMDSXB0_OUT1PASSTHROUGH .assign 12 ; +DEMDSXB0_OUTSRCSEL2 .assign 10 ; +DEMDSXB0_OUTSRCSEL1 .assign 8 ; +DEMDSXB0_B4SRCSEL .assign 6 ; +DEMDSXB0_B3SRCSEL .assign 4 ; +DEMDSXB0_B2SRCSEL .assign 2 ; +DEMDSXB0_B1SRCSEL .assign 0 ; +; -------------------------------------------------------------- +; DEMD2XB0 +; +DEMD2XB0 .assign 62 +DEMD2XB0_B3SRCSEL .assign 10 ; +DEMD2XB0_OUT2PASSTHROUGH .assign 9 ; +DEMD2XB0_OUT1PASSTHROUGH .assign 8 ; +DEMD2XB0_OUTSRCSEL2 .assign 6 ; +DEMD2XB0_OUTSRCSEL1 .assign 4 ; +DEMD2XB0_B2SRCSEL .assign 2 ; +DEMD2XB0_B1SRCSEL .assign 0 ; +; -------------------------------------------------------------- +; DEMFIFE0 +; +DEMFIFE0 .assign 63 +DEMFIFE0_FINEFOESEL .assign 11 ; +DEMFIFE0_FOCFFSEL .assign 9 ; +DEMFIFE0_ACCCNTMODE .assign 8 ; +DEMFIFE0_ACCPERIOD .assign 6 ; +DEMFIFE0_ACCEN .assign 5 ; +DEMFIFE0_IIRUSEINITIAL .assign 4 ; +DEMFIFE0_IIRGAIN .assign 1 ; +DEMFIFE0_IIREN .assign 0 ; +; -------------------------------------------------------------- +; DEMMAFI0 +; +DEMMAFI0 .assign 64 +DEMMAFI0_C1C7 .assign 8 ; +DEMMAFI0_C0C8 .assign 0 ; +; -------------------------------------------------------------- +; DEMMAFI1 +; +DEMMAFI1 .assign 65 +DEMMAFI1_C3C5 .assign 8 ; +DEMMAFI1_C2C6 .assign 0 ; +; -------------------------------------------------------------- +; DEMMAFI2 +; +DEMMAFI2 .assign 66 +DEMMAFI2_C4 .assign 0 ; +; -------------------------------------------------------------- +; DEMMAFI3 +; +DEMMAFI3 .assign 67 +DEMMAFI3_K .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE0 +; +DEMC1BE0 .assign 68 +DEMC1BE0_MASKB .assign 11 ; +DEMC1BE0_MASKA .assign 6 ; +DEMC1BE0_CASCCONF .assign 4 ; +DEMC1BE0_COPYCONF .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE1 +; +DEMC1BE1 .assign 69 +DEMC1BE1_THRESHOLDB .assign 8 ; +DEMC1BE1_THRESHOLDA .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE2 +; +DEMC1BE2 .assign 70 +DEMC1BE2_PEAKCONF .assign 8 ; +DEMC1BE2_THRESHOLDC .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE10 +; +DEMC1BE10 .assign 71 +DEMC1BE10_PEAKCONF_G .assign 15 ; +DEMC1BE10_PEAKCONF_CF .assign 13 ; +DEMC1BE10_MASKE .assign 8 ; +DEMC1BE10_MASKD .assign 3 ; +DEMC1BE10_CASCCONF .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE11 +; +DEMC1BE11 .assign 72 +DEMC1BE11_THRESHOLDE .assign 8 ; +DEMC1BE11_THRESHOLDD .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE12 +; +DEMC1BE12 .assign 73 +DEMC1BE12_THRESHOLDG .assign 8 ; +DEMC1BE12_THRESHOLDF .assign 0 ; +; -------------------------------------------------------------- +; MDMSYNC0 +; +MDMSYNC0 .assign 74 +MDMSYNC0_SWA15C0 .assign 0 ; +; -------------------------------------------------------------- +; MDMSYNC1 +; +MDMSYNC1 .assign 75 +MDMSYNC1_SWA31C16 .assign 0 ; +; -------------------------------------------------------------- +; MDMSYNC2 +; +MDMSYNC2 .assign 76 +MDMSYNC2_SWB15C0 .assign 0 ; +; -------------------------------------------------------------- +; MDMSYNC3 +; +MDMSYNC3 .assign 77 +MDMSYNC3_SWB31C16 .assign 0 ; +; -------------------------------------------------------------- +; DEMSWQU0 +; +DEMSWQU0 .assign 78 +DEMSWQU0_SYNC_MODE .assign 7 ; +DEMSWQU0_AUTOMAFC .assign 6 ; +DEMSWQU0_RUN .assign 5 ; +DEMSWQU0_REFLEN .assign 0 ; +; -------------------------------------------------------------- +; DEMFB2P0 +; +DEMFB2P0 .assign 79 +DEMFB2P0_BETA .assign 8 ; +DEMFB2P0_ALPHA .assign 0 ; +; -------------------------------------------------------------- +; DEMFB2P1 +; +DEMFB2P1 .assign 80 +DEMFB2P1_FB2P_OPEN .assign 14 ; +DEMFB2P1_HDIS_PRS .assign 12 ; +DEMFB2P1_IIR_GAIN .assign 10 ; +DEMFB2P1_IIR_BW .assign 7 ; +DEMFB2P1_FB2PLL_LIMIT .assign 0 ; +; -------------------------------------------------------------- +; DEMPHAC0 +; +DEMPHAC0 .assign 81 +DEMPHAC0_REF_B .assign 8 ; +DEMPHAC0_REF_A .assign 0 ; +; -------------------------------------------------------------- +; DEMPHAC1 +; +DEMPHAC1 .assign 82 +DEMPHAC1_PHAC_TR_LEN .assign 10 ; +DEMPHAC1_PHAC_SYM_LEN .assign 7 ; +DEMPHAC1_PHASE_INCR .assign 0 ; +; -------------------------------------------------------------- +; DEMPHAC2 +; +DEMPHAC2 .assign 83 +DEMPHAC2_ALPHA .assign 8 ; +DEMPHAC2_BETA .assign 0 ; +; -------------------------------------------------------------- +; DEMPHAC3 +; +DEMPHAC3 .assign 84 +DEMPHAC3_IIR_BW .assign 0 ; +; -------------------------------------------------------------- +; DEMPHAC4 +; +DEMPHAC4 .assign 85 +DEMPHAC4_TR_15_0 .assign 0 ; +; -------------------------------------------------------------- +; DEMPHAC5 +; +DEMPHAC5 .assign 86 +DEMPHAC5_TR_31_16 .assign 0 ; +; -------------------------------------------------------------- +; DEMPHAC6 +; +DEMPHAC6 .assign 87 +DEMPHAC6_TR_47_32 .assign 0 ; +; -------------------------------------------------------------- +; DEMPHAC7 +; +DEMPHAC7 .assign 88 +DEMPHAC7_TR_63_48 .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BEREF0 +; +DEMC1BEREF0 .assign 89 +DEMC1BEREF0_CAR15C0 .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BEREF1 +; +DEMC1BEREF1 .assign 90 +DEMC1BEREF1_CAR31C16 .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BEREF2 +; +DEMC1BEREF2 .assign 91 +DEMC1BEREF2_CBR15C0 .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BEREF3 +; +DEMC1BEREF3 .assign 92 +DEMC1BEREF3_CBR31C16 .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BEREF4 +; +DEMC1BEREF4 .assign 93 +DEMC1BEREF4_CDR15C0 .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BEREF5 +; +DEMC1BEREF5 .assign 94 +DEMC1BEREF5_CDR31C16 .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BEREF6 +; +DEMC1BEREF6 .assign 95 +DEMC1BEREF6_CER15C0 .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BEREF7 +; +DEMC1BEREF7 .assign 96 +DEMC1BEREF7_CER31C16 .assign 0 ; +; -------------------------------------------------------------- +; DEMMLSE4MAP +; +DEMMLSE4MAP .assign 97 +DEMMLSE4MAP_MAP_P3 .assign 6 ; +DEMMLSE4MAP_MAP_P1 .assign 4 ; +DEMMLSE4MAP_MAP_M1 .assign 2 ; +DEMMLSE4MAP_MAP_M3 .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE13 +; +DEMC1BE13 .assign 98 +DEMC1BE13_CORRVALUED .assign 0 ; +; -------------------------------------------------------------- +; MODCTRL +; +MODCTRL .assign 99 +MODCTRL_CDC_COL_RESTART .assign 12 ; +MODCTRL_DSBUSEL .assign 11 ; +MODCTRL_HDISMODE .assign 10 ; +MODCTRL_PARBITQUALEN .assign 9 ; +MODCTRL_STIMEARLYLATE .assign 7 ; +MODCTRL_EARLYLATE .assign 6 ; +MODCTRL_SOFTPDIFFMODE .assign 5 ; +MODCTRL_SOFTTXENABLE .assign 4 ; +MODCTRL_FECENABLE .assign 3 ; +MODCTRL_FEC5TERMINATE .assign 2 ; +MODCTRL_TONEINSERT .assign 1 ; +MODCTRL_PREAMBLEINSERT .assign 0 ; +; -------------------------------------------------------------- +; MODPREAMBLE +; +MODPREAMBLE .assign 100 +MODPREAMBLE_WORD .assign 0 ; +; -------------------------------------------------------------- +; DEMFRAC0 +; +DEMFRAC0 .assign 101 +DEMFRAC0_P15C0 .assign 0 ; +; -------------------------------------------------------------- +; DEMFRAC1 +; +DEMFRAC1 .assign 102 +DEMFRAC1_P27C16 .assign 0 ; +; -------------------------------------------------------------- +; DEMFRAC2 +; +DEMFRAC2 .assign 103 +DEMFRAC2_Q15C0 .assign 0 ; +; -------------------------------------------------------------- +; DEMFRAC3 +; +DEMFRAC3 .assign 104 +DEMFRAC3_Q27C16 .assign 0 ; +; -------------------------------------------------------------- +; DEMCODC1 +; +DEMCODC1 .assign 105 +DEMCODC1_COMPIVAL .assign 0 ; +; -------------------------------------------------------------- +; DEMCODC2 +; +DEMCODC2 .assign 106 +DEMCODC2_COMPQVAL .assign 0 ; +; -------------------------------------------------------------- +; DEMFIDC1 +; +DEMFIDC1 .assign 107 +DEMFIDC1_COMPIVAL .assign 0 ; +; -------------------------------------------------------------- +; DEMFIDC2 +; +DEMFIDC2 .assign 108 +DEMFIDC2_COMPQVAL .assign 0 ; +; -------------------------------------------------------------- +; DEMFIFE1 +; +DEMFIFE1 .assign 109 +DEMFIFE1_FOCFBREGVAL .assign 0 ; +; -------------------------------------------------------------- +; DEMTHRD0 +; +DEMTHRD0 .assign 110 +DEMTHRD0_THR2 .assign 8 ; +DEMTHRD0_RESERVED .assign 7 ; +DEMTHRD0_THR1 .assign 0 ; +; -------------------------------------------------------------- +; DEMTHRD1 +; +DEMTHRD1 .assign 111 +DEMTHRD1_THR3 .assign 0 ; +; -------------------------------------------------------------- +; DEMMAFC0 +; +DEMMAFC0 .assign 112 +DEMMAFC0_COMPVAL .assign 0 ; +; -------------------------------------------------------------- +; DEMMAFI4 +; +DEMMAFI4 .assign 113 +DEMMAFI4_TERM_VAL .assign 0 ; +; -------------------------------------------------------------- +; DEMSWIMBAL +; +DEMSWIMBAL .assign 114 +DEMSWIMBAL_IMBALB .assign 8 ; +DEMSWIMBAL_IMBALA .assign 0 ; +; -------------------------------------------------------------- +; DEMSOFTPDIFF +; +DEMSOFTPDIFF .assign 115 +DEMSOFTPDIFF_SOFTPDIFF .assign 0 ; +; -------------------------------------------------------------- +; DEMDEBUG +; +DEMDEBUG .assign 116 +DEMDEBUG_DECSTAGEDEBUG .assign 5 ; +DEMDEBUG_FRONTENDDEBUG .assign 1 ; +DEMDEBUG_LOOPBACKMODE .assign 0 ; +; -------------------------------------------------------------- +; VITCTRL +; +VITCTRL .assign 117 +VITCTRL_METRSEL .assign 10 ; +VITCTRL_READEPTH .assign 6 ; +VITCTRL_APMRDBACKSEL .assign 2 ; +VITCTRL_ACSITERATIONS .assign 1 ; +VITCTRL_SOFTMETRICS .assign 0 ; +; -------------------------------------------------------------- +; VITCOMPUTE +; +VITCOMPUTE .assign 118 +VITCOMPUTE_COMPUTE .assign 0 ; +; -------------------------------------------------------------- +; VITAPMRDBACK +; +VITAPMRDBACK .assign 119 +VITAPMRDBACK_VALUE .assign 0 ; +; -------------------------------------------------------------- +; VITSTATE +; +VITSTATE .assign 120 +VITSTATE_VALUE .assign 0 ; +; -------------------------------------------------------------- +; VITBRMETRIC10 +; +VITBRMETRIC10 .assign 121 +VITBRMETRIC10_MET1 .assign 8 ; +VITBRMETRIC10_MET0 .assign 0 ; +; -------------------------------------------------------------- +; VITBRMETRIC32 +; +VITBRMETRIC32 .assign 122 +VITBRMETRIC32_MET3 .assign 8 ; +VITBRMETRIC32_MET2 .assign 0 ; +; -------------------------------------------------------------- +; VITBRMETRIC54 +; +VITBRMETRIC54 .assign 123 +VITBRMETRIC54_MET5 .assign 8 ; +VITBRMETRIC54_MET4 .assign 0 ; +; -------------------------------------------------------------- +; VITBRMETRIC76 +; +VITBRMETRIC76 .assign 124 +VITBRMETRIC76_MET7 .assign 8 ; +VITBRMETRIC76_MET6 .assign 0 ; +; -------------------------------------------------------------- +; VITBRSEL0 +; +VITBRSEL0 .assign 125 +VITBRSEL0_BR3MUX .assign 9 ; +VITBRSEL0_BR2MUX .assign 6 ; +VITBRSEL0_BR1MUX .assign 3 ; +VITBRSEL0_BR0MUX .assign 0 ; +; -------------------------------------------------------------- +; VITAPMSEL0 +; +VITAPMSEL0 .assign 126 +VITAPMSEL0_APM3MUX .assign 9 ; +VITAPMSEL0_APM2MUX .assign 6 ; +VITAPMSEL0_APM1MUX .assign 3 ; +VITAPMSEL0_APM0MUX .assign 0 ; +; -------------------------------------------------------------- +; VITBRSEL1 +; +VITBRSEL1 .assign 127 +VITBRSEL1_BR3MUX .assign 9 ; +VITBRSEL1_BR2MUX .assign 6 ; +VITBRSEL1_BR1MUX .assign 3 ; +VITBRSEL1_BR0MUX .assign 0 ; +; -------------------------------------------------------------- +; VITAPMSEL1 +; +VITAPMSEL1 .assign 128 +VITAPMSEL1_APM3MUX .assign 9 ; +VITAPMSEL1_APM2MUX .assign 6 ; +VITAPMSEL1_APM1MUX .assign 3 ; +VITAPMSEL1_APM0MUX .assign 0 ; +; -------------------------------------------------------------- +; VITBRSEL2 +; +VITBRSEL2 .assign 129 +VITBRSEL2_BR3MUX .assign 9 ; +VITBRSEL2_BR2MUX .assign 6 ; +VITBRSEL2_BR1MUX .assign 3 ; +VITBRSEL2_BR0MUX .assign 0 ; +; -------------------------------------------------------------- +; VITAPMSEL2 +; +VITAPMSEL2 .assign 130 +VITAPMSEL2_APM3MUX .assign 9 ; +VITAPMSEL2_APM2MUX .assign 6 ; +VITAPMSEL2_APM1MUX .assign 3 ; +VITAPMSEL2_APM0MUX .assign 0 ; +; -------------------------------------------------------------- +; VITBRSEL3 +; +VITBRSEL3 .assign 131 +VITBRSEL3_BR3MUX .assign 9 ; +VITBRSEL3_BR2MUX .assign 6 ; +VITBRSEL3_BR1MUX .assign 3 ; +VITBRSEL3_BR0MUX .assign 0 ; +; -------------------------------------------------------------- +; VITAPMSEL3 +; +VITAPMSEL3 .assign 132 +VITAPMSEL3_APM3MUX .assign 9 ; +VITAPMSEL3_APM2MUX .assign 6 ; +VITAPMSEL3_APM1MUX .assign 3 ; +VITAPMSEL3_APM0MUX .assign 0 ; +; -------------------------------------------------------------- +; VITBRSEL4 +; +VITBRSEL4 .assign 133 +VITBRSEL4_BR3MUX .assign 9 ; +VITBRSEL4_BR2MUX .assign 6 ; +VITBRSEL4_BR1MUX .assign 3 ; +VITBRSEL4_BR0MUX .assign 0 ; +; -------------------------------------------------------------- +; VITAPMSEL4 +; +VITAPMSEL4 .assign 134 +VITAPMSEL4_APM3MUX .assign 9 ; +VITAPMSEL4_APM2MUX .assign 6 ; +VITAPMSEL4_APM1MUX .assign 3 ; +VITAPMSEL4_APM0MUX .assign 0 ; +; -------------------------------------------------------------- +; VITBRSEL5 +; +VITBRSEL5 .assign 135 +VITBRSEL5_BR3MUX .assign 9 ; +VITBRSEL5_BR2MUX .assign 6 ; +VITBRSEL5_BR1MUX .assign 3 ; +VITBRSEL5_BR0MUX .assign 0 ; +; -------------------------------------------------------------- +; VITAPMSEL5 +; +VITAPMSEL5 .assign 136 +VITAPMSEL5_APM3MUX .assign 9 ; +VITAPMSEL5_APM2MUX .assign 6 ; +VITAPMSEL5_APM1MUX .assign 3 ; +VITAPMSEL5_APM0MUX .assign 0 ; +; -------------------------------------------------------------- +; VITBRSEL6 +; +VITBRSEL6 .assign 137 +VITBRSEL6_BR3MUX .assign 9 ; +VITBRSEL6_BR2MUX .assign 6 ; +VITBRSEL6_BR1MUX .assign 3 ; +VITBRSEL6_BR0MUX .assign 0 ; +; -------------------------------------------------------------- +; VITAPMSEL6 +; +VITAPMSEL6 .assign 138 +VITAPMSEL6_APM3MUX .assign 9 ; +VITAPMSEL6_APM2MUX .assign 6 ; +VITAPMSEL6_APM1MUX .assign 3 ; +VITAPMSEL6_APM0MUX .assign 0 ; +; -------------------------------------------------------------- +; VITBRSEL7 +; +VITBRSEL7 .assign 139 +VITBRSEL7_BR3MUX .assign 9 ; +VITBRSEL7_BR2MUX .assign 6 ; +VITBRSEL7_BR1MUX .assign 3 ; +VITBRSEL7_BR0MUX .assign 0 ; +; -------------------------------------------------------------- +; VITAPMSEL7 +; +VITAPMSEL7 .assign 140 +VITAPMSEL7_APM3MUX .assign 9 ; +VITAPMSEL7_APM2MUX .assign 6 ; +VITAPMSEL7_APM1MUX .assign 3 ; +VITAPMSEL7_APM0MUX .assign 0 ; +; -------------------------------------------------------------- +; LOCMULTA +; +LOCMULTA .assign 141 +LOCMULTA_AVALUE .assign 0 ; +; -------------------------------------------------------------- +; LOCMULTB +; +LOCMULTB .assign 142 +LOCMULTB_BVALUE .assign 0 ; +; -------------------------------------------------------------- +; LOCMULTC0 +; +LOCMULTC0 .assign 143 +LOCMULTC0_C15C0 .assign 0 ; +; -------------------------------------------------------------- +; LOCMULTC1 +; +LOCMULTC1 .assign 144 +LOCMULTC1_C31C16 .assign 0 ; +; -------------------------------------------------------------- +; TIMCTRL +; +TIMCTRL .assign 145 +TIMCTRL_CAPTURESOURCE .assign 8 ; +TIMCTRL_ENABLECAPTURE .assign 7 ; +TIMCTRL_COUNTERSOURCE .assign 5 ; +TIMCTRL_CLEARCOUNTER .assign 4 ; +TIMCTRL_ENABLECOUNTER .assign 3 ; +TIMCTRL_TIMERSOURCE .assign 1 ; +TIMCTRL_ENABLETIMER .assign 0 ; +; -------------------------------------------------------------- +; TIMINC +; +TIMINC .assign 146 +TIMINC_INCUNIT .assign 0 ; +; -------------------------------------------------------------- +; TIMPERIOD +; +TIMPERIOD .assign 147 +TIMPERIOD_PERIOD .assign 0 ; +; -------------------------------------------------------------- +; TIMCOUNTER +; +TIMCOUNTER .assign 148 +TIMCOUNTER_VALUE .assign 0 ; +; -------------------------------------------------------------- +; TIMCAPT +; +TIMCAPT .assign 149 +TIMCAPT_VALUE .assign 0 ; +; -------------------------------------------------------------- +; TIMEBASE +; +TIMEBASE .assign 150 +TIMEBASE_FLUSH .assign 0 ; +; -------------------------------------------------------------- +; COUNT1IN +; +COUNT1IN .assign 151 +COUNT1IN_VAL .assign 0 ; +; -------------------------------------------------------------- +; COUNT1RES +; +COUNT1RES .assign 152 +COUNT1RES_COUNT .assign 0 ; +; -------------------------------------------------------------- +; BRMACC0 +; +BRMACC0 .assign 153 +BRMACC0_SYM1ST .assign 8 ; +BRMACC0_SYM2ND .assign 0 ; +; -------------------------------------------------------------- +; BRMACC1 +; +BRMACC1 .assign 154 +BRMACC1_METRIC01 .assign 8 ; +BRMACC1_METRIC00 .assign 0 ; +; -------------------------------------------------------------- +; BRMACC2 +; +BRMACC2 .assign 155 +BRMACC2_METRIC11 .assign 8 ; +BRMACC2_METRIC10 .assign 0 ; +; -------------------------------------------------------------- +; VITACCCTRL +; +VITACCCTRL .assign 156 +VITACCCTRL_POLYNOM1 .assign 9 ; +VITACCCTRL_POLYNOM0 .assign 2 ; +VITACCCTRL_CODELENGTH .assign 0 ; +; -------------------------------------------------------------- +; VITACCRDBIT +; +VITACCRDBIT .assign 157 +VITACCRDBIT_RXBIT .assign 0 ; +; -------------------------------------------------------------- +; MCETRCSEND +; +MCETRCSEND .assign 158 +MCETRCSEND_SEND .assign 0 ; +; -------------------------------------------------------------- +; MCETRCBUSY +; +MCETRCBUSY .assign 159 +MCETRCBUSY_BUSY .assign 0 ; +; -------------------------------------------------------------- +; MCETRCCMD +; +MCETRCCMD .assign 160 +MCETRCCMD_PARCNT .assign 8 ; +MCETRCCMD_PKTHDR .assign 0 ; +; -------------------------------------------------------------- +; MCETRCPAR0 +; +MCETRCPAR0 .assign 161 +MCETRCPAR0_PAR0 .assign 0 ; +; -------------------------------------------------------------- +; MCETRCPAR1 +; +MCETRCPAR1 .assign 162 +MCETRCPAR1_PAR1 .assign 0 ; +; -------------------------------------------------------------- +; RDCAPT0 +; +RDCAPT0 .assign 163 +RDCAPT0_DEMDSBU1 .assign 15 ; +RDCAPT0_DEMC1BEX .assign 14 ; +RDCAPT0_DEMSOFD0 .assign 13 ; +RDCAPT0_DEMLQIE0 .assign 12 ; +RDCAPT0_DEMSTIM1 .assign 11 ; +RDCAPT0_DEMSTIM0 .assign 10 ; +RDCAPT0_DEMFIFE2 .assign 9 ; +RDCAPT0_DEMPDIF0 .assign 8 ; +RDCAPT0_DEMCA2P0 .assign 7 ; +RDCAPT0_DEMFIDC4 .assign 6 ; +RDCAPT0_DEMFIDC3 .assign 5 ; +RDCAPT0_DEMMGEX2 .assign 4 ; +RDCAPT0_DEMMGEX1 .assign 3 ; +RDCAPT0_DEMDSBU0 .assign 2 ; +RDCAPT0_DEMCODC4 .assign 1 ; +RDCAPT0_DEMCODC3 .assign 0 ; +; -------------------------------------------------------------- +; DEMCODC3 +; +DEMCODC3 .assign 164 +DEMCODC3_ESTOUTI .assign 0 ; +; -------------------------------------------------------------- +; DEMCODC4 +; +DEMCODC4 .assign 165 +DEMCODC4_ESTOUTQ .assign 0 ; +; -------------------------------------------------------------- +; DEMMGEx1 +; +DEMMGEX1 .assign 166 +DEMMGEX1_MGE1ESTOUT .assign 0 ; +; -------------------------------------------------------------- +; DEMMGEx2 +; +DEMMGEX2 .assign 167 +DEMMGEX2_MGE2ESTOUT .assign 0 ; +; -------------------------------------------------------------- +; DEMFIDC3 +; +DEMFIDC3 .assign 168 +DEMFIDC3_ESTOUTI .assign 0 ; +; -------------------------------------------------------------- +; DEMFIDC4 +; +DEMFIDC4 .assign 169 +DEMFIDC4_ESTOUTQ .assign 0 ; +; -------------------------------------------------------------- +; DEMCA2P0 +; +DEMCA2P0 .assign 170 +DEMCA2P0_PHASE .assign 0 ; +; -------------------------------------------------------------- +; DEMPDIF0 +; +DEMPDIF0 .assign 171 +DEMPDIF0_PDIFF .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE3 +; +DEMC1BE3 .assign 172 +DEMC1BE3_CORRVALUEA .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE4 +; +DEMC1BE4 .assign 173 +DEMC1BE4_CORRVALUEB .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE5 +; +DEMC1BE5 .assign 174 +DEMC1BE5_CORRVALUEC .assign 0 ; +; -------------------------------------------------------------- +; DEMFIFE2 +; +DEMFIFE2 .assign 175 +DEMFIFE2_FINEFOCEST .assign 0 ; +; -------------------------------------------------------------- +; DEMDSBU0 +; +DEMDSBU0 .assign 176 +DEMDSBU0_RDPOUT .assign 0 ; +; -------------------------------------------------------------- +; DEMDSBU1 +; +DEMDSBU1 .assign 177 +DEMDSBU1_AVGVAL .assign 0 ; +; -------------------------------------------------------------- +; DEMSTIM0 +; +DEMSTIM0 .assign 178 +DEMSTIM0_EVENTS .assign 0 ; +; -------------------------------------------------------------- +; DEMSTIM1 +; +DEMSTIM1 .assign 179 +DEMSTIM1_GARDNERERROR .assign 4 ; +DEMSTIM1_DELTA .assign 0 ; +; -------------------------------------------------------------- +; DEMSWQU1 +; +DEMSWQU1 .assign 180 +DEMSWQU1_MAFCCOMPVAL .assign 2 ; +DEMSWQU1_SWSEL .assign 1 ; +DEMSWQU1_SYNCED .assign 0 ; +; -------------------------------------------------------------- +; DEMLQIE0 +; +DEMLQIE0 .assign 181 +DEMLQIE0_LQI .assign 0 ; +; -------------------------------------------------------------- +; DEMSOFD0 +; +DEMSOFD0 .assign 182 +DEMSOFD0_SOFTSYMBOL .assign 0 ; +; -------------------------------------------------------------- +; RDCAPT1 +; +RDCAPT1 .assign 183 +RDCAPT1_DEMHDIS0 .assign 13 ; +RDCAPT1_DEMFB2P2 .assign 12 ; +RDCAPT1_DEMPHAC .assign 11 ; +RDCAPT1_DEMMAFI5 .assign 10 ; +RDCAPT1_DEMMLSE4BITS .assign 9 ; +RDCAPT1_DEMPNSOFT .assign 8 ; +RDCAPT1_DEMMLSEBIT .assign 7 ; +RDCAPT1_DEMTHRD4 .assign 6 ; +RDCAPT1_DEMBDEC0 .assign 5 ; +RDCAPT1_DEMBDEC1 .assign 4 ; +RDCAPT1_DEMCHFI0 .assign 3 ; +RDCAPT1_DEMCHFI1 .assign 2 ; +RDCAPT1_DEMFRAC4 .assign 1 ; +RDCAPT1_DEMFRAC5 .assign 0 ; +; -------------------------------------------------------------- +; DEMTHRD4 +; +DEMTHRD4 .assign 184 +DEMTHRD4_DECISION .assign 0 ; +; -------------------------------------------------------------- +; DEMMLSEBIT +; +DEMMLSEBIT .assign 185 +DEMMLSEBIT_MLSEBIT .assign 0 ; +; -------------------------------------------------------------- +; DEMMLSE4BITS +; +DEMMLSE4BITS .assign 186 +DEMMLSE4BITS_MLSE4BITS .assign 0 ; +; -------------------------------------------------------------- +; DEMBDEC0 +; +DEMBDEC0 .assign 187 +DEMBDEC0_IVAL .assign 0 ; +; -------------------------------------------------------------- +; DEMBDEC1 +; +DEMBDEC1 .assign 188 +DEMBDEC1_QVAL .assign 0 ; +; -------------------------------------------------------------- +; DEMCHFI0 +; +DEMCHFI0 .assign 189 +DEMCHFI0_IVAL .assign 0 ; +; -------------------------------------------------------------- +; DEMCHFI1 +; +DEMCHFI1 .assign 190 +DEMCHFI1_QVAL .assign 0 ; +; -------------------------------------------------------------- +; DEMFRAC4 +; +DEMFRAC4 .assign 191 +DEMFRAC4_IVAL .assign 0 ; +; -------------------------------------------------------------- +; DEMFRAC5 +; +DEMFRAC5 .assign 192 +DEMFRAC5_QVAL .assign 0 ; +; -------------------------------------------------------------- +; DEMPNSOFT +; +DEMPNSOFT .assign 193 +DEMPNSOFT_PNSOFT .assign 0 ; +; -------------------------------------------------------------- +; DEMMAFI5 +; +DEMMAFI5 .assign 194 +DEMMAFI5_MAFIOUT .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE6 +; +DEMC1BE6 .assign 195 +DEMC1BE6_VAL .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE7 +; +DEMC1BE7 .assign 196 +DEMC1BE7_VAL .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE8 +; +DEMC1BE8 .assign 197 +DEMC1BE8_VAL .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE9 +; +DEMC1BE9 .assign 198 +DEMC1BE9_VAL .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BEA +; +DEMC1BEA .assign 199 +DEMC1BEA_QUALB .assign 6 ; +DEMC1BEA_QUALA .assign 0 ; +; -------------------------------------------------------------- +; MDMSPAR0 +; +MDMSPAR0 .assign 200 +MDMSPAR0_VAL .assign 0 ; +; -------------------------------------------------------------- +; MDMSPAR1 +; +MDMSPAR1 .assign 201 +MDMSPAR1_VAL .assign 0 ; +; -------------------------------------------------------------- +; MDMSPAR2 +; +MDMSPAR2 .assign 202 +MDMSPAR2_VAL .assign 0 ; +; -------------------------------------------------------------- +; MDMSPAR3 +; +MDMSPAR3 .assign 203 +MDMSPAR3_VAL .assign 0 ; +; -------------------------------------------------------------- +; DEMSOFD1 +; +DEMSOFD1 .assign 204 +DEMSOFD1_SOFTX0 .assign 0 ; +; -------------------------------------------------------------- +; DEMSOFD2 +; +DEMSOFD2 .assign 205 +DEMSOFD2_SOFTX1 .assign 0 ; +; -------------------------------------------------------------- +; DEMSOFD3 +; +DEMSOFD3 .assign 206 +DEMSOFD3_SOFTX2 .assign 0 ; +; -------------------------------------------------------------- +; DEMSOFD4 +; +DEMSOFD4 .assign 207 +DEMSOFD4_SOFTX3 .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE14 +; +DEMC1BE14 .assign 208 +DEMC1BE14_CORRVALUEE .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE15 +; +DEMC1BE15 .assign 209 +DEMC1BE15_CORRVALUEF .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE16 +; +DEMC1BE16 .assign 210 +DEMC1BE16_VAL .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE17 +; +DEMC1BE17 .assign 211 +DEMC1BE17_VAL .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE18 +; +DEMC1BE18 .assign 212 +DEMC1BE18_VAL .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE19 +; +DEMC1BE19 .assign 213 +DEMC1BE19_VAL .assign 0 ; +; -------------------------------------------------------------- +; DEMC1BE20 +; +DEMC1BE20 .assign 214 +DEMC1BE20_CORRVALUEG .assign 0 ; +; -------------------------------------------------------------- +; DEMDSBU3 +; +DEMDSBU3 .assign 215 +DEMDSBU3_WRPOUT .assign 0 ; +; -------------------------------------------------------------- +; MCEDUMP0 +; +MCEDUMP0 .assign 216 +MCEDUMP0_DONE .assign 0 ; +; -------------------------------------------------------------- +; MCEGPO0 +; +MCEGPO0 .assign 217 +MCEGPO0_HWDATAMUX .assign 11 ; +MCEGPO0_HWCLKSTRETCH .assign 9 ; +MCEGPO0_HWCLKMUX .assign 5 ; +MCEGPO0_FWCTRL .assign 4 ; +MCEGPO0_GPO3 .assign 3 ; +MCEGPO0_GPO2 .assign 2 ; +MCEGPO0_GPO1 .assign 1 ; +MCEGPO0_GPO0 .assign 0 ; +; -------------------------------------------------------------- +; DEMPHAC8 +; +DEMPHAC8 .assign 218 +DEMPHAC8_METRIC01 .assign 8 ; +DEMPHAC8_METRIC00 .assign 0 ; +; -------------------------------------------------------------- +; DEMPHAC9 +; +DEMPHAC9 .assign 219 +DEMPHAC9_METRIC11 .assign 8 ; +DEMPHAC9_METRIC10 .assign 0 ; +; -------------------------------------------------------------- +; DEMFB2P2 +; +DEMFB2P2 .assign 220 +DEMFB2P2_VAL .assign 0 ; +; -------------------------------------------------------------- +; DEMHDIS0 +; +DEMHDIS0 .assign 221 +DEMHDIS0_VAL .assign 0 ; + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;;;; mce_ram_bank.asm +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +.DEFINE LMD_DATA_SPACE 1 ;; LMD Data Space (Tables) +.DEFINE MDMCONF_IQDUMP 12 ;; Configuration Information +.DEFINE MAIN 48 ;; Main Program + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;;;; dbg.asm +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +__DBG__ .assign 1 +;;; Include file for handling debug print in TOPsm + +;;; -------------------------------------------------------------------------------- +;;; Macro for handling code generated from DBG_PRINT0 +.MACRO _DBG0 cmd +.ifdef __DBG__ + lli \cmd, r0 + jsr _DBG_PRINT +.endif __DBG__ +.ENDM + +;;; -------------------------------------------------------------------------------- +;;; Macro for handling code generated from DBG_PRINT1 +.MACRO _DBG1 cmd, reg0 +.ifdef __DBG__ + lli \cmd, r0 + output \reg0, MCETRCPAR0 + jsr _DBG_PRINT +.endif __DBG__ +.ENDM + +;;; -------------------------------------------------------------------------------- +;;; Macro for handling code generated from DBG_PRINT2 +.MACRO _DBG2 cmd, reg0, reg1 +.ifdef __DBG__ + lli \cmd, r0 + output \reg0, MCETRCPAR0 + output \reg1, MCETRCPAR1 + jsr _DBG_PRINT +.endif __DBG__ +.ENDM + +;;; -------------------------------------------------------------------------------- +;;; Macro for inserting handling code for debug printing - insert once in source file + +.MACRO DBG_FUNC +.ifdef __DBG__ +;;; DBG_PRINT +;;; R0 = pkt hdr +_DBG_PRINT: + output r0, MCETRCCMD ; R0 = pkt hdr +_DBG_PRINT_WAIT: + input MCETRCBUSY, r0 ; Wait until BUSY is released + btst 0, r0 ; Test bit 0 + bne _DBG_PRINT_WAIT + outbset MCETRCSEND_SEND, MCETRCSEND + rts +.endif __DBG__ +.ENDM + diff --git a/defs.inc b/defs.inc index 047ba9f..66ae78b 100644 --- a/defs.inc +++ b/defs.inc @@ -1,13 +1,13 @@ -; vim: set ft=asm: +; vim: set ft=nasm: -.DEFINE CMD_OK 1 -.DEFINE CMD_ERR 2 +%define CMD_OK 1 +%define CMD_ERR 2 -.DEFINE MDMCONF_IQDUMP_FIRST_REG 43 ; ADCDIGCONF -.DEFINE MDMCONF_IQDUMP_LAST_REG 78 ; DEMSWQU0 +%define MDMCONF_IQDUMP_FIRST_REG 43 ; ADCDIGCONF +%define MDMCONF_IQDUMP_LAST_REG 78 ; DEMSWQU0 ;;; Length of configuration (number of .DATA words) -.DEFINE MDMCONF_IQDUMP_LENGTH 36 +%define MDMCONF_IQDUMP_LENGTH 36 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -17,79 +17,79 @@ ; -------------------------------------------------------------- ; MCEEVENT0 event register bit positions ; -.DEFINE MCEEVENT0_MDMAPI_WR 0 ; New command from CPE received in MDMAPI register -.DEFINE MCEEVENT0_TIMER_IRQ 1 ; Timer period expired in local timer -.DEFINE MCEEVENT0_CLKEN_4BAUD 2 ; Clock enable event at 4 times baud rate -.DEFINE MCEEVENT0_FIFO_ERR_UNDERFLOW 3 ; FIFO underflow error event -.DEFINE MCEEVENT0_FIFO_ERR_OVERFLOW 4 ; FIFO overflow error event -.DEFINE MCEEVENT0_RFECMD_IRQ 5 ; New command from RFE received in MCERCEV register -.DEFINE MCEEVENT0_COUNTER_IRQ 6 ; Counter value reached in local timer -.DEFINE MCEEVENT0_MDMFIFO_WR 7 ; A write to the MDMFIFO register from CPE -.DEFINE MCEEVENT0_CPEFWEVENT0 8 ; Firmware defined event from CPE -.DEFINE MCEEVENT0_CPEFWEVENT1 9 ; Firmware defined event from CPE -.DEFINE MCEEVENT0_BDEC_EN 10 ; BDEC output enable -.DEFINE MCEEVENT0_FRAC_EN 11 ; FRAC output enable -.DEFINE MCEEVENT0_DL_TX_DONE 12 ; SMI serdes data word transmit done -.DEFINE MCEEVENT0_CL_TX_DONE 13 ; SMI serdes command word transmit done -.DEFINE MCEEVENT0_DL_RX_IRQ 14 ; SMI serdes data word receive interrupt -.DEFINE MCEEVENT0_CL_RX_IRQ 15 ; SMI serdes command word receive interrupt +%define MCEEVENT0_MDMAPI_WR 0 ; New command from CPE received in MDMAPI register +%define MCEEVENT0_TIMER_IRQ 1 ; Timer period expired in local timer +%define MCEEVENT0_CLKEN_4BAUD 2 ; Clock enable event at 4 times baud rate +%define MCEEVENT0_FIFO_ERR_UNDERFLOW 3 ; FIFO underflow error event +%define MCEEVENT0_FIFO_ERR_OVERFLOW 4 ; FIFO overflow error event +%define MCEEVENT0_RFECMD_IRQ 5 ; New command from RFE received in MCERCEV register +%define MCEEVENT0_COUNTER_IRQ 6 ; Counter value reached in local timer +%define MCEEVENT0_MDMFIFO_WR 7 ; A write to the MDMFIFO register from CPE +%define MCEEVENT0_CPEFWEVENT0 8 ; Firmware defined event from CPE +%define MCEEVENT0_CPEFWEVENT1 9 ; Firmware defined event from CPE +%define MCEEVENT0_BDEC_EN 10 ; BDEC output enable +%define MCEEVENT0_FRAC_EN 11 ; FRAC output enable +%define MCEEVENT0_DL_TX_DONE 12 ; SMI serdes data word transmit done +%define MCEEVENT0_CL_TX_DONE 13 ; SMI serdes command word transmit done +%define MCEEVENT0_DL_RX_IRQ 14 ; SMI serdes data word receive interrupt +%define MCEEVENT0_CL_RX_IRQ 15 ; SMI serdes command word receive interrupt ; -------------------------------------------------------------- ; MCEEVENT1 event register bit positions ; -.DEFINE MCEEVENT1_PREAMBLE_DONE 0 ; Preamble done interrupt from modulator -.DEFINE MCEEVENT1_CLKEN_BAUD 1 ; Baud indication -.DEFINE MCEEVENT1_FIFOWR_READY 2 ; It is legal to write to MDMFIFOWR register -.DEFINE MCEEVENT1_FIFORD_VALID 3 ; It is leval to read from MDMFIFORD register -.DEFINE MCEEVENT1_VITACC 4 ; Unused event -.DEFINE MCEEVENT1_MDMCMDPAR0_WR 5 ; A write to MDMCMDPAR0 register from CPE -.DEFINE MCEEVENT1_MDMCMDPAR1_WR 6 ; A write to MDMCMDPAR1 register from CPE -.DEFINE MCEEVENT1_CLKEN_BAUD_F 7 ; Flushed Baud Indication -.DEFINE MCEEVENT1_RAT_EVENT0 8 ; Radio timer event 0 -.DEFINE MCEEVENT1_RAT_EVENT1 9 ; Radio timer event 1 -.DEFINE MCEEVENT1_RAT_EVENT2 10 ; Radio timer event 2 -.DEFINE MCEEVENT1_RAT_EVENT3 11 ; Radio timer event 3 -.DEFINE MCEEVENT1_RAT_EVENT4 12 ; Radio timer event 4 -.DEFINE MCEEVENT1_RAT_EVENT5 13 ; Radio timer event 5 -.DEFINE MCEEVENT1_RAT_EVENT6 14 ; Radio timer event 6 -.DEFINE MCEEVENT1_RAT_EVENT7 15 ; Radio timer event 7 +%define MCEEVENT1_PREAMBLE_DONE 0 ; Preamble done interrupt from modulator +%define MCEEVENT1_CLKEN_BAUD 1 ; Baud indication +%define MCEEVENT1_FIFOWR_READY 2 ; It is legal to write to MDMFIFOWR register +%define MCEEVENT1_FIFORD_VALID 3 ; It is leval to read from MDMFIFORD register +%define MCEEVENT1_VITACC 4 ; Unused event +%define MCEEVENT1_MDMCMDPAR0_WR 5 ; A write to MDMCMDPAR0 register from CPE +%define MCEEVENT1_MDMCMDPAR1_WR 6 ; A write to MDMCMDPAR1 register from CPE +%define MCEEVENT1_CLKEN_BAUD_F 7 ; Flushed Baud Indication +%define MCEEVENT1_RAT_EVENT0 8 ; Radio timer event 0 +%define MCEEVENT1_RAT_EVENT1 9 ; Radio timer event 1 +%define MCEEVENT1_RAT_EVENT2 10 ; Radio timer event 2 +%define MCEEVENT1_RAT_EVENT3 11 ; Radio timer event 3 +%define MCEEVENT1_RAT_EVENT4 12 ; Radio timer event 4 +%define MCEEVENT1_RAT_EVENT5 13 ; Radio timer event 5 +%define MCEEVENT1_RAT_EVENT6 14 ; Radio timer event 6 +%define MCEEVENT1_RAT_EVENT7 15 ; Radio timer event 7 ; -------------------------------------------------------------- ; MCEEVENT2 event register bit positions ; -.DEFINE MCEEVENT2_C1BE_A_POS_PEAK 0 ; Correlator peak detect: corr A > thr A (occurs one sample after peak) -.DEFINE MCEEVENT2_C1BE_A_NEG_PEAK 1 ; Correlator peak detect: corr A < -thr A (occurs one sample after peak) -.DEFINE MCEEVENT2_C1BE_A_ANY_PEAK 2 ; Correlator peak detect: abs(corr A) > thr A (occurs one sample after peak) -.DEFINE MCEEVENT2_C1BE_B_POS_PEAK 3 ; Correlator peak detect: corr B > thr B (occurs one sample after peak) -.DEFINE MCEEVENT2_C1BE_B_NEG_PEAK 4 ; Correlator peak detect: corr B < -thr B (occurs one sample after peak) -.DEFINE MCEEVENT2_C1BE_B_ANY_PEAK 5 ; Correlator peak detect: abs(corr B) > thr B (occurs one sample after peak) -.DEFINE MCEEVENT2_C1BE_C_POS_PEAK 6 ; Correlator peak detect: corr C > thr C (occurs one sample after peak) -.DEFINE MCEEVENT2_C1BE_C_NEG_PEAK 7 ; Correlator peak detect: corr C < -thr C (occurs one sample after peak) -.DEFINE MCEEVENT2_C1BE_C_ANY_PEAK 8 ; Correlator peak detect: abs(corr C) > thr C (occurs one sample after peak) -.DEFINE MCEEVENT2_C1BE_CMB_POS_PEAK 9 ; Correlator peak detect: corr CMB > thr CMB (occurs one sample after peak) -.DEFINE MCEEVENT2_C1BE_CMB_NEG_PEAK 10 ; Correlator peak detect: corr CMB < -thr CMB (occurs one sample after peak) -.DEFINE MCEEVENT2_C1BE_CMB_ANY_PEAK 11 ; Correlator peak detect: abs(corr CMB) > thr CMB (occurs one sample after peak) -.DEFINE MCEEVENT2_C1BE_B_LOADED 12 ; Correlator B loaded (by auto-copy function) -.DEFINE MCEEVENT2_SWQU_SYNCED_IRQ 13 ; Sync word qualifier detected sync word -.DEFINE MCEEVENT2_MDMGPI0 14 ; Event from RFCore GPI 0 -.DEFINE MCEEVENT2_MDMGPI1 15 ; Event from RFCore GPI 1 +%define MCEEVENT2_C1BE_A_POS_PEAK 0 ; Correlator peak detect: corr A > thr A (occurs one sample after peak) +%define MCEEVENT2_C1BE_A_NEG_PEAK 1 ; Correlator peak detect: corr A < -thr A (occurs one sample after peak) +%define MCEEVENT2_C1BE_A_ANY_PEAK 2 ; Correlator peak detect: abs(corr A) > thr A (occurs one sample after peak) +%define MCEEVENT2_C1BE_B_POS_PEAK 3 ; Correlator peak detect: corr B > thr B (occurs one sample after peak) +%define MCEEVENT2_C1BE_B_NEG_PEAK 4 ; Correlator peak detect: corr B < -thr B (occurs one sample after peak) +%define MCEEVENT2_C1BE_B_ANY_PEAK 5 ; Correlator peak detect: abs(corr B) > thr B (occurs one sample after peak) +%define MCEEVENT2_C1BE_C_POS_PEAK 6 ; Correlator peak detect: corr C > thr C (occurs one sample after peak) +%define MCEEVENT2_C1BE_C_NEG_PEAK 7 ; Correlator peak detect: corr C < -thr C (occurs one sample after peak) +%define MCEEVENT2_C1BE_C_ANY_PEAK 8 ; Correlator peak detect: abs(corr C) > thr C (occurs one sample after peak) +%define MCEEVENT2_C1BE_CMB_POS_PEAK 9 ; Correlator peak detect: corr CMB > thr CMB (occurs one sample after peak) +%define MCEEVENT2_C1BE_CMB_NEG_PEAK 10 ; Correlator peak detect: corr CMB < -thr CMB (occurs one sample after peak) +%define MCEEVENT2_C1BE_CMB_ANY_PEAK 11 ; Correlator peak detect: abs(corr CMB) > thr CMB (occurs one sample after peak) +%define MCEEVENT2_C1BE_B_LOADED 12 ; Correlator B loaded (by auto-copy function) +%define MCEEVENT2_SWQU_SYNCED_IRQ 13 ; Sync word qualifier detected sync word +%define MCEEVENT2_MDMGPI0 14 ; Event from RFCore GPI 0 +%define MCEEVENT2_MDMGPI1 15 ; Event from RFCore GPI 1 ; -------------------------------------------------------------- ; MCEEVENT3 event register bit positions ; -.DEFINE MCEEVENT3_C1BE_D_POS_PEAK 0 ; Correlator peak detect: corr A > thr A (occurs one sample after peak) -.DEFINE MCEEVENT3_C1BE_D_NEG_PEAK 1 ; Correlator peak detect: corr A < -thr A (occurs one sample after peak) -.DEFINE MCEEVENT3_C1BE_D_ANY_PEAK 2 ; Correlator peak detect: abs(corr A) > thr A (occurs one sample after peak) -.DEFINE MCEEVENT3_C1BE_E_POS_PEAK 3 ; Correlator peak detect: corr B > thr B (occurs one sample after peak) -.DEFINE MCEEVENT3_C1BE_E_NEG_PEAK 4 ; Correlator peak detect: corr B < -thr B (occurs one sample after peak) -.DEFINE MCEEVENT3_C1BE_E_ANY_PEAK 5 ; Correlator peak detect: abs(corr B) > thr B (occurs one sample after peak) -.DEFINE MCEEVENT3_C1BE_F_POS_PEAK 6 ; Correlator peak detect: corr C > thr C (occurs one sample after peak) -.DEFINE MCEEVENT3_C1BE_F_NEG_PEAK 7 ; Correlator peak detect: corr C < -thr C (occurs one sample after peak) -.DEFINE MCEEVENT3_C1BE_F_ANY_PEAK 8 ; Correlator peak detect: abs(corr C) > thr C (occurs one sample after peak) -.DEFINE MCEEVENT3_C1BE_CMB_DE_POS_PEAK 9 ; Correlator peak detect: corr CMB > thr CMB (occurs one sample after peak) -.DEFINE MCEEVENT3_C1BE_CMB_DE_NEG_PEAK 10 ; Correlator peak detect: corr CMB < -thr CMB (occurs one sample after peak) -.DEFINE MCEEVENT3_C1BE_CMB_DE_ANY_PEAK 11 ; Correlator peak detect: abs(corr CMB) > thr CMB (occurs one sample after peak) -.DEFINE MCEEVENT3_C1BE_G_POS_PEAK 12 ; Correlator peak detect: corr G > thr G -.DEFINE MCEEVENT3_C1BE_G_NEG_PEAK 13 ; Correlator peak detect: corr G < -thr G -.DEFINE MCEEVENT3_C1BE_G_ANY_PEAK 14 ; Correlator peak detect: abs(corr G) > thr G -.DEFINE MCEEVENT3_SWQU_FALSE_SYNC_IRQ 15 ; Sync owrd qualifier false sync +%define MCEEVENT3_C1BE_D_POS_PEAK 0 ; Correlator peak detect: corr A > thr A (occurs one sample after peak) +%define MCEEVENT3_C1BE_D_NEG_PEAK 1 ; Correlator peak detect: corr A < -thr A (occurs one sample after peak) +%define MCEEVENT3_C1BE_D_ANY_PEAK 2 ; Correlator peak detect: abs(corr A) > thr A (occurs one sample after peak) +%define MCEEVENT3_C1BE_E_POS_PEAK 3 ; Correlator peak detect: corr B > thr B (occurs one sample after peak) +%define MCEEVENT3_C1BE_E_NEG_PEAK 4 ; Correlator peak detect: corr B < -thr B (occurs one sample after peak) +%define MCEEVENT3_C1BE_E_ANY_PEAK 5 ; Correlator peak detect: abs(corr B) > thr B (occurs one sample after peak) +%define MCEEVENT3_C1BE_F_POS_PEAK 6 ; Correlator peak detect: corr C > thr C (occurs one sample after peak) +%define MCEEVENT3_C1BE_F_NEG_PEAK 7 ; Correlator peak detect: corr C < -thr C (occurs one sample after peak) +%define MCEEVENT3_C1BE_F_ANY_PEAK 8 ; Correlator peak detect: abs(corr C) > thr C (occurs one sample after peak) +%define MCEEVENT3_C1BE_CMB_DE_POS_PEAK 9 ; Correlator peak detect: corr CMB > thr CMB (occurs one sample after peak) +%define MCEEVENT3_C1BE_CMB_DE_NEG_PEAK 10 ; Correlator peak detect: corr CMB < -thr CMB (occurs one sample after peak) +%define MCEEVENT3_C1BE_CMB_DE_ANY_PEAK 11 ; Correlator peak detect: abs(corr CMB) > thr CMB (occurs one sample after peak) +%define MCEEVENT3_C1BE_G_POS_PEAK 12 ; Correlator peak detect: corr G > thr G +%define MCEEVENT3_C1BE_G_NEG_PEAK 13 ; Correlator peak detect: corr G < -thr G +%define MCEEVENT3_C1BE_G_ANY_PEAK 14 ; Correlator peak detect: abs(corr G) > thr G +%define MCEEVENT3_SWQU_FALSE_SYNC_IRQ 15 ; Sync owrd qualifier false sync ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;; mdm_regs.asm @@ -98,1688 +98,1691 @@ ; -------------------------------------------------------------- ; MDMENABLE ; -MDMENABLE .assign 0 -MDMENABLE_PDIF2 .assign 11 ; -MDMENABLE_PHASECORR .assign 10 ; -MDMENABLE_HILBDISC .assign 9 ; -MDMENABLE_FB2PLL .assign 8 ; -MDMENABLE_VITACC .assign 7 ; -MDMENABLE_ADCDIG .assign 6 ; -MDMENABLE_SMI .assign 5 ; -MDMENABLE_DEMODULATOR .assign 4 ; -MDMENABLE_MODULATOR .assign 3 ; -MDMENABLE_TIMEBASE .assign 2 ; -MDMENABLE_TXRXFIFO .assign 1 ; -MDMENABLE_mce .assign 0 ; +%define MDMENABLE 0 +%define MDMENABLE_PDIF2 11 ; +%define MDMENABLE_PHASECORR 10 ; +%define MDMENABLE_HILBDISC 9 ; +%define MDMENABLE_FB2PLL 8 ; +%define MDMENABLE_VITACC 7 ; +%define MDMENABLE_ADCDIG 6 ; +%define MDMENABLE_SMI 5 ; +%define MDMENABLE_DEMODULATOR 4 ; +%define MDMENABLE_MODULATOR 3 ; +%define MDMENABLE_TIMEBASE 2 ; +%define MDMENABLE_TXRXFIFO 1 ; +%define MDMENABLE_mce 0 ; ; -------------------------------------------------------------- ; MDMINIT ; -MDMINIT .assign 1 -MDMINIT_PDIF2 .assign 11 ; -MDMINIT_PHASECORR .assign 10 ; -MDMINIT_HILBDISC .assign 9 ; -MDMINIT_FB2PLL .assign 8 ; -MDMINIT_VITACC .assign 7 ; -MDMINIT_ADCDIG .assign 6 ; -MDMINIT_SMI .assign 5 ; -MDMINIT_DEMODULATOR .assign 4 ; -MDMINIT_MODULATOR .assign 3 ; -MDMINIT_TIMEBASE .assign 2 ; -MDMINIT_TXRXFIFO .assign 1 ; -MDMINIT_mce .assign 0 ; +%define MDMINIT 1 +%define MDMINIT_PDIF2 11 ; +%define MDMINIT_PHASECORR 10 ; +%define MDMINIT_HILBDISC 9 ; +%define MDMINIT_FB2PLL 8 ; +%define MDMINIT_VITACC 7 ; +%define MDMINIT_ADCDIG 6 ; +%define MDMINIT_SMI 5 ; +%define MDMINIT_DEMODULATOR 4 ; +%define MDMINIT_MODULATOR 3 ; +%define MDMINIT_TIMEBASE 2 ; +%define MDMINIT_TXRXFIFO 1 ; +%define MDMINIT_mce 0 ; ; -------------------------------------------------------------- ; MDMPDREQ ; -MDMPDREQ .assign 2 -MDMPDREQ_mcePDREQ .assign 0 ; +%define MDMPDREQ 2 +%define MDMPDREQ_mcePDREQ 0 ; ; -------------------------------------------------------------- ; DEMENABLE0 ; -DEMENABLE0 .assign 3 -DEMENABLE0_FE23 .assign 15 ; -DEMENABLE0_FE13 .assign 14 ; -DEMENABLE0_FELP .assign 13 ; -DEMENABLE0_THRD .assign 12 ; -DEMENABLE0_FRAC .assign 11 ; -DEMENABLE0_FIDC .assign 10 ; -DEMENABLE0_CHFI .assign 9 ; -DEMENABLE0_BDEC .assign 8 ; -DEMENABLE0_IQMC .assign 7 ; -DEMENABLE0_MGE2 .assign 6 ; -DEMENABLE0_MGE1 .assign 5 ; -DEMENABLE0_RSVD .assign 4 ; -DEMENABLE0_CODC .assign 3 ; -DEMENABLE0_CMI4 .assign 2 ; -DEMENABLE0_CMIX .assign 1 ; -DEMENABLE0_HILB .assign 0 ; +%define DEMENABLE0 3 +%define DEMENABLE0_FE23 15 ; +%define DEMENABLE0_FE13 14 ; +%define DEMENABLE0_FELP 13 ; +%define DEMENABLE0_THRD 12 ; +%define DEMENABLE0_FRAC 11 ; +%define DEMENABLE0_FIDC 10 ; +%define DEMENABLE0_CHFI 9 ; +%define DEMENABLE0_BDEC 8 ; +%define DEMENABLE0_IQMC 7 ; +%define DEMENABLE0_MGE2 6 ; +%define DEMENABLE0_MGE1 5 ; +%define DEMENABLE0_RSVD 4 ; +%define DEMENABLE0_CODC 3 ; +%define DEMENABLE0_CMI4 2 ; +%define DEMENABLE0_CMIX 1 ; +%define DEMENABLE0_HILB 0 ; ; -------------------------------------------------------------- ; DEMENABLE1 ; -DEMENABLE1 .assign 4 -DEMENABLE1_VITE .assign 15 ; -DEMENABLE1_MLSE .assign 14 ; -DEMENABLE1_SOFD .assign 13 ; -DEMENABLE1_SWQU .assign 12 ; -DEMENABLE1_MAFC .assign 11 ; -DEMENABLE1_MAFI .assign 10 ; -DEMENABLE1_FIFE .assign 9 ; -DEMENABLE1_PDIF .assign 8 ; -DEMENABLE1_CA2P .assign 7 ; -DEMENABLE1_FECP .assign 6 ; -DEMENABLE1_FEC5 .assign 5 ; -DEMENABLE1_C1BE .assign 4 ; -DEMENABLE1_LQIE .assign 3 ; -DEMENABLE1_F4BA .assign 2 ; -DEMENABLE1_STIM .assign 1 ; -DEMENABLE1_DSBU .assign 0 ; +%define DEMENABLE1 4 +%define DEMENABLE1_VITE 15 ; +%define DEMENABLE1_MLSE 14 ; +%define DEMENABLE1_SOFD 13 ; +%define DEMENABLE1_SWQU 12 ; +%define DEMENABLE1_MAFC 11 ; +%define DEMENABLE1_MAFI 10 ; +%define DEMENABLE1_FIFE 9 ; +%define DEMENABLE1_PDIF 8 ; +%define DEMENABLE1_CA2P 7 ; +%define DEMENABLE1_FECP 6 ; +%define DEMENABLE1_FEC5 5 ; +%define DEMENABLE1_C1BE 4 ; +%define DEMENABLE1_LQIE 3 ; +%define DEMENABLE1_F4BA 2 ; +%define DEMENABLE1_STIM 1 ; +%define DEMENABLE1_DSBU 0 ; ; -------------------------------------------------------------- ; DEMINIT0 ; -DEMINIT0 .assign 5 -DEMINIT0_FE23 .assign 15 ; -DEMINIT0_FE13 .assign 14 ; -DEMINIT0_FELP .assign 13 ; -DEMINIT0_THRD .assign 12 ; -DEMINIT0_FRAC .assign 11 ; -DEMINIT0_FIDC .assign 10 ; -DEMINIT0_CHFI .assign 9 ; -DEMINIT0_BDEC .assign 8 ; -DEMINIT0_IQMC .assign 7 ; -DEMINIT0_MGE2 .assign 6 ; -DEMINIT0_MGE1 .assign 5 ; -DEMINIT0_RSVD .assign 4 ; -DEMINIT0_CODC .assign 3 ; -DEMINIT0_CMI4 .assign 2 ; -DEMINIT0_CMIX .assign 1 ; -DEMINIT0_HILB .assign 0 ; +%define DEMINIT0 5 +%define DEMINIT0_FE23 15 ; +%define DEMINIT0_FE13 14 ; +%define DEMINIT0_FELP 13 ; +%define DEMINIT0_THRD 12 ; +%define DEMINIT0_FRAC 11 ; +%define DEMINIT0_FIDC 10 ; +%define DEMINIT0_CHFI 9 ; +%define DEMINIT0_BDEC 8 ; +%define DEMINIT0_IQMC 7 ; +%define DEMINIT0_MGE2 6 ; +%define DEMINIT0_MGE1 5 ; +%define DEMINIT0_RSVD 4 ; +%define DEMINIT0_CODC 3 ; +%define DEMINIT0_CMI4 2 ; +%define DEMINIT0_CMIX 1 ; +%define DEMINIT0_HILB 0 ; ; -------------------------------------------------------------- ; DEMINIT1 ; -DEMINIT1 .assign 6 -DEMINIT1_VITE .assign 15 ; -DEMINIT1_MLSE .assign 14 ; -DEMINIT1_SOFD .assign 13 ; -DEMINIT1_SWQU .assign 12 ; -DEMINIT1_MAFC .assign 11 ; -DEMINIT1_MAFI .assign 10 ; -DEMINIT1_FIFE .assign 9 ; -DEMINIT1_PDIF .assign 8 ; -DEMINIT1_CA2P .assign 7 ; -DEMINIT1_FECP .assign 6 ; -DEMINIT1_FEC5 .assign 5 ; -DEMINIT1_C1BE .assign 4 ; -DEMINIT1_LQIE .assign 3 ; -DEMINIT1_F4BA .assign 2 ; -DEMINIT1_STIM .assign 1 ; -DEMINIT1_DSBU .assign 0 ; +%define DEMINIT1 6 +%define DEMINIT1_VITE 15 ; +%define DEMINIT1_MLSE 14 ; +%define DEMINIT1_SOFD 13 ; +%define DEMINIT1_SWQU 12 ; +%define DEMINIT1_MAFC 11 ; +%define DEMINIT1_MAFI 10 ; +%define DEMINIT1_FIFE 9 ; +%define DEMINIT1_PDIF 8 ; +%define DEMINIT1_CA2P 7 ; +%define DEMINIT1_FECP 6 ; +%define DEMINIT1_FEC5 5 ; +%define DEMINIT1_C1BE 4 ; +%define DEMINIT1_LQIE 3 ; +%define DEMINIT1_F4BA 2 ; +%define DEMINIT1_STIM 1 ; +%define DEMINIT1_DSBU 0 ; ; -------------------------------------------------------------- ; MCESTROBES0 ; -MCESTROBES0 .assign 7 -MCESTROBES0_EVENT5 .assign 12 ; -MCESTROBES0_EVENT4 .assign 11 ; -MCESTROBES0_ROMDUMP .assign 10 ; -MCESTROBES0_VITACCSTART .assign 9 ; -MCESTROBES0_MLSETERM .assign 8 ; -MCESTROBES0_EVENT3 .assign 7 ; -MCESTROBES0_EVENT2 .assign 6 ; -MCESTROBES0_EVENT1 .assign 5 ; -MCESTROBES0_EVENT0 .assign 4 ; -MCESTROBES0_MCETIMBALIGN .assign 3 ; -MCESTROBES0_DSBURESTART .assign 2 ; -MCESTROBES0_RSVD .assign 1 ; -MCESTROBES0_CMDDONE .assign 0 ; +%define MCESTROBES0 7 +%define MCESTROBES0_EVENT5 12 ; +%define MCESTROBES0_EVENT4 11 ; +%define MCESTROBES0_ROMDUMP 10 ; +%define MCESTROBES0_VITACCSTART 9 ; +%define MCESTROBES0_MLSETERM 8 ; +%define MCESTROBES0_EVENT3 7 ; +%define MCESTROBES0_EVENT2 6 ; +%define MCESTROBES0_EVENT1 5 ; +%define MCESTROBES0_EVENT0 4 ; +%define MCESTROBES0_MCETIMBALIGN 3 ; +%define MCESTROBES0_DSBURESTART 2 ; +%define MCESTROBES0_RSVD 1 ; +%define MCESTROBES0_CMDDONE 0 ; ; -------------------------------------------------------------- ; MCESTROBES1 ; -MCESTROBES1 .assign 8 -MCESTROBES1_C1BECOPYCMD2 .assign 15 ; -MCESTROBES1_C1BEPEAKGCMD .assign 14 ; -MCESTROBES1_C1BEPEAKDECMD .assign 13 ; -MCESTROBES1_C1BEPEAKFCMD .assign 12 ; -MCESTROBES1_C1BEPEAKECMD .assign 11 ; -MCESTROBES1_C1BEPEAKDCMD .assign 10 ; -MCESTROBES1_C1BEPEAKABCMD .assign 9 ; -MCESTROBES1_C1BEPEAKCCMD .assign 8 ; -MCESTROBES1_C1BEPEAKBCMD .assign 7 ; -MCESTROBES1_C1BEPEAKACMD .assign 6 ; -MCESTROBES1_C1BEADVANCECMD .assign 5 ; -MCESTROBES1_C1BESTALLCMD .assign 4 ; -MCESTROBES1_C1BEROTCMD .assign 2 ; -MCESTROBES1_C1BECOPYCMD .assign 1 ; -MCESTROBES1_RESERVED .assign 0 ; +%define MCESTROBES1 8 +%define MCESTROBES1_C1BECOPYCMD2 15 ; +%define MCESTROBES1_C1BEPEAKGCMD 14 ; +%define MCESTROBES1_C1BEPEAKDECMD 13 ; +%define MCESTROBES1_C1BEPEAKFCMD 12 ; +%define MCESTROBES1_C1BEPEAKECMD 11 ; +%define MCESTROBES1_C1BEPEAKDCMD 10 ; +%define MCESTROBES1_C1BEPEAKABCMD 9 ; +%define MCESTROBES1_C1BEPEAKCCMD 8 ; +%define MCESTROBES1_C1BEPEAKBCMD 7 ; +%define MCESTROBES1_C1BEPEAKACMD 6 ; +%define MCESTROBES1_C1BEADVANCECMD 5 ; +%define MCESTROBES1_C1BESTALLCMD 4 ; +%define MCESTROBES1_C1BEROTCMD 2 ; +%define MCESTROBES1_C1BECOPYCMD 1 ; +%define MCESTROBES1_RESERVED 0 ; ; -------------------------------------------------------------- ; MCEEVENT0 ; -MCEEVENT0 .assign 9 -MCEEVENT0_CL_RX_IRQ .assign 15 ; -MCEEVENT0_DL_RX_IRQ .assign 14 ; -MCEEVENT0_CL_TX_DONE .assign 13 ; -MCEEVENT0_DL_TX_DONE .assign 12 ; -MCEEVENT0_FRAC_EN .assign 11 ; -MCEEVENT0_BDEC_EN .assign 10 ; -MCEEVENT0_CPEFWEVENT1 .assign 9 ; -MCEEVENT0_CPEFWEVENT0 .assign 8 ; -MCEEVENT0_MDMFIFO_WR .assign 7 ; -MCEEVENT0_COUNTER_IRQ .assign 6 ; -MCEEVENT0_RFECMD_IRQ .assign 5 ; -MCEEVENT0_FIFO_ERR_OVERFLOW .assign 4 ; -MCEEVENT0_FIFO_ERR_UNDERFLOW .assign 3 ; -MCEEVENT0_CLKEN_4BAUD .assign 2 ; -MCEEVENT0_TIMER_IRQ .assign 1 ; -MCEEVENT0_MDMAPI_WR .assign 0 ; +%define MCEEVENT0 9 +%define MCEEVENT0_CL_RX_IRQ 15 ; +%define MCEEVENT0_DL_RX_IRQ 14 ; +%define MCEEVENT0_CL_TX_DONE 13 ; +%define MCEEVENT0_DL_TX_DONE 12 ; +%define MCEEVENT0_FRAC_EN 11 ; +%define MCEEVENT0_BDEC_EN 10 ; +%define MCEEVENT0_CPEFWEVENT1 9 ; +%define MCEEVENT0_CPEFWEVENT0 8 ; +%define MCEEVENT0_MDMFIFO_WR 7 ; +%define MCEEVENT0_COUNTER_IRQ 6 ; +%define MCEEVENT0_RFECMD_IRQ 5 ; +%define MCEEVENT0_FIFO_ERR_OVERFLOW 4 ; +%define MCEEVENT0_FIFO_ERR_UNDERFLOW 3 ; +%define MCEEVENT0_CLKEN_4BAUD 2 ; +%define MCEEVENT0_TIMER_IRQ 1 ; +%define MCEEVENT0_MDMAPI_WR 0 ; ; -------------------------------------------------------------- ; MCEEVENT1 ; -MCEEVENT1 .assign 10 -MCEEVENT1_RAT_EVENT7 .assign 15 ; -MCEEVENT1_RAT_EVENT6 .assign 14 ; -MCEEVENT1_RAT_EVENT5 .assign 13 ; -MCEEVENT1_RAT_EVENT4 .assign 12 ; -MCEEVENT1_RAT_EVENT3 .assign 11 ; -MCEEVENT1_RAT_EVENT2 .assign 10 ; -MCEEVENT1_RAT_EVENT1 .assign 9 ; -MCEEVENT1_RAT_EVENT0 .assign 8 ; -MCEEVENT1_CLKEN_BAUD_F .assign 7 ; -MCEEVENT1_MDMCMDPAR1_WR .assign 6 ; -MCEEVENT1_MDMCMDPAR0_WR .assign 5 ; -MCEEVENT1_VITACC .assign 4 ; -MCEEVENT1_FIFORD_VALID .assign 3 ; -MCEEVENT1_FIFOWR_READY .assign 2 ; -MCEEVENT1_CLKEN_BAUD .assign 1 ; -MCEEVENT1_PREAMBLE_DONE .assign 0 ; +%define MCEEVENT1 10 +%define MCEEVENT1_RAT_EVENT7 15 ; +%define MCEEVENT1_RAT_EVENT6 14 ; +%define MCEEVENT1_RAT_EVENT5 13 ; +%define MCEEVENT1_RAT_EVENT4 12 ; +%define MCEEVENT1_RAT_EVENT3 11 ; +%define MCEEVENT1_RAT_EVENT2 10 ; +%define MCEEVENT1_RAT_EVENT1 9 ; +%define MCEEVENT1_RAT_EVENT0 8 ; +%define MCEEVENT1_CLKEN_BAUD_F 7 ; +%define MCEEVENT1_MDMCMDPAR1_WR 6 ; +%define MCEEVENT1_MDMCMDPAR0_WR 5 ; +%define MCEEVENT1_VITACC 4 ; +%define MCEEVENT1_FIFORD_VALID 3 ; +%define MCEEVENT1_FIFOWR_READY 2 ; +%define MCEEVENT1_CLKEN_BAUD 1 ; +%define MCEEVENT1_PREAMBLE_DONE 0 ; ; -------------------------------------------------------------- ; MCEEVENT2 ; -MCEEVENT2 .assign 11 -MCEEVENT2_MDMGPI1 .assign 15 ; -MCEEVENT2_MDMGPI0 .assign 14 ; -MCEEVENT2_SWQU_SYNCED_IRQ .assign 13 ; -MCEEVENT2_C1BE_B_LOADED .assign 12 ; -MCEEVENT2_C1BE_CMB_ANY_PEAK .assign 11 ; -MCEEVENT2_C1BE_CMB_NEG_PEAK .assign 10 ; -MCEEVENT2_C1BE_CMB_POS_PEAK .assign 9 ; -MCEEVENT2_C1BE_C_ANY_PEAK .assign 8 ; -MCEEVENT2_C1BE_C_NEG_PEAK .assign 7 ; -MCEEVENT2_C1BE_C_POS_PEAK .assign 6 ; -MCEEVENT2_C1BE_B_ANY_PEAK .assign 5 ; -MCEEVENT2_C1BE_B_NEG_PEAK .assign 4 ; -MCEEVENT2_C1BE_B_POS_PEAK .assign 3 ; -MCEEVENT2_C1BE_A_ANY_PEAK .assign 2 ; -MCEEVENT2_C1BE_A_NEG_PEAK .assign 1 ; -MCEEVENT2_C1BE_A_POS_PEAK .assign 0 ; +%define MCEEVENT2 11 +%define MCEEVENT2_MDMGPI1 15 ; +%define MCEEVENT2_MDMGPI0 14 ; +%define MCEEVENT2_SWQU_SYNCED_IRQ 13 ; +%define MCEEVENT2_C1BE_B_LOADED 12 ; +%define MCEEVENT2_C1BE_CMB_ANY_PEAK 11 ; +%define MCEEVENT2_C1BE_CMB_NEG_PEAK 10 ; +%define MCEEVENT2_C1BE_CMB_POS_PEAK 9 ; +%define MCEEVENT2_C1BE_C_ANY_PEAK 8 ; +%define MCEEVENT2_C1BE_C_NEG_PEAK 7 ; +%define MCEEVENT2_C1BE_C_POS_PEAK 6 ; +%define MCEEVENT2_C1BE_B_ANY_PEAK 5 ; +%define MCEEVENT2_C1BE_B_NEG_PEAK 4 ; +%define MCEEVENT2_C1BE_B_POS_PEAK 3 ; +%define MCEEVENT2_C1BE_A_ANY_PEAK 2 ; +%define MCEEVENT2_C1BE_A_NEG_PEAK 1 ; +%define MCEEVENT2_C1BE_A_POS_PEAK 0 ; ; -------------------------------------------------------------- ; MCEEVENT3 ; -MCEEVENT3 .assign 12 -MCEEVENT3_SWQU_FALSE_SYNC_IRQ .assign 15 ; -MCEEVENT3_C1BE_G_ANY_PEAK .assign 14 ; -MCEEVENT3_C1BE_G_NEG_PEAK .assign 13 ; -MCEEVENT3_C1BE_G_POS_PEAK .assign 12 ; -MCEEVENT3_C1BE_CMB_DE_ANY_PEAK .assign 11 ; -MCEEVENT3_C1BE_CMB_DE_NEG_PEAK .assign 10 ; -MCEEVENT3_C1BE_CMB_DE_POS_PEAK .assign 9 ; -MCEEVENT3_C1BE_F_ANY_PEAK .assign 8 ; -MCEEVENT3_C1BE_F_NEG_PEAK .assign 7 ; -MCEEVENT3_C1BE_F_POS_PEAK .assign 6 ; -MCEEVENT3_C1BE_E_ANY_PEAK .assign 5 ; -MCEEVENT3_C1BE_E_NEG_PEAK .assign 4 ; -MCEEVENT3_C1BE_E_POS_PEAK .assign 3 ; -MCEEVENT3_C1BE_D_ANY_PEAK .assign 2 ; -MCEEVENT3_C1BE_D_NEG_PEAK .assign 1 ; -MCEEVENT3_C1BE_D_POS_PEAK .assign 0 ; +%define MCEEVENT3 12 +%define MCEEVENT3_SWQU_FALSE_SYNC_IRQ 15 ; +%define MCEEVENT3_C1BE_G_ANY_PEAK 14 ; +%define MCEEVENT3_C1BE_G_NEG_PEAK 13 ; +%define MCEEVENT3_C1BE_G_POS_PEAK 12 ; +%define MCEEVENT3_C1BE_CMB_DE_ANY_PEAK 11 ; +%define MCEEVENT3_C1BE_CMB_DE_NEG_PEAK 10 ; +%define MCEEVENT3_C1BE_CMB_DE_POS_PEAK 9 ; +%define MCEEVENT3_C1BE_F_ANY_PEAK 8 ; +%define MCEEVENT3_C1BE_F_NEG_PEAK 7 ; +%define MCEEVENT3_C1BE_F_POS_PEAK 6 ; +%define MCEEVENT3_C1BE_E_ANY_PEAK 5 ; +%define MCEEVENT3_C1BE_E_NEG_PEAK 4 ; +%define MCEEVENT3_C1BE_E_POS_PEAK 3 ; +%define MCEEVENT3_C1BE_D_ANY_PEAK 2 ; +%define MCEEVENT3_C1BE_D_NEG_PEAK 1 ; +%define MCEEVENT3_C1BE_D_POS_PEAK 0 ; ; -------------------------------------------------------------- ; MCEEVENTMSK0 ; -MCEEVENTMSK0 .assign 13 -MCEEVENTMSK0_CL_RX_IRQ .assign 15 ; -MCEEVENTMSK0_DL_RX_IRQ .assign 14 ; -MCEEVENTMSK0_CL_TX_DONE .assign 13 ; -MCEEVENTMSK0_DL_TX_DONE .assign 12 ; -MCEEVENTMSK0_FRAC_EN .assign 11 ; -MCEEVENTMSK0_BDEC_EN .assign 10 ; -MCEEVENTMSK0_CPEFWEVENT1 .assign 9 ; -MCEEVENTMSK0_CPEFWEVENT0 .assign 8 ; -MCEEVENTMSK0_MDMFIFO_WR .assign 7 ; -MCEEVENTMSK0_COUNTER_IRQ .assign 6 ; -MCEEVENTMSK0_RFECMD_IRQ .assign 5 ; -MCEEVENTMSK0_FIFO_ERR_OVERFLOW .assign 4 ; -MCEEVENTMSK0_FIFO_ERR_UNDERFLOW .assign 3 ; -MCEEVENTMSK0_CLKEN_4BAUD .assign 2 ; -MCEEVENTMSK0_TIMER_IRQ .assign 1 ; -MCEEVENTMSK0_MDMAPI_WR .assign 0 ; +%define MCEEVENTMSK0 13 +%define MCEEVENTMSK0_CL_RX_IRQ 15 ; +%define MCEEVENTMSK0_DL_RX_IRQ 14 ; +%define MCEEVENTMSK0_CL_TX_DONE 13 ; +%define MCEEVENTMSK0_DL_TX_DONE 12 ; +%define MCEEVENTMSK0_FRAC_EN 11 ; +%define MCEEVENTMSK0_BDEC_EN 10 ; +%define MCEEVENTMSK0_CPEFWEVENT1 9 ; +%define MCEEVENTMSK0_CPEFWEVENT0 8 ; +%define MCEEVENTMSK0_MDMFIFO_WR 7 ; +%define MCEEVENTMSK0_COUNTER_IRQ 6 ; +%define MCEEVENTMSK0_RFECMD_IRQ 5 ; +%define MCEEVENTMSK0_FIFO_ERR_OVERFLOW 4 ; +%define MCEEVENTMSK0_FIFO_ERR_UNDERFLOW 3 ; +%define MCEEVENTMSK0_CLKEN_4BAUD 2 ; +%define MCEEVENTMSK0_TIMER_IRQ 1 ; +%define MCEEVENTMSK0_MDMAPI_WR 0 ; ; -------------------------------------------------------------- ; MCEEVENTMSK1 ; -MCEEVENTMSK1 .assign 14 -MCEEVENTMSK1_RAT_EVENT7 .assign 15 ; -MCEEVENTMSK1_RAT_EVENT6 .assign 14 ; -MCEEVENTMSK1_RAT_EVENT5 .assign 13 ; -MCEEVENTMSK1_RAT_EVENT4 .assign 12 ; -MCEEVENTMSK1_RAT_EVENT3 .assign 11 ; -MCEEVENTMSK1_RAT_EVENT2 .assign 10 ; -MCEEVENTMSK1_RAT_EVENT1 .assign 9 ; -MCEEVENTMSK1_RAT_EVENT0 .assign 8 ; -MCEEVENTMSK1_CLKEN_BAUD_F .assign 7 ; -MCEEVENTMSK1_MDMCMDPAR1_WR .assign 6 ; -MCEEVENTMSK1_MDMCMDPAR0_WR .assign 5 ; -MCEEVENTMSK1_VITACC .assign 4 ; -MCEEVENTMSK1_FIFORD_VALID .assign 3 ; -MCEEVENTMSK1_FIFOWR_READY .assign 2 ; -MCEEVENTMSK1_CLKEN_BAUD .assign 1 ; -MCEEVENTMSK1_PREAMBLE_DONE .assign 0 ; +%define MCEEVENTMSK1 14 +%define MCEEVENTMSK1_RAT_EVENT7 15 ; +%define MCEEVENTMSK1_RAT_EVENT6 14 ; +%define MCEEVENTMSK1_RAT_EVENT5 13 ; +%define MCEEVENTMSK1_RAT_EVENT4 12 ; +%define MCEEVENTMSK1_RAT_EVENT3 11 ; +%define MCEEVENTMSK1_RAT_EVENT2 10 ; +%define MCEEVENTMSK1_RAT_EVENT1 9 ; +%define MCEEVENTMSK1_RAT_EVENT0 8 ; +%define MCEEVENTMSK1_CLKEN_BAUD_F 7 ; +%define MCEEVENTMSK1_MDMCMDPAR1_WR 6 ; +%define MCEEVENTMSK1_MDMCMDPAR0_WR 5 ; +%define MCEEVENTMSK1_VITACC 4 ; +%define MCEEVENTMSK1_FIFORD_VALID 3 ; +%define MCEEVENTMSK1_FIFOWR_READY 2 ; +%define MCEEVENTMSK1_CLKEN_BAUD 1 ; +%define MCEEVENTMSK1_PREAMBLE_DONE 0 ; ; -------------------------------------------------------------- ; MCEEVENTMSK2 ; -MCEEVENTMSK2 .assign 15 -MCEEVENTMSK2_MDMGPI1 .assign 15 ; -MCEEVENTMSK2_MDMGPI0 .assign 14 ; -MCEEVENTMSK2_SWQU_SYNCED_IRQ .assign 13 ; -MCEEVENTMSK2_C1BE_B_LOADED .assign 12 ; -MCEEVENTMSK2_C1BE_CMB_ANY_PEAK .assign 11 ; -MCEEVENTMSK2_C1BE_CMB_NEG_PEAK .assign 10 ; -MCEEVENTMSK2_C1BE_CMB_POS_PEAK .assign 9 ; -MCEEVENTMSK2_C1BE_C_ANY_PEAK .assign 8 ; -MCEEVENTMSK2_C1BE_C_NEG_PEAK .assign 7 ; -MCEEVENTMSK2_C1BE_C_POS_PEAK .assign 6 ; -MCEEVENTMSK2_C1BE_B_ANY_PEAK .assign 5 ; -MCEEVENTMSK2_C1BE_B_NEG_PEAK .assign 4 ; -MCEEVENTMSK2_C1BE_B_POS_PEAK .assign 3 ; -MCEEVENTMSK2_C1BE_A_ANY_PEAK .assign 2 ; -MCEEVENTMSK2_C1BE_A_NEG_PEAK .assign 1 ; -MCEEVENTMSK2_C1BE_A_POS_PEAK .assign 0 ; +%define MCEEVENTMSK2 15 +%define MCEEVENTMSK2_MDMGPI1 15 ; +%define MCEEVENTMSK2_MDMGPI0 14 ; +%define MCEEVENTMSK2_SWQU_SYNCED_IRQ 13 ; +%define MCEEVENTMSK2_C1BE_B_LOADED 12 ; +%define MCEEVENTMSK2_C1BE_CMB_ANY_PEAK 11 ; +%define MCEEVENTMSK2_C1BE_CMB_NEG_PEAK 10 ; +%define MCEEVENTMSK2_C1BE_CMB_POS_PEAK 9 ; +%define MCEEVENTMSK2_C1BE_C_ANY_PEAK 8 ; +%define MCEEVENTMSK2_C1BE_C_NEG_PEAK 7 ; +%define MCEEVENTMSK2_C1BE_C_POS_PEAK 6 ; +%define MCEEVENTMSK2_C1BE_B_ANY_PEAK 5 ; +%define MCEEVENTMSK2_C1BE_B_NEG_PEAK 4 ; +%define MCEEVENTMSK2_C1BE_B_POS_PEAK 3 ; +%define MCEEVENTMSK2_C1BE_A_ANY_PEAK 2 ; +%define MCEEVENTMSK2_C1BE_A_NEG_PEAK 1 ; +%define MCEEVENTMSK2_C1BE_A_POS_PEAK 0 ; ; -------------------------------------------------------------- ; MCEEVENTMSK3 ; -MCEEVENTMSK3 .assign 16 -MCEEVENTMSK3_SWQU_FALSE_SYNC_IRQ .assign 15 ; -MCEEVENTMSK3_C1BE_G_ANY_PEAK .assign 14 ; -MCEEVENTMSK3_C1BE_G_NEG_PEAK .assign 13 ; -MCEEVENTMSK3_C1BE_G_POS_PEAK .assign 12 ; -MCEEVENTMSK3_C1BE_CMB_DE_ANY_PEAK .assign 11 ; -MCEEVENTMSK3_C1BE_CMB_DE_NEG_PEAK .assign 10 ; -MCEEVENTMSK3_C1BE_CMB_DE_POS_PEAK .assign 9 ; -MCEEVENTMSK3_C1BE_F_ANY_PEAK .assign 8 ; -MCEEVENTMSK3_C1BE_F_NEG_PEAK .assign 7 ; -MCEEVENTMSK3_C1BE_F_POS_PEAK .assign 6 ; -MCEEVENTMSK3_C1BE_E_ANY_PEAK .assign 5 ; -MCEEVENTMSK3_C1BE_E_NEG_PEAK .assign 4 ; -MCEEVENTMSK3_C1BE_E_POS_PEAK .assign 3 ; -MCEEVENTMSK3_C1BE_D_ANY_PEAK .assign 2 ; -MCEEVENTMSK3_C1BE_D_NEG_PEAK .assign 1 ; -MCEEVENTMSK3_C1BE_D_POS_PEAK .assign 0 ; +%define MCEEVENTMSK3 16 +%define MCEEVENTMSK3_SWQU_FALSE_SYNC_IRQ 15 ; +%define MCEEVENTMSK3_C1BE_G_ANY_PEAK 14 ; +%define MCEEVENTMSK3_C1BE_G_NEG_PEAK 13 ; +%define MCEEVENTMSK3_C1BE_G_POS_PEAK 12 ; +%define MCEEVENTMSK3_C1BE_CMB_DE_ANY_PEAK 11 ; +%define MCEEVENTMSK3_C1BE_CMB_DE_NEG_PEAK 10 ; +%define MCEEVENTMSK3_C1BE_CMB_DE_POS_PEAK 9 ; +%define MCEEVENTMSK3_C1BE_F_ANY_PEAK 8 ; +%define MCEEVENTMSK3_C1BE_F_NEG_PEAK 7 ; +%define MCEEVENTMSK3_C1BE_F_POS_PEAK 6 ; +%define MCEEVENTMSK3_C1BE_E_ANY_PEAK 5 ; +%define MCEEVENTMSK3_C1BE_E_NEG_PEAK 4 ; +%define MCEEVENTMSK3_C1BE_E_POS_PEAK 3 ; +%define MCEEVENTMSK3_C1BE_D_ANY_PEAK 2 ; +%define MCEEVENTMSK3_C1BE_D_NEG_PEAK 1 ; +%define MCEEVENTMSK3_C1BE_D_POS_PEAK 0 ; ; -------------------------------------------------------------- ; MCEEVENTCLR0 ; -MCEEVENTCLR0 .assign 17 -MCEEVENTCLR0_CL_RX_IRQ .assign 15 ; -MCEEVENTCLR0_DL_RX_IRQ .assign 14 ; -MCEEVENTCLR0_CL_TX_DONE .assign 13 ; -MCEEVENTCLR0_DL_TX_DONE .assign 12 ; -MCEEVENTCLR0_FRAC_EN .assign 11 ; -MCEEVENTCLR0_BDEC_EN .assign 10 ; -MCEEVENTCLR0_CPEFWEVENT1 .assign 9 ; -MCEEVENTCLR0_CPEFWEVENT0 .assign 8 ; -MCEEVENTCLR0_MDMFIFO_WR .assign 7 ; -MCEEVENTCLR0_COUNTER_IRQ .assign 6 ; -MCEEVENTCLR0_RFECMD_IRQ .assign 5 ; -MCEEVENTCLR0_FIFO_ERR_OVERFLOW .assign 4 ; -MCEEVENTCLR0_FIFO_ERR_UNDERFLOW .assign 3 ; -MCEEVENTCLR0_CLKEN_4BAUD .assign 2 ; -MCEEVENTCLR0_TIMER_IRQ .assign 1 ; -MCEEVENTCLR0_MDMAPI_WR .assign 0 ; +%define MCEEVENTCLR0 17 +%define MCEEVENTCLR0_CL_RX_IRQ 15 ; +%define MCEEVENTCLR0_DL_RX_IRQ 14 ; +%define MCEEVENTCLR0_CL_TX_DONE 13 ; +%define MCEEVENTCLR0_DL_TX_DONE 12 ; +%define MCEEVENTCLR0_FRAC_EN 11 ; +%define MCEEVENTCLR0_BDEC_EN 10 ; +%define MCEEVENTCLR0_CPEFWEVENT1 9 ; +%define MCEEVENTCLR0_CPEFWEVENT0 8 ; +%define MCEEVENTCLR0_MDMFIFO_WR 7 ; +%define MCEEVENTCLR0_COUNTER_IRQ 6 ; +%define MCEEVENTCLR0_RFECMD_IRQ 5 ; +%define MCEEVENTCLR0_FIFO_ERR_OVERFLOW 4 ; +%define MCEEVENTCLR0_FIFO_ERR_UNDERFLOW 3 ; +%define MCEEVENTCLR0_CLKEN_4BAUD 2 ; +%define MCEEVENTCLR0_TIMER_IRQ 1 ; +%define MCEEVENTCLR0_MDMAPI_WR 0 ; ; -------------------------------------------------------------- ; MCEEVENTCLR1 ; -MCEEVENTCLR1 .assign 18 -MCEEVENTCLR1_RAT_EVENT7 .assign 15 ; -MCEEVENTCLR1_RAT_EVENT6 .assign 14 ; -MCEEVENTCLR1_RAT_EVENT5 .assign 13 ; -MCEEVENTCLR1_RAT_EVENT4 .assign 12 ; -MCEEVENTCLR1_RAT_EVENT3 .assign 11 ; -MCEEVENTCLR1_RAT_EVENT2 .assign 10 ; -MCEEVENTCLR1_RAT_EVENT1 .assign 9 ; -MCEEVENTCLR1_RAT_EVENT0 .assign 8 ; -MCEEVENTCLR1_CLKEN_BAUD_F .assign 7 ; -MCEEVENTCLR1_MDMCMDPAR1_WR .assign 6 ; -MCEEVENTCLR1_MDMCMDPAR0_WR .assign 5 ; -MCEEVENTCLR1_VITACC .assign 4 ; -MCEEVENTCLR1_FIFORD_VALID .assign 3 ; -MCEEVENTCLR1_FIFOWR_READY .assign 2 ; -MCEEVENTCLR1_CLKEN_BAUD .assign 1 ; -MCEEVENTCLR1_PREAMBLE_DONE .assign 0 ; +%define MCEEVENTCLR1 18 +%define MCEEVENTCLR1_RAT_EVENT7 15 ; +%define MCEEVENTCLR1_RAT_EVENT6 14 ; +%define MCEEVENTCLR1_RAT_EVENT5 13 ; +%define MCEEVENTCLR1_RAT_EVENT4 12 ; +%define MCEEVENTCLR1_RAT_EVENT3 11 ; +%define MCEEVENTCLR1_RAT_EVENT2 10 ; +%define MCEEVENTCLR1_RAT_EVENT1 9 ; +%define MCEEVENTCLR1_RAT_EVENT0 8 ; +%define MCEEVENTCLR1_CLKEN_BAUD_F 7 ; +%define MCEEVENTCLR1_MDMCMDPAR1_WR 6 ; +%define MCEEVENTCLR1_MDMCMDPAR0_WR 5 ; +%define MCEEVENTCLR1_VITACC 4 ; +%define MCEEVENTCLR1_FIFORD_VALID 3 ; +%define MCEEVENTCLR1_FIFOWR_READY 2 ; +%define MCEEVENTCLR1_CLKEN_BAUD 1 ; +%define MCEEVENTCLR1_PREAMBLE_DONE 0 ; ; -------------------------------------------------------------- ; MCEEVENTCLR2 ; -MCEEVENTCLR2 .assign 19 -MCEEVENTCLR2_MDMGPI1 .assign 15 ; -MCEEVENTCLR2_MDMGPI0 .assign 14 ; -MCEEVENTCLR2_SWQU_SYNCED_IRQ .assign 13 ; -MCEEVENTCLR2_C1BE_B_LOADED .assign 12 ; -MCEEVENTCLR2_C1BE_CMB_ANY_PEAK .assign 11 ; -MCEEVENTCLR2_C1BE_CMB_NEG_PEAK .assign 10 ; -MCEEVENTCLR2_C1BE_CMB_POS_PEAK .assign 9 ; -MCEEVENTCLR2_C1BE_C_ANY_PEAK .assign 8 ; -MCEEVENTCLR2_C1BE_C_NEG_PEAK .assign 7 ; -MCEEVENTCLR2_C1BE_C_POS_PEAK .assign 6 ; -MCEEVENTCLR2_C1BE_B_ANY_PEAK .assign 5 ; -MCEEVENTCLR2_C1BE_B_NEG_PEAK .assign 4 ; -MCEEVENTCLR2_C1BE_B_POS_PEAK .assign 3 ; -MCEEVENTCLR2_C1BE_A_ANY_PEAK .assign 2 ; -MCEEVENTCLR2_C1BE_A_NEG_PEAK .assign 1 ; -MCEEVENTCLR2_C1BE_A_POS_PEAK .assign 0 ; +%define MCEEVENTCLR2 19 +%define MCEEVENTCLR2_MDMGPI1 15 ; +%define MCEEVENTCLR2_MDMGPI0 14 ; +%define MCEEVENTCLR2_SWQU_SYNCED_IRQ 13 ; +%define MCEEVENTCLR2_C1BE_B_LOADED 12 ; +%define MCEEVENTCLR2_C1BE_CMB_ANY_PEAK 11 ; +%define MCEEVENTCLR2_C1BE_CMB_NEG_PEAK 10 ; +%define MCEEVENTCLR2_C1BE_CMB_POS_PEAK 9 ; +%define MCEEVENTCLR2_C1BE_C_ANY_PEAK 8 ; +%define MCEEVENTCLR2_C1BE_C_NEG_PEAK 7 ; +%define MCEEVENTCLR2_C1BE_C_POS_PEAK 6 ; +%define MCEEVENTCLR2_C1BE_B_ANY_PEAK 5 ; +%define MCEEVENTCLR2_C1BE_B_NEG_PEAK 4 ; +%define MCEEVENTCLR2_C1BE_B_POS_PEAK 3 ; +%define MCEEVENTCLR2_C1BE_A_ANY_PEAK 2 ; +%define MCEEVENTCLR2_C1BE_A_NEG_PEAK 1 ; +%define MCEEVENTCLR2_C1BE_A_POS_PEAK 0 ; ; -------------------------------------------------------------- ; MCEEVENTCLR3 ; -MCEEVENTCLR3 .assign 20 -MCEEVENTCLR3_SWQU_FALSE_SYNC_IRQ .assign 15 ; -MCEEVENTCLR3_C1BE_G_ANY_PEAK .assign 14 ; -MCEEVENTCLR3_C1BE_G_NEG_PEAK .assign 13 ; -MCEEVENTCLR3_C1BE_G_POS_PEAK .assign 12 ; -MCEEVENTCLR3_C1BE_CMB_DE_ANY_PEAK .assign 11 ; -MCEEVENTCLR3_C1BE_CMB_DE_NEG_PEAK .assign 10 ; -MCEEVENTCLR3_C1BE_CMB_DE_POS_PEAK .assign 9 ; -MCEEVENTCLR3_C1BE_F_ANY_PEAK .assign 8 ; -MCEEVENTCLR3_C1BE_F_NEG_PEAK .assign 7 ; -MCEEVENTCLR3_C1BE_F_POS_PEAK .assign 6 ; -MCEEVENTCLR3_C1BE_E_ANY_PEAK .assign 5 ; -MCEEVENTCLR3_C1BE_E_NEG_PEAK .assign 4 ; -MCEEVENTCLR3_C1BE_E_POS_PEAK .assign 3 ; -MCEEVENTCLR3_C1BE_D_ANY_PEAK .assign 2 ; -MCEEVENTCLR3_C1BE_D_NEG_PEAK .assign 1 ; -MCEEVENTCLR3_C1BE_D_POS_PEAK .assign 0 ; +%define MCEEVENTCLR3 20 +%define MCEEVENTCLR3_SWQU_FALSE_SYNC_IRQ 15 ; +%define MCEEVENTCLR3_C1BE_G_ANY_PEAK 14 ; +%define MCEEVENTCLR3_C1BE_G_NEG_PEAK 13 ; +%define MCEEVENTCLR3_C1BE_G_POS_PEAK 12 ; +%define MCEEVENTCLR3_C1BE_CMB_DE_ANY_PEAK 11 ; +%define MCEEVENTCLR3_C1BE_CMB_DE_NEG_PEAK 10 ; +%define MCEEVENTCLR3_C1BE_CMB_DE_POS_PEAK 9 ; +%define MCEEVENTCLR3_C1BE_F_ANY_PEAK 8 ; +%define MCEEVENTCLR3_C1BE_F_NEG_PEAK 7 ; +%define MCEEVENTCLR3_C1BE_F_POS_PEAK 6 ; +%define MCEEVENTCLR3_C1BE_E_ANY_PEAK 5 ; +%define MCEEVENTCLR3_C1BE_E_NEG_PEAK 4 ; +%define MCEEVENTCLR3_C1BE_E_POS_PEAK 3 ; +%define MCEEVENTCLR3_C1BE_D_ANY_PEAK 2 ; +%define MCEEVENTCLR3_C1BE_D_NEG_PEAK 1 ; +%define MCEEVENTCLR3_C1BE_D_POS_PEAK 0 ; ; -------------------------------------------------------------- ; MCEPROGRAMSRC ; -MCEPROGRAMSRC .assign 21 -MCEPROGRAMSRC_ROMBANK .assign 1 ; -MCEPROGRAMSRC_RAMROM .assign 0 ; +%define MCEPROGRAMSRC 21 +%define MCEPROGRAMSRC_ROMBANK 1 ; +%define MCEPROGRAMSRC_RAMROM 0 ; ; -------------------------------------------------------------- ; MDMAPI ; -MDMAPI .assign 22 -MDMAPI_PROTOCOLID .assign 8 ; -MDMAPI_MDMCMD .assign 0 ; +%define MDMAPI 22 +%define MDMAPI_PROTOCOLID 8 ; +%define MDMAPI_MDMCMD 0 ; ; -------------------------------------------------------------- ; MDMCMDPAR0 ; -MDMCMDPAR0 .assign 23 -MDMCMDPAR0_PAR0 .assign 0 ; +%define MDMCMDPAR0 23 +%define MDMCMDPAR0_PAR0 0 ; ; -------------------------------------------------------------- ; MDMCMDPAR1 ; -MDMCMDPAR1 .assign 24 -MDMCMDPAR1_PAR1 .assign 0 ; +%define MDMCMDPAR1 24 +%define MDMCMDPAR1_PAR1 0 ; ; -------------------------------------------------------------- ; MDMCMDPAR2 ; -MDMCMDPAR2 .assign 25 -MDMCMDPAR2_PAR .assign 0 ; +%define MDMCMDPAR2 25 +%define MDMCMDPAR2_PAR 0 ; ; -------------------------------------------------------------- ; MDMRFCHANNEL ; -MDMRFCHANNEL .assign 26 -MDMRFCHANNEL_VALUE .assign 0 ; +%define MDMRFCHANNEL 26 +%define MDMRFCHANNEL_VALUE 0 ; ; -------------------------------------------------------------- ; MDMSTATUS ; -MDMSTATUS .assign 27 -MDMSTATUS_VALUE .assign 0 ; +%define MDMSTATUS 27 +%define MDMSTATUS_VALUE 0 ; ; -------------------------------------------------------------- ; MDMFIFOWR ; -MDMFIFOWR .assign 28 -MDMFIFOWR_PAYLOADIN .assign 0 ; +%define MDMFIFOWR 28 +%define MDMFIFOWR_PAYLOADIN 0 ; ; -------------------------------------------------------------- ; MDMFIFORD ; -MDMFIFORD .assign 29 -MDMFIFORD_PAYLOADOUT .assign 0 ; +%define MDMFIFORD 29 +%define MDMFIFORD_PAYLOADOUT 0 ; ; -------------------------------------------------------------- ; MDMFIFOWRCTRL ; -MDMFIFOWRCTRL .assign 30 -MDMFIFOWRCTRL_FIFOWRPORT .assign 4 ; -MDMFIFOWRCTRL_WORDSZWR .assign 0 ; +%define MDMFIFOWRCTRL 30 +%define MDMFIFOWRCTRL_FIFOWRPORT 4 ; +%define MDMFIFOWRCTRL_WORDSZWR 0 ; ; -------------------------------------------------------------- ; MDMFIFORDCTRL ; -MDMFIFORDCTRL .assign 31 -MDMFIFORDCTRL_FIFORDPORT .assign 4 ; -MDMFIFORDCTRL_WORDSZRD .assign 0 ; +%define MDMFIFORDCTRL 31 +%define MDMFIFORDCTRL_FIFORDPORT 4 ; +%define MDMFIFORDCTRL_WORDSZRD 0 ; ; -------------------------------------------------------------- ; MDMFIFOCFG ; -MDMFIFOCFG .assign 32 -MDMFIFOCFG_AFULLTHR .assign 8 ; -MDMFIFOCFG_AEMPTYTHR .assign 0 ; +%define MDMFIFOCFG 32 +%define MDMFIFOCFG_AFULLTHR 8 ; +%define MDMFIFOCFG_AEMPTYTHR 0 ; ; -------------------------------------------------------------- ; MDMFIFOSTA ; -MDMFIFOSTA .assign 33 -MDMFIFOSTA_OVERFLOW .assign 5 ; -MDMFIFOSTA_ALMOSTFULL .assign 4 ; -MDMFIFOSTA_ALMOSTEMPTY .assign 3 ; -MDMFIFOSTA_UNDERFLOW .assign 2 ; -MDMFIFOSTA_RXVALID .assign 1 ; -MDMFIFOSTA_TXREADY .assign 0 ; +%define MDMFIFOSTA 33 +%define MDMFIFOSTA_OVERFLOW 5 ; +%define MDMFIFOSTA_ALMOSTFULL 4 ; +%define MDMFIFOSTA_ALMOSTEMPTY 3 ; +%define MDMFIFOSTA_UNDERFLOW 2 ; +%define MDMFIFOSTA_RXVALID 1 ; +%define MDMFIFOSTA_TXREADY 0 ; ; -------------------------------------------------------------- ; CPEFWEVENT ; -CPEFWEVENT .assign 34 -CPEFWEVENT_EVENT3 .assign 3 ; -CPEFWEVENT_EVENT2 .assign 2 ; -CPEFWEVENT_EVENT1 .assign 1 ; -CPEFWEVENT_EVENT0 .assign 0 ; +%define CPEFWEVENT 34 +%define CPEFWEVENT_EVENT3 3 ; +%define CPEFWEVENT_EVENT2 2 ; +%define CPEFWEVENT_EVENT1 1 ; +%define CPEFWEVENT_EVENT0 0 ; ; -------------------------------------------------------------- ; RFESEND ; -RFESEND .assign 35 -RFESEND_MCECMD .assign 0 ; +%define RFESEND 35 +%define RFESEND_MCECMD 0 ; ; -------------------------------------------------------------- ; RFERCEV ; -RFERCEV .assign 36 -RFERCEV_RFECMD .assign 0 ; +%define RFERCEV 36 +%define RFERCEV_RFECMD 0 ; ; -------------------------------------------------------------- ; SMICONF ; -SMICONF .assign 37 -SMICONF_SMIENABLE .assign 8 ; -SMICONF_PRESCALER .assign 4 ; -SMICONF_MLENGTH .assign 0 ; +%define SMICONF 37 +%define SMICONF_SMIENABLE 8 ; +%define SMICONF_PRESCALER 4 ; +%define SMICONF_MLENGTH 0 ; ; -------------------------------------------------------------- ; SMIDLOUTG ; -SMIDLOUTG .assign 38 -SMIDLOUTG_DL .assign 0 ; +%define SMIDLOUTG 38 +%define SMIDLOUTG_DL 0 ; ; -------------------------------------------------------------- ; SMICLOUTG ; -SMICLOUTG .assign 39 -SMICLOUTG_CL .assign 0 ; +%define SMICLOUTG 39 +%define SMICLOUTG_CL 0 ; ; -------------------------------------------------------------- ; SMIDLINC ; -SMIDLINC .assign 40 -SMIDLINC_DL .assign 0 ; +%define SMIDLINC 40 +%define SMIDLINC_DL 0 ; ; -------------------------------------------------------------- ; SMICLINC ; -SMICLINC .assign 41 -SMICLINC_CL .assign 0 ; +%define SMICLINC 41 +%define SMICLINC_CL 0 ; ; -------------------------------------------------------------- ; SMISTA ; -SMISTA .assign 42 -SMISTA_INCCLERROR .assign 1 ; -SMISTA_INCDLERROR .assign 0 ; +%define SMISTA 42 +%define SMISTA_INCCLERROR 1 ; +%define SMISTA_INCDLERROR 0 ; ; -------------------------------------------------------------- ; ADCDIGCONF ; -ADCDIGCONF .assign 43 -ADCDIGCONF_QBRANCHEN .assign 1 ; -ADCDIGCONF_IBRANCHEN .assign 0 ; +%define ADCDIGCONF 43 +%define ADCDIGCONF_QBRANCHEN 1 ; +%define ADCDIGCONF_IBRANCHEN 0 ; ; -------------------------------------------------------------- ; MODPRECTRL ; -MODPRECTRL .assign 44 -MODPRECTRL_REPS .assign 4 ; -MODPRECTRL_SIZE .assign 0 ; +%define MODPRECTRL 44 +%define MODPRECTRL_REPS 4 ; +%define MODPRECTRL_SIZE 0 ; ; -------------------------------------------------------------- ; MODSYMMAP0 ; -MODSYMMAP0 .assign 45 -MODSYMMAP0_SYM3 .assign 12 ; -MODSYMMAP0_SYM2 .assign 8 ; -MODSYMMAP0_SYM1 .assign 4 ; -MODSYMMAP0_SYM0 .assign 0 ; +%define MODSYMMAP0 45 +%define MODSYMMAP0_SYM3 12 ; +%define MODSYMMAP0_SYM2 8 ; +%define MODSYMMAP0_SYM1 4 ; +%define MODSYMMAP0_SYM0 0 ; ; -------------------------------------------------------------- ; MODSYMMAP1 ; -MODSYMMAP1 .assign 46 -MODSYMMAP1_SYM7 .assign 12 ; -MODSYMMAP1_SYM6 .assign 8 ; -MODSYMMAP1_SYM5 .assign 4 ; -MODSYMMAP1_SYM4 .assign 0 ; +%define MODSYMMAP1 46 +%define MODSYMMAP1_SYM7 12 ; +%define MODSYMMAP1_SYM6 8 ; +%define MODSYMMAP1_SYM5 4 ; +%define MODSYMMAP1_SYM4 0 ; ; -------------------------------------------------------------- ; MODSOFTTX ; -MODSOFTTX .assign 47 -MODSOFTTX_SOFTSYMBOL .assign 0 ; +%define MODSOFTTX 47 +%define MODSOFTTX_SOFTSYMBOL 0 ; ; -------------------------------------------------------------- ; MDMBAUD ; -MDMBAUD .assign 48 -MDMBAUD_RATEWORD .assign 0 ; +%define MDMBAUD 48 +%define MDMBAUD_RATEWORD 0 ; ; -------------------------------------------------------------- ; MDMBAUDPRE ; -MDMBAUDPRE .assign 49 -MDMBAUDPRE_ALIGNVALUE .assign 13 ; -MDMBAUDPRE_EXTRATEWORD .assign 8 ; -MDMBAUDPRE_PRESCALER .assign 0 ; +%define MDMBAUDPRE 49 +%define MDMBAUDPRE_ALIGNVALUE 13 ; +%define MDMBAUDPRE_EXTRATEWORD 8 ; +%define MDMBAUDPRE_PRESCALER 0 ; ; -------------------------------------------------------------- ; MODMAIN ; -MODMAIN .assign 50 -MODMAIN_SPREADFACTOR .assign 6 ; -MODMAIN_FECSELECT .assign 2 ; -MODMAIN_MODLEVELS .assign 0 ; +%define MODMAIN 50 +%define MODMAIN_SPREADFACTOR 6 ; +%define MODMAIN_FECSELECT 2 ; +%define MODMAIN_MODLEVELS 0 ; ; -------------------------------------------------------------- ; DEMMISC0 ; -DEMMISC0 .assign 51 -DEMMISC0_CMI4FMIXSIGN .assign 12 ; -DEMMISC0_HILBREMOVEREAL .assign 11 ; -DEMMISC0_HILBEN .assign 10 ; -DEMMISC0_CMIXN .assign 0 ; +%define DEMMISC0 51 +%define DEMMISC0_CMI4FMIXSIGN 12 ; +%define DEMMISC0_HILBREMOVEREAL 11 ; +%define DEMMISC0_HILBEN 10 ; +%define DEMMISC0_CMIXN 0 ; ; -------------------------------------------------------------- ; DEMMISC1 ; -DEMMISC1 .assign 52 -DEMMISC1_MGE2SRCSEL .assign 2 ; -DEMMISC1_CHFIBW .assign 0 ; +%define DEMMISC1 52 +%define DEMMISC1_MGE2SRCSEL 2 ; +%define DEMMISC1_CHFIBW 0 ; ; -------------------------------------------------------------- ; DEMMISC2 ; -DEMMISC2 .assign 53 -DEMMISC2_LQIPERIOD .assign 14 ; -DEMMISC2_MLSERUN .assign 13 ; -DEMMISC2_MAFCGAIN .assign 11 ; -DEMMISC2_STIMESTONLY .assign 10 ; -DEMMISC2_STIMTEAPERIOD .assign 7 ; -DEMMISC2_STIMTEAGAIN .assign 4 ; -DEMMISC2_PDIFLINPREDEN .assign 3 ; -DEMMISC2_PDIFDESPECKLEREN .assign 2 ; -DEMMISC2_PDIFIQCONJEN .assign 1 ; -DEMMISC2_PDIFLIMITRANGE .assign 0 ; +%define DEMMISC2 53 +%define DEMMISC2_LQIPERIOD 14 ; +%define DEMMISC2_MLSERUN 13 ; +%define DEMMISC2_MAFCGAIN 11 ; +%define DEMMISC2_STIMESTONLY 10 ; +%define DEMMISC2_STIMTEAPERIOD 7 ; +%define DEMMISC2_STIMTEAGAIN 4 ; +%define DEMMISC2_PDIFLINPREDEN 3 ; +%define DEMMISC2_PDIFDESPECKLEREN 2 ; +%define DEMMISC2_PDIFIQCONJEN 1 ; +%define DEMMISC2_PDIFLIMITRANGE 0 ; ; -------------------------------------------------------------- ; DEMMISC3 ; -DEMMISC3 .assign 54 -DEMMISC3_BDE1DVGA .assign 10 ; -DEMMISC3_BDE2DVGA .assign 8 ; -DEMMISC3_BDE1NUMSTAGES .assign 5 ; -DEMMISC3_PDIFDECIM .assign 3 ; -DEMMISC3_BDECNUMSTAGES .assign 0 ; +%define DEMMISC3 54 +%define DEMMISC3_BDE1DVGA 10 ; +%define DEMMISC3_BDE2DVGA 8 ; +%define DEMMISC3_BDE1NUMSTAGES 5 ; +%define DEMMISC3_PDIFDECIM 3 ; +%define DEMMISC3_BDECNUMSTAGES 0 ; ; -------------------------------------------------------------- ; DEMIQMC0 ; -DEMIQMC0 .assign 55 -DEMIQMC0_GAINFACTOR .assign 8 ; -DEMIQMC0_PHASEFACTOR .assign 0 ; +%define DEMIQMC0 55 +%define DEMIQMC0_GAINFACTOR 8 ; +%define DEMIQMC0_PHASEFACTOR 0 ; ; -------------------------------------------------------------- ; DEMDSBU ; -DEMDSBU .assign 56 -DEMDSBU_DSBUDELAY .assign 0 ; +%define DEMDSBU 56 +%define DEMDSBU_DSBUDELAY 0 ; ; -------------------------------------------------------------- ; DEMDSBU2 ; -DEMDSBU2 .assign 57 -DEMDSBU2_DSBUAVGLENGTH .assign 0 ; +%define DEMDSBU2 57 +%define DEMDSBU2_DSBUAVGLENGTH 0 ; ; -------------------------------------------------------------- ; DEMCODC0 ; -DEMCODC0 .assign 58 -DEMCODC0_ESTSEL .assign 11 ; -DEMCODC0_COMPSEL .assign 9 ; -DEMCODC0_IIRUSEINITIAL .assign 8 ; -DEMCODC0_IIRGAIN .assign 5 ; -DEMCODC0_IIREN .assign 4 ; -DEMCODC0_ACCCONTMODE .assign 3 ; -DEMCODC0_ACCPERIOD .assign 1 ; -DEMCODC0_ACCEN .assign 0 ; +%define DEMCODC0 58 +%define DEMCODC0_ESTSEL 11 ; +%define DEMCODC0_COMPSEL 9 ; +%define DEMCODC0_IIRUSEINITIAL 8 ; +%define DEMCODC0_IIRGAIN 5 ; +%define DEMCODC0_IIREN 4 ; +%define DEMCODC0_ACCCONTMODE 3 ; +%define DEMCODC0_ACCPERIOD 1 ; +%define DEMCODC0_ACCEN 0 ; ; -------------------------------------------------------------- ; DEMFIDC0 ; -DEMFIDC0 .assign 59 -DEMFIDC0_COMPSEL .assign 4 ; -DEMFIDC0_ACCPERIOD .assign 2 ; -DEMFIDC0_ACCCONTMODE .assign 1 ; -DEMFIDC0_ACCEN .assign 0 ; +%define DEMFIDC0 59 +%define DEMFIDC0_COMPSEL 4 ; +%define DEMFIDC0_ACCPERIOD 2 ; +%define DEMFIDC0_ACCCONTMODE 1 ; +%define DEMFIDC0_ACCEN 0 ; ; -------------------------------------------------------------- ; DEMFEXB0 ; -DEMFEXB0 .assign 60 -DEMFEXB0_OUT2PASSTHROUGH .assign 13 ; -DEMFEXB0_OUT2SRCSEL .assign 11 ; -DEMFEXB0_OUT1PASSTHROUGH .assign 10 ; -DEMFEXB0_OUT1SRCSEL .assign 8 ; -DEMFEXB0_B4SRCSEL .assign 6 ; -DEMFEXB0_B3SRCSEL .assign 4 ; -DEMFEXB0_B2SRCSEL .assign 2 ; -DEMFEXB0_B1SRCSEL .assign 0 ; +%define DEMFEXB0 60 +%define DEMFEXB0_OUT2PASSTHROUGH 13 ; +%define DEMFEXB0_OUT2SRCSEL 11 ; +%define DEMFEXB0_OUT1PASSTHROUGH 10 ; +%define DEMFEXB0_OUT1SRCSEL 8 ; +%define DEMFEXB0_B4SRCSEL 6 ; +%define DEMFEXB0_B3SRCSEL 4 ; +%define DEMFEXB0_B2SRCSEL 2 ; +%define DEMFEXB0_B1SRCSEL 0 ; ; -------------------------------------------------------------- ; DEMDSXB0 ; -DEMDSXB0 .assign 61 -DEMDSXB0_OUT2PASSTHROUGH .assign 13 ; -DEMDSXB0_OUT1PASSTHROUGH .assign 12 ; -DEMDSXB0_OUTSRCSEL2 .assign 10 ; -DEMDSXB0_OUTSRCSEL1 .assign 8 ; -DEMDSXB0_B4SRCSEL .assign 6 ; -DEMDSXB0_B3SRCSEL .assign 4 ; -DEMDSXB0_B2SRCSEL .assign 2 ; -DEMDSXB0_B1SRCSEL .assign 0 ; +%define DEMDSXB0 61 +%define DEMDSXB0_OUT2PASSTHROUGH 13 ; +%define DEMDSXB0_OUT1PASSTHROUGH 12 ; +%define DEMDSXB0_OUTSRCSEL2 10 ; +%define DEMDSXB0_OUTSRCSEL1 8 ; +%define DEMDSXB0_B4SRCSEL 6 ; +%define DEMDSXB0_B3SRCSEL 4 ; +%define DEMDSXB0_B2SRCSEL 2 ; +%define DEMDSXB0_B1SRCSEL 0 ; ; -------------------------------------------------------------- ; DEMD2XB0 ; -DEMD2XB0 .assign 62 -DEMD2XB0_B3SRCSEL .assign 10 ; -DEMD2XB0_OUT2PASSTHROUGH .assign 9 ; -DEMD2XB0_OUT1PASSTHROUGH .assign 8 ; -DEMD2XB0_OUTSRCSEL2 .assign 6 ; -DEMD2XB0_OUTSRCSEL1 .assign 4 ; -DEMD2XB0_B2SRCSEL .assign 2 ; -DEMD2XB0_B1SRCSEL .assign 0 ; +%define DEMD2XB0 62 +%define DEMD2XB0_B3SRCSEL 10 ; +%define DEMD2XB0_OUT2PASSTHROUGH 9 ; +%define DEMD2XB0_OUT1PASSTHROUGH 8 ; +%define DEMD2XB0_OUTSRCSEL2 6 ; +%define DEMD2XB0_OUTSRCSEL1 4 ; +%define DEMD2XB0_B2SRCSEL 2 ; +%define DEMD2XB0_B1SRCSEL 0 ; ; -------------------------------------------------------------- ; DEMFIFE0 ; -DEMFIFE0 .assign 63 -DEMFIFE0_FINEFOESEL .assign 11 ; -DEMFIFE0_FOCFFSEL .assign 9 ; -DEMFIFE0_ACCCNTMODE .assign 8 ; -DEMFIFE0_ACCPERIOD .assign 6 ; -DEMFIFE0_ACCEN .assign 5 ; -DEMFIFE0_IIRUSEINITIAL .assign 4 ; -DEMFIFE0_IIRGAIN .assign 1 ; -DEMFIFE0_IIREN .assign 0 ; +%define DEMFIFE0 63 +%define DEMFIFE0_FINEFOESEL 11 ; +%define DEMFIFE0_FOCFFSEL 9 ; +%define DEMFIFE0_ACCCNTMODE 8 ; +%define DEMFIFE0_ACCPERIOD 6 ; +%define DEMFIFE0_ACCEN 5 ; +%define DEMFIFE0_IIRUSEINITIAL 4 ; +%define DEMFIFE0_IIRGAIN 1 ; +%define DEMFIFE0_IIREN 0 ; ; -------------------------------------------------------------- ; DEMMAFI0 ; -DEMMAFI0 .assign 64 -DEMMAFI0_C1C7 .assign 8 ; -DEMMAFI0_C0C8 .assign 0 ; +%define DEMMAFI0 64 +%define DEMMAFI0_C1C7 8 ; +%define DEMMAFI0_C0C8 0 ; ; -------------------------------------------------------------- ; DEMMAFI1 ; -DEMMAFI1 .assign 65 -DEMMAFI1_C3C5 .assign 8 ; -DEMMAFI1_C2C6 .assign 0 ; +%define DEMMAFI1 65 +%define DEMMAFI1_C3C5 8 ; +%define DEMMAFI1_C2C6 0 ; ; -------------------------------------------------------------- ; DEMMAFI2 ; -DEMMAFI2 .assign 66 -DEMMAFI2_C4 .assign 0 ; +%define DEMMAFI2 66 +%define DEMMAFI2_C4 0 ; ; -------------------------------------------------------------- ; DEMMAFI3 ; -DEMMAFI3 .assign 67 -DEMMAFI3_K .assign 0 ; +%define DEMMAFI3 67 +%define DEMMAFI3_K 0 ; ; -------------------------------------------------------------- ; DEMC1BE0 ; -DEMC1BE0 .assign 68 -DEMC1BE0_MASKB .assign 11 ; -DEMC1BE0_MASKA .assign 6 ; -DEMC1BE0_CASCCONF .assign 4 ; -DEMC1BE0_COPYCONF .assign 0 ; +%define DEMC1BE0 68 +%define DEMC1BE0_MASKB 11 ; +%define DEMC1BE0_MASKA 6 ; +%define DEMC1BE0_CASCCONF 4 ; +%define DEMC1BE0_COPYCONF 0 ; ; -------------------------------------------------------------- ; DEMC1BE1 ; -DEMC1BE1 .assign 69 -DEMC1BE1_THRESHOLDB .assign 8 ; -DEMC1BE1_THRESHOLDA .assign 0 ; +%define DEMC1BE1 69 +%define DEMC1BE1_THRESHOLDB 8 ; +%define DEMC1BE1_THRESHOLDA 0 ; ; -------------------------------------------------------------- ; DEMC1BE2 ; -DEMC1BE2 .assign 70 -DEMC1BE2_PEAKCONF .assign 8 ; -DEMC1BE2_THRESHOLDC .assign 0 ; +%define DEMC1BE2 70 +%define DEMC1BE2_PEAKCONF 8 ; +%define DEMC1BE2_THRESHOLDC 0 ; ; -------------------------------------------------------------- ; DEMC1BE10 ; -DEMC1BE10 .assign 71 -DEMC1BE10_PEAKCONF_G .assign 15 ; -DEMC1BE10_PEAKCONF_CF .assign 13 ; -DEMC1BE10_MASKE .assign 8 ; -DEMC1BE10_MASKD .assign 3 ; -DEMC1BE10_CASCCONF .assign 0 ; +%define DEMC1BE10 71 +%define DEMC1BE10_PEAKCONF_G 15 ; +%define DEMC1BE10_PEAKCONF_CF 13 ; +%define DEMC1BE10_MASKE 8 ; +%define DEMC1BE10_MASKD 3 ; +%define DEMC1BE10_CASCCONF 0 ; ; -------------------------------------------------------------- ; DEMC1BE11 ; -DEMC1BE11 .assign 72 -DEMC1BE11_THRESHOLDE .assign 8 ; -DEMC1BE11_THRESHOLDD .assign 0 ; +%define DEMC1BE11 72 +%define DEMC1BE11_THRESHOLDE 8 ; +%define DEMC1BE11_THRESHOLDD 0 ; ; -------------------------------------------------------------- ; DEMC1BE12 ; -DEMC1BE12 .assign 73 -DEMC1BE12_THRESHOLDG .assign 8 ; -DEMC1BE12_THRESHOLDF .assign 0 ; +%define DEMC1BE12 73 +%define DEMC1BE12_THRESHOLDG 8 ; +%define DEMC1BE12_THRESHOLDF 0 ; ; -------------------------------------------------------------- ; MDMSYNC0 ; -MDMSYNC0 .assign 74 -MDMSYNC0_SWA15C0 .assign 0 ; +%define MDMSYNC0 74 +%define MDMSYNC0_SWA15C0 0 ; ; -------------------------------------------------------------- ; MDMSYNC1 ; -MDMSYNC1 .assign 75 -MDMSYNC1_SWA31C16 .assign 0 ; +%define MDMSYNC1 75 +%define MDMSYNC1_SWA31C16 0 ; ; -------------------------------------------------------------- ; MDMSYNC2 ; -MDMSYNC2 .assign 76 -MDMSYNC2_SWB15C0 .assign 0 ; +%define MDMSYNC2 76 +%define MDMSYNC2_SWB15C0 0 ; ; -------------------------------------------------------------- ; MDMSYNC3 ; -MDMSYNC3 .assign 77 -MDMSYNC3_SWB31C16 .assign 0 ; +%define MDMSYNC3 77 +%define MDMSYNC3_SWB31C16 0 ; ; -------------------------------------------------------------- ; DEMSWQU0 ; -DEMSWQU0 .assign 78 -DEMSWQU0_SYNC_MODE .assign 7 ; -DEMSWQU0_AUTOMAFC .assign 6 ; -DEMSWQU0_RUN .assign 5 ; -DEMSWQU0_REFLEN .assign 0 ; +%define DEMSWQU0 78 +%define DEMSWQU0_SYNC_MODE 7 ; +%define DEMSWQU0_AUTOMAFC 6 ; +%define DEMSWQU0_RUN 5 ; +%define DEMSWQU0_REFLEN 0 ; ; -------------------------------------------------------------- ; DEMFB2P0 ; -DEMFB2P0 .assign 79 -DEMFB2P0_BETA .assign 8 ; -DEMFB2P0_ALPHA .assign 0 ; +%define DEMFB2P0 79 +%define DEMFB2P0_BETA 8 ; +%define DEMFB2P0_ALPHA 0 ; ; -------------------------------------------------------------- ; DEMFB2P1 ; -DEMFB2P1 .assign 80 -DEMFB2P1_FB2P_OPEN .assign 14 ; -DEMFB2P1_HDIS_PRS .assign 12 ; -DEMFB2P1_IIR_GAIN .assign 10 ; -DEMFB2P1_IIR_BW .assign 7 ; -DEMFB2P1_FB2PLL_LIMIT .assign 0 ; +%define DEMFB2P1 80 +%define DEMFB2P1_FB2P_OPEN 14 ; +%define DEMFB2P1_HDIS_PRS 12 ; +%define DEMFB2P1_IIR_GAIN 10 ; +%define DEMFB2P1_IIR_BW 7 ; +%define DEMFB2P1_FB2PLL_LIMIT 0 ; ; -------------------------------------------------------------- ; DEMPHAC0 ; -DEMPHAC0 .assign 81 -DEMPHAC0_REF_B .assign 8 ; -DEMPHAC0_REF_A .assign 0 ; +%define DEMPHAC0 81 +%define DEMPHAC0_REF_B 8 ; +%define DEMPHAC0_REF_A 0 ; ; -------------------------------------------------------------- ; DEMPHAC1 ; -DEMPHAC1 .assign 82 -DEMPHAC1_PHAC_TR_LEN .assign 10 ; -DEMPHAC1_PHAC_SYM_LEN .assign 7 ; -DEMPHAC1_PHASE_INCR .assign 0 ; +%define DEMPHAC1 82 +%define DEMPHAC1_PHAC_TR_LEN 10 ; +%define DEMPHAC1_PHAC_SYM_LEN 7 ; +%define DEMPHAC1_PHASE_INCR 0 ; ; -------------------------------------------------------------- ; DEMPHAC2 ; -DEMPHAC2 .assign 83 -DEMPHAC2_ALPHA .assign 8 ; -DEMPHAC2_BETA .assign 0 ; +%define DEMPHAC2 83 +%define DEMPHAC2_ALPHA 8 ; +%define DEMPHAC2_BETA 0 ; ; -------------------------------------------------------------- ; DEMPHAC3 ; -DEMPHAC3 .assign 84 -DEMPHAC3_IIR_BW .assign 0 ; +%define DEMPHAC3 84 +%define DEMPHAC3_IIR_BW 0 ; ; -------------------------------------------------------------- ; DEMPHAC4 ; -DEMPHAC4 .assign 85 -DEMPHAC4_TR_15_0 .assign 0 ; +%define DEMPHAC4 85 +%define DEMPHAC4_TR_15_0 0 ; ; -------------------------------------------------------------- ; DEMPHAC5 ; -DEMPHAC5 .assign 86 -DEMPHAC5_TR_31_16 .assign 0 ; +%define DEMPHAC5 86 +%define DEMPHAC5_TR_31_16 0 ; ; -------------------------------------------------------------- ; DEMPHAC6 ; -DEMPHAC6 .assign 87 -DEMPHAC6_TR_47_32 .assign 0 ; +%define DEMPHAC6 87 +%define DEMPHAC6_TR_47_32 0 ; ; -------------------------------------------------------------- ; DEMPHAC7 ; -DEMPHAC7 .assign 88 -DEMPHAC7_TR_63_48 .assign 0 ; +%define DEMPHAC7 88 +%define DEMPHAC7_TR_63_48 0 ; ; -------------------------------------------------------------- ; DEMC1BEREF0 ; -DEMC1BEREF0 .assign 89 -DEMC1BEREF0_CAR15C0 .assign 0 ; +%define DEMC1BEREF0 89 +%define DEMC1BEREF0_CAR15C0 0 ; ; -------------------------------------------------------------- ; DEMC1BEREF1 ; -DEMC1BEREF1 .assign 90 -DEMC1BEREF1_CAR31C16 .assign 0 ; +%define DEMC1BEREF1 90 +%define DEMC1BEREF1_CAR31C16 0 ; ; -------------------------------------------------------------- ; DEMC1BEREF2 ; -DEMC1BEREF2 .assign 91 -DEMC1BEREF2_CBR15C0 .assign 0 ; +%define DEMC1BEREF2 91 +%define DEMC1BEREF2_CBR15C0 0 ; ; -------------------------------------------------------------- ; DEMC1BEREF3 ; -DEMC1BEREF3 .assign 92 -DEMC1BEREF3_CBR31C16 .assign 0 ; +%define DEMC1BEREF3 92 +%define DEMC1BEREF3_CBR31C16 0 ; ; -------------------------------------------------------------- ; DEMC1BEREF4 ; -DEMC1BEREF4 .assign 93 -DEMC1BEREF4_CDR15C0 .assign 0 ; +%define DEMC1BEREF4 93 +%define DEMC1BEREF4_CDR15C0 0 ; ; -------------------------------------------------------------- ; DEMC1BEREF5 ; -DEMC1BEREF5 .assign 94 -DEMC1BEREF5_CDR31C16 .assign 0 ; +%define DEMC1BEREF5 94 +%define DEMC1BEREF5_CDR31C16 0 ; ; -------------------------------------------------------------- ; DEMC1BEREF6 ; -DEMC1BEREF6 .assign 95 -DEMC1BEREF6_CER15C0 .assign 0 ; +%define DEMC1BEREF6 95 +%define DEMC1BEREF6_CER15C0 0 ; ; -------------------------------------------------------------- ; DEMC1BEREF7 ; -DEMC1BEREF7 .assign 96 -DEMC1BEREF7_CER31C16 .assign 0 ; +%define DEMC1BEREF7 96 +%define DEMC1BEREF7_CER31C16 0 ; ; -------------------------------------------------------------- ; DEMMLSE4MAP ; -DEMMLSE4MAP .assign 97 -DEMMLSE4MAP_MAP_P3 .assign 6 ; -DEMMLSE4MAP_MAP_P1 .assign 4 ; -DEMMLSE4MAP_MAP_M1 .assign 2 ; -DEMMLSE4MAP_MAP_M3 .assign 0 ; +%define DEMMLSE4MAP 97 +%define DEMMLSE4MAP_MAP_P3 6 ; +%define DEMMLSE4MAP_MAP_P1 4 ; +%define DEMMLSE4MAP_MAP_M1 2 ; +%define DEMMLSE4MAP_MAP_M3 0 ; ; -------------------------------------------------------------- ; DEMC1BE13 ; -DEMC1BE13 .assign 98 -DEMC1BE13_CORRVALUED .assign 0 ; +%define DEMC1BE13 98 +%define DEMC1BE13_CORRVALUED 0 ; ; -------------------------------------------------------------- ; MODCTRL ; -MODCTRL .assign 99 -MODCTRL_CDC_COL_RESTART .assign 12 ; -MODCTRL_DSBUSEL .assign 11 ; -MODCTRL_HDISMODE .assign 10 ; -MODCTRL_PARBITQUALEN .assign 9 ; -MODCTRL_STIMEARLYLATE .assign 7 ; -MODCTRL_EARLYLATE .assign 6 ; -MODCTRL_SOFTPDIFFMODE .assign 5 ; -MODCTRL_SOFTTXENABLE .assign 4 ; -MODCTRL_FECENABLE .assign 3 ; -MODCTRL_FEC5TERMINATE .assign 2 ; -MODCTRL_TONEINSERT .assign 1 ; -MODCTRL_PREAMBLEINSERT .assign 0 ; +%define MODCTRL 99 +%define MODCTRL_CDC_COL_RESTART 12 ; +%define MODCTRL_DSBUSEL 11 ; +%define MODCTRL_HDISMODE 10 ; +%define MODCTRL_PARBITQUALEN 9 ; +%define MODCTRL_STIMEARLYLATE 7 ; +%define MODCTRL_EARLYLATE 6 ; +%define MODCTRL_SOFTPDIFFMODE 5 ; +%define MODCTRL_SOFTTXENABLE 4 ; +%define MODCTRL_FECENABLE 3 ; +%define MODCTRL_FEC5TERMINATE 2 ; +%define MODCTRL_TONEINSERT 1 ; +%define MODCTRL_PREAMBLEINSERT 0 ; ; -------------------------------------------------------------- ; MODPREAMBLE ; -MODPREAMBLE .assign 100 -MODPREAMBLE_WORD .assign 0 ; +%define MODPREAMBLE 100 +%define MODPREAMBLE_WORD 0 ; ; -------------------------------------------------------------- ; DEMFRAC0 ; -DEMFRAC0 .assign 101 -DEMFRAC0_P15C0 .assign 0 ; +%define DEMFRAC0 101 +%define DEMFRAC0_P15C0 0 ; ; -------------------------------------------------------------- ; DEMFRAC1 ; -DEMFRAC1 .assign 102 -DEMFRAC1_P27C16 .assign 0 ; +%define DEMFRAC1 102 +%define DEMFRAC1_P27C16 0 ; ; -------------------------------------------------------------- ; DEMFRAC2 ; -DEMFRAC2 .assign 103 -DEMFRAC2_Q15C0 .assign 0 ; +%define DEMFRAC2 103 +%define DEMFRAC2_Q15C0 0 ; ; -------------------------------------------------------------- ; DEMFRAC3 ; -DEMFRAC3 .assign 104 -DEMFRAC3_Q27C16 .assign 0 ; +%define DEMFRAC3 104 +%define DEMFRAC3_Q27C16 0 ; ; -------------------------------------------------------------- ; DEMCODC1 ; -DEMCODC1 .assign 105 -DEMCODC1_COMPIVAL .assign 0 ; +%define DEMCODC1 105 +%define DEMCODC1_COMPIVAL 0 ; ; -------------------------------------------------------------- ; DEMCODC2 ; -DEMCODC2 .assign 106 -DEMCODC2_COMPQVAL .assign 0 ; +%define DEMCODC2 106 +%define DEMCODC2_COMPQVAL 0 ; ; -------------------------------------------------------------- ; DEMFIDC1 ; -DEMFIDC1 .assign 107 -DEMFIDC1_COMPIVAL .assign 0 ; +%define DEMFIDC1 107 +%define DEMFIDC1_COMPIVAL 0 ; ; -------------------------------------------------------------- ; DEMFIDC2 ; -DEMFIDC2 .assign 108 -DEMFIDC2_COMPQVAL .assign 0 ; +%define DEMFIDC2 108 +%define DEMFIDC2_COMPQVAL 0 ; ; -------------------------------------------------------------- ; DEMFIFE1 ; -DEMFIFE1 .assign 109 -DEMFIFE1_FOCFBREGVAL .assign 0 ; +%define DEMFIFE1 109 +%define DEMFIFE1_FOCFBREGVAL 0 ; ; -------------------------------------------------------------- ; DEMTHRD0 ; -DEMTHRD0 .assign 110 -DEMTHRD0_THR2 .assign 8 ; -DEMTHRD0_RESERVED .assign 7 ; -DEMTHRD0_THR1 .assign 0 ; +%define DEMTHRD0 110 +%define DEMTHRD0_THR2 8 ; +%define DEMTHRD0_RESERVED 7 ; +%define DEMTHRD0_THR1 0 ; ; -------------------------------------------------------------- ; DEMTHRD1 ; -DEMTHRD1 .assign 111 -DEMTHRD1_THR3 .assign 0 ; +%define DEMTHRD1 111 +%define DEMTHRD1_THR3 0 ; ; -------------------------------------------------------------- ; DEMMAFC0 ; -DEMMAFC0 .assign 112 -DEMMAFC0_COMPVAL .assign 0 ; +%define DEMMAFC0 112 +%define DEMMAFC0_COMPVAL 0 ; ; -------------------------------------------------------------- ; DEMMAFI4 ; -DEMMAFI4 .assign 113 -DEMMAFI4_TERM_VAL .assign 0 ; +%define DEMMAFI4 113 +%define DEMMAFI4_TERM_VAL 0 ; ; -------------------------------------------------------------- ; DEMSWIMBAL ; -DEMSWIMBAL .assign 114 -DEMSWIMBAL_IMBALB .assign 8 ; -DEMSWIMBAL_IMBALA .assign 0 ; +%define DEMSWIMBAL 114 +%define DEMSWIMBAL_IMBALB 8 ; +%define DEMSWIMBAL_IMBALA 0 ; ; -------------------------------------------------------------- ; DEMSOFTPDIFF ; -DEMSOFTPDIFF .assign 115 -DEMSOFTPDIFF_SOFTPDIFF .assign 0 ; +%define DEMSOFTPDIFF 115 +%define DEMSOFTPDIFF_SOFTPDIFF 0 ; ; -------------------------------------------------------------- ; DEMDEBUG ; -DEMDEBUG .assign 116 -DEMDEBUG_DECSTAGEDEBUG .assign 5 ; -DEMDEBUG_FRONTENDDEBUG .assign 1 ; -DEMDEBUG_LOOPBACKMODE .assign 0 ; +%define DEMDEBUG 116 +%define DEMDEBUG_DECSTAGEDEBUG 5 ; +%define DEMDEBUG_FRONTENDDEBUG 1 ; +%define DEMDEBUG_LOOPBACKMODE 0 ; ; -------------------------------------------------------------- ; VITCTRL ; -VITCTRL .assign 117 -VITCTRL_METRSEL .assign 10 ; -VITCTRL_READEPTH .assign 6 ; -VITCTRL_APMRDBACKSEL .assign 2 ; -VITCTRL_ACSITERATIONS .assign 1 ; -VITCTRL_SOFTMETRICS .assign 0 ; +%define VITCTRL 117 +%define VITCTRL_METRSEL 10 ; +%define VITCTRL_READEPTH 6 ; +%define VITCTRL_APMRDBACKSEL 2 ; +%define VITCTRL_ACSITERATIONS 1 ; +%define VITCTRL_SOFTMETRICS 0 ; ; -------------------------------------------------------------- ; VITCOMPUTE ; -VITCOMPUTE .assign 118 -VITCOMPUTE_COMPUTE .assign 0 ; +%define VITCOMPUTE 118 +%define VITCOMPUTE_COMPUTE 0 ; ; -------------------------------------------------------------- ; VITAPMRDBACK ; -VITAPMRDBACK .assign 119 -VITAPMRDBACK_VALUE .assign 0 ; +%define VITAPMRDBACK 119 +%define VITAPMRDBACK_VALUE 0 ; ; -------------------------------------------------------------- ; VITSTATE ; -VITSTATE .assign 120 -VITSTATE_VALUE .assign 0 ; +%define VITSTATE 120 +%define VITSTATE_VALUE 0 ; ; -------------------------------------------------------------- ; VITBRMETRIC10 ; -VITBRMETRIC10 .assign 121 -VITBRMETRIC10_MET1 .assign 8 ; -VITBRMETRIC10_MET0 .assign 0 ; +%define VITBRMETRIC10 121 +%define VITBRMETRIC10_MET1 8 ; +%define VITBRMETRIC10_MET0 0 ; ; -------------------------------------------------------------- ; VITBRMETRIC32 ; -VITBRMETRIC32 .assign 122 -VITBRMETRIC32_MET3 .assign 8 ; -VITBRMETRIC32_MET2 .assign 0 ; +%define VITBRMETRIC32 122 +%define VITBRMETRIC32_MET3 8 ; +%define VITBRMETRIC32_MET2 0 ; ; -------------------------------------------------------------- ; VITBRMETRIC54 ; -VITBRMETRIC54 .assign 123 -VITBRMETRIC54_MET5 .assign 8 ; -VITBRMETRIC54_MET4 .assign 0 ; +%define VITBRMETRIC54 123 +%define VITBRMETRIC54_MET5 8 ; +%define VITBRMETRIC54_MET4 0 ; ; -------------------------------------------------------------- ; VITBRMETRIC76 ; -VITBRMETRIC76 .assign 124 -VITBRMETRIC76_MET7 .assign 8 ; -VITBRMETRIC76_MET6 .assign 0 ; +%define VITBRMETRIC76 124 +%define VITBRMETRIC76_MET7 8 ; +%define VITBRMETRIC76_MET6 0 ; ; -------------------------------------------------------------- ; VITBRSEL0 ; -VITBRSEL0 .assign 125 -VITBRSEL0_BR3MUX .assign 9 ; -VITBRSEL0_BR2MUX .assign 6 ; -VITBRSEL0_BR1MUX .assign 3 ; -VITBRSEL0_BR0MUX .assign 0 ; +%define VITBRSEL0 125 +%define VITBRSEL0_BR3MUX 9 ; +%define VITBRSEL0_BR2MUX 6 ; +%define VITBRSEL0_BR1MUX 3 ; +%define VITBRSEL0_BR0MUX 0 ; ; -------------------------------------------------------------- ; VITAPMSEL0 ; -VITAPMSEL0 .assign 126 -VITAPMSEL0_APM3MUX .assign 9 ; -VITAPMSEL0_APM2MUX .assign 6 ; -VITAPMSEL0_APM1MUX .assign 3 ; -VITAPMSEL0_APM0MUX .assign 0 ; +%define VITAPMSEL0 126 +%define VITAPMSEL0_APM3MUX 9 ; +%define VITAPMSEL0_APM2MUX 6 ; +%define VITAPMSEL0_APM1MUX 3 ; +%define VITAPMSEL0_APM0MUX 0 ; ; -------------------------------------------------------------- ; VITBRSEL1 ; -VITBRSEL1 .assign 127 -VITBRSEL1_BR3MUX .assign 9 ; -VITBRSEL1_BR2MUX .assign 6 ; -VITBRSEL1_BR1MUX .assign 3 ; -VITBRSEL1_BR0MUX .assign 0 ; +%define VITBRSEL1 127 +%define VITBRSEL1_BR3MUX 9 ; +%define VITBRSEL1_BR2MUX 6 ; +%define VITBRSEL1_BR1MUX 3 ; +%define VITBRSEL1_BR0MUX 0 ; ; -------------------------------------------------------------- ; VITAPMSEL1 ; -VITAPMSEL1 .assign 128 -VITAPMSEL1_APM3MUX .assign 9 ; -VITAPMSEL1_APM2MUX .assign 6 ; -VITAPMSEL1_APM1MUX .assign 3 ; -VITAPMSEL1_APM0MUX .assign 0 ; +%define VITAPMSEL1 128 +%define VITAPMSEL1_APM3MUX 9 ; +%define VITAPMSEL1_APM2MUX 6 ; +%define VITAPMSEL1_APM1MUX 3 ; +%define VITAPMSEL1_APM0MUX 0 ; ; -------------------------------------------------------------- ; VITBRSEL2 ; -VITBRSEL2 .assign 129 -VITBRSEL2_BR3MUX .assign 9 ; -VITBRSEL2_BR2MUX .assign 6 ; -VITBRSEL2_BR1MUX .assign 3 ; -VITBRSEL2_BR0MUX .assign 0 ; +%define VITBRSEL2 129 +%define VITBRSEL2_BR3MUX 9 ; +%define VITBRSEL2_BR2MUX 6 ; +%define VITBRSEL2_BR1MUX 3 ; +%define VITBRSEL2_BR0MUX 0 ; ; -------------------------------------------------------------- ; VITAPMSEL2 ; -VITAPMSEL2 .assign 130 -VITAPMSEL2_APM3MUX .assign 9 ; -VITAPMSEL2_APM2MUX .assign 6 ; -VITAPMSEL2_APM1MUX .assign 3 ; -VITAPMSEL2_APM0MUX .assign 0 ; +%define VITAPMSEL2 130 +%define VITAPMSEL2_APM3MUX 9 ; +%define VITAPMSEL2_APM2MUX 6 ; +%define VITAPMSEL2_APM1MUX 3 ; +%define VITAPMSEL2_APM0MUX 0 ; ; -------------------------------------------------------------- ; VITBRSEL3 ; -VITBRSEL3 .assign 131 -VITBRSEL3_BR3MUX .assign 9 ; -VITBRSEL3_BR2MUX .assign 6 ; -VITBRSEL3_BR1MUX .assign 3 ; -VITBRSEL3_BR0MUX .assign 0 ; +%define VITBRSEL3 131 +%define VITBRSEL3_BR3MUX 9 ; +%define VITBRSEL3_BR2MUX 6 ; +%define VITBRSEL3_BR1MUX 3 ; +%define VITBRSEL3_BR0MUX 0 ; ; -------------------------------------------------------------- ; VITAPMSEL3 ; -VITAPMSEL3 .assign 132 -VITAPMSEL3_APM3MUX .assign 9 ; -VITAPMSEL3_APM2MUX .assign 6 ; -VITAPMSEL3_APM1MUX .assign 3 ; -VITAPMSEL3_APM0MUX .assign 0 ; +%define VITAPMSEL3 132 +%define VITAPMSEL3_APM3MUX 9 ; +%define VITAPMSEL3_APM2MUX 6 ; +%define VITAPMSEL3_APM1MUX 3 ; +%define VITAPMSEL3_APM0MUX 0 ; ; -------------------------------------------------------------- ; VITBRSEL4 ; -VITBRSEL4 .assign 133 -VITBRSEL4_BR3MUX .assign 9 ; -VITBRSEL4_BR2MUX .assign 6 ; -VITBRSEL4_BR1MUX .assign 3 ; -VITBRSEL4_BR0MUX .assign 0 ; +%define VITBRSEL4 133 +%define VITBRSEL4_BR3MUX 9 ; +%define VITBRSEL4_BR2MUX 6 ; +%define VITBRSEL4_BR1MUX 3 ; +%define VITBRSEL4_BR0MUX 0 ; ; -------------------------------------------------------------- ; VITAPMSEL4 ; -VITAPMSEL4 .assign 134 -VITAPMSEL4_APM3MUX .assign 9 ; -VITAPMSEL4_APM2MUX .assign 6 ; -VITAPMSEL4_APM1MUX .assign 3 ; -VITAPMSEL4_APM0MUX .assign 0 ; +%define VITAPMSEL4 134 +%define VITAPMSEL4_APM3MUX 9 ; +%define VITAPMSEL4_APM2MUX 6 ; +%define VITAPMSEL4_APM1MUX 3 ; +%define VITAPMSEL4_APM0MUX 0 ; ; -------------------------------------------------------------- ; VITBRSEL5 ; -VITBRSEL5 .assign 135 -VITBRSEL5_BR3MUX .assign 9 ; -VITBRSEL5_BR2MUX .assign 6 ; -VITBRSEL5_BR1MUX .assign 3 ; -VITBRSEL5_BR0MUX .assign 0 ; +%define VITBRSEL5 135 +%define VITBRSEL5_BR3MUX 9 ; +%define VITBRSEL5_BR2MUX 6 ; +%define VITBRSEL5_BR1MUX 3 ; +%define VITBRSEL5_BR0MUX 0 ; ; -------------------------------------------------------------- ; VITAPMSEL5 ; -VITAPMSEL5 .assign 136 -VITAPMSEL5_APM3MUX .assign 9 ; -VITAPMSEL5_APM2MUX .assign 6 ; -VITAPMSEL5_APM1MUX .assign 3 ; -VITAPMSEL5_APM0MUX .assign 0 ; +%define VITAPMSEL5 136 +%define VITAPMSEL5_APM3MUX 9 ; +%define VITAPMSEL5_APM2MUX 6 ; +%define VITAPMSEL5_APM1MUX 3 ; +%define VITAPMSEL5_APM0MUX 0 ; ; -------------------------------------------------------------- ; VITBRSEL6 ; -VITBRSEL6 .assign 137 -VITBRSEL6_BR3MUX .assign 9 ; -VITBRSEL6_BR2MUX .assign 6 ; -VITBRSEL6_BR1MUX .assign 3 ; -VITBRSEL6_BR0MUX .assign 0 ; +%define VITBRSEL6 137 +%define VITBRSEL6_BR3MUX 9 ; +%define VITBRSEL6_BR2MUX 6 ; +%define VITBRSEL6_BR1MUX 3 ; +%define VITBRSEL6_BR0MUX 0 ; ; -------------------------------------------------------------- ; VITAPMSEL6 ; -VITAPMSEL6 .assign 138 -VITAPMSEL6_APM3MUX .assign 9 ; -VITAPMSEL6_APM2MUX .assign 6 ; -VITAPMSEL6_APM1MUX .assign 3 ; -VITAPMSEL6_APM0MUX .assign 0 ; +%define VITAPMSEL6 138 +%define VITAPMSEL6_APM3MUX 9 ; +%define VITAPMSEL6_APM2MUX 6 ; +%define VITAPMSEL6_APM1MUX 3 ; +%define VITAPMSEL6_APM0MUX 0 ; ; -------------------------------------------------------------- ; VITBRSEL7 ; -VITBRSEL7 .assign 139 -VITBRSEL7_BR3MUX .assign 9 ; -VITBRSEL7_BR2MUX .assign 6 ; -VITBRSEL7_BR1MUX .assign 3 ; -VITBRSEL7_BR0MUX .assign 0 ; +%define VITBRSEL7 139 +%define VITBRSEL7_BR3MUX 9 ; +%define VITBRSEL7_BR2MUX 6 ; +%define VITBRSEL7_BR1MUX 3 ; +%define VITBRSEL7_BR0MUX 0 ; ; -------------------------------------------------------------- ; VITAPMSEL7 ; -VITAPMSEL7 .assign 140 -VITAPMSEL7_APM3MUX .assign 9 ; -VITAPMSEL7_APM2MUX .assign 6 ; -VITAPMSEL7_APM1MUX .assign 3 ; -VITAPMSEL7_APM0MUX .assign 0 ; +%define VITAPMSEL7 140 +%define VITAPMSEL7_APM3MUX 9 ; +%define VITAPMSEL7_APM2MUX 6 ; +%define VITAPMSEL7_APM1MUX 3 ; +%define VITAPMSEL7_APM0MUX 0 ; ; -------------------------------------------------------------- ; LOCMULTA ; -LOCMULTA .assign 141 -LOCMULTA_AVALUE .assign 0 ; +%define LOCMULTA 141 +%define LOCMULTA_AVALUE 0 ; ; -------------------------------------------------------------- ; LOCMULTB ; -LOCMULTB .assign 142 -LOCMULTB_BVALUE .assign 0 ; +%define LOCMULTB 142 +%define LOCMULTB_BVALUE 0 ; ; -------------------------------------------------------------- ; LOCMULTC0 ; -LOCMULTC0 .assign 143 -LOCMULTC0_C15C0 .assign 0 ; +%define LOCMULTC0 143 +%define LOCMULTC0_C15C0 0 ; ; -------------------------------------------------------------- ; LOCMULTC1 ; -LOCMULTC1 .assign 144 -LOCMULTC1_C31C16 .assign 0 ; +%define LOCMULTC1 144 +%define LOCMULTC1_C31C16 0 ; ; -------------------------------------------------------------- ; TIMCTRL ; -TIMCTRL .assign 145 -TIMCTRL_CAPTURESOURCE .assign 8 ; -TIMCTRL_ENABLECAPTURE .assign 7 ; -TIMCTRL_COUNTERSOURCE .assign 5 ; -TIMCTRL_CLEARCOUNTER .assign 4 ; -TIMCTRL_ENABLECOUNTER .assign 3 ; -TIMCTRL_TIMERSOURCE .assign 1 ; -TIMCTRL_ENABLETIMER .assign 0 ; +%define TIMCTRL 145 +%define TIMCTRL_CAPTURESOURCE 8 ; +%define TIMCTRL_ENABLECAPTURE 7 ; +%define TIMCTRL_COUNTERSOURCE 5 ; +%define TIMCTRL_CLEARCOUNTER 4 ; +%define TIMCTRL_ENABLECOUNTER 3 ; +%define TIMCTRL_TIMERSOURCE 1 ; +%define TIMCTRL_ENABLETIMER 0 ; ; -------------------------------------------------------------- ; TIMINC ; -TIMINC .assign 146 -TIMINC_INCUNIT .assign 0 ; +%define TIMINC 146 +%define TIMINC_INCUNIT 0 ; ; -------------------------------------------------------------- ; TIMPERIOD ; -TIMPERIOD .assign 147 -TIMPERIOD_PERIOD .assign 0 ; +%define TIMPERIOD 147 +%define TIMPERIOD_PERIOD 0 ; ; -------------------------------------------------------------- ; TIMCOUNTER ; -TIMCOUNTER .assign 148 -TIMCOUNTER_VALUE .assign 0 ; +%define TIMCOUNTER 148 +%define TIMCOUNTER_VALUE 0 ; ; -------------------------------------------------------------- ; TIMCAPT ; -TIMCAPT .assign 149 -TIMCAPT_VALUE .assign 0 ; +%define TIMCAPT 149 +%define TIMCAPT_VALUE 0 ; ; -------------------------------------------------------------- ; TIMEBASE ; -TIMEBASE .assign 150 -TIMEBASE_FLUSH .assign 0 ; +%define TIMEBASE 150 +%define TIMEBASE_FLUSH 0 ; ; -------------------------------------------------------------- ; COUNT1IN ; -COUNT1IN .assign 151 -COUNT1IN_VAL .assign 0 ; +%define COUNT1IN 151 +%define COUNT1IN_VAL 0 ; ; -------------------------------------------------------------- ; COUNT1RES ; -COUNT1RES .assign 152 -COUNT1RES_COUNT .assign 0 ; +%define COUNT1RES 152 +%define COUNT1RES_COUNT 0 ; ; -------------------------------------------------------------- ; BRMACC0 ; -BRMACC0 .assign 153 -BRMACC0_SYM1ST .assign 8 ; -BRMACC0_SYM2ND .assign 0 ; +%define BRMACC0 153 +%define BRMACC0_SYM1ST 8 ; +%define BRMACC0_SYM2ND 0 ; ; -------------------------------------------------------------- ; BRMACC1 ; -BRMACC1 .assign 154 -BRMACC1_METRIC01 .assign 8 ; -BRMACC1_METRIC00 .assign 0 ; +%define BRMACC1 154 +%define BRMACC1_METRIC01 8 ; +%define BRMACC1_METRIC00 0 ; ; -------------------------------------------------------------- ; BRMACC2 ; -BRMACC2 .assign 155 -BRMACC2_METRIC11 .assign 8 ; -BRMACC2_METRIC10 .assign 0 ; +%define BRMACC2 155 +%define BRMACC2_METRIC11 8 ; +%define BRMACC2_METRIC10 0 ; ; -------------------------------------------------------------- ; VITACCCTRL ; -VITACCCTRL .assign 156 -VITACCCTRL_POLYNOM1 .assign 9 ; -VITACCCTRL_POLYNOM0 .assign 2 ; -VITACCCTRL_CODELENGTH .assign 0 ; +%define VITACCCTRL 156 +%define VITACCCTRL_POLYNOM1 9 ; +%define VITACCCTRL_POLYNOM0 2 ; +%define VITACCCTRL_CODELENGTH 0 ; ; -------------------------------------------------------------- ; VITACCRDBIT ; -VITACCRDBIT .assign 157 -VITACCRDBIT_RXBIT .assign 0 ; +%define VITACCRDBIT 157 +%define VITACCRDBIT_RXBIT 0 ; ; -------------------------------------------------------------- ; MCETRCSEND ; -MCETRCSEND .assign 158 -MCETRCSEND_SEND .assign 0 ; +%define MCETRCSEND 158 +%define MCETRCSEND_SEND 0 ; ; -------------------------------------------------------------- ; MCETRCBUSY ; -MCETRCBUSY .assign 159 -MCETRCBUSY_BUSY .assign 0 ; +%define MCETRCBUSY 159 +%define MCETRCBUSY_BUSY 0 ; ; -------------------------------------------------------------- ; MCETRCCMD ; -MCETRCCMD .assign 160 -MCETRCCMD_PARCNT .assign 8 ; -MCETRCCMD_PKTHDR .assign 0 ; +%define MCETRCCMD 160 +%define MCETRCCMD_PARCNT 8 ; +%define MCETRCCMD_PKTHDR 0 ; ; -------------------------------------------------------------- ; MCETRCPAR0 ; -MCETRCPAR0 .assign 161 -MCETRCPAR0_PAR0 .assign 0 ; +%define MCETRCPAR0 161 +%define MCETRCPAR0_PAR0 0 ; ; -------------------------------------------------------------- ; MCETRCPAR1 ; -MCETRCPAR1 .assign 162 -MCETRCPAR1_PAR1 .assign 0 ; +%define MCETRCPAR1 162 +%define MCETRCPAR1_PAR1 0 ; ; -------------------------------------------------------------- ; RDCAPT0 ; -RDCAPT0 .assign 163 -RDCAPT0_DEMDSBU1 .assign 15 ; -RDCAPT0_DEMC1BEX .assign 14 ; -RDCAPT0_DEMSOFD0 .assign 13 ; -RDCAPT0_DEMLQIE0 .assign 12 ; -RDCAPT0_DEMSTIM1 .assign 11 ; -RDCAPT0_DEMSTIM0 .assign 10 ; -RDCAPT0_DEMFIFE2 .assign 9 ; -RDCAPT0_DEMPDIF0 .assign 8 ; -RDCAPT0_DEMCA2P0 .assign 7 ; -RDCAPT0_DEMFIDC4 .assign 6 ; -RDCAPT0_DEMFIDC3 .assign 5 ; -RDCAPT0_DEMMGEX2 .assign 4 ; -RDCAPT0_DEMMGEX1 .assign 3 ; -RDCAPT0_DEMDSBU0 .assign 2 ; -RDCAPT0_DEMCODC4 .assign 1 ; -RDCAPT0_DEMCODC3 .assign 0 ; +%define RDCAPT0 163 +%define RDCAPT0_DEMDSBU1 15 ; +%define RDCAPT0_DEMC1BEX 14 ; +%define RDCAPT0_DEMSOFD0 13 ; +%define RDCAPT0_DEMLQIE0 12 ; +%define RDCAPT0_DEMSTIM1 11 ; +%define RDCAPT0_DEMSTIM0 10 ; +%define RDCAPT0_DEMFIFE2 9 ; +%define RDCAPT0_DEMPDIF0 8 ; +%define RDCAPT0_DEMCA2P0 7 ; +%define RDCAPT0_DEMFIDC4 6 ; +%define RDCAPT0_DEMFIDC3 5 ; +%define RDCAPT0_DEMMGEX2 4 ; +%define RDCAPT0_DEMMGEX1 3 ; +%define RDCAPT0_DEMDSBU0 2 ; +%define RDCAPT0_DEMCODC4 1 ; +%define RDCAPT0_DEMCODC3 0 ; ; -------------------------------------------------------------- ; DEMCODC3 ; -DEMCODC3 .assign 164 -DEMCODC3_ESTOUTI .assign 0 ; +%define DEMCODC3 164 +%define DEMCODC3_ESTOUTI 0 ; ; -------------------------------------------------------------- ; DEMCODC4 ; -DEMCODC4 .assign 165 -DEMCODC4_ESTOUTQ .assign 0 ; +%define DEMCODC4 165 +%define DEMCODC4_ESTOUTQ 0 ; ; -------------------------------------------------------------- ; DEMMGEx1 ; -DEMMGEX1 .assign 166 -DEMMGEX1_MGE1ESTOUT .assign 0 ; +%define DEMMGEX1 166 +%define DEMMGEX1_MGE1ESTOUT 0 ; ; -------------------------------------------------------------- ; DEMMGEx2 ; -DEMMGEX2 .assign 167 -DEMMGEX2_MGE2ESTOUT .assign 0 ; +%define DEMMGEX2 167 +%define DEMMGEX2_MGE2ESTOUT 0 ; ; -------------------------------------------------------------- ; DEMFIDC3 ; -DEMFIDC3 .assign 168 -DEMFIDC3_ESTOUTI .assign 0 ; +%define DEMFIDC3 168 +%define DEMFIDC3_ESTOUTI 0 ; ; -------------------------------------------------------------- ; DEMFIDC4 ; -DEMFIDC4 .assign 169 -DEMFIDC4_ESTOUTQ .assign 0 ; +%define DEMFIDC4 169 +%define DEMFIDC4_ESTOUTQ 0 ; ; -------------------------------------------------------------- ; DEMCA2P0 ; -DEMCA2P0 .assign 170 -DEMCA2P0_PHASE .assign 0 ; +%define DEMCA2P0 170 +%define DEMCA2P0_PHASE 0 ; ; -------------------------------------------------------------- ; DEMPDIF0 ; -DEMPDIF0 .assign 171 -DEMPDIF0_PDIFF .assign 0 ; +%define DEMPDIF0 171 +%define DEMPDIF0_PDIFF 0 ; ; -------------------------------------------------------------- ; DEMC1BE3 ; -DEMC1BE3 .assign 172 -DEMC1BE3_CORRVALUEA .assign 0 ; +%define DEMC1BE3 172 +%define DEMC1BE3_CORRVALUEA 0 ; ; -------------------------------------------------------------- ; DEMC1BE4 ; -DEMC1BE4 .assign 173 -DEMC1BE4_CORRVALUEB .assign 0 ; +%define DEMC1BE4 173 +%define DEMC1BE4_CORRVALUEB 0 ; ; -------------------------------------------------------------- ; DEMC1BE5 ; -DEMC1BE5 .assign 174 -DEMC1BE5_CORRVALUEC .assign 0 ; +%define DEMC1BE5 174 +%define DEMC1BE5_CORRVALUEC 0 ; ; -------------------------------------------------------------- ; DEMFIFE2 ; -DEMFIFE2 .assign 175 -DEMFIFE2_FINEFOCEST .assign 0 ; +%define DEMFIFE2 175 +%define DEMFIFE2_FINEFOCEST 0 ; ; -------------------------------------------------------------- ; DEMDSBU0 ; -DEMDSBU0 .assign 176 -DEMDSBU0_RDPOUT .assign 0 ; +%define DEMDSBU0 176 +%define DEMDSBU0_RDPOUT 0 ; ; -------------------------------------------------------------- ; DEMDSBU1 ; -DEMDSBU1 .assign 177 -DEMDSBU1_AVGVAL .assign 0 ; +%define DEMDSBU1 177 +%define DEMDSBU1_AVGVAL 0 ; ; -------------------------------------------------------------- ; DEMSTIM0 ; -DEMSTIM0 .assign 178 -DEMSTIM0_EVENTS .assign 0 ; +%define DEMSTIM0 178 +%define DEMSTIM0_EVENTS 0 ; ; -------------------------------------------------------------- ; DEMSTIM1 ; -DEMSTIM1 .assign 179 -DEMSTIM1_GARDNERERROR .assign 4 ; -DEMSTIM1_DELTA .assign 0 ; +%define DEMSTIM1 179 +%define DEMSTIM1_GARDNERERROR 4 ; +%define DEMSTIM1_DELTA 0 ; ; -------------------------------------------------------------- ; DEMSWQU1 ; -DEMSWQU1 .assign 180 -DEMSWQU1_MAFCCOMPVAL .assign 2 ; -DEMSWQU1_SWSEL .assign 1 ; -DEMSWQU1_SYNCED .assign 0 ; +%define DEMSWQU1 180 +%define DEMSWQU1_MAFCCOMPVAL 2 ; +%define DEMSWQU1_SWSEL 1 ; +%define DEMSWQU1_SYNCED 0 ; ; -------------------------------------------------------------- ; DEMLQIE0 ; -DEMLQIE0 .assign 181 -DEMLQIE0_LQI .assign 0 ; +%define DEMLQIE0 181 +%define DEMLQIE0_LQI 0 ; ; -------------------------------------------------------------- ; DEMSOFD0 ; -DEMSOFD0 .assign 182 -DEMSOFD0_SOFTSYMBOL .assign 0 ; +%define DEMSOFD0 182 +%define DEMSOFD0_SOFTSYMBOL 0 ; ; -------------------------------------------------------------- ; RDCAPT1 ; -RDCAPT1 .assign 183 -RDCAPT1_DEMHDIS0 .assign 13 ; -RDCAPT1_DEMFB2P2 .assign 12 ; -RDCAPT1_DEMPHAC .assign 11 ; -RDCAPT1_DEMMAFI5 .assign 10 ; -RDCAPT1_DEMMLSE4BITS .assign 9 ; -RDCAPT1_DEMPNSOFT .assign 8 ; -RDCAPT1_DEMMLSEBIT .assign 7 ; -RDCAPT1_DEMTHRD4 .assign 6 ; -RDCAPT1_DEMBDEC0 .assign 5 ; -RDCAPT1_DEMBDEC1 .assign 4 ; -RDCAPT1_DEMCHFI0 .assign 3 ; -RDCAPT1_DEMCHFI1 .assign 2 ; -RDCAPT1_DEMFRAC4 .assign 1 ; -RDCAPT1_DEMFRAC5 .assign 0 ; +%define RDCAPT1 183 +%define RDCAPT1_DEMHDIS0 13 ; +%define RDCAPT1_DEMFB2P2 12 ; +%define RDCAPT1_DEMPHAC 11 ; +%define RDCAPT1_DEMMAFI5 10 ; +%define RDCAPT1_DEMMLSE4BITS 9 ; +%define RDCAPT1_DEMPNSOFT 8 ; +%define RDCAPT1_DEMMLSEBIT 7 ; +%define RDCAPT1_DEMTHRD4 6 ; +%define RDCAPT1_DEMBDEC0 5 ; +%define RDCAPT1_DEMBDEC1 4 ; +%define RDCAPT1_DEMCHFI0 3 ; +%define RDCAPT1_DEMCHFI1 2 ; +%define RDCAPT1_DEMFRAC4 1 ; +%define RDCAPT1_DEMFRAC5 0 ; ; -------------------------------------------------------------- ; DEMTHRD4 ; -DEMTHRD4 .assign 184 -DEMTHRD4_DECISION .assign 0 ; +%define DEMTHRD4 184 +%define DEMTHRD4_DECISION 0 ; ; -------------------------------------------------------------- ; DEMMLSEBIT ; -DEMMLSEBIT .assign 185 -DEMMLSEBIT_MLSEBIT .assign 0 ; +%define DEMMLSEBIT 185 +%define DEMMLSEBIT_MLSEBIT 0 ; ; -------------------------------------------------------------- ; DEMMLSE4BITS ; -DEMMLSE4BITS .assign 186 -DEMMLSE4BITS_MLSE4BITS .assign 0 ; +%define DEMMLSE4BITS 186 +%define DEMMLSE4BITS_MLSE4BITS 0 ; ; -------------------------------------------------------------- ; DEMBDEC0 ; -DEMBDEC0 .assign 187 -DEMBDEC0_IVAL .assign 0 ; +%define DEMBDEC0 187 +%define DEMBDEC0_IVAL 0 ; ; -------------------------------------------------------------- ; DEMBDEC1 ; -DEMBDEC1 .assign 188 -DEMBDEC1_QVAL .assign 0 ; +%define DEMBDEC1 188 +%define DEMBDEC1_QVAL 0 ; ; -------------------------------------------------------------- ; DEMCHFI0 ; -DEMCHFI0 .assign 189 -DEMCHFI0_IVAL .assign 0 ; +%define DEMCHFI0 189 +%define DEMCHFI0_IVAL 0 ; ; -------------------------------------------------------------- ; DEMCHFI1 ; -DEMCHFI1 .assign 190 -DEMCHFI1_QVAL .assign 0 ; +%define DEMCHFI1 190 +%define DEMCHFI1_QVAL 0 ; ; -------------------------------------------------------------- ; DEMFRAC4 ; -DEMFRAC4 .assign 191 -DEMFRAC4_IVAL .assign 0 ; +%define DEMFRAC4 191 +%define DEMFRAC4_IVAL 0 ; ; -------------------------------------------------------------- ; DEMFRAC5 ; -DEMFRAC5 .assign 192 -DEMFRAC5_QVAL .assign 0 ; +%define DEMFRAC5 192 +%define DEMFRAC5_QVAL 0 ; ; -------------------------------------------------------------- ; DEMPNSOFT ; -DEMPNSOFT .assign 193 -DEMPNSOFT_PNSOFT .assign 0 ; +%define DEMPNSOFT 193 +%define DEMPNSOFT_PNSOFT 0 ; ; -------------------------------------------------------------- ; DEMMAFI5 ; -DEMMAFI5 .assign 194 -DEMMAFI5_MAFIOUT .assign 0 ; +%define DEMMAFI5 194 +%define DEMMAFI5_MAFIOUT 0 ; ; -------------------------------------------------------------- ; DEMC1BE6 ; -DEMC1BE6 .assign 195 -DEMC1BE6_VAL .assign 0 ; +%define DEMC1BE6 195 +%define DEMC1BE6_VAL 0 ; ; -------------------------------------------------------------- ; DEMC1BE7 ; -DEMC1BE7 .assign 196 -DEMC1BE7_VAL .assign 0 ; +%define DEMC1BE7 196 +%define DEMC1BE7_VAL 0 ; ; -------------------------------------------------------------- ; DEMC1BE8 ; -DEMC1BE8 .assign 197 -DEMC1BE8_VAL .assign 0 ; +%define DEMC1BE8 197 +%define DEMC1BE8_VAL 0 ; ; -------------------------------------------------------------- ; DEMC1BE9 ; -DEMC1BE9 .assign 198 -DEMC1BE9_VAL .assign 0 ; +%define DEMC1BE9 198 +%define DEMC1BE9_VAL 0 ; ; -------------------------------------------------------------- ; DEMC1BEA ; -DEMC1BEA .assign 199 -DEMC1BEA_QUALB .assign 6 ; -DEMC1BEA_QUALA .assign 0 ; +%define DEMC1BEA 199 +%define DEMC1BEA_QUALB 6 ; +%define DEMC1BEA_QUALA 0 ; ; -------------------------------------------------------------- ; MDMSPAR0 ; -MDMSPAR0 .assign 200 -MDMSPAR0_VAL .assign 0 ; +%define MDMSPAR0 200 +%define MDMSPAR0_VAL 0 ; ; -------------------------------------------------------------- ; MDMSPAR1 ; -MDMSPAR1 .assign 201 -MDMSPAR1_VAL .assign 0 ; +%define MDMSPAR1 201 +%define MDMSPAR1_VAL 0 ; ; -------------------------------------------------------------- ; MDMSPAR2 ; -MDMSPAR2 .assign 202 -MDMSPAR2_VAL .assign 0 ; +%define MDMSPAR2 202 +%define MDMSPAR2_VAL 0 ; ; -------------------------------------------------------------- ; MDMSPAR3 ; -MDMSPAR3 .assign 203 -MDMSPAR3_VAL .assign 0 ; +%define MDMSPAR3 203 +%define MDMSPAR3_VAL 0 ; ; -------------------------------------------------------------- ; DEMSOFD1 ; -DEMSOFD1 .assign 204 -DEMSOFD1_SOFTX0 .assign 0 ; +%define DEMSOFD1 204 +%define DEMSOFD1_SOFTX0 0 ; ; -------------------------------------------------------------- ; DEMSOFD2 ; -DEMSOFD2 .assign 205 -DEMSOFD2_SOFTX1 .assign 0 ; +%define DEMSOFD2 205 +%define DEMSOFD2_SOFTX1 0 ; ; -------------------------------------------------------------- ; DEMSOFD3 ; -DEMSOFD3 .assign 206 -DEMSOFD3_SOFTX2 .assign 0 ; +%define DEMSOFD3 206 +%define DEMSOFD3_SOFTX2 0 ; ; -------------------------------------------------------------- ; DEMSOFD4 ; -DEMSOFD4 .assign 207 -DEMSOFD4_SOFTX3 .assign 0 ; +%define DEMSOFD4 207 +%define DEMSOFD4_SOFTX3 0 ; ; -------------------------------------------------------------- ; DEMC1BE14 ; -DEMC1BE14 .assign 208 -DEMC1BE14_CORRVALUEE .assign 0 ; +%define DEMC1BE14 208 +%define DEMC1BE14_CORRVALUEE 0 ; ; -------------------------------------------------------------- ; DEMC1BE15 ; -DEMC1BE15 .assign 209 -DEMC1BE15_CORRVALUEF .assign 0 ; +%define DEMC1BE15 209 +%define DEMC1BE15_CORRVALUEF 0 ; ; -------------------------------------------------------------- ; DEMC1BE16 ; -DEMC1BE16 .assign 210 -DEMC1BE16_VAL .assign 0 ; +%define DEMC1BE16 210 +%define DEMC1BE16_VAL 0 ; ; -------------------------------------------------------------- ; DEMC1BE17 ; -DEMC1BE17 .assign 211 -DEMC1BE17_VAL .assign 0 ; +%define DEMC1BE17 211 +%define DEMC1BE17_VAL 0 ; ; -------------------------------------------------------------- ; DEMC1BE18 ; -DEMC1BE18 .assign 212 -DEMC1BE18_VAL .assign 0 ; +%define DEMC1BE18 212 +%define DEMC1BE18_VAL 0 ; ; -------------------------------------------------------------- ; DEMC1BE19 ; -DEMC1BE19 .assign 213 -DEMC1BE19_VAL .assign 0 ; +%define DEMC1BE19 213 +%define DEMC1BE19_VAL 0 ; ; -------------------------------------------------------------- ; DEMC1BE20 ; -DEMC1BE20 .assign 214 -DEMC1BE20_CORRVALUEG .assign 0 ; +%define DEMC1BE20 214 +%define DEMC1BE20_CORRVALUEG 0 ; ; -------------------------------------------------------------- ; DEMDSBU3 ; -DEMDSBU3 .assign 215 -DEMDSBU3_WRPOUT .assign 0 ; +%define DEMDSBU3 215 +%define DEMDSBU3_WRPOUT 0 ; ; -------------------------------------------------------------- ; MCEDUMP0 ; -MCEDUMP0 .assign 216 -MCEDUMP0_DONE .assign 0 ; +%define MCEDUMP0 216 +%define MCEDUMP0_DONE 0 ; ; -------------------------------------------------------------- ; MCEGPO0 ; -MCEGPO0 .assign 217 -MCEGPO0_HWDATAMUX .assign 11 ; -MCEGPO0_HWCLKSTRETCH .assign 9 ; -MCEGPO0_HWCLKMUX .assign 5 ; -MCEGPO0_FWCTRL .assign 4 ; -MCEGPO0_GPO3 .assign 3 ; -MCEGPO0_GPO2 .assign 2 ; -MCEGPO0_GPO1 .assign 1 ; -MCEGPO0_GPO0 .assign 0 ; +%define MCEGPO0 217 +%define MCEGPO0_HWDATAMUX 11 ; +%define MCEGPO0_HWCLKSTRETCH 9 ; +%define MCEGPO0_HWCLKMUX 5 ; +%define MCEGPO0_FWCTRL 4 ; +%define MCEGPO0_GPO3 3 ; +%define MCEGPO0_GPO2 2 ; +%define MCEGPO0_GPO1 1 ; +%define MCEGPO0_GPO0 0 ; ; -------------------------------------------------------------- ; DEMPHAC8 ; -DEMPHAC8 .assign 218 -DEMPHAC8_METRIC01 .assign 8 ; -DEMPHAC8_METRIC00 .assign 0 ; +%define DEMPHAC8 218 +%define DEMPHAC8_METRIC01 8 ; +%define DEMPHAC8_METRIC00 0 ; ; -------------------------------------------------------------- ; DEMPHAC9 ; -DEMPHAC9 .assign 219 -DEMPHAC9_METRIC11 .assign 8 ; -DEMPHAC9_METRIC10 .assign 0 ; +%define DEMPHAC9 219 +%define DEMPHAC9_METRIC11 8 ; +%define DEMPHAC9_METRIC10 0 ; ; -------------------------------------------------------------- ; DEMFB2P2 ; -DEMFB2P2 .assign 220 -DEMFB2P2_VAL .assign 0 ; +%define DEMFB2P2 220 +%define DEMFB2P2_VAL 0 ; ; -------------------------------------------------------------- ; DEMHDIS0 ; -DEMHDIS0 .assign 221 -DEMHDIS0_VAL .assign 0 ; +%define DEMHDIS0 221 +%define DEMHDIS0_VAL 0 ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;; mce_ram_bank.asm ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -.DEFINE LMD_DATA_SPACE 1 ;; LMD Data Space (Tables) -.DEFINE MDMCONF_IQDUMP 12 ;; Configuration Information -.DEFINE MAIN 48 ;; Main Program +%define LMD_DATA_SPACE 1 ;; LMD Data Space (Tables) +%define MDMCONF_IQDUMP 12 ;; Configuration Information +%define MAIN 48 ;; Main Program ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;; dbg.asm ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -__DBG__ .assign 1 +%define __DBG__ 1 ;;; Include file for handling debug print in TOPsm ;;; -------------------------------------------------------------------------------- ;;; Macro for handling code generated from DBG_PRINT0 -.MACRO _DBG0 cmd -.ifdef __DBG__ - lli \cmd, r0 +%macro _DBG0 1 +%ifdef __DBG__ + lli %1, r0 jsr _DBG_PRINT -.endif __DBG__ -.ENDM +%endif +%endmacro +%macro DBG_PRINT0 1 + _DBG0 %1 +%endmacro ;;; -------------------------------------------------------------------------------- ;;; Macro for handling code generated from DBG_PRINT1 -.MACRO _DBG1 cmd, reg0 -.ifdef __DBG__ - lli \cmd, r0 - output \reg0, MCETRCPAR0 +%macro _DBG1 2 +%ifdef __DBG__ + lli %1, r0 + output %2, MCETRCPAR0 jsr _DBG_PRINT -.endif __DBG__ -.ENDM +%endif +%endmacro ;;; -------------------------------------------------------------------------------- ;;; Macro for handling code generated from DBG_PRINT2 -.MACRO _DBG2 cmd, reg0, reg1 -.ifdef __DBG__ - lli \cmd, r0 - output \reg0, MCETRCPAR0 - output \reg1, MCETRCPAR1 +%macro _DBG2 3 +%ifdef __DBG__ + lli %1, r0 + output %2, MCETRCPAR0 + output %3, MCETRCPAR1 jsr _DBG_PRINT -.endif __DBG__ -.ENDM +%endif +%endmacro ;;; -------------------------------------------------------------------------------- ;;; Macro for inserting handling code for debug printing - insert once in source file -.MACRO DBG_FUNC -.ifdef __DBG__ +%macro DBG_FUNC 0 +%ifdef __DBG__ ;;; DBG_PRINT ;;; R0 = pkt hdr _DBG_PRINT: @@ -1790,6 +1793,6 @@ _DBG_PRINT_WAIT: bne _DBG_PRINT_WAIT outbset MCETRCSEND_SEND, MCETRCSEND rts -.endif __DBG__ -.ENDM +%endif +%endmacro diff --git a/isa.inc b/isa.inc new file mode 100644 index 0000000..6b4c13a --- /dev/null +++ b/isa.inc @@ -0,0 +1,244 @@ +; vim: set ft=nasm: + +r0 equ 0 +r1 equ 1 +r2 equ 2 +r3 equ 3 +r4 equ 4 +r5 equ 5 +r6 equ 6 +r7 equ 7 +r8 equ 8 +r9 equ 9 +r10 equ 10 +r11 equ 11 +r12 equ 12 +r13 equ 13 +r14 equ 14 +r15 equ 15 +pc equ 16 + +;;;;; alu ops ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +%macro or 2 + %ifid %1 + dw 0x0000 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4) + %else + dw 0x0200 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4) + %endif +%endmacro + +%macro and 2 + %ifid %1 + dw 0x0400 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4) + %else + dw 0x0600 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4) + %endif +%endmacro + +%macro xor 2 + %ifid %1 + dw 0x0800 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4) + %else + dw 0x0a00 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4) + %endif +%endmacro + +%macro tst 2 + %ifid %1 + dw 0x0c00 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4) + %else + dw 0x0e00 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4) + %endif +%endmacro + +%macro mov 2 + %ifid %1 + dw 0x1000 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4) + %else + dw 0x1200 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4) + %endif +%endmacro + +%macro add 2 + %ifid %1 + dw 0x1400 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4) + %else + dw 0x1600 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4) + %endif +%endmacro + +%macro sub 2 + %ifid %1 + dw 0x1800 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4) + %else + dw 0x1a00 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4) + %endif +%endmacro + +%macro cmp 2 + %ifid %1 + dw 0x1c00 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4) + %else + dw 0x1e00 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4) + %endif +%endmacro + +;;;;; bit ops ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +%macro btst 2 + dw 0x2200 | (((%2)&0xf) << 0) | (((%1)&0xf) << 4) +%endmacro + +%macro bclr 2 + dw 0x2a00 | (((%2)&0xf) << 0) | (((%1)&0xf) << 4) +%endmacro + +;;;;; shift ops ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +%macro sl0 2 + %ifid %1 + dw 0x3000 | (((%2)&0xf) << 0) | (((%1)&0xf) << 4) + %else + dw 0x3100 | (((%2)&0xf) << 0) | (((%1)&0xf) << 4) + %endif +%endmacro + +%macro sr0 2 + %ifid %1 + dw 0x3800 | (((%2)&0xf) << 0) | (((%1)&0xf) << 4) + %else + dw 0x3900 | (((%2)&0xf) << 0) | (((%1)&0xf) << 4) + %endif +%endmacro + +%macro srx 2 + %ifid %1 + dw 0x3c00 | (((%2)&0xf) << 0) | (((%1)&0xf) << 4) + %else + dw 0x3d00 | (((%2)&0xf) << 0) | (((%1)&0xf) << 4) + %endif +%endmacro + +;;;;; branch ops ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +%macro beq 1 + dw 0x4000 | ((((%1)&0x7ff)<<0)>>1) +%endmacro + +%macro bne 1 + dw 0x4400 | ((((%1)&0x7ff)<<0)>>1) +%endmacro + +%macro bmi 1 + dw 0x4800 | ((((%1)&0x7ff)<<0)>>1) +%endmacro + +%macro bpl 1 + dw 0x4c00 | ((((%1)&0x7ff)<<0)>>1) +%endmacro + +;;;;; jump+regind ops ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +%macro jmp 1 + %ifid %1 + ; jmp abs + dw 0x6000 | (((((%1)+0)&0x7ff)<<0)>>1) + %else + ; jmp (reg) + dw 0x6c00 | (((%1)&0xf)<<0) + %endif +%endmacro + +%macro jsr 1 + dw 0x6400 | (((((%1)+0)&0x7ff)<<0)>>1) +%endmacro + +%macro loop 1 + dw 0x6800 | (((((%1)+0)&0x7ff)<<0)>>1) +%endmacro + +%macro input 2 + %ifid %1 + ; input abs, reg + dw 0x8000 | (((%1)&0xff)<<4) | ((%2)&0xf) + %elifnum %1 + ; input abs, reg + dw 0x8000 | (((%1)&0xff)<<4) | ((%2)&0xf) + %else + ; input (reg), reg + dw 0x6d00 | (((%2)&0xf)<<0) | (((%1)&0xf)<<4) + %endif +%endmacro + +%macro output 2 + %ifid %2 + ; output reg, abs + dw 0x9000 | (((%2)&0xff)<<4) | ((%1)&0xf) + %elifnum %2 + ; output reg, abs + dw 0x9000 | (((%2)&0xff)<<4) | ((%1)&0xf) + %else + ; output reg, (reg) + dw 0x6e00 | (((%1)&0xf)<<0) | (((%2)&0xf)<<4) + %endif +%endmacro + +%macro lmd 2 + %ifid %1 + ; lmd abs, reg + dw 0x7800 | ((((%1)&0xff)<<4)>>1) | (((%2)&0xf)<<0) + %elifnum %1 + ; lmd abs, reg + dw 0x7800 | ((((%1)&0xff)<<4)>>1) | (((%2)&0xf)<<0) + %else + ; lmd (reg), reg + dw 0x6f00 | (((%2)&0xf)<<0) | (((%1)&0xf)<<4) + %endif +%endmacro + +;;;;; I/O + misc ops ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +%macro rts 0 + dw 0x7000 +%endmacro + +%macro wait 0 + dw 0x7100 +%endmacro + +%macro outclr 1 + dw 0x7200 | ((%1)&0xff) +%endmacro + +%macro outset 1 + dw 0x7300 | ((%1)&0xff) +%endmacro + +;;;;; I/O bit ops ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +%macro outbclr 2 + dw 0xa000 | ((%1)&0xf) | (((%2)&0xff)<<4) +%endmacro +; this is a bug in the original source! this shouldn't happen! +%macro outclr 2 + outclr %1 + ;outbclr %1, %2 +%endmacro + +%macro outbset 2 + dw 0xb000 | ((%1)&0xf) | (((%2)&0xff)<<4) +%endmacro +;%macro outset 2 +; outbset %1, %2 +;%endmacro + +;;;;; lli ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +%macro lli 2 + dw 0xc000 | (((%1)&0x3ff)<<4) | (((%2)&0xf)<<0) +%endmacro + +%macro nop 0 + or r0, r0 +%endmacro diff --git a/nasm.sh b/nasm.sh new file mode 100755 index 0000000..4ec8790 --- /dev/null +++ b/nasm.sh @@ -0,0 +1,7 @@ +#!/usr/bin/env bash + +set -e +set -x + +yasm -fbin -i. -lreasm.lst -oreasm.bin text.asm +hexdump -C reasm.bin > reasm.hd diff --git a/text.asm b/text.asm index 61c1928..81aa764 100644 --- a/text.asm +++ b/text.asm @@ -1,17 +1,20 @@ ; vim: set ft=nasm: -.ORG 0 +%include 'isa.inc' +%include 'defs.inc' + +org 0 jmp START_PROCESS -.ORG LMD_DATA_SPACE +;org LMD_DATA_SPACE DEMENABLE0_RX_IQDUMP: - .DATA 0x2FCF ; DEMENABLE0 settings (felp, frac,fidc,chfi,bdec,iqmc,mge2,codc,cmix) + dw 0x2FCF ; DEMENABLE0 settings (felp, frac,fidc,chfi,bdec,iqmc,mge2,codc,cmix) DEMENABLE1_RX_IQDUMP: - .DATA 0x3F9D ; DEMENABLE1 + dw 0x3F9D ; DEMENABLE1 VITACCCTRL_REG_DEFAULT: ; Transp, downsample + IIR filter setting - .DATA 0x0001 ; [7:0]=0: no filter + dw 0x0001 ; [7:0]=0: no filter ; [7:0]=1: k=1/2 ; [7:0]=2: k=1/4 ; [7:0]=3: k=1/8 @@ -22,65 +25,65 @@ VITACCCTRL_REG_DEFAULT: ; Transp, downsample + IIR filter setting ; [15: 8]=4, transparent downsample by sixteen DEMC1BE0_MASKA_BITS: ; Various bit masks - .DATA 0x003F + dw 0x003F IQDUMP_MASK_BITS_15_8: - .DATA 0xFF00 + dw 0xFF00 IQDUMP_TEST_MAX_VAL: - .DATA 0x0FFF + dw 0x0FFF IQDUMP_MAX_POS_VAL: - .DATA 0x07FF ; 2^11 - 1 = 2047 + dw 0x07FF ; 2^11 - 1 = 2047 IQDUMP_MIN_NEG_VAL: - .DATA 0xF800 ; -2048 + dw 0xF800 ; -2048 TRANSPARENT_CAPT: - .DATA 0x0300 ; Combined RDCAPT0_DEMPDIF0 and RDCAPT0_DEMFIFE2 + dw 0x0300 ; Combined RDCAPT0_DEMPDIF0 and RDCAPT0_DEMFIFE2 CORR_DEFG_THR: - .DATA 0x8080 + dw 0x8080 TX_TONE_COUNT: - .DATA 0x06 ; Default number of clock ticks for tone in front of preamble + dw 0x06 ; Default number of clock ticks for tone in front of preamble -.ORG MDMCONF_IQDUMP +;org MDMCONF_IQDUMP -.DATA 0x0003 ; ADCDIGCONF -.DATA 0x0017 ; MODPRECTRL -.DATA 0x3D1F ; MODSYMMAP0 -.DATA 0x0000 ; MODSYMMAP1 -.DATA 0x0000 ; MODSOFTTX -.DATA 0x0800 ; MDMBAUD -.DATA 0x000F ; MDMBAUDPRE -.DATA 0x0000 ; MODMAIN -.DATA 0x0387 ; DEMMISC0 -.DATA 0x0000 ; DEMMISC1 -.DATA 0x4074 ; DEMMISC2 -.DATA 0x0043 ; DEMMISC3 -.DATA 0x8000 ; DEMIQMC0 -.DATA 0x0082 ; DEMDSBU -.DATA 0x0080 ; DEMDSBU2 -.DATA 0x06F0 ; DEMCODC0 -.DATA 0x0000 ; DEMFIDC0 -.DATA 0x091E ; DEMFEXB0 -.DATA 0x0510 ; DEMDSXB0 -.DATA 0x0054 ; DEMD2XB0 -.DATA 0x0007 ; DEMFIFE0 -.DATA 0x0000 ; DEMMAFI0 -.DATA 0x5014 ; DEMMAFI1 -.DATA 0x0050 ; DEMMAFI2 -.DATA 0x0000 ; DEMMAFI3 -.DATA 0xC02F ; DEMC1BE0 -.DATA 0x0C30 ; DEMC1BE1 -.DATA 0x017F ; DEMC1BE2 -.DATA 0x0000 ; DEMC1BE10 -.DATA 0x0000 ; DEMC1BE11 -.DATA 0x0000 ; DEMC1BE12 -.DATA 0x0000 ; MDMSYNC0 -.DATA 0x0000 ; MDMSYNC1 -.DATA 0x0000 ; MDMSYNC2 -.DATA 0xAA00 ; MDMSYNC3 -.DATA 0x0000 ; DEMSWQU0 +dw 0x0003 ; ADCDIGCONF +dw 0x0017 ; MODPRECTRL +dw 0x3D1F ; MODSYMMAP0 +dw 0x0000 ; MODSYMMAP1 +dw 0x0000 ; MODSOFTTX +dw 0x0800 ; MDMBAUD +dw 0x000F ; MDMBAUDPRE +dw 0x0000 ; MODMAIN +dw 0x0387 ; DEMMISC0 +dw 0x0000 ; DEMMISC1 +dw 0x4074 ; DEMMISC2 +dw 0x0043 ; DEMMISC3 +dw 0x8000 ; DEMIQMC0 +dw 0x0082 ; DEMDSBU +dw 0x0080 ; DEMDSBU2 +dw 0x06F0 ; DEMCODC0 +dw 0x0000 ; DEMFIDC0 +dw 0x091E ; DEMFEXB0 +dw 0x0510 ; DEMDSXB0 +dw 0x0054 ; DEMD2XB0 +dw 0x0007 ; DEMFIFE0 +dw 0x0000 ; DEMMAFI0 +dw 0x5014 ; DEMMAFI1 +dw 0x0050 ; DEMMAFI2 +dw 0x0000 ; DEMMAFI3 +dw 0xC02F ; DEMC1BE0 +dw 0x0C30 ; DEMC1BE1 +dw 0x017F ; DEMC1BE2 +dw 0x0000 ; DEMC1BE10 +dw 0x0000 ; DEMC1BE11 +dw 0x0000 ; DEMC1BE12 +dw 0x0000 ; MDMSYNC0 +dw 0x0000 ; MDMSYNC1 +dw 0x0000 ; MDMSYNC2 +dw 0xAA00 ; MDMSYNC3 +dw 0x0000 ; DEMSWQU0 MDMCONF_IQDUMP_END: - .ORG MAIN +;org MAIN START_PROCESS: ;; Do hard initialization of all submodules of the modem @@ -214,7 +217,7 @@ MDMCONF_IQDUMP_END: MCFG_Entry: ; NOTE: = lli text, r0; jsr _DBG_PRINT - DBG_PRINT0 "MCFG - IQ Dump Configuration" + DBG_PRINT0 3;"MCFG - IQ Dump Configuration" lli MDMCONF_IQDUMP, r1 ; Points R1 to the WMBUS data lli MDMCONF_IQDUMP_FIRST_REG, r2 ; Points to the first IO address for configiration lli MDMCONF_IQDUMP_LAST_REG, r0 ; Points to the last of the IO address @@ -414,7 +417,7 @@ MDMCONF_IQDUMP_END: outset MCEEVENTCLR1 ;; Normal mode (1bit per symbol) proceeds here - DBG_PRINT0 "IQDump___ NoFEC, TX Started" + DBG_PRINT0 4;"IQDump___ NoFEC, TX Started" lli 0x10, r0 ; MDMFIFORDCTRL, 1 bits reads, from modem output r0, MDMFIFORDCTRL jsr MTX_Iqdump_Common_Preamble ; Send Preamble @@ -434,7 +437,7 @@ MDMCONF_IQDUMP_END: outset MCEEVENTCLR0 outset MCEEVENTCLR1 - DBG_PRINT0 "IQDump___ Multi-level FSK TX Mode" + DBG_PRINT0 5;"IQDump___ Multi-level FSK TX Mode" lli 0x03, r0 ; 4 bit reads, from register output r0, MDMFIFORDCTRL ;; Set modctrl to read from modsofftx: @@ -467,7 +470,7 @@ MDMCONF_IQDUMP_END: cmp 2, r0 bne MTX_MFSK_ToneLoop ;; At this point, we can actually read data from the FIFO, 4 bits at a time - DBG_PRINT0 "Starting MFSK Symbol Loop" + DBG_PRINT0 6;"Starting MFSK Symbol Loop" MTX_MFSK_SymbolLoop: wait outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTCLR1 ; Clear CLKEN Baud @@ -489,7 +492,7 @@ MDMCONF_IQDUMP_END: beq MTX_MFSK_SymbolLoop ;; ;; FIFO is now empty, so terminate - DBG_PRINT0 "Stopping MFSK Symbol Loop" + DBG_PRINT0 7;"Stopping MFSK Symbol Loop" outbclr MODCTRL_SOFTTXENABLE, MODCTRL jsr MTX_Iqdump_Termination jmp CMD_OK_END @@ -507,7 +510,7 @@ MDMCONF_IQDUMP_END: outset MCEEVENTCLR1 jsr MRX_SETUP - DBG_PRINT0 "########################### Blind REGISTER MODE -> IQ Dump starting at once ########################" + DBG_PRINT0 8;"########################### Blind REGISTER MODE -> IQ Dump starting at once ########################" outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; enable the clkenbaud_4f event lli 3, r5 ; to trigger capture of I and Q @@ -555,7 +558,7 @@ MDMCONF_IQDUMP_END: loop LOOP_SAMPLES_FIFO_BLIND_WAIT - DBG_PRINT0 "########################### Blind RFC FIFO Mode -> IQ Dump starting at once (DataRate <= 12,5 kbps) ########################" + DBG_PRINT0 9;"########################### Blind RFC FIFO Mode -> IQ Dump starting at once (DataRate <= 12,5 kbps) ########################" lli 3, r5 ; to trigger capture of I and Q LOOP_SAMPLES_FIFO_BLIND: @@ -629,7 +632,7 @@ MDMCONF_IQDUMP_END: wait loop LOOP_SAMPLES_TRANSPARENT_FIFO_WAIT - DBG_PRINT0 "########################### Transparent FIFO Mode -> PDIFF streaming starting at once ########################" + DBG_PRINT0 10;"########################### Transparent FIFO Mode -> PDIFF streaming starting at once ########################" lmd TRANSPARENT_CAPT, r13 ; Combined RDCAPT0_DEMPDIF0 and RDCAPT0_DEMFIFE2 input VITACCCTRL, r14 ; Capture for later use, time optimization @@ -644,7 +647,7 @@ MDMCONF_IQDUMP_END: btst 1, r0 bne CAPT_FREQUENCY outbset 1, RFESEND ; Notify by bit 1 in RFESEND (i.e. Stop AGC) - DBG_PRINT0 "########################### Transparent FIFO Mode Stop AGC ########################" + DBG_PRINT0 11;"########################### Transparent FIFO Mode Stop AGC ########################" CAPT_FREQUENCY: @@ -757,7 +760,7 @@ MDMCONF_IQDUMP_END: ;;; IQ dump start after SFD detection ;;; MRX_Entry_REG_SYNC: - DBG_PRINT0 "########################### IQ Dump REGISTER MODE, RX started, Wait for Sync ########################" + DBG_PRINT0 12;"########################### IQ Dump REGISTER MODE, RX started, Wait for Sync ########################" ;;; Just to be sure those interrupts are disabled, there is no normal termination. outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; disable the clkenbaud_4f event outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 ; disable correlation event @@ -782,7 +785,7 @@ MDMCONF_IQDUMP_END: DUMP_SAMPLES: outbset 1, RFESEND ; Notify by bit 1 in RFESEND (sync found) - DBG_PRINT0 "########################### Sync Found REGISTER MODE -> IQ Dump starting ########################" + DBG_PRINT0 13;"########################### Sync Found REGISTER MODE -> IQ Dump starting ########################" outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2 ; clear the event flag outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 ; disable correlation event outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; enable the clkenbaud_4f event @@ -803,7 +806,7 @@ MDMCONF_IQDUMP_END: ;;; - IQ dump start after SFD detection ;;; MRX_Entry_FIFO_SYNC: - DBG_PRINT0 "########################### IQ Dump through RFC FIFO, RX started, Wait for Sync (DataRate <= 12.5 kbps) ########################" + DBG_PRINT0 14;"########################### IQ Dump through RFC FIFO, RX started, Wait for Sync (DataRate <= 12.5 kbps) ########################" ;;; Just to be sure those interrupts are disabled, there is no normal termination. outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; disable the clkenbaud_4f event outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 ; disable correlation event @@ -840,7 +843,7 @@ MDMCONF_IQDUMP_END: outbset MCESTROBES0_EVENT0, MCESTROBES0 ; signal Sync Found outbset 1, RFESEND ; Notify by bit 1 in RFESEND (sync found) - DBG_PRINT0 "########################### Sync Found RFC FIFO MODE-> IQ samples through FIFO starting ########################" + DBG_PRINT0 15;"########################### Sync Found RFC FIFO MODE-> IQ samples through FIFO starting ########################" outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2 ; clear the event flag outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 ; disable correlation event outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; enable the clkenbaud_4 event @@ -915,7 +918,7 @@ MDMCONF_IQDUMP_END: jmp MRX_SETUP ; Go back to test received event RFE_Started: - DBG_PRINT0 "########################### RX Started ########################" + DBG_PRINT0 16;"########################### RX Started ########################" outbset MCEEVENT0_CPEFWEVENT0, MCEEVENTCLR0 ; Clear any pending CPEFWEVENT0 @@ -1075,7 +1078,7 @@ MDMCONF_IQDUMP_END: sl0 8, r4 or r0,r4 output r4, MDMSTATUS ; Warning: CPE use MDMSTATUS[1:0] for CMD_DONE checking - DBG_PRINT0 "All bits received, MCE Ending" + DBG_PRINT0 17;"All bits received, MCE Ending" ;; Hard init of all modules except FIFO outset TIMCTRL ; outclr TIMCTRL ; diff --git a/text.lst b/text.lst new file mode 100644 index 0000000..ac9e819 --- /dev/null +++ b/text.lst @@ -0,0 +1,726 @@ +0000: 6030 jmp 0x0030 jmp START_PROCESS +0001: 2fcf .DATA 0x2FCF +0002: 3f9d .DATA 0x3F9D +0003: 0001 .DATA 0x0001 +0004: 003f .DATA 0x003F +0005: ff00 .DATA 0xFF00 +0006: 0fff .DATA 0x0FFF +0007: 07ff .DATA 0x07FF +0008: f800 .DATA 0xF800 +0009: 0300 .DATA 0x0300 +000a: 8080 .DATA 0x8080 +000b: 0006 .DATA 0x06 +000c: 0003 .DATA 0x0003 +000d: 0017 .DATA 0x0017 +000e: 3d1f .DATA 0x3D1F +000f: 0000 .DATA 0x0000 +0010: 0000 .DATA 0x0000 +0011: 0800 .DATA 0x0800 +0012: 000f .DATA 0x000F +0013: 0000 .DATA 0x0000 +0014: 0387 .DATA 0x0387 +0015: 0000 .DATA 0x0000 +0016: 4074 .DATA 0x4074 +0017: 0043 .DATA 0x0043 +0018: 8000 .DATA 0x8000 +0019: 0082 .DATA 0x0082 +001a: 0080 .DATA 0x0080 +001b: 06f0 .DATA 0x06F0 +001c: 0000 .DATA 0x0000 +001d: 091e .DATA 0x091E +001e: 0510 .DATA 0x0510 +001f: 0054 .DATA 0x0054 +0020: 0007 .DATA 0x0007 +0021: 0000 .DATA 0x0000 +0022: 5014 .DATA 0x5014 +0023: 0050 .DATA 0x0050 +0024: 0000 .DATA 0x0000 +0025: c02f .DATA 0xC02F +0026: 0c30 .DATA 0x0C30 +0027: 017f .DATA 0x017F +0028: 0000 .DATA 0x0000 +0029: 0000 .DATA 0x0000 +002a: 0000 .DATA 0x0000 +002b: 0000 .DATA 0x0000 +002c: 0000 .DATA 0x0000 +002d: 0000 .DATA 0x0000 +002e: aa00 .DATA 0xAA00 +002f: 0000 .DATA 0x0000 +0030: 7223 outclr 0x23 outclr RFESEND +0031: 66ca jsr 0x02ca jsr MODCTRL_CLR +0032: a35d outbclr 13, 0x35 outbclr DEMMISC2_MLSERUN,DEMMISC2 +0033: a4e5 outbclr 5, 0x4e outbclr DEMSWQU0_RUN, DEMSWQU0 +0034: 7303 outset 0x03 outset DEMENABLE0 +0035: 7305 outset 0x05 outset DEMINIT0 +0036: 7203 outclr 0x03 outclr DEMENABLE0 +0037: 7304 outset 0x04 outset DEMENABLE1 +0038: 7306 outset 0x06 outset DEMINIT1 +0039: 7204 outclr 0x04 outclr DEMENABLE1 +003a: 7391 outset 0x91 outset TIMCTRL +003b: 7291 outclr 0x91 outclr TIMCTRL +003c: b008 outbset 8, 0x00 outbset MDMENABLE_FB2PLL, MDMENABLE +003d: ffc0 lli 0x3fc, r0 lli 0x3FC, r0 +003e: 9010 output r0, 0x01 output r0, MDMINIT +003f: a008 outbclr 8, 0x00 outbclr MDMENABLE_FB2PLL, MDMENABLE +0040: 720d outclr 0x0d outclr MCEEVENTMSK0 +0041: 720e outclr 0x0e outclr MCEEVENTMSK1 +0042: 720f outclr 0x0f outclr MCEEVENTMSK2 +0043: 7210 outclr 0x10 outclr MCEEVENTMSK3 +0044: b0d0 outbset 0, 0x0d outbset MCEEVENT0_MDMAPI_WR, MCEEVENTMSK0 +0045: 7100 wait wait +0046: b110 outbset 0, 0x11 outbset MCEEVENT0_MDMAPI_WR, MCEEVENTCLR0 +0047: a0d0 outbclr 0, 0x0d outbclr MCEEVENT0_MDMAPI_WR, MCEEVENTMSK0 +0048: 721b outclr 0x1b outclr MDMSTATUS +0049: 8162 input 0x16, r2 input MDMAPI, r2 +004a: 1020 mov r2, r0 mov r2, r0 +004b: 3952 sr0 5, r2 sr0 5, r2 +004c: 0670 and 7, r0 and 7, r0 +004d: 0020 or r2, r0 or r2, r0 +004e: 1630 add 3, r0 add 3, r0 +004f: 1101 mov pc, r1 mov pc, r1 +0050: 1401 add r0, r1 add r0, r1 +0051: 6c01 jmp (r1) jmp (r1) +0052: 6087 jmp 0x0087 jmp MNOP_Entry +0053: 6088 jmp 0x0088 jmp MCFG_Entry +0054: 6104 jmp 0x0104 jmp MTX_Entry +0055: 613e jmp 0x013e jmp MRX_Entry_REG_BLIND +0056: 6087 jmp 0x0087 jmp MNOP_Entry +0057: 6087 jmp 0x0087 jmp MNOP_Entry +0058: 6087 jmp 0x0087 jmp MNOP_Entry +0059: 6087 jmp 0x0087 jmp MNOP_Entry +005a: 6087 jmp 0x0087 jmp MNOP_Entry +005b: 6088 jmp 0x0088 jmp MCFG_Entry +005c: 6104 jmp 0x0104 jmp MTX_Entry +005d: 61e4 jmp 0x01e4 jmp MRX_Entry_REG_SYNC +005e: 6087 jmp 0x0087 jmp MNOP_Entry +005f: 6087 jmp 0x0087 jmp MNOP_Entry +0060: 6087 jmp 0x0087 jmp MNOP_Entry +0061: 6087 jmp 0x0087 jmp MNOP_Entry +0062: 6087 jmp 0x0087 jmp MNOP_Entry +0063: 6088 jmp 0x0088 jmp MCFG_Entry +0064: 6104 jmp 0x0104 jmp MTX_Entry +0065: 614e jmp 0x014e jmp MRX_Entry_FIFO_BLIND +0066: 6087 jmp 0x0087 jmp MNOP_Entry +0067: 6087 jmp 0x0087 jmp MNOP_Entry +0068: 6087 jmp 0x0087 jmp MNOP_Entry +0069: 6087 jmp 0x0087 jmp MNOP_Entry +006a: 6087 jmp 0x0087 jmp MNOP_Entry +006b: 6088 jmp 0x0088 jmp MCFG_Entry +006c: 6104 jmp 0x0104 jmp MTX_Entry +006d: 6200 jmp 0x0200 jmp MRX_Entry_FIFO_SYNC +006e: 6087 jmp 0x0087 jmp MNOP_Entry +006f: 6087 jmp 0x0087 jmp MNOP_Entry +0070: 6087 jmp 0x0087 jmp MNOP_Entry +0071: 6087 jmp 0x0087 jmp MNOP_Entry +0072: 6087 jmp 0x0087 jmp MNOP_Entry +0073: 6088 jmp 0x0088 jmp MCFG_Entry +0074: 6104 jmp 0x0104 jmp MTX_Entry +0075: 6186 jmp 0x0186 jmp MRX_Entry_TRANSPARENT_FIFO +0076: 6087 jmp 0x0087 jmp MNOP_Entry +0077: 6087 jmp 0x0087 jmp MNOP_Entry +0078: 6087 jmp 0x0087 jmp MNOP_Entry +0079: 6087 jmp 0x0087 jmp MNOP_Entry +007a: 6088 jmp 0x0088 jmp MCFG_Entry +007b: 6112 jmp 0x0112 jmp MTX_MFSK +007c: 614e jmp 0x014e jmp MRX_Entry_FIFO_BLIND +007d: 1210 mov 1, r0 mov CMD_OK, r0 +007e: 7223 outclr 0x23 outclr RFESEND +007f: 7311 outset 0x11 outset MCEEVENTCLR0 +0080: 7312 outset 0x12 outset MCEEVENTCLR1 +0081: 7313 outset 0x13 outset MCEEVENTCLR2 +0082: 81b1 input 0x1b, r1 input MDMSTATUS, r1 +0083: 0010 or r1, r0 or r1, r0 +0084: 91b0 output r0, 0x1b output r0, MDMSTATUS +0085: b070 outbset 0, 0x07 outbset 0, MCESTROBES0 +0086: 6044 jmp 0x0044 jmp CMD_PROC +0087: 607d jmp 0x007d jmp CMD_OK_END +0088: c030 lli 0x3, r0 lli "MCFG - IQ Dump Configuration" +0088: 66d0 jsr 0x02d0 jsr _DBG_PRINT +008a: c0c1 lli 0xc, r1 lli MDMCONF_IQDUMP, r1 +008b: c2b2 lli 0x2b, r2 lli MDMCONF_IQDUMP_FIRST_REG, r2 +008c: c4e0 lli 0x4e, r0 lli MDMCONF_IQDUMP_LAST_REG, r0 +008d: 1820 sub r2, r0 sub r2,r0 +008e: 6f13 lmd (r1), r3 lmd (r1), r3 +008f: 6e23 output r3, (r2) output r3, (r2) +0090: 1611 add 1, r1 add 1, r1 +0091: 1612 add 1, r2 add 1, r2 +0092: 688e loop 0x008e loop MCFG_Iqdump_Loop +0093: 7830 lmd 0x3, r0 lmd VITACCCTRL_REG_DEFAULT,r0 +0094: 99c0 output r0, 0x9c output r0,VITACCCTRL +0095: 78a0 lmd 0xa, r0 lmd CORR_DEFG_THR, r0 +0096: 9480 output r0, 0x48 output r0, DEMC1BE11 +0097: 9490 output r0, 0x49 output r0, DEMC1BE12 +0098: c4f2 lli 0x4f, r2 lli DEMFB2P0, r2 +0099: c750 lli 0x75, r0 lli VITCTRL, r0 +009a: 1820 sub r2, r0 sub r2,r0 +009b: 40a0 beq 0x00a0 beq ZERO_DONE +009c: 1203 mov 0, r3 mov 0, r3 +009d: 6e23 output r3, (r2) output r3, (r2) +009e: 1612 add 1, r2 add 1, r2 +009f: 689d loop 0x009d loop ZERO_LOOP +00a0: 78b0 lmd 0xb, r0 lmd TX_TONE_COUNT, r0 +00a1: 9990 output r0, 0x99 output r0, BRMACC0 +00a2: 7263 outclr 0x63 outclr MODCTRL +00a3: b63c outbset 12, 0x63 outbset MODCTRL_CDC_COL_RESTART, MODCTRL +00a4: 607d jmp 0x007d jmp CMD_OK_END +00a5: 8190 input 0x19, r0 input MDMCMDPAR2, r0 +00a6: 9640 output r0, 0x64 output r0, MODPREAMBLE +00a7: 8170 input 0x17, r0 input MDMCMDPAR0, r0 +00a8: 3980 sr0 8, r0 sr0 8, r0 +00a9: 2a70 bclr 7, r0 bclr 7, r0 +00aa: 1001 mov r0, r1 mov r0, r1 +00ab: 1611 add 1, r1 add 1, r1 +00ac: 84a2 input 0x4a, r2 input MDMSYNC0, r2 +00ad: 84b4 input 0x4b, r4 input MDMSYNC1, r4 +00ae: c0f3 lli 0xf, r3 lli 15, r3 +00af: c0f5 lli 0xf, r5 lli 15, r5 +00b0: c200 lli 0x20, r0 lli 32, r0 +00b1: 1c01 cmp r0, r1 cmp r0, r1 +00b2: 40c9 beq 0x00c9 beq MTX_Iqdump_Common_Preamble_RFESEND +00b3: c100 lli 0x10, r0 lli 16, r0 +00b4: 1c10 cmp r1, r0 cmp r1, r0 +00b5: 40bf beq 0x00bf beq MTX_Iqdump_Common_Preamble_16bitSyncWord +00b6: 4cc1 bpl 0x00c1 bpl MTX_Iqdump_Common_Preamble_ShortSyncWord +00b7: 1013 mov r1, r3 mov r1, r3 +00b8: 1803 sub r0, r3 sub r0, r3 +00b9: 1830 sub r3, r0 sub r3, r0 +00ba: 1a13 sub 1, r3 sub 1, r3 +00bb: 1a10 sub 1, r0 sub 1, r0 +00bc: 3912 sr0 1, r2 sr0 1, r2 +00bd: 68bc loop 0x00bc loop MTX_Iqdump_Common_Preamble_SyncWord_ShiftLoop1 +00be: 60c9 jmp 0x00c9 jmp MTX_Iqdump_Common_Preamble_RFESEND +00bf: 13f3 mov 31, r3 mov 0x1F, r3 +00c0: 60c9 jmp 0x00c9 jmp MTX_Iqdump_Common_Preamble_RFESEND +00c1: 13f3 mov 31, r3 mov 0x1F, r3 +00c2: 1015 mov r1, r5 mov r1, r5 +00c3: c100 lli 0x10, r0 lli 16, r0 +00c4: 1850 sub r5, r0 sub r5, r0 +00c5: 1a15 sub 1, r5 sub 1, r5 +00c6: 1a10 sub 1, r0 sub 1, r0 +00c7: 3914 sr0 1, r4 sr0 1, r4 +00c8: 68c7 loop 0x00c7 loop MTX_Iqdump_Common_Preamble_SyncWord_ShiftLoop2 +00c9: b0e8 outbset 8, 0x0e outbset MCEEVENT1_RAT_EVENT0, MCEEVENTMSK1 +00ca: 7100 wait wait +00cb: b128 outbset 8, 0x12 outbset MCEEVENT1_RAT_EVENT0, MCEEVENTCLR1 +00cc: a0e8 outbclr 8, 0x0e outbclr MCEEVENT1_RAT_EVENT0, MCEEVENTMSK1 +00cd: b230 outbset 0, 0x23 outbset 0,RFESEND +00ce: b910 outbset 0, 0x91 outbset TIMCTRL_ENABLETIMER, TIMCTRL +00cf: 8990 input 0x99, r0 input BRMACC0, r0 +00d0: 9930 output r0, 0x93 output r0, TIMPERIOD +00d1: b111 outbset 1, 0x11 outbset MCEEVENT0_TIMER_IRQ, MCEEVENTCLR0 +00d2: b0d1 outbset 1, 0x0d outbset MCEEVENT0_TIMER_IRQ, MCEEVENTMSK0 +00d3: 7100 wait wait +00d4: b002 outbset 2, 0x00 outbset MDMENABLE_TIMEBASE, MDMENABLE +00d5: b012 outbset 2, 0x01 outbset MDMINIT_TIMEBASE, MDMINIT +00d6: b111 outbset 1, 0x11 outbset MCEEVENT0_TIMER_IRQ, MCEEVENTCLR0 +00d7: a0d1 outbclr 1, 0x0d outbclr MCEEVENT0_TIMER_IRQ, MCEEVENTMSK0 +00d8: 7291 outclr 0x91 outclr TIMCTRL +00d9: b630 outbset 0, 0x63 outbset MODCTRL_PREAMBLEINSERT, MODCTRL +00da: b003 outbset 3, 0x00 outbset MDMENABLE_MODULATOR, MDMENABLE +00db: b013 outbset 3, 0x01 outbset MDMINIT_MODULATOR, MDMINIT +00dc: 722c outclr 0x2c outclr MODPRECTRL +00dd: b0e0 outbset 0, 0x0e outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTMSK1 +00de: 7100 wait wait +00df: b120 outbset 0, 0x12 outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTCLR1 +00e0: 8170 input 0x17, r0 input MDMCMDPAR0, r0 +00e1: 92c0 output r0, 0x2c output r0, MODPRECTRL +00e2: 7100 wait wait +00e3: b120 outbset 0, 0x12 outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTCLR1 +00e4: 8170 input 0x17, r0 input MDMCMDPAR0, r0 +00e5: 22f0 btst 15, r0 btst 15, r0 +00e6: 44e2 bne 0x00e2 bne MTX_Iqdump_Common_Preamble_Loop +00e7: 13f0 mov 31, r0 mov 0x1F, r0 +00e8: 1c03 cmp r0, r3 cmp r0, r3 +00e9: 40ee beq 0x00ee beq MTX_Iqdump_Common_Preamble_Send_One_SW +00ea: 92c3 output r3, 0x2c output r3, MODPRECTRL +00eb: 9642 output r2, 0x64 output r2, MODPREAMBLE +00ec: 7100 wait wait +00ed: b120 outbset 0, 0x12 outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTCLR1 +00ee: 92c5 output r5, 0x2c output r5, MODPRECTRL +00ef: 9644 output r4, 0x64 output r4, MODPREAMBLE +00f0: 7100 wait wait +00f1: b120 outbset 0, 0x12 outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTCLR1 +00f2: b0e0 outbset 0, 0x0e outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTMSK1 +00f3: a630 outbclr 0, 0x63 outbclr MODCTRL_PREAMBLEINSERT, MODCTRL +00f4: 7000 rts rts +00f5: a0e1 outbclr 1, 0x0e outbclr MCEEVENT1_CLKEN_BAUD, MCEEVENTMSK1 +00f6: c030 lli 0x3, r0 lli 0x03,r0 +00f7: 9910 output r0, 0x91 output r0, TIMCTRL +00f8: c040 lli 0x4, r0 lli 0x04, r0 +00f9: 9930 output r0, 0x93 output r0, TIMPERIOD +00fa: b111 outbset 1, 0x11 outbset MCEEVENT0_TIMER_IRQ, MCEEVENTCLR0 +00fb: b0d1 outbset 1, 0x0d outbset MCEEVENT0_TIMER_IRQ, MCEEVENTMSK0 +00fc: 7100 wait wait +00fd: b111 outbset 1, 0x11 outbset MCEEVENT0_TIMER_IRQ, MCEEVENTCLR0 +00fe: a0d1 outbclr 1, 0x0d outbclr MCEEVENT0_TIMER_IRQ, MCEEVENTMSK0 +00ff: 7291 outclr 0x91 outclr TIMCTRL +0100: a003 outbclr 3, 0x00 outbclr MDMENABLE_MODULATOR, MDMENABLE +0101: a002 outbclr 2, 0x00 outbclr MDMENABLE_TIMEBASE, MDMENABLE +0102: a230 outbclr 0, 0x23 outbclr 0, RFESEND +0103: 7000 rts rts +0104: 7311 outset 0x11 outset MCEEVENTCLR0 +0105: 7312 outset 0x12 outset MCEEVENTCLR1 +0106: c040 lli 0x4, r0 lli "IQDump___ NoFEC, TX Started" +0106: 66d0 jsr 0x02d0 jsr _DBG_PRINT +0108: c100 lli 0x10, r0 lli 0x10, r0 +0109: 91f0 output r0, 0x1f output r0, MDMFIFORDCTRL +010a: 64a5 jsr 0x00a5 jsr MTX_Iqdump_Common_Preamble +010b: b633 outbset 3, 0x63 outbset MODCTRL_FECENABLE, MODCTRL +010c: b113 outbset 3, 0x11 outbset MCEEVENT0_FIFO_ERR_UNDERFLOW, MCEEVENTCLR0 +010d: b0d3 outbset 3, 0x0d outbset MCEEVENT0_FIFO_ERR_UNDERFLOW, MCEEVENTMSK0 +010e: 7100 wait wait +010f: a0d3 outbclr 3, 0x0d outbclr MCEEVENT0_FIFO_ERR_UNDERFLOW, MCEEVENTMSK0 +0110: 64f5 jsr 0x00f5 jsr MTX_Iqdump_Termination +0111: 607d jmp 0x007d jmp CMD_OK_END +0112: 7311 outset 0x11 outset MCEEVENTCLR0 +0113: 7312 outset 0x12 outset MCEEVENTCLR1 +0114: c050 lli 0x5, r0 lli "IQDump___ Multi-level FSK TX Mode" +0114: 66d0 jsr 0x02d0 jsr _DBG_PRINT +0116: c030 lli 0x3, r0 lli 0x03, r0 +0117: 91f0 output r0, 0x1f output r0, MDMFIFORDCTRL +0118: b634 outbset 4, 0x63 outbset MODCTRL_SOFTTXENABLE, MODCTRL +0119: b0e8 outbset 8, 0x0e outbset MCEEVENT1_RAT_EVENT0, MCEEVENTMSK1 +011a: 7100 wait wait +011b: b128 outbset 8, 0x12 outbset MCEEVENT1_RAT_EVENT0, MCEEVENTCLR1 +011c: a0e8 outbclr 8, 0x0e outbclr MCEEVENT1_RAT_EVENT0, MCEEVENTMSK1 +011d: b230 outbset 0, 0x23 outbset 0,RFESEND +011e: b002 outbset 2, 0x00 outbset MDMENABLE_TIMEBASE, MDMENABLE +011f: b012 outbset 2, 0x01 outbset MDMINIT_TIMEBASE, MDMINIT +0120: b003 outbset 3, 0x00 outbset MDMENABLE_MODULATOR, MDMENABLE +0121: b013 outbset 3, 0x01 outbset MDMINIT_MODULATOR, MDMINIT +0122: 1200 mov 0, r0 mov 0, r0 +0123: 92f0 output r0, 0x2f output r0, MODSOFTTX +0124: b121 outbset 1, 0x12 outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTCLR1 +0125: b0e1 outbset 1, 0x0e outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTMSK1 +0126: 7100 wait wait +0127: b121 outbset 1, 0x12 outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTCLR1 +0128: 8210 input 0x21, r0 input MDMFIFOSTA, r0 +0129: 0620 and 2, r0 and 2, r0 +012a: 1e20 cmp 2, r0 cmp 2, r0 +012b: 4526 bne 0x0126 bne MTX_MFSK_ToneLoop +012c: c060 lli 0x6, r0 lli "Starting MFSK Symbol Loop" +012c: 66d0 jsr 0x02d0 jsr _DBG_PRINT +012e: 7100 wait wait +012f: b121 outbset 1, 0x12 outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTCLR1 +0130: 81d1 input 0x1d, r1 input MDMFIFORD, r1 +0131: 92f1 output r1, 0x2f output r1, MODSOFTTX +0132: 0000 or r0, r0 nop +0133: 0000 or r0, r0 nop +0134: 0000 or r0, r0 nop +0135: 8212 input 0x21, r2 input MDMFIFOSTA, r2 +0136: 0622 and 2, r2 and 2, r2 +0137: 1e22 cmp 2, r2 cmp 2, r2 +0138: 412e beq 0x012e beq MTX_MFSK_SymbolLoop +0139: c070 lli 0x7, r0 lli "Stopping MFSK Symbol Loop" +0139: 66d0 jsr 0x02d0 jsr _DBG_PRINT +013b: a634 outbclr 4, 0x63 outbclr MODCTRL_SOFTTXENABLE, MODCTRL +013c: 64f5 jsr 0x00f5 jsr MTX_Iqdump_Termination +013d: 607d jmp 0x007d jmp CMD_OK_END +013e: a0d2 outbclr 2, 0x0d outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 +013f: a0f0 outbclr 0, 0x0f outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 +0140: a0f3 outbclr 3, 0x0f outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2 +0141: 7311 outset 0x11 outset MCEEVENTCLR0 +0142: 7312 outset 0x12 outset MCEEVENTCLR1 +0143: 6644 jsr 0x0244 jsr MRX_SETUP +0144: c080 lli 0x8, r0 lli "########################### Blind REGISTER MODE -> IQ Dump starting at once ########################" +0144: 66d0 jsr 0x02d0 jsr _DBG_PRINT +0146: b0d2 outbset 2, 0x0d outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 +0147: c035 lli 0x3, r5 lli 3, r5 +0148: 7100 wait wait +0149: 9b75 output r5, 0xb7 output r5, RDCAPT1 +014a: ba38 outbset 8, 0xa3 outbset RDCAPT0_DEMPDIF0, RDCAPT0 +014b: b074 outbset 4, 0x07 outbset MCESTROBES0_EVENT0, MCESTROBES0 +014c: b112 outbset 2, 0x11 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0 +014d: 6148 jmp 0x0148 jmp LOOP_SAMPLES_BLIND +014e: a0d2 outbclr 2, 0x0d outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 +014f: a0f0 outbclr 0, 0x0f outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 +0150: a0f3 outbclr 3, 0x0f outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2 +0151: 7311 outset 0x11 outset MCEEVENTCLR0 +0152: 7312 outset 0x12 outset MCEEVENTCLR1 +0153: 6644 jsr 0x0244 jsr MRX_SETUP +0154: c18b lli 0x18, r11 lli 24, r11 +0155: c000 lli 0x0, r0 lli 0x0, r0 +0156: 91e0 output r0, 0x1e output r0, MDMFIFOWRCTRL +0157: 120c mov 0, r12 mov 0, r12 +0158: 1218 mov 1, r8 mov 1, r8 +0159: 786a lmd 0x6, r10 lmd IQDUMP_TEST_MAX_VAL, r10 +015a: 787d lmd 0x7, r13 lmd IQDUMP_MAX_POS_VAL, r13 +015b: 788e lmd 0x8, r14 lmd IQDUMP_MIN_NEG_VAL, r14 +015c: 10a9 mov r10, r9 mov r10, r9 +015d: b074 outbset 4, 0x07 outbset MCESTROBES0_EVENT0, MCESTROBES0 +015e: b0d2 outbset 2, 0x0d outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 +015f: c050 lli 0x5, r0 lli 5, r0 +0160: b112 outbset 2, 0x11 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0 +0161: 7100 wait wait +0162: 6960 loop 0x0160 loop LOOP_SAMPLES_FIFO_BLIND_WAIT +0163: c090 lli 0x9, r0 lli "########################### Blind RFC FIFO Mode -> IQ Dump starting at once (DataRate <= 12,5 kbps) ########################" +0163: 66d0 jsr 0x02d0 jsr _DBG_PRINT +0165: c035 lli 0x3, r5 lli 3, r5 +0166: b112 outbset 2, 0x11 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0 +0167: 7100 wait wait +0168: 9b75 output r5, 0xb7 output r5, RDCAPT1 +0169: 8bf0 input 0xbf, r0 input DEMFRAC4, r0 +016a: 65d9 jsr 0x01d9 jsr SignExt_and_Saturate +016b: 8ca1 input 0xca, r1 input MDMSPAR2, r1 +016c: 2201 btst 0, r1 btst 0, r1 +016d: 4173 beq 0x0173 beq LOOP_SAMPLES_FIFO_BLIND_DEMFRAC4WR +016e: 1080 mov r8, r0 mov r8, r0 +016f: 1ca8 cmp r10, r8 cmp r10, r8 +0170: 4572 bne 0x0172 bne TEST_PATTERN_ADD_BLIND +0171: 1208 mov 0, r8 mov 0, r8 +0172: 1618 add 1, r8 add 1, r8 +0173: 65d0 jsr 0x01d0 jsr MDMFIFOWR_AND_WAIT10 +0174: 8c00 input 0xc0, r0 input DEMFRAC5, r0 +0175: 65d9 jsr 0x01d9 jsr SignExt_and_Saturate +0176: 8ca1 input 0xca, r1 input MDMSPAR2, r1 +0177: 2201 btst 0, r1 btst 0, r1 +0178: 417e beq 0x017e beq LOOP_SAMPLES_FIFO_BLIND_DEMFRAC5WR +0179: 1090 mov r9, r0 mov r9, r0 +017a: 1a19 sub 1, r9 sub 1, r9 +017b: 1e09 cmp 0, r9 cmp 0, r9 +017c: 457e bne 0x017e bne LOOP_SAMPLES_FIFO_BLIND_DEMFRAC5WR +017d: 10a9 mov r10, r9 mov r10, r9 +017e: 65d0 jsr 0x01d0 jsr MDMFIFOWR_AND_WAIT10 +017f: 8184 input 0x18, r4 input MDMCMDPAR1, r4 +0180: 1e04 cmp 0, r4 cmp 0, r4 +0181: 4166 beq 0x0166 beq LOOP_SAMPLES_FIFO_BLIND +0182: 14bc add r11, r12 add r11, r12 +0183: 1c4c cmp r4, r12 cmp r4, r12 +0184: 4eb3 bpl 0x02b3 bpl MRX_GenFSK_CommonEnd +0185: 6166 jmp 0x0166 jmp LOOP_SAMPLES_FIFO_BLIND +0186: a0d2 outbclr 2, 0x0d outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 +0187: a0f0 outbclr 0, 0x0f outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 +0188: a0f3 outbclr 3, 0x0f outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2 +0189: 7311 outset 0x11 outset MCEEVENTCLR0 +018a: 7312 outset 0x12 outset MCEEVENTCLR1 +018b: 6644 jsr 0x0244 jsr MRX_SETUP +018c: 721e outclr 0x1e outclr MDMFIFOWRCTRL +018d: 120c mov 0, r12 mov 0, r12 +018e: 1205 mov 0, r5 mov 0, r5 +018f: b074 outbset 4, 0x07 outbset MCESTROBES0_EVENT0, MCESTROBES0 +0190: b0d2 outbset 2, 0x0d outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 +0191: c050 lli 0x5, r0 lli 5, r0 +0192: b112 outbset 2, 0x11 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0 +0193: 7100 wait wait +0194: 6992 loop 0x0192 loop LOOP_SAMPLES_TRANSPARENT_FIFO_WAIT +0195: c0a0 lli 0xa, r0 lli "########################### Transparent FIFO Mode -> PDIFF streaming starting at once ########################" +0195: 66d0 jsr 0x02d0 jsr _DBG_PRINT +0197: 789d lmd 0x9, r13 lmd TRANSPARENT_CAPT, r13 +0198: 89ce input 0x9c, r14 input VITACCCTRL, r14 +0199: b112 outbset 2, 0x11 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0 +019a: 7100 wait wait +019b: 8c90 input 0xc9, r0 input MDMSPAR1, r0 +019c: 2200 btst 0, r0 btst 0, r0 +019d: 41a4 beq 0x01a4 beq CAPT_FREQUENCY +019e: 8230 input 0x23, r0 input RFESEND, r0 +019f: 2210 btst 1, r0 btst 1, r0 +01a0: 45a4 bne 0x01a4 bne CAPT_FREQUENCY +01a1: b231 outbset 1, 0x23 outbset 1, RFESEND +01a2: c0b0 lli 0xb, r0 lli "########################### Transparent FIFO Mode Stop AGC ########################" +01a2: 66d0 jsr 0x02d0 jsr _DBG_PRINT +01a4: 9a3d output r13, 0xa3 output r13, RDCAPT0 +01a5: 8ab2 input 0xab, r2 input DEMPDIF0, r2 +01a6: 3182 sl0 8, r2 sl0 8, r2 +01a7: 3d82 srx 8, r2 srx 8, r2 +01a8: 8af0 input 0xaf, r0 input DEMFIFE2,r0 +01a9: 3180 sl0 8, r0 sl0 8, r0 +01aa: 3d80 srx 8, r0 srx 8, r0 +01ab: 1802 sub r0, r2 sub r0, r2 +01ac: 063e and 3, r14 and 3, r14 +01ad: 1e0e cmp 0, r14 cmp 0, r14 +01ae: 41c6 beq 0x01c6 beq NO_IIR_FILTER +01af: 1e2e cmp 2, r14 cmp 2, r14 +01b0: 41b8 beq 0x01b8 beq IIR_K4 +01b1: 1e3e cmp 3, r14 cmp 3, r14 +01b2: 41bf beq 0x01bf beq IIR_K8 +01b3: 1056 mov r5, r6 mov r5, r6 +01b4: 1426 add r2, r6 add r2, r6 +01b5: 3d16 srx 1, r6 srx 1, r6 +01b6: 1065 mov r6, r5 mov r6, r5 +01b7: 61c7 jmp 0x01c7 jmp HARD_DECISION +01b8: 1056 mov r5, r6 mov r5, r6 +01b9: 3126 sl0 2, r6 sl0 2, r6 +01ba: 1856 sub r5, r6 sub r5,r6 +01bb: 1426 add r2, r6 add r2, r6 +01bc: 3d26 srx 2, r6 srx 2, r6 +01bd: 1065 mov r6, r5 mov r6, r5 +01be: 61c7 jmp 0x01c7 jmp HARD_DECISION +01bf: 1056 mov r5, r6 mov r5, r6 +01c0: 3136 sl0 3, r6 sl0 3, r6 +01c1: 1856 sub r5, r6 sub r5,r6 +01c2: 1426 add r2, r6 add r2, r6 +01c3: 3d36 srx 3, r6 srx 3, r6 +01c4: 1065 mov r6, r5 mov r6, r5 +01c5: 61c7 jmp 0x01c7 jmp HARD_DECISION +01c6: 1026 mov r2, r6 mov r2, r6 +01c7: 3976 sr0 7, r6 sr0 7, r6 +01c8: 91c6 output r6, 0x1c output r6, MDMFIFOWR +01c9: 8184 input 0x18, r4 input MDMCMDPAR1, r4 +01ca: 1e04 cmp 0, r4 cmp 0, r4 +01cb: 4199 beq 0x0199 beq LOOP_SAMPLES_TRANSPARENT_FIFO +01cc: 161c add 1, r12 add 1, r12 +01cd: 1c4c cmp r4, r12 cmp r4, r12 +01ce: 4eb3 bpl 0x02b3 bpl MRX_GenFSK_CommonEnd +01cf: 6199 jmp 0x0199 jmp LOOP_SAMPLES_TRANSPARENT_FIFO +01d0: 1001 mov r0, r1 mov r0, r1 +01d1: c0b0 lli 0xb, r0 lli 11, r0 +01d2: 91c1 output r1, 0x1c output r1, MDMFIFOWR +01d3: 3911 sr0 1, r1 sr0 1, r1 +01d4: 1000 mov r0, r0 mov r0, r0 +01d5: 1000 mov r0, r0 mov r0, r0 +01d6: 1000 mov r0, r0 mov r0, r0 +01d7: 69d2 loop 0x01d2 loop LOOP_MDMFIFOWR +01d8: 7000 rts rts +01d9: 3130 sl0 3, r0 sl0 3, r0 +01da: 3d30 srx 3, r0 srx 3, r0 +01db: 1cd0 cmp r13, r0 cmp r13, r0 +01dc: 4de0 bpl 0x01e0 bpl Pos_Sat +01dd: 1ce0 cmp r14, r0 cmp r14, r0 +01de: 49e2 bmi 0x01e2 bmi Neg_Sat +01df: 7000 rts rts +01e0: 10d0 mov r13, r0 mov r13, r0 +01e1: 7000 rts rts +01e2: 10e0 mov r14, r0 mov r14, r0 +01e3: 7000 rts rts +01e4: c0c0 lli 0xc, r0 lli "########################### IQ Dump REGISTER MODE, RX started, Wait for Sync ########################" +01e4: 66d0 jsr 0x02d0 jsr _DBG_PRINT +01e6: a0d2 outbclr 2, 0x0d outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 +01e7: a0f0 outbclr 0, 0x0f outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 +01e8: a0f3 outbclr 3, 0x0f outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2 +01e9: 7311 outset 0x11 outset MCEEVENTCLR0 +01ea: 7312 outset 0x12 outset MCEEVENTCLR1 +01eb: 6644 jsr 0x0244 jsr MRX_SETUP +01ec: b130 outbset 0, 0x13 outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2 +01ed: b0f0 outbset 0, 0x0f outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 +01ee: 7100 wait wait +01ef: 80b0 input 0x0b, r0 input MCEEVENT2, r0 +01f0: 2200 btst 0, r0 btst MCEEVENT2_C1BE_A_POS_PEAK, r0 +01f1: 45f3 bne 0x01f3 bne DUMP_SAMPLES +01f2: 61ee jmp 0x01ee jmp SYNC_SEARCH +01f3: b231 outbset 1, 0x23 outbset 1, RFESEND +01f4: c0d0 lli 0xd, r0 lli "########################### Sync Found REGISTER MODE -> IQ Dump starting ########################" +01f4: 66d0 jsr 0x02d0 jsr _DBG_PRINT +01f6: b130 outbset 0, 0x13 outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2 +01f7: a0f0 outbclr 0, 0x0f outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 +01f8: b0d2 outbset 2, 0x0d outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 +01f9: c035 lli 0x3, r5 lli 3, r5 +01fa: 7100 wait wait +01fb: 9b75 output r5, 0xb7 output r5, RDCAPT1 +01fc: ba38 outbset 8, 0xa3 outbset RDCAPT0_DEMPDIF0, RDCAPT0 +01fd: b074 outbset 4, 0x07 outbset MCESTROBES0_EVENT0, MCESTROBES0 +01fe: b112 outbset 2, 0x11 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0 +01ff: 61fa jmp 0x01fa jmp LOOP_SAMPLES +0200: c0e0 lli 0xe, r0 lli "########################### IQ Dump through RFC FIFO, RX started, Wait for Sync (DataRate <= 12.5 kbps) ########################" +0200: 66d0 jsr 0x02d0 jsr _DBG_PRINT +0202: a0d2 outbclr 2, 0x0d outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 +0203: a0f0 outbclr 0, 0x0f outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 +0204: a0f3 outbclr 3, 0x0f outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2 +0205: 7311 outset 0x11 outset MCEEVENTCLR0 +0206: 7312 outset 0x12 outset MCEEVENTCLR1 +0207: 6644 jsr 0x0244 jsr MRX_SETUP +0208: c18b lli 0x18, r11 lli 24, r11 +0209: c000 lli 0x0, r0 lli 0x0, r0 +020a: 91e0 output r0, 0x1e output r0, MDMFIFOWRCTRL +020b: 120c mov 0, r12 mov 0, r12 +020c: 1218 mov 1, r8 mov 1, r8 +020d: 786a lmd 0x6, r10 lmd IQDUMP_TEST_MAX_VAL, r10 +020e: 787d lmd 0x7, r13 lmd IQDUMP_MAX_POS_VAL, r13 +020f: 788e lmd 0x8, r14 lmd IQDUMP_MIN_NEG_VAL, r14 +0210: 10a9 mov r10, r9 mov r10, r9 +0211: b130 outbset 0, 0x13 outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2 +0212: b0f0 outbset 0, 0x0f outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 +0213: 7100 wait wait +0214: 80b0 input 0x0b, r0 input MCEEVENT2, r0 +0215: 2200 btst 0, r0 btst MCEEVENT2_C1BE_A_POS_PEAK, r0 +0216: 4618 bne 0x0218 bne DUMP_SAMPLES_FIFO +0217: 6213 jmp 0x0213 jmp SYNC_SEARCH_FIFO +0218: b074 outbset 4, 0x07 outbset MCESTROBES0_EVENT0, MCESTROBES0 +0219: b231 outbset 1, 0x23 outbset 1, RFESEND +021a: c0f0 lli 0xf, r0 lli "########################### Sync Found RFC FIFO MODE-> IQ samples through FIFO starting ########################" +021a: 66d0 jsr 0x02d0 jsr _DBG_PRINT +021c: b130 outbset 0, 0x13 outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2 +021d: a0f0 outbclr 0, 0x0f outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 +021e: b0d2 outbset 2, 0x0d outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 +021f: c020 lli 0x2, r0 lli 2, r0 +0220: b112 outbset 2, 0x11 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0 +0221: 7100 wait wait +0222: 6a20 loop 0x0220 loop LOOP_SAMPLES_FIFO_SYNC_WAIT +0223: c035 lli 0x3, r5 lli 3, r5 +0224: b112 outbset 2, 0x11 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0 +0225: 7100 wait wait +0226: 9b75 output r5, 0xb7 output r5, RDCAPT1 +0227: 8bf0 input 0xbf, r0 input DEMFRAC4, r0 +0228: 65d9 jsr 0x01d9 jsr SignExt_and_Saturate +0229: 8ca1 input 0xca, r1 input MDMSPAR2, r1 +022a: 2201 btst 0, r1 btst 0, r1 +022b: 4231 beq 0x0231 beq LOOP_SAMPLES_FIFO_SYNC_DEMFRAC4WR +022c: 1080 mov r8, r0 mov r8, r0 +022d: 1ca8 cmp r10, r8 cmp r10, r8 +022e: 4630 bne 0x0230 bne TEST_PATTERN_ADD_SYNC +022f: 1208 mov 0, r8 mov 0, r8 +0230: 1618 add 1, r8 add 1, r8 +0231: 65d0 jsr 0x01d0 jsr MDMFIFOWR_AND_WAIT10 +0232: 8c00 input 0xc0, r0 input DEMFRAC5, r0 +0233: 65d9 jsr 0x01d9 jsr SignExt_and_Saturate +0234: 8ca1 input 0xca, r1 input MDMSPAR2, r1 +0235: 2201 btst 0, r1 btst 0, r1 +0236: 423c beq 0x023c beq LOOP_SAMPLES_FIFO_SYNC_DEMFRAC5WR +0237: 1090 mov r9, r0 mov r9, r0 +0238: 1a19 sub 1, r9 sub 1, r9 +0239: 1e09 cmp 0, r9 cmp 0, r9 +023a: 463c bne 0x023c bne LOOP_SAMPLES_FIFO_SYNC_DEMFRAC5WR +023b: 10a9 mov r10, r9 mov r10, r9 +023c: 65d0 jsr 0x01d0 jsr MDMFIFOWR_AND_WAIT10 +023d: 8184 input 0x18, r4 input MDMCMDPAR1, r4 +023e: 1e04 cmp 0, r4 cmp 0, r4 +023f: 4224 beq 0x0224 beq LOOP_SAMPLES_FIFO_SYNC +0240: 14bc add r11, r12 add r11, r12 +0241: 1c4c cmp r4, r12 cmp r4, r12 +0242: 4eb3 bpl 0x02b3 bpl MRX_GenFSK_CommonEnd +0243: 6224 jmp 0x0224 jmp LOOP_SAMPLES_FIFO_SYNC +0244: 8240 input 0x24, r0 input RFERCEV, r0 +0245: 2230 btst 3, r0 btst 3, r0 +0246: 464c bne 0x024c bne RFE_Started +0247: b0d5 outbset 5, 0x0d outbset MCEEVENT0_RFECMD_IRQ, MCEEVENTMSK0 +0248: 7100 wait wait +0249: b115 outbset 5, 0x11 outbset MCEEVENT0_RFECMD_IRQ, MCEEVENTCLR0 +024a: a0d5 outbclr 5, 0x0d outbclr MCEEVENT0_RFECMD_IRQ, MCEEVENTMSK0 +024b: 6244 jmp 0x0244 jmp MRX_SETUP +024c: c100 lli 0x10, r0 lli "########################### RX Started ########################" +024c: 66d0 jsr 0x02d0 jsr _DBG_PRINT +024e: b118 outbset 8, 0x11 outbset MCEEVENT0_CPEFWEVENT0, MCEEVENTCLR0 +024f: b006 outbset 6, 0x00 outbset MDMENABLE_ADCDIG, MDMENABLE +0250: b016 outbset 6, 0x01 outbset MDMINIT_ADCDIG, MDMINIT +0251: b004 outbset 4, 0x00 outbset MDMENABLE_DEMODULATOR, MDMENABLE +0252: b014 outbset 4, 0x01 outbset MDMINIT_DEMODULATOR, MDMINIT +0253: b002 outbset 2, 0x00 outbset MDMENABLE_TIMEBASE, MDMENABLE +0254: b012 outbset 2, 0x01 outbset MDMINIT_TIMEBASE, MDMINIT +0255: 8440 input 0x44, r0 input DEMC1BE0, r0 +0256: 7842 lmd 0x4, r2 lmd DEMC1BE0_MASKA_BITS, r2 +0257: 0420 and r2, r0 and r2, r0 +0258: 8173 input 0x17, r3 input MDMCMDPAR0, r3 +0259: 3983 sr0 8, r3 sr0 8, r3 +025a: 2a73 bclr 7, r3 bclr 7, r3 +025b: 94e3 output r3, 0x4e output r3, DEMSWQU0 +025c: c1f2 lli 0x1f, r2 lli 31, r2 +025d: 1832 sub r3, r2 sub r3, r2 +025e: 3162 sl0 6, r2 sl0 DEMC1BE0_MASKA, r2 +025f: 1021 mov r2, r1 mov r2, r1 +0260: 3151 sl0 5, r1 sl0 5, r1 +0261: 0012 or r1, r2 or r1, r2 +0262: 0020 or r2, r0 or r2, r0 +0263: 9440 output r0, 0x44 output r0, DEMC1BE0 +0264: 1030 mov r3, r0 mov r3, r0 +0265: 1610 add 1, r0 add 1,r0 +0266: 3930 sr0 3, r0 sr0 3,r0 +0267: 2210 btst 1, r0 btst 1, r0 +0268: 426a beq 0x026a beq GEN_FSK_AVG_LEN_CORRECT +0269: 1220 mov 2, r0 mov 2, r0 +026a: 3150 sl0 5, r0 sl0 5,r0 +026b: 1003 mov r0, r3 mov r0, r3 +026c: 3180 sl0 8, r0 sl0 8, r0 +026d: 1630 add 3, r0 add 3,r0 +026e: 9380 output r0, 0x38 output r0, DEMDSBU +026f: 1202 mov 0, r2 mov 0, r2 +0270: 1204 mov 0, r4 mov 0, r4 +0271: 2273 btst 7, r3 btst 7, r3 +0272: 427c beq 0x027c beq GEN_FSK_DSBU_AVG_LEN_16_SYMBOLS_CHECK +0273: 84a0 input 0x4a, r0 input MDMSYNC0, r0 +0274: 9970 output r0, 0x97 output r0, COUNT1IN +0275: 8982 input 0x98, r2 input COUNT1RES, r2 +0276: 1a82 sub 8, r2 sub 8, r2 +0277: 84c0 input 0x4c, r0 input MDMSYNC2, r0 +0278: 9970 output r0, 0x97 output r0, COUNT1IN +0279: 8984 input 0x98, r4 input COUNT1RES, r4 +027a: 1a84 sub 8, r4 sub 8, r4 +027b: 627e jmp 0x027e jmp GEN_FSK_DSBU_AVG_LEN_16_SYMBOLS +027c: 2263 btst 6, r3 btst 6, r3 +027d: 4289 beq 0x0289 beq GEN_FSK_DSBU_AVG_LEN_8_SYMBOLS +027e: 84b0 input 0x4b, r0 input MDMSYNC1, r0 +027f: 9970 output r0, 0x97 output r0, COUNT1IN +0280: 8980 input 0x98, r0 input COUNT1RES, r0 +0281: 1a80 sub 8, r0 sub 8, r0 +0282: 1402 add r0, r2 add r0, r2 +0283: 84d0 input 0x4d, r0 input MDMSYNC3, r0 +0284: 9970 output r0, 0x97 output r0, COUNT1IN +0285: 8980 input 0x98, r0 input COUNT1RES, r0 +0286: 1a80 sub 8, r0 sub 8, r0 +0287: 1404 add r0, r4 add r0, r4 +0288: 6295 jmp 0x0295 jmp GEN_FSK_CALC_DEMSWIMBAL +0289: 84b0 input 0x4b, r0 input MDMSYNC1, r0 +028a: 7851 lmd 0x5, r1 lmd IQDUMP_MASK_BITS_15_8, r1 +028b: 0410 and r1, r0 and r1,r0 +028c: 9970 output r0, 0x97 output r0, COUNT1IN +028d: 8982 input 0x98, r2 input COUNT1RES, r2 +028e: 1a42 sub 4, r2 sub 4, r2 +028f: 84d0 input 0x4d, r0 input MDMSYNC3, r0 +0290: 7851 lmd 0x5, r1 lmd IQDUMP_MASK_BITS_15_8, r1 +0291: 0410 and r1, r0 and r1,r0 +0292: 9970 output r0, 0x97 output r0, COUNT1IN +0293: 8984 input 0x98, r4 input COUNT1RES, r4 +0294: 1a44 sub 4, r4 sub 4, r4 +0295: 3152 sl0 5, r2 sl0 5, r2 +0296: 3154 sl0 5, r4 sl0 5, r4 +0297: 3963 sr0 6, r3 sr0 6, r3 +0298: 0633 and 3, r3 and 3, r3 +0299: 1613 add 1, r3 add 1, r3 +029a: 3832 sr0 r3, r2 sr0 r3, r2 +029b: 3834 sr0 r3, r4 sr0 r3, r4 +029c: 3182 sl0 8, r2 sl0 8, r2 +029d: 3982 sr0 8, r2 sr0 8, r2 +029e: 3184 sl0 8, r4 sl0 8, r4 +029f: 0042 or r4, r2 or r4, r2 +02a0: 9722 output r2, 0x72 output r2, DEMSWIMBAL +02a1: 84a0 input 0x4a, r0 input MDMSYNC0, r0 +02a2: 9590 output r0, 0x59 output r0, DEMC1BEREF0 +02a3: 84b0 input 0x4b, r0 input MDMSYNC1, r0 +02a4: 95a0 output r0, 0x5a output r0, DEMC1BEREF1 +02a5: 84c0 input 0x4c, r0 input MDMSYNC2, r0 +02a6: 95b0 output r0, 0x5b output r0, DEMC1BEREF2 +02a7: 84d0 input 0x4d, r0 input MDMSYNC3, r0 +02a8: 95c0 output r0, 0x5c output r0, DEMC1BEREF3 +02a9: 7810 lmd 0x1, r0 lmd DEMENABLE0_RX_IQDUMP, r0 +02aa: 9030 output r0, 0x03 output r0, DEMENABLE0 +02ab: 9050 output r0, 0x05 output r0, DEMINIT0 +02ac: 7820 lmd 0x2, r0 lmd DEMENABLE1_RX_IQDUMP, r0 +02ad: 9040 output r0, 0x04 output r0, DEMENABLE1 +02ae: 9060 output r0, 0x06 output r0, DEMINIT1 +02af: b235 outbset 5, 0x23 outbset 5, RFESEND +02b0: cd90 lli 0xd9, r0 lli 0xD9, r0 +02b1: 9170 output r0, 0x17 output r0, MDMCMDPAR0 +02b2: 7000 rts rts +02b3: a235 outbclr 5, 0x23 outbclr 5, RFESEND +02b4: b112 outbset 2, 0x11 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0 +02b5: 7100 wait wait +02b6: a0d2 outbclr 2, 0x0d outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 +02b7: b112 outbset 2, 0x11 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0 +02b8: ba3c outbset 12, 0xa3 outbset RDCAPT0_DEMLQIE0, RDCAPT0 +02b9: 81b0 input 0x1b, r0 input MDMSTATUS, r0 +02ba: 8b54 input 0xb5, r4 input DEMLQIE0, r4 +02bb: 3924 sr0 2, r4 sr0 2, r4 +02bc: 3184 sl0 8, r4 sl0 8, r4 +02bd: 0004 or r0, r4 or r0,r4 +02be: 91b4 output r4, 0x1b output r4, MDMSTATUS +02bf: c110 lli 0x11, r0 lli "All bits received, MCE Ending" +02bf: 66d0 jsr 0x02d0 jsr _DBG_PRINT +02c1: 7391 outset 0x91 outset TIMCTRL +02c2: 7291 outclr 0x91 outclr TIMCTRL +02c3: 66ca jsr 0x02ca jsr MODCTRL_CLR +02c4: 7206 outclr 0x06 outclr MDMENABLE_ADCDIG, MDMENABLE +02c5: 7202 outclr 0x02 outclr MDMENABLE_TIMEBASE, MDMENABLE +02c6: 7204 outclr 0x04 outclr MDMENABLE_DEMODULATOR, MDMENABLE +02c7: 7305 outset 0x05 outset DEMINIT0 +02c8: 7306 outset 0x06 outset DEMINIT1 +02c9: 607d jmp 0x007d jmp CMD_OK_END +02ca: 8630 input 0x63, r0 input MODCTRL, r0 +02cb: c801 lli 0x80, r1 lli 0x80, r1 +02cc: 3151 sl0 5, r1 sl0 5, r1 +02cd: 0410 and r1, r0 and r1, r0 +02ce: 9630 output r0, 0x63 output r0, MODCTRL +02cf: 7000 rts rts +02d0: 9a00 output r0, 0xa0 output r0, MCETRCCMD +02d0: 89f0 input 0x9f, r0 input MCETRCBUSY, r0 +02d0: 2200 btst 0, r0 btst 0, r0 +02d0: 46d1 bne 0x02d1 bne _DBG_PRINT_WAIT +02d0: b9e0 outbset 0, 0x9e outbset MCETRCSEND_SEND, MCETRCSEND +02d0: 7000 rts rts diff --git a/text.s b/text.s new file mode 100644 index 0000000..61c1928 --- /dev/null +++ b/text.s @@ -0,0 +1,1105 @@ +; vim: set ft=nasm: + +.ORG 0 + jmp START_PROCESS + +.ORG LMD_DATA_SPACE + +DEMENABLE0_RX_IQDUMP: + .DATA 0x2FCF ; DEMENABLE0 settings (felp, frac,fidc,chfi,bdec,iqmc,mge2,codc,cmix) +DEMENABLE1_RX_IQDUMP: + .DATA 0x3F9D ; DEMENABLE1 + +VITACCCTRL_REG_DEFAULT: ; Transp, downsample + IIR filter setting + .DATA 0x0001 ; [7:0]=0: no filter + ; [7:0]=1: k=1/2 + ; [7:0]=2: k=1/4 + ; [7:0]=3: k=1/8 + ; [15: 8]=0, no transparent downsample + ; [15: 8]=1, transparent downsample by two + ; [15: 8]=2, transparent downsample by four + ; [15: 8]=3, transparent downsample by eight + ; [15: 8]=4, transparent downsample by sixteen + +DEMC1BE0_MASKA_BITS: ; Various bit masks + .DATA 0x003F +IQDUMP_MASK_BITS_15_8: + .DATA 0xFF00 + +IQDUMP_TEST_MAX_VAL: + .DATA 0x0FFF +IQDUMP_MAX_POS_VAL: + .DATA 0x07FF ; 2^11 - 1 = 2047 +IQDUMP_MIN_NEG_VAL: + .DATA 0xF800 ; -2048 +TRANSPARENT_CAPT: + .DATA 0x0300 ; Combined RDCAPT0_DEMPDIF0 and RDCAPT0_DEMFIFE2 +CORR_DEFG_THR: + .DATA 0x8080 +TX_TONE_COUNT: + .DATA 0x06 ; Default number of clock ticks for tone in front of preamble + +.ORG MDMCONF_IQDUMP + +.DATA 0x0003 ; ADCDIGCONF +.DATA 0x0017 ; MODPRECTRL +.DATA 0x3D1F ; MODSYMMAP0 +.DATA 0x0000 ; MODSYMMAP1 +.DATA 0x0000 ; MODSOFTTX +.DATA 0x0800 ; MDMBAUD +.DATA 0x000F ; MDMBAUDPRE +.DATA 0x0000 ; MODMAIN +.DATA 0x0387 ; DEMMISC0 +.DATA 0x0000 ; DEMMISC1 +.DATA 0x4074 ; DEMMISC2 +.DATA 0x0043 ; DEMMISC3 +.DATA 0x8000 ; DEMIQMC0 +.DATA 0x0082 ; DEMDSBU +.DATA 0x0080 ; DEMDSBU2 +.DATA 0x06F0 ; DEMCODC0 +.DATA 0x0000 ; DEMFIDC0 +.DATA 0x091E ; DEMFEXB0 +.DATA 0x0510 ; DEMDSXB0 +.DATA 0x0054 ; DEMD2XB0 +.DATA 0x0007 ; DEMFIFE0 +.DATA 0x0000 ; DEMMAFI0 +.DATA 0x5014 ; DEMMAFI1 +.DATA 0x0050 ; DEMMAFI2 +.DATA 0x0000 ; DEMMAFI3 +.DATA 0xC02F ; DEMC1BE0 +.DATA 0x0C30 ; DEMC1BE1 +.DATA 0x017F ; DEMC1BE2 +.DATA 0x0000 ; DEMC1BE10 +.DATA 0x0000 ; DEMC1BE11 +.DATA 0x0000 ; DEMC1BE12 +.DATA 0x0000 ; MDMSYNC0 +.DATA 0x0000 ; MDMSYNC1 +.DATA 0x0000 ; MDMSYNC2 +.DATA 0xAA00 ; MDMSYNC3 +.DATA 0x0000 ; DEMSWQU0 + +MDMCONF_IQDUMP_END: + + .ORG MAIN + + START_PROCESS: + ;; Do hard initialization of all submodules of the modem + outclr RFESEND ; Clear RFE send + jsr MODCTRL_CLR ; + outbclr DEMMISC2_MLSERUN,DEMMISC2 ; Make sure MLSE can be stopped + outbclr DEMSWQU0_RUN, DEMSWQU0 ; Make sure door is open for init + outset DEMENABLE0 ; + outset DEMINIT0 ; + outclr DEMENABLE0 ; + outset DEMENABLE1 ; + outset DEMINIT1 ; + outclr DEMENABLE1 ; + outset TIMCTRL ; + outclr TIMCTRL ; + outbset MDMENABLE_FB2PLL, MDMENABLE ; enable fb2pll module so that can be reset + lli 0x3FC, r0 ; dont't touch fifo and topsm + output r0, MDMINIT ; + outbclr MDMENABLE_FB2PLL, MDMENABLE ; disable fb2pll module again + outclr MCEEVENTMSK0 ; + outclr MCEEVENTMSK1 ; + outclr MCEEVENTMSK2 ; + outclr MCEEVENTMSK3 ; + + ;;; Move into Command processing + ;;; -------------------------------------------------------------------------------- + ;;; Step 1. Main Command Processing Loop + + CMD_PROC: + outbset MCEEVENT0_MDMAPI_WR, MCEEVENTMSK0 ; Enable event 0 = MDMAPI write + wait ; Waits until a command arrives + outbset MCEEVENT0_MDMAPI_WR, MCEEVENTCLR0 ; Clear the event 0 + outbclr MCEEVENT0_MDMAPI_WR, MCEEVENTMSK0 ; Clear the event 0 + outclr MDMSTATUS ; + input MDMAPI, r2 ; Protocol ID [15:8] API [7:0] put together as [4:3][2:0] + mov r2, r0 ; Copy first into R0 + sr0 5, r2 ; Shift 5 positions R2 + and 7, r0 ; Clear all above bit 2 in R0 + or r2, r0 ; Put them together + add 3, r0 ; offset +3 + mov pc, r1 + add r0, r1 + jmp (r1) + jmp MNOP_Entry ; Jump tables Prot 0 Call 0 (MNOP) + jmp MCFG_Entry ; Jump tables Prot 0 Call 1 (MCFG) + jmp MTX_Entry ; Jump tables Prot 0 Call 2 (MTX) + jmp MRX_Entry_REG_BLIND ; Jump tables Prot 0 Call 3 (MRX-BLIND-REGISTER MODE) + jmp MNOP_Entry ; Jump tables Prot 0 Call 4 + jmp MNOP_Entry ; Jump tables Prot 0 Call 5 + jmp MNOP_Entry ; Jump tables Prot 0 Call 6 + jmp MNOP_Entry ; Jump tables Prot 0 Call 7 + jmp MNOP_Entry ; Jump tables Prot 1 Call 0 + jmp MCFG_Entry ; Jump tables Prot 1 Call 1 (MCFG) + jmp MTX_Entry ; Jump tables Prot 1 Call 2 (MTX) + jmp MRX_Entry_REG_SYNC ; Jump tables Prot 1 Call 3 (MRX-SYNC-REGISTER MODE) + jmp MNOP_Entry ; Jump tables Prot 1 Call 4 + jmp MNOP_Entry ; Jump tables Prot 1 Call 5 + jmp MNOP_Entry ; Jump tables Prot 1 Call 6 + jmp MNOP_Entry ; Jump tables Prot 1 Call 7 + jmp MNOP_Entry ; Jump tables Prot 2 Call 0 + jmp MCFG_Entry ; Jump tables Prot 2 Call 1 (MCFG) + jmp MTX_Entry ; Jump tables Prot 2 Call 2 (MTX) + jmp MRX_Entry_FIFO_BLIND ; Jump tables Prot 2 Call 3 (MRX-BLIND-RFC FIFO MODE) + jmp MNOP_Entry ; Jump tables Prot 2 Call 4 + jmp MNOP_Entry ; Jump tables Prot 2 Call 5 + jmp MNOP_Entry ; Jump tables Prot 2 Call 6 + jmp MNOP_Entry ; Jump tables Prot 2 Call 7 + jmp MNOP_Entry ; Jump tables Prot 3 Call 0 + jmp MCFG_Entry ; Jump tables Prot 3 Call 1 (MCFG) + jmp MTX_Entry ; Jump tables Prot 3 Call 2 (MTX) + jmp MRX_Entry_FIFO_SYNC ; Jump tables Prot 3 Call 3 (MRX-SYNC-RFC FIFO MODE) + jmp MNOP_Entry ; Jump tables Prot 3 Call 4 + jmp MNOP_Entry ; Jump tables Prot 3 Call 5 + jmp MNOP_Entry ; Jump tables Prot 3 Call 6 + jmp MNOP_Entry ; Jump tables Prot 3 Call 7 + jmp MNOP_Entry ; Jump tables Prot 4 Call 0 + jmp MCFG_Entry ; Jump tables Prot 4 Call 1 (MCFG) + jmp MTX_Entry ; Jump tables Prot 4 Call 2 (MTX) + jmp MRX_Entry_TRANSPARENT_FIFO ; Jump tables Prot 4 Call 3 (MRX-TRANSPARENT-RFC FIFO MODE) + jmp MNOP_Entry ; Jump tables Prot 4 Call 5 + jmp MNOP_Entry ; Jump tables Prot 4 Call 6 + jmp MNOP_Entry ; Jump tables Prot 4 Call 7 + jmp MNOP_Entry ; Jump tables Prot 5 Call 0 + jmp MCFG_Entry ; Jump tables Prot 5 Call 1 (MCFG) + jmp MTX_MFSK ; Jump tables Prot 5 Call 2 (MTX multi mode) + jmp MRX_Entry_FIFO_BLIND ; Jump tables Prot 5 Call 3 (MRX-BLIND-RFC FIFO MODE) + + + + ;;; End of Command Processing, start of the commands themselves + + ;;; -------------------------------------------------------------------------------- + ;;; General end of command routine + ;;; + CMD_OK_END: + mov CMD_OK, r0 ; Normal end of command + CPE_NOTIFY: + outclr RFESEND ; Clear RFE send + outset MCEEVENTCLR0 ; Clear all events: NOTE, this will BREAK command pipelining! + outset MCEEVENTCLR1 ; Clear all events + outset MCEEVENTCLR2 ; Clear all events + input MDMSTATUS, r1 ; + or r1, r0 ; + output r0, MDMSTATUS + outbset 0, MCESTROBES0 ; Notify CPE of completion + jmp CMD_PROC ; Ready for another command + + ;;; -------------------------------------------------------------------------------- + ;;; MNOP + ;;; + + MNOP_Entry: + jmp CMD_OK_END + + + ;;; -------------------------------------------------------------------------------- + ;;; iqdump IQDUMP (Generic FSK) + ;;; + ;;; This iqdump supports a Generic 2(G)FSK modem in which most of the parameters + ;;; are configured by the upper layer. + ;;; In general, it uses the standard 2(G)FSK configuration, and supports three FECs + ;;; Option 1) No FEC (use MLSE in RX) + ;;; Option 2) 1/2 K=4 FEC, as defined in the 802.15.4g FSK standard + ;;; Option 3) TBD + ;;; + ;;; -------------------------------------------------------------------------------- + + ;;; -------------------------------------------------------------------------------- + ;;; MCFG + ;;; -------------------------------------------------------------------------------- + + MCFG_Entry: + ; NOTE: = lli text, r0; jsr _DBG_PRINT + DBG_PRINT0 "MCFG - IQ Dump Configuration" + lli MDMCONF_IQDUMP, r1 ; Points R1 to the WMBUS data + lli MDMCONF_IQDUMP_FIRST_REG, r2 ; Points to the first IO address for configiration + lli MDMCONF_IQDUMP_LAST_REG, r0 ; Points to the last of the IO address + sub r2,r0 ; R0 now holds number of iterations for CONF_LOOP, r0 implitly used by loop instruction + MCFG_Iqdump_Loop: + lmd (r1), r3 ; Load ROM data + output r3, (r2) ; Send to register bank + add 1, r1 ; Increase memory pointer + add 1, r2 ; Increase regbank pointer + loop MCFG_Iqdump_Loop ; + + lmd VITACCCTRL_REG_DEFAULT,r0 + output r0,VITACCCTRL + + lmd CORR_DEFG_THR, r0 + output r0, DEMC1BE11 + output r0, DEMC1BE12 + + lli DEMFB2P0, r2 ; First register to clear + lli VITCTRL, r0 ; Last register to clear + sub r2,r0 ; R0 now holds number of iterations for first zero loop, r0 implitly used by loop instruction + beq ZERO_DONE ; No values to write + mov 0, r3 ; Set all regs to 0 + ZERO_LOOP: + output r3, (r2) ; Send to register bank + add 1, r2 ; Increase regbank pointer + loop ZERO_LOOP ; + ZERO_DONE: + + ;; Set tone duration in BRMACC0 + lmd TX_TONE_COUNT, r0 ; + output r0, BRMACC0 ; + + ;; Set Collision restart for CDC FIFO + outclr MODCTRL ; + outbset MODCTRL_CDC_COL_RESTART, MODCTRL ; + + jmp CMD_OK_END ; Done + + ;;; -------------------------------------------------------------------------------- + ;;; MTX Common Entry + ;;; -------------------------------------------------------------------------------- + + ;;; -------------------------------------------------------------------------- + ;;; MTX GenericFSK Send Preamble and Sync Word function + ;;; + MTX_Iqdump_Common_Preamble: + ;; Fetch information from MDMPAR0|2: Preamble settings + input MDMCMDPAR2, r0 + output r0, MODPREAMBLE ; Send directly to MODPREAMBLE + input MDMCMDPAR0, r0 + sr0 8, r0 ; [15:8] => Sync Word Length + bclr 7, r0 + mov r0, r1 ; R1 = SyncWordLength + add 1, r1 ; In [32..1] format + ;; We are now going to process the SyncWord, and prepare it for later + ;; In general this is where we are putting things: + ;; R2 = MDMSYNC0, R3 = 15, R4 = MDMSYNC1, R5 = 15 + ;; This would apply to a full 32-bit sync word. If the syncword is + ;; between 32 to 17 bits, we would transmit both. If is 16 or less + ;; only the second one (R4) would be transmitted. + ;; Also, those syncwords come left-aligned. We need to bit-shift to be + ;; right aligned. + ;; Step 0. General Case (32-bit case) + input MDMSYNC0, r2 + input MDMSYNC1, r4 + lli 15, r3 + lli 15, r5 + ;; Step 1. Check if SyncWord is 32 bits + lli 32, r0 + cmp r0, r1 ; Special case, 32 bits + beq MTX_Iqdump_Common_Preamble_RFESEND ; if yes, we are done + ;; Step 2. Check if in [31..17] bits range + lli 16, r0 + cmp r1, r0 + beq MTX_Iqdump_Common_Preamble_16bitSyncWord + bpl MTX_Iqdump_Common_Preamble_ShortSyncWord + ;; R2 = MDMSYNC0-right-aligned, R3 = num of bits, R4 = MDMSYNC1, R5 = 15 + MTX_Iqdump_Common_Preamble_LongSyncWord: + mov r1, r3 ; R3 = [32..17] + sub r0, r3 ; R3 = R3-16 + sub r3, r0 ; R0 = 16-R3 + sub 1, r3 ; R3 = # bits to send + sub 1, r0 ; R0 = # bits to shift down + MTX_Iqdump_Common_Preamble_SyncWord_ShiftLoop1: + sr0 1, r2 ; MDMSYNC0-right-aligned + loop MTX_Iqdump_Common_Preamble_SyncWord_ShiftLoop1 + jmp MTX_Iqdump_Common_Preamble_RFESEND + ;; Step 3. Must be in [16..1] bits range + MTX_Iqdump_Common_Preamble_16bitSyncWord: + mov 0x1F, r3 ; Illegal value to indicate 16 bit or shorter sw + jmp MTX_Iqdump_Common_Preamble_RFESEND + MTX_Iqdump_Common_Preamble_ShortSyncWord: + ;; Results, R2 = XXX, R3 = 0, R4 = MDMSYNC1, R5 = num of bits + mov 0x1F, r3 ; Illegal value to indicate 16 bit or shorter sw + mov r1, r5 ; R5 = [16..1] + lli 16, r0 ; R0 = 16 + sub r5, r0 ; R0 = 16-R5 + sub 1, r5 ; R5 = # bits to send + sub 1, r0 ; R0 = # bits to shift down + MTX_Iqdump_Common_Preamble_SyncWord_ShiftLoop2: + sr0 1, r4 ; MDMSYNC0-right-aligned + loop MTX_Iqdump_Common_Preamble_SyncWord_ShiftLoop2 + ;; and done with SyncWordProcessing + MTX_Iqdump_Common_Preamble_RFESEND: + ;; ============================================ + ;; Wait for RAT event + outbset MCEEVENT1_RAT_EVENT0, MCEEVENTMSK1 ; enable wait for RAT + wait + outbset MCEEVENT1_RAT_EVENT0, MCEEVENTCLR1 ; Clear event again + outbclr MCEEVENT1_RAT_EVENT0, MCEEVENTMSK1 ; disable wait for RAT + ;; Send message to RFE that modulation is starting + outbset 0,RFESEND + + ;; Set up timer for tone in front of preamble + outbset TIMCTRL_ENABLETIMER, TIMCTRL ; + input BRMACC0, r0 ; Tone count + output r0, TIMPERIOD ; + outbset MCEEVENT0_TIMER_IRQ, MCEEVENTCLR0 ; Clear IRQ + ;; A delay to precisely time the start of the Preamble + outbset MCEEVENT0_TIMER_IRQ, MCEEVENTMSK0 ; Enable the mask! + wait + + ;; Enable modulator and timebase now + outbset MDMENABLE_TIMEBASE, MDMENABLE + outbset MDMINIT_TIMEBASE, MDMINIT + + outbset MCEEVENT0_TIMER_IRQ, MCEEVENTCLR0 ; Clear IRQ + outbclr MCEEVENT0_TIMER_IRQ, MCEEVENTMSK0 ; Disable Mask + outclr TIMCTRL ; Switch off timer + + ;; Step 2. Go to Preamble insert, Send MDMSYNC0, MDMSYNC1 + outbset MODCTRL_PREAMBLEINSERT, MODCTRL ; Go to preamble insert mode + outbset MDMENABLE_MODULATOR, MDMENABLE + outbset MDMINIT_MODULATOR, MDMINIT + ;; Preamble insert mode from start + MTX_Iqdump_FirstBit: + outclr MODPRECTRL ; Send ONE bit + outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTMSK1 ; wait for preamble done + wait + outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTCLR1 ; Clear Preamble Done + ;; Reload MOCPRECTRL with proper value now + input MDMCMDPAR0, r0 + output r0, MODPRECTRL ; Send directly to MODPRECTRL again + MTX_Iqdump_Common_Preamble_Loop: + wait + outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTCLR1 ; Clear Preamble Done + ;; Infinite preamble? Indicated by MSB of MDMCMDPAR0 + input MDMCMDPAR0, r0 + btst 15, r0 + bne MTX_Iqdump_Common_Preamble_Loop + ;; Preamble is done now, start with SyncWord. Use the R2, R3, R4, R5 values from above + mov 0x1F, r0 ; + cmp r0, r3 ; check if less than 16 bit SW + beq MTX_Iqdump_Common_Preamble_Send_One_SW + MTX_Iqdump_Common_Preamble_Send_Two_SW: + output r3, MODPRECTRL + output r2, MODPREAMBLE + wait + outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTCLR1 ; Clear Preamble Done + MTX_Iqdump_Common_Preamble_Send_One_SW: + output r5, MODPRECTRL + output r4, MODPREAMBLE + wait + outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTCLR1 ; Clear Preamble Done + outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTMSK1 ; Disable PREAMBLE_DONE from now on + outbclr MODCTRL_PREAMBLEINSERT, MODCTRL ; No more preamble insert + rts + + ;;; -------------------------------------------------------------------------- + ;;; MTX GenericFSK Termination + ;;; + MTX_Iqdump_Termination: + ;; Termination, Step 2. wait 4 clock baud periods before switching off + outbclr MCEEVENT1_CLKEN_BAUD, MCEEVENTMSK1 ; Disable CLKEN_BAUD events + lli 0x03,r0 ; Wait for 4 baud periods before switching + output r0, TIMCTRL ; the modulator off + lli 0x04, r0 ; Four periods + output r0, TIMPERIOD + outbset MCEEVENT0_TIMER_IRQ, MCEEVENTCLR0 ; Clear IRQ + outbset MCEEVENT0_TIMER_IRQ, MCEEVENTMSK0 ; Enable the mask! + wait + outbset MCEEVENT0_TIMER_IRQ, MCEEVENTCLR0 ; Clear IRQ + outbclr MCEEVENT0_TIMER_IRQ, MCEEVENTMSK0 ; Disable Mask + outclr TIMCTRL ; Switch off counter + outbclr MDMENABLE_MODULATOR, MDMENABLE ; Disable modulator, timebase + outbclr MDMENABLE_TIMEBASE, MDMENABLE + ;; Send message to RFE that modulation is stopping + outbclr 0, RFESEND ; + rts + + ;;; -------------------------------------------------------------------------- + ;;; No FEC, directly read data from FIFO and send out. TOPsm is mostly free + ;;; + MTX_Entry: + outset MCEEVENTCLR0 + outset MCEEVENTCLR1 + + ;; Normal mode (1bit per symbol) proceeds here + DBG_PRINT0 "IQDump___ NoFEC, TX Started" + lli 0x10, r0 ; MDMFIFORDCTRL, 1 bits reads, from modem + output r0, MDMFIFORDCTRL + jsr MTX_Iqdump_Common_Preamble ; Send Preamble + + outbset MODCTRL_FECENABLE, MODCTRL ; And enable the noFEC-"FEC" + outbset MCEEVENT0_FIFO_ERR_UNDERFLOW, MCEEVENTCLR0 ; clear any previous + outbset MCEEVENT0_FIFO_ERR_UNDERFLOW, MCEEVENTMSK0 ; allow FIFO UNDERFLOW errors + wait ; WAITS for FIFO underflow here + outbclr MCEEVENT0_FIFO_ERR_UNDERFLOW, MCEEVENTMSK0 ; Remove FIFO UNDERFLOW events + jsr MTX_Iqdump_Termination + jmp CMD_OK_END + + ;;; -------------------------------------------------------------------------- + ;;; Multi-level FSK modulation, directly feed 4-bits into SOFT TX register, at baud rate + ;;; + MTX_MFSK: + outset MCEEVENTCLR0 + outset MCEEVENTCLR1 + + DBG_PRINT0 "IQDump___ Multi-level FSK TX Mode" + lli 0x03, r0 ; 4 bit reads, from register + output r0, MDMFIFORDCTRL + ;; Set modctrl to read from modsofftx: + outbset MODCTRL_SOFTTXENABLE, MODCTRL + ;; ============================================ + ;; Wait for RAT event + outbset MCEEVENT1_RAT_EVENT0, MCEEVENTMSK1 ; enable wait for RAT + wait + outbset MCEEVENT1_RAT_EVENT0, MCEEVENTCLR1 ; Clear event again + outbclr MCEEVENT1_RAT_EVENT0, MCEEVENTMSK1 ; disable wait for RAT + ;; Send message to RFE that modulation is starting + outbset 0,RFESEND + ;; Enable modulator and timebase now + outbset MDMENABLE_TIMEBASE, MDMENABLE + outbset MDMINIT_TIMEBASE, MDMINIT + outbset MDMENABLE_MODULATOR, MDMENABLE + outbset MDMINIT_MODULATOR, MDMINIT + + ;; This mode uses no preamble or SW, just direct symbols from the FIFO. + ;; It starts by waiting if no symbols are present + mov 0, r0 ; Start by sending symbol 0 + output r0, MODSOFTTX ; ready to go + outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTCLR1 ; Clear CLKEN Baud + outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTMSK1 ; will iterate on CLKEN baud ticks + MTX_MFSK_ToneLoop: + wait + outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTCLR1 ; Clear CLKEN Baud + input MDMFIFOSTA, r0 + and 2, r0 ; Check with bit 1 (data present) + cmp 2, r0 + bne MTX_MFSK_ToneLoop + ;; At this point, we can actually read data from the FIFO, 4 bits at a time + DBG_PRINT0 "Starting MFSK Symbol Loop" + MTX_MFSK_SymbolLoop: + wait + outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTCLR1 ; Clear CLKEN Baud + input MDMFIFORD, r1 ; get new nibble + output r1, MODSOFTTX ; send to MODISF + nop + nop + nop + input MDMFIFOSTA, r2 + and 2, r2 ; check with bit 1 (data present) + ;; DEBUG: + ;sl0 8, r1 ; Make signed + ;sl0 4, r1 + ;srx 8, r1 ; make signed + ;srx 4, r1 + ;DBG_PRINT1 "Payload: %d", r1 + ;; END OF DEBUG + cmp 2, r2 + beq MTX_MFSK_SymbolLoop + ;; + ;; FIFO is now empty, so terminate + DBG_PRINT0 "Stopping MFSK Symbol Loop" + outbclr MODCTRL_SOFTTXENABLE, MODCTRL + jsr MTX_Iqdump_Termination + jmp CMD_OK_END + + ;;; -------------------------------------------------------------------------- + ;;; MRX IQdump REGISTER Blind MODE, update the following registers DEMFRAC4/DEMFRAC5/DEMPDIF0 + ;;; Infinite, must be end by abort command + ;;; + MRX_Entry_REG_BLIND: + ;;; Just to be sure those interrupts are disabled, there is no normal termination. + outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; disable the clkenbaud_4f event + outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 ; disable correlation event + outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2 ; disable correlation event + outset MCEEVENTCLR0 + outset MCEEVENTCLR1 + jsr MRX_SETUP + + DBG_PRINT0 "########################### Blind REGISTER MODE -> IQ Dump starting at once ########################" + outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; enable the clkenbaud_4f event + lli 3, r5 ; to trigger capture of I and Q + + LOOP_SAMPLES_BLIND: + wait + output r5, RDCAPT1 ; capture I + Q from FRAC + outbset RDCAPT0_DEMPDIF0, RDCAPT0 ; capture instantaneous frequency + outbset MCESTROBES0_EVENT0, MCESTROBES0 ; signal 4BAUD + outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0 ; clear the clkenbaud_4f event + + jmp LOOP_SAMPLES_BLIND ; + + ;;; -------------------------------------------------------------------------- + ;;; MRX IQdump blind FIFO MODE started where IQ samples are moved into RFC FIFO + ;;; - Packet size can be programmed by the API + ;;; + MRX_Entry_FIFO_BLIND: + ;;; Just to be sure those interrupts are disabled, there is no normal termination. + outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; disable the clkenbaud_4f event + outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 ; disable correlation event + outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2 ; disable correlation event + outset MCEEVENTCLR0 + outset MCEEVENTCLR1 + jsr MRX_SETUP + + lli 24, r11 ; Set Word Counter + lli 0x0, r0 ; MDMFIFOWRCTRL, 1 bits write, from modem + output r0, MDMFIFOWRCTRL + mov 0, r12 ; Clear bit counter + mov 1, r8 ; preload register for known pattern generation + lmd IQDUMP_TEST_MAX_VAL, r10 ; Test pattern wrap value + lmd IQDUMP_MAX_POS_VAL, r13 ; Positive Saturation value for 12 bit resolution + lmd IQDUMP_MIN_NEG_VAL, r14 ; Negative Saturation value for 12 bit resolution + mov r10, r9 ; preload register for known pattern generation + + outbset MCESTROBES0_EVENT0, MCESTROBES0 ; signal Sync Found immediately + outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; enable the clkenbaud_4 event + + ;;; Add delay between sync found is signalled and first RFC FIFO write. + ;;; Wait loop for cm0 to be ready to do full speed readout from RFC FIFO (otherwise longer delay than 8.4us has been observed!) + lli 5, r0 + LOOP_SAMPLES_FIFO_BLIND_WAIT: + outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0 ; clear the clkenbaud_4 event + wait + loop LOOP_SAMPLES_FIFO_BLIND_WAIT + + + DBG_PRINT0 "########################### Blind RFC FIFO Mode -> IQ Dump starting at once (DataRate <= 12,5 kbps) ########################" + lli 3, r5 ; to trigger capture of I and Q + + LOOP_SAMPLES_FIFO_BLIND: + outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0 ; clear the clkenbaud_4 event + wait ; Only 4baud event wakes up TopSM + output r5, RDCAPT1 ; capture I + Q from FRAC + input DEMFRAC4, r0 + + jsr SignExt_and_Saturate ; Saturate to 12 bit word + + input MDMSPAR2, r1 ; MDMSPAR2[0] 0-> IQ data, 1 -> Known Test pattern (counter value) + btst 0, r1 + beq LOOP_SAMPLES_FIFO_BLIND_DEMFRAC4WR + mov r8, r0 ; Known link test pattern + cmp r10, r8 + bne TEST_PATTERN_ADD_BLIND + mov 0, r8 + TEST_PATTERN_ADD_BLIND: + add 1, r8 + LOOP_SAMPLES_FIFO_BLIND_DEMFRAC4WR: + jsr MDMFIFOWR_AND_WAIT10 + + + input DEMFRAC5, r0 + jsr SignExt_and_Saturate ; Saturate to 12 bit word + input MDMSPAR2, r1 ; MDMSPAR2[0] 0-> IQ data, 1 -> Known Test pattern (counter value) + btst 0, r1 + beq LOOP_SAMPLES_FIFO_BLIND_DEMFRAC5WR + mov r9, r0 ; Known link test pattern + sub 1, r9 + cmp 0, r9 + bne LOOP_SAMPLES_FIFO_BLIND_DEMFRAC5WR + mov r10, r9 + LOOP_SAMPLES_FIFO_BLIND_DEMFRAC5WR: + jsr MDMFIFOWR_AND_WAIT10 + + input MDMCMDPAR1, r4 ; check if length has been given + cmp 0, r4 ; if length is zero, infinite length is assumed + beq LOOP_SAMPLES_FIFO_BLIND + add r11, r12 ; increment bit counter + cmp r4, r12 ; End if rxbits - pktLen >= 0 + bpl MRX_GenFSK_CommonEnd ; if so jump to end + jmp LOOP_SAMPLES_FIFO_BLIND ; + + + ;;; -------------------------------------------------------------------------- + ;;; MRX Transparent FIFO MODE started where pdiff hard decisions are moved into FIFO + ;;; - Packet size and stop AGC can be programmed by the API + ;;; + MRX_Entry_TRANSPARENT_FIFO: + ;;; Just to be sure those interrupts are disabled, there is no normal termination. + outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; disable the clkenbaud_4f event + outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 ; disable correlation event + outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2 ; disable correlation event + outset MCEEVENTCLR0 + outset MCEEVENTCLR1 + jsr MRX_SETUP + + outclr MDMFIFOWRCTRL ; MDMFIFOWRCTRL, 1 bits write, from modem + mov 0, r12 ; Clear bit counter + mov 0, r5 ; Data filtered soft samples + + outbset MCESTROBES0_EVENT0, MCESTROBES0 ; signal Sync Found immediately + outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; enable the clkenbaud_4 event + + ;;; Add delay between sync found is signalled and first RFC FIFO write. + ;;; Wait loop for cm0 to be ready to do full speed readout from RFC FIFO (otherwise longer delay than 8.4us has been observed!) + lli 5, r0 + LOOP_SAMPLES_TRANSPARENT_FIFO_WAIT: + outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0 ; clear the clkenbaud_4 event + wait + loop LOOP_SAMPLES_TRANSPARENT_FIFO_WAIT + + DBG_PRINT0 "########################### Transparent FIFO Mode -> PDIFF streaming starting at once ########################" + + lmd TRANSPARENT_CAPT, r13 ; Combined RDCAPT0_DEMPDIF0 and RDCAPT0_DEMFIFE2 + input VITACCCTRL, r14 ; Capture for later use, time optimization + + LOOP_SAMPLES_TRANSPARENT_FIFO: + outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0 ; clear the clkenbaud_4 event + wait ; Only 4baud event wakes up TopSM + input MDMSPAR1, r0 + btst 0, r0 + beq CAPT_FREQUENCY + input RFESEND, r0 + btst 1, r0 + bne CAPT_FREQUENCY + outbset 1, RFESEND ; Notify by bit 1 in RFESEND (i.e. Stop AGC) + DBG_PRINT0 "########################### Transparent FIFO Mode Stop AGC ########################" + + + CAPT_FREQUENCY: + output r13, RDCAPT0 ; capture instantaneous frequency and fife + input DEMPDIF0, r2 + sl0 8, r2 ; Sign Extend + srx 8, r2 + input DEMFIFE2,r0 + sl0 8, r0 ; Sign Extend + srx 8, r0 ; + ;mov r0, r9 ; For debug only + sub r0, r2 ; Subtract Frequency offset + + and 3, r14 ; extract lower two bits + cmp 0, r14 ; + beq NO_IIR_FILTER ; + cmp 2, r14 ; + beq IIR_K4 ; + cmp 3, r14 ; + beq IIR_K8 ; + IIR_K2: + ;; make a simple IIR y[n] = y[n-1]/2 + x[n]/2 + ;; r5 = y + ;; first calculate y[n-1]*2 + mov r5, r6 ; y[n-1] into r6 + add r2, r6 ; add new sample + srx 1, r6 ; scale back to normal again + mov r6, r5 ; copy to r5 + jmp HARD_DECISION ; + IIR_K4: + ;; make a simple IIR y[n] = y[n-1]3/4 + x[n]/4 + ;; r5 = y + ;; first calculate y[n-1]*3/4 + mov r5, r6 ; y[n-1] into r6 + sl0 2, r6 ; multiply by 4 + sub r5,r6 ; sub x1 to get multiply by 3 + add r2, r6 ; add new sample + srx 2, r6 ; scale back to normal again + mov r6, r5 ; copy to r5 + jmp HARD_DECISION ; + IIR_K8: + ;; make a simple IIR y[n] = y[n-1]7/8 + x[n]/8 + ;; r5 = y + ;; first calculate y[n-1]*7/8 + mov r5, r6 ; y[n-1] into r6 + sl0 3, r6 ; multiply by 8 + sub r5,r6 ; sub x1 to get multiply by 7 + add r2, r6 ; add new sample + srx 3, r6 ; scale back to normal again + mov r6, r5 ; copy to r5 + jmp HARD_DECISION ; + NO_IIR_FILTER: + mov r2, r6 ; + + HARD_DECISION: + ;mov r6, r8 ; For debugging only + sr0 7, r6 + output r6, MDMFIFOWR ; Send hard decision to FIFO + ;DBG_PRINT1 "Sample: %d", r8 + input MDMCMDPAR1, r4 ; check if length has been given + cmp 0, r4 ; if length is zero, infinite length is assumed + beq LOOP_SAMPLES_TRANSPARENT_FIFO + add 1, r12 ; increment bit counter + cmp r4, r12 ; End if rxbits - pktLen >= 0 + bpl MRX_GenFSK_CommonEnd ; if so jump to end + jmp LOOP_SAMPLES_TRANSPARENT_FIFO ; + + ;;; -------------------------------------------------------------------------- + ;;; Sub-routine wirte to FIFO and wait + ;;; + ;;; + MDMFIFOWR_AND_WAIT10: + mov r0, r1 + lli 11, r0 + LOOP_MDMFIFOWR: + output r1, MDMFIFOWR + sr0 1, r1 + mov r0, r0 ; + mov r0, r0 ; + mov r0, r0 ; + loop LOOP_MDMFIFOWR + rts + + + ;;; -------------------------------------------------------------------------- + ;;; Sub-routine doing sign extension and Saturate to 12 bits + ;;; + ;;; + SignExt_and_Saturate: + sl0 3, r0 + srx 3, r0 ; Sign extend to 16 bits + + cmp r13, r0 ; + bpl Pos_Sat ; if r0 is > MAX_VAL, saturate to MAX_VAL + cmp r14, r0 + bmi Neg_Sat ; if r0 is < MIN_VAL, saturate to MIN_VAL + rts + + Pos_Sat: + mov r13, r0 + rts + + Neg_Sat: + mov r14, r0 + rts + + ;;; -------------------------------------------------------------------------- + ;;; MRX IQdump REGISTER Sync MODE, update the following registers DEMFRAC4/DEMFRAC5/DEMPDIF0 + ;;; Infinite, must be end by abort command + ;;; IQ dump start after SFD detection + ;;; + MRX_Entry_REG_SYNC: + DBG_PRINT0 "########################### IQ Dump REGISTER MODE, RX started, Wait for Sync ########################" + ;;; Just to be sure those interrupts are disabled, there is no normal termination. + outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; disable the clkenbaud_4f event + outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 ; disable correlation event + outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2 ; disable correlation event + outset MCEEVENTCLR0 + outset MCEEVENTCLR1 + jsr MRX_SETUP + + ;; Enable Correlator event + outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2 ; Clear correlator event + outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 ; enable correlation event + + + SYNC_SEARCH: + wait + input MCEEVENT2, r0 ; + btst MCEEVENT2_C1BE_A_POS_PEAK, r0 ; check if correlator peak + bne DUMP_SAMPLES ; + jmp SYNC_SEARCH ; otherwise continue sync search + + + DUMP_SAMPLES: + outbset 1, RFESEND ; Notify by bit 1 in RFESEND (sync found) + + DBG_PRINT0 "########################### Sync Found REGISTER MODE -> IQ Dump starting ########################" + outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2 ; clear the event flag + outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 ; disable correlation event + outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; enable the clkenbaud_4f event + lli 3, r5 ; to trigger capture of I and Q + + + LOOP_SAMPLES: + wait + output r5, RDCAPT1 ; capture I + Q from FRAC + outbset RDCAPT0_DEMPDIF0, RDCAPT0 ; capture instantaneous frequency + outbset MCESTROBES0_EVENT0, MCESTROBES0 ; signal 4BAUD to cm0/cm3 + outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0 ; clear the clkenbaud_4f event + jmp LOOP_SAMPLES ; + + ;;; -------------------------------------------------------------------------- + ;;; MRX IQdump Sync FIFO MODE started where IQ samples are moved into RFC FIFO + ;;; - Packet size can be programmed by the API + ;;; - IQ dump start after SFD detection + ;;; + MRX_Entry_FIFO_SYNC: + DBG_PRINT0 "########################### IQ Dump through RFC FIFO, RX started, Wait for Sync (DataRate <= 12.5 kbps) ########################" + ;;; Just to be sure those interrupts are disabled, there is no normal termination. + outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; disable the clkenbaud_4f event + outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 ; disable correlation event + outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2 ; disable correlation event + outset MCEEVENTCLR0 + outset MCEEVENTCLR1 + jsr MRX_SETUP + + lli 24, r11 ; Set Word Counter + lli 0x0, r0 ; MDMFIFOWRCTRL, 1 bits write, from modem + output r0, MDMFIFOWRCTRL + mov 0, r12 ; Clear bit counter + mov 1, r8 ; preload register for known pattern generation + lmd IQDUMP_TEST_MAX_VAL, r10 ; Test pattern wrap value + lmd IQDUMP_MAX_POS_VAL, r13 ; Positive Saturation value for 12 bit resolution + lmd IQDUMP_MIN_NEG_VAL, r14 ; Negative Saturation value for 12 bit resolution + mov r10, r9 ; preload register for known pattern generation + + + ;; Enable Correlator event + outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2 ; Clear correlator event + outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 ; enable correlation event + + + SYNC_SEARCH_FIFO: + wait + input MCEEVENT2, r0 ; + btst MCEEVENT2_C1BE_A_POS_PEAK, r0 ; check if correlator peak + bne DUMP_SAMPLES_FIFO ; + jmp SYNC_SEARCH_FIFO ; otherwise continue sync search + + + DUMP_SAMPLES_FIFO: + outbset MCESTROBES0_EVENT0, MCESTROBES0 ; signal Sync Found + outbset 1, RFESEND ; Notify by bit 1 in RFESEND (sync found) + + DBG_PRINT0 "########################### Sync Found RFC FIFO MODE-> IQ samples through FIFO starting ########################" + outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2 ; clear the event flag + outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 ; disable correlation event + outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; enable the clkenbaud_4 event + + ;;; Add delay between sync found is signalled and first RFC FIFO write. + ;;; Wait loop for cm0 to be ready to do full speed readout from RFC FIFO (otherwise longer delay than 8.4us has been observed!) + lli 2, r0 + LOOP_SAMPLES_FIFO_SYNC_WAIT: + outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0 ; clear the clkenbaud_4 event + wait + loop LOOP_SAMPLES_FIFO_SYNC_WAIT + + lli 3, r5 ; to trigger capture of I and Q + + LOOP_SAMPLES_FIFO_SYNC: + outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0 ; clear the clkenbaud_4 event + wait ; Only 4baud event wakes up TopSM + output r5, RDCAPT1 ; capture I + Q from FRAC + input DEMFRAC4, r0 + jsr SignExt_and_Saturate ; Saturate to 12 bit word + + input MDMSPAR2, r1 ; MDMSPAR2[0] 0-> IQ data, 1 -> Known Test pattern (counter value) + btst 0, r1 + beq LOOP_SAMPLES_FIFO_SYNC_DEMFRAC4WR + mov r8, r0 ; Known link test pattern + cmp r10, r8 + bne TEST_PATTERN_ADD_SYNC + mov 0, r8 + TEST_PATTERN_ADD_SYNC: + add 1, r8 + LOOP_SAMPLES_FIFO_SYNC_DEMFRAC4WR: + jsr MDMFIFOWR_AND_WAIT10 + + + input DEMFRAC5, r0 + jsr SignExt_and_Saturate ; Saturate to 12 bit word + input MDMSPAR2, r1 ; MDMSPAR2[0] 0-> IQ data, 1 -> Known Test pattern (counter value) + btst 0, r1 + beq LOOP_SAMPLES_FIFO_SYNC_DEMFRAC5WR + mov r9, r0 ; Known link test pattern + sub 1, r9 + cmp 0, r9 + bne LOOP_SAMPLES_FIFO_SYNC_DEMFRAC5WR + mov r10, r9 + LOOP_SAMPLES_FIFO_SYNC_DEMFRAC5WR: + jsr MDMFIFOWR_AND_WAIT10 + + input MDMCMDPAR1, r4 ; check if length has been given + cmp 0, r4 ; if length is zero, infinite length is assumed + beq LOOP_SAMPLES_FIFO_SYNC + add r11, r12 ; increment bit counter + cmp r4, r12 ; End if rxbits - pktLen >= 0 + bpl MRX_GenFSK_CommonEnd ; if so jump to end + jmp LOOP_SAMPLES_FIFO_SYNC ; + + + + MRX_SETUP: + + ;; Wait for RFE to finish enabling Rx chain + input RFERCEV, r0 ; + btst 3, r0 ; + bne RFE_Started ; + + outbset MCEEVENT0_RFECMD_IRQ, MCEEVENTMSK0 + wait ; Wait for RFE to be done + outbset MCEEVENT0_RFECMD_IRQ, MCEEVENTCLR0 + + ;; Disable event + outbclr MCEEVENT0_RFECMD_IRQ, MCEEVENTMSK0 + + jmp MRX_SETUP ; Go back to test received event + + RFE_Started: + DBG_PRINT0 "########################### RX Started ########################" + outbset MCEEVENT0_CPEFWEVENT0, MCEEVENTCLR0 ; Clear any pending CPEFWEVENT0 + + + ;; Enable Demodulator, ADCDIG, Timebase and submodules + ;;; Enable ADCDIG, and start sync search + outbset MDMENABLE_ADCDIG, MDMENABLE + outbset MDMINIT_ADCDIG, MDMINIT + ;;; Enable RX, and start sync search + outbset MDMENABLE_DEMODULATOR, MDMENABLE + outbset MDMINIT_DEMODULATOR, MDMINIT + ;; Enable timebase now. + outbset MDMENABLE_TIMEBASE, MDMENABLE + outbset MDMINIT_TIMEBASE, MDMINIT + + + ;; Compute MASKA+MASKB for SyncWords < 32 bits + ;; (the threshold adjusted automatically by the CPE) + input DEMC1BE0, r0 ; Load DEMC1BE0 + lmd DEMC1BE0_MASKA_BITS, r2 ; Clear only bits [15:6], keep rest + and r2, r0 ; + input MDMCMDPAR0, r3 ; Get number of bits in SyncWord again + sr0 8, r3 ; MDMCMDPAR0[15:8] + bclr 7, r3 ; Ignore MSB always + output r3, DEMSWQU0 ; set SyncWordBits-1 in DEMSWQU0 for future reference + lli 31, r2 ; Compute 31-X + sub r3, r2 ; R2 = 31-SyncWordBits + sl0 DEMC1BE0_MASKA, r2 ; Shift to proper position + mov r2, r1 ; copy + sl0 5, r1 ; shift to mask b position + or r1, r2 ; combine mask a + mask b + or r2, r0 ; put together + output r0, DEMC1BE0 ; and done + + ;; IQDUMP use running sum hardware in DSBU for frequency offset estimation, FOE (for supporting non random data) + ;; The DSBU delay shall be the synw word length+a few samples for processing delay + ;; DSBBU avg length shall be set to 8, 16 or 32 symbols (rounded down from the sync word length) due to division needed + ;;; Start calculating DSBU.LEN + mov r3, r0 ; Load r0 with SyncWordBits-1 + add 1,r0 ; Calculate SyncWordBits + sr0 3,r0 ; Floor(SyncWordBits/8) (number of whole bytes in sw) + + btst 1, r0 ; we don't allow 3 bytes averaging, set this to two bytes + beq GEN_FSK_AVG_LEN_CORRECT + mov 2, r0 ; force a 16 bit avg length + GEN_FSK_AVG_LEN_CORRECT: + sl0 5,r0 ; 4*8*Floor(SyncWordBits/8), i.e. osr = 4 (number of samples in DSBU averaging) + mov r0, r3 ; DSBUAVGLENGTH for future use + + sl0 8, r0 ; Shift to proper position + add 3,r0 ; DSBUDELAY = DSBUAVGLENGTH+3 + output r0, DEMDSBU + + + ;; Find imbalance in that part of sync word which is used in dsbu averaging + ;; Implement this equation: DEMSWIMBAL = (sum(sw)-DEMDSBU.dsbuavglength/2)*4*32/DEMDSBU.dsbuavglength + mov 0, r2 ; + mov 0, r4 ; + GEN_FSK_DSBU_AVG_LEN_32_SYMBOLS_CHECK: + btst 7, r3 ; Check if we got 128 sample averaging + beq GEN_FSK_DSBU_AVG_LEN_16_SYMBOLS_CHECK ; + GEN_FSK_DSBU_AVG_LEN_32_SYMBOLS: + input MDMSYNC0, r0 ; 16 first symbols of sw A is in MDMSYNC0 + output r0, COUNT1IN ; Find number of ones + input COUNT1RES, r2 ; r2 is keeping the number of 1s in the sw A + sub 8, r2 ; subtract 8 to get imbalance between 1's and 0's in this 16 bits part of SW + input MDMSYNC2, r0 ; 16 first symbols of sw A is in MDMSYNC2 + output r0, COUNT1IN ; Find number of ones + input COUNT1RES, r4 ; r4 is keeping the number of 1s in the sw B + sub 8, r4 ; subtract 8 to get imbalance between 1's and 0's in this 16 bits part of SW + jmp GEN_FSK_DSBU_AVG_LEN_16_SYMBOLS ; For 32 bit sync use both SYNC0 and SYNC1 + GEN_FSK_DSBU_AVG_LEN_16_SYMBOLS_CHECK: + btst 6, r3 ; Check if DSBU memory is 16 symbols (or 64 samples) + beq GEN_FSK_DSBU_AVG_LEN_8_SYMBOLS ; + GEN_FSK_DSBU_AVG_LEN_16_SYMBOLS: + input MDMSYNC1, r0 ; 16 Last transmitted sync bits of sw A is located in SYNC1, swlen>=16 + output r0, COUNT1IN ; Find number of ones in the sw and store in DEMSWIMBAL for future reference + input COUNT1RES, r0 ; + sub 8, r0 ; subtract 8 to get imbalance in this 16 bit part of sw A + add r0, r2 ; load r2 = sum(x) + input MDMSYNC3, r0 ; 16 Last transmitted sync bits of sw B is located in SYNC1, swlen>=16 + output r0, COUNT1IN ; Find number of ones in the sw and store in DEMSWIMBAL for future reference + input COUNT1RES, r0 ; + sub 8, r0 ; subtract 8 to get imbalance in this 16 bit part of sw B + add r0, r4 ; load r4 = sum(x) + jmp GEN_FSK_CALC_DEMSWIMBAL ; sum(sw) done for 32 symbols FOE + GEN_FSK_DSBU_AVG_LEN_8_SYMBOLS: + input MDMSYNC1, r0 ;8 Last transmitted sync bits of SW A is located in SYNC1(31:24), swlen>=8 + lmd IQDUMP_MASK_BITS_15_8, r1 + and r1,r0 + output r0, COUNT1IN ; Find number of ones in the sw A and store in DEMSWIMBAL for future reference + input COUNT1RES, r2 ; load r2 = sum(x) + sub 4, r2 ; subtract 4 to get imbalance in this byte of SW A + input MDMSYNC3, r0 ;8 Last transmitted sync bits of SW B is located in SYNC3(31:24), swlen>=8 + lmd IQDUMP_MASK_BITS_15_8, r1 + and r1,r0 + output r0, COUNT1IN ; Find number of ones in the sw B and store in DEMSWIMBAL for future reference + input COUNT1RES, r4 ; load r4 = sum(x) + sub 4, r4 ; subtract 4 to get imbalance in this byte of SW B + GEN_FSK_CALC_DEMSWIMBAL: + ;; balance between 1's and 0's in SW will have to be scaled with the dsbu avg length + ;; 32 bit avg length we shall multiply by 4 + ;; 16 bit avg length we shall multiply by 8 + ;; 8 bit avg length we shall multiply by 16 + ;; to make a more efficient shift below we start with a multiply by 32 + sl0 5, r2 ; always multiply sw a imbalance by 32 + sl0 5, r4 ; always multiply sw b imbalance by 32 + sr0 6, r3 ; shift avg length down + and 3, r3 ; mask other bits + add 1, r3 ; + sr0 r3, r2 ; divide with 2 or 4 or 8 depending on avg length + sr0 r3, r4 ; divide with 2 or 4 or 8 depending on avg length + sl0 8, r2 ; + sr0 8, r2 ; + sl0 8, r4 ; + or r4, r2 ; combine swA and sw b + output r2, DEMSWIMBAL ; + GEN_FSK_CALC_DEMSWIMBAL_DONE: + + ;; Copy all sync registers to new correlator registers + input MDMSYNC0, r0 + output r0, DEMC1BEREF0 + input MDMSYNC1, r0 + output r0, DEMC1BEREF1 + input MDMSYNC2, r0 + output r0, DEMC1BEREF2 + input MDMSYNC3, r0 + output r0, DEMC1BEREF3 + + ;; Initial Module Enables + lmd DEMENABLE0_RX_IQDUMP, r0 + output r0, DEMENABLE0 ; cmix, ctil, bdec, chfi, fidc, frac ,iqmc, enable + output r0, DEMINIT0 + lmd DEMENABLE1_RX_IQDUMP, r0 + output r0, DEMENABLE1 ; + output r0, DEMINIT1 + outbset 5, RFESEND ; send message to rfe that reception is starting + + lli 0xD9, r0 ; + output r0, MDMCMDPAR0 ; + rts + + ;;; ============================================================================================ + ;;; Common End of RX function + + MRX_GenFSK_CommonEnd: + outbclr 5, RFESEND ; tell RFE packet is ending + ;;; Wait to let RFE end + outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0 ; clear the clkenbaud_4 event + wait + + outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; disable the clkenbaud_4f event + outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0 ; clear the clkenbaud_4f event + outbset RDCAPT0_DEMLQIE0, RDCAPT0 ; Capture LQI into MDMSTATUS[15:8] + input MDMSTATUS, r0 + input DEMLQIE0, r4 + sr0 2, r4 ; Divide by 4 first + sl0 8, r4 + or r0,r4 + output r4, MDMSTATUS ; Warning: CPE use MDMSTATUS[1:0] for CMD_DONE checking + DBG_PRINT0 "All bits received, MCE Ending" + ;; Hard init of all modules except FIFO + outset TIMCTRL ; + outclr TIMCTRL ; + jsr MODCTRL_CLR ; + + outclr MDMENABLE_ADCDIG, MDMENABLE ; + outclr MDMENABLE_TIMEBASE, MDMENABLE ; + outclr MDMENABLE_DEMODULATOR, MDMENABLE ; + outset DEMINIT0 ; + outset DEMINIT1 ; + jmp CMD_OK_END + + + ;; clear all bits in MODCTRL exept bit 12 (keep bit 12) + MODCTRL_CLR: + input MODCTRL, r0 ; + lli 0x80, r1 ; + sl0 5, r1 ; set bit 12 to 1 + and r1, r0 ; + output r0, MODCTRL ; + rts + + + + + DBG_FUNC +