diff --git a/src/hardware/fx2lafw/dslogic.c b/src/hardware/fx2lafw/dslogic.c
index ec8d5342..2f0ffa32 100644
--- a/src/hardware/fx2lafw/dslogic.c
+++ b/src/hardware/fx2lafw/dslogic.c
@@ -25,7 +25,12 @@
 #include "protocol.h"
 #include "dslogic.h"
 
-#define FW_BUFSIZE (4 * 1024)
+/*
+ * This should be larger than the FPGA bitstream image so that it'll get
+ * uploaded in one big operation. There seem to be issues when uploading
+ * it in chunks.
+ */
+#define FW_BUFSIZE (1024 * 1024)
 
 #define FPGA_UPLOAD_DELAY (10 * 1000)
 
diff --git a/src/hardware/fx2lafw/dslogic.h b/src/hardware/fx2lafw/dslogic.h
index 54067693..411e8331 100644
--- a/src/hardware/fx2lafw/dslogic.h
+++ b/src/hardware/fx2lafw/dslogic.h
@@ -64,7 +64,7 @@ struct dslogic_trigger_pos {
  */
 #define _DS_CFG(variable, wordcnt) ((variable << 8) | wordcnt)
 #define _DS_CFG_PAD(variable, wordcnt) ((_DS_CFG(variable, wordcnt) << 16) | 0xffff)
-#define DS_CFG_START		0xffffffff
+#define DS_CFG_START		0xf5a5f5a5
 #define DS_CFG_MODE		_DS_CFG(0, 1)
 #define DS_CFG_DIVIDER		_DS_CFG_PAD(1, 2)
 #define DS_CFG_COUNT		_DS_CFG_PAD(3, 2)
@@ -82,7 +82,7 @@ struct dslogic_trigger_pos {
 #define DS_CFG_TRIG_COUNT1	_DS_CFG_PAD(29, 16)
 #define DS_CFG_TRIG_LOGIC0	_DS_CFG_PAD(32, 16)
 #define DS_CFG_TRIG_LOGIC1	_DS_CFG_PAD(33, 16)
-#define DS_CFG_END		0x00000000
+#define DS_CFG_END		0xfa5afa5a
 
 struct dslogic_fpga_config {
 	uint32_t sync;