From 780c5e246689290c1e28ec270da42a6049bf30f2 Mon Sep 17 00:00:00 2001 From: Joel Holdsworth Date: Mon, 12 Jun 2017 16:46:31 -0600 Subject: [PATCH] dslogic: Added half and quater-mode flags --- src/hardware/dslogic/dslogic.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/hardware/dslogic/dslogic.c b/src/hardware/dslogic/dslogic.c index 4d466143..297af2b0 100644 --- a/src/hardware/dslogic/dslogic.c +++ b/src/hardware/dslogic/dslogic.c @@ -345,6 +345,12 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi) v16 = DS_MODE_EXT_TEST; else if (devc->mode == DS_OP_LOOPBACK_TEST) v16 = DS_MODE_LPB_TEST; + + if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 2) + v16 |= DS_MODE_HALF_MODE; + else if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 4) + v16 |= DS_MODE_QUAR_MODE; + if (devc->continuous_mode) v16 |= DS_MODE_STREAM_MODE; if (devc->external_clock) {