diff --git a/src/main.rs b/src/main.rs index 65df08c..cfc45c5 100644 --- a/src/main.rs +++ b/src/main.rs @@ -395,6 +395,8 @@ fn parse_instruction(mut bytes: &[u16]) -> (Instruction, usize) { consumed += 1; //println!("{:016b}", aw); + + // this shiftright shouldn't be needed... but it is. aw >>= 4; for i in 0..register_count { registers.insert(0_usize, Register::into_register(aw & 0b1111)); @@ -513,13 +515,13 @@ impl Machine { let arg0 = ci.args[0].as_immediate(); self.write(ci.args[1], arg0); self.RSTAT.set(Flags::FZERO, arg0 == 0); - //eprintln!("copying {} to {:?}", arg0, ci.args[1]); + log::info!("copying {} to {:?}", arg0, ci.args[1]); } OP::CMP => { let a = self.read(ci.args[0]); let b = self.read(ci.args[1]); - log::debug!("CMP({}, {})", a, b); + log::info!("CMP({}, {})", a, b); self.RSTAT.set(Flags::FZERO, a == 0 || b == 0); self.RSTAT.set(Flags::FEQUL, a == b); @@ -547,7 +549,7 @@ impl Machine { let mut val = self.read(ci.args[0]); val = val.wrapping_add(1); self.write(ci.args[0], val); - log::debug!("INC({:?}) to {}", ci.args[0], val); + log::info!("INC({:?}) to {}", ci.args[0], val); self.RSTAT.set(Flags::FZERO, val == 0); } OP::READ => { @@ -647,7 +649,7 @@ impl Machine { self.write(ci.args[0], val); self.RSTAT.set(Flags::FZERO, val == 0); } - _ => { eprintln!("unsupported opcode {:?}, continuing", oc); return false; } + _ => { eprintln!("unsupported opcode {:?}", oc); return false; } } if should_inc_ip { @@ -683,7 +685,7 @@ fn main() { let mut m = Machine::default(); m.SIN[1..=sin.inner().len()].copy_from_slice(sin.inner()); m.SCODE[1..=code.inner().len()].copy_from_slice(code.inner()); - m.input = b"\x09\x0f\xcc\xcc\xcc\xcc\x0c\x0c\x00\x00\x00\x0a".to_vec(); + m.input = b"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x0a".to_vec(); // dump_instructions(&m.SCODE[1..=code.inner().len()]);