diff --git a/src/main.rs b/src/main.rs
index a056555..990cb95 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -1,6 +1,7 @@
 use byteorder::{ReadBytesExt, LE};
 use std::io::Cursor;
 use std::convert::{TryInto, TryFrom};
+use std::io::Read;
 
 struct Machine {
     RX: u16,
@@ -522,20 +523,32 @@ impl Machine {
             }
             OP::JEQU => {
                 if self.RSTAT.contains(Flags::FEQUL) {
+                    if self.RTRGT == 0 {
+                        return false;
+                    }
                     self.IP = self.RTRGT;
                     should_inc_ip = false;
                 }
             }
+            OP::JUMP => {
+                if self.RTRGT == 0 {
+                    return false;
+                }
+
+                self.IP = self.RTRGT;
+                should_inc_ip = false;
+            }
             OP::INC => {
                 let mut val = self.read(ci.args[0]);
-                val += 1;
+                val = val.wrapping_add(1);
                 self.write(ci.args[0], val);
                 self.RSTAT.set(Flags::FZERO, val == 0);
             }
             OP::READ => {
                 let input = 0;
+                std::io::stdin().read(&mut [input]).unwrap();
 
-                self.write(ci.args[0], input);
+                self.write(ci.args[0], input as u16);
                 self.RSTAT.set(Flags::FZERO, input == 0);
             }
             OP::CPY => {
@@ -558,6 +571,19 @@ impl Machine {
                 self.push_stack(self.RTRGT);
                 self.RTRGT = 0;
             }
+            OP::RCPT => {
+                let by: i32 = if ci.def.sign() == 1 {
+                    self.RTRGT as i32
+                } else {
+                    -(self.RTRGT as i32)
+                };
+
+                let from = self.read(ci.args[0]);
+                let to = ci.args[1].offset(by);
+                self.write(to, from);
+
+                self.RSTAT.set(Flags::FZERO, from == 0);
+            }
             OP::RCPF => {
                 let by: i32 = if ci.def.sign() == 1 {
                     self.RTRGT as i32