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kicad/qa/data/pcbnew/complex_hierarchy.kicad_pro

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Adding QA project files
2020-07-28 17:44:51 +00:00
{
"board": {
Update QA boards' fills
2023-07-20 19:08:17 +00:00
"3dviewports": [],
Fix typo
2020-09-23 21:00:39 +00:00
"design_settings": {
"defaults": {
"board_outline_line_width": 0.2032,
"copper_line_width": 0.381,
"copper_text_italic": false,
"copper_text_size_h": 1.524,
"copper_text_size_v": 2.032,
"copper_text_thickness": 0.30479999999999996,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.8128,
"height": 2.286,
"width": 2.286
},
"silk_line_width": 0.381,
"silk_text_italic": false,
"silk_text_size_h": 1.524,
"silk_text_size_v": 1.524,
"silk_text_thickness": 0.30479999999999996,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.508
}
},
Apply same nettie hack to zone filler The nettie hack is used in DRC but we also need to use it in zone filler to allow zones to be used with netties. We limit this to the appropriate nets in the nettie Fixes https://gitlab.com/kicad/code/kicad/issues/7351
2021-02-01 00:15:24 +00:00
"diff_pair_dimensions": [],
Fix typo
2020-09-23 21:00:39 +00:00
"drc_exclusions": [],
"meta": {
Apply same nettie hack to zone filler The nettie hack is used in DRC but we also need to use it in zone filler to allow zones to be used with netties. We limit this to the appropriate nets in the nettie Fixes https://gitlab.com/kicad/code/kicad/issues/7351
2021-02-01 00:15:24 +00:00
"filename": "board_design_settings.json",
Outline font support.
2022-01-01 01:21:03 +00:00
"version": 2
Fix typo
2020-09-23 21:00:39 +00:00
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
Update QA boards' fills
2023-07-20 19:08:17 +00:00
"connection_width": "warning",
Fix typo
2020-09-23 21:00:39 +00:00
"copper_edge_clearance": "error",
Outline font support.
2022-01-01 01:21:03 +00:00
"copper_sliver": "warning",
Fix typo
2020-09-23 21:00:39 +00:00
"courtyards_overlap": "error",
Allow creating new projects when doing a Save As in eeschema
2020-10-06 02:13:06 +00:00
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
Don't simplify hierarchical nets based on weak drivers This behavior provided shorter net names, but was confusing if the user gives an explicit strong driver in the subsheet but not one in the parent sheet. Testcases updated for net name changes; connectivity is the same Fixes https://gitlab.com/kicad/code/kicad/-/issues/4201
2021-01-14 03:10:56 +00:00
"drill_out_of_range": "error",
Fix typo
2020-09-23 21:00:39 +00:00
"duplicate_footprints": "warning",
"extra_footprint": "warning",
Update QA boards' fills
2023-07-20 19:08:17 +00:00
"footprint": "error",
"footprint_type_mismatch": "ignore",
Fix typo
2020-09-23 21:00:39 +00:00
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
Update QA boards' fills
2023-07-20 19:08:17 +00:00
"isolated_copper": "warning",
Fix typo
2020-09-23 21:00:39 +00:00
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
Allow creating new projects when doing a Save As in eeschema
2020-10-06 02:13:06 +00:00
"length_out_of_range": "error",
Update QA boards' fills
2023-07-20 19:08:17 +00:00
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
Fix typo
2020-09-23 21:00:39 +00:00
"malformed_courtyard": "error",
Don't simplify hierarchical nets based on weak drivers This behavior provided shorter net names, but was confusing if the user gives an explicit strong driver in the subsheet but not one in the parent sheet. Testcases updated for net name changes; connectivity is the same Fixes https://gitlab.com/kicad/code/kicad/-/issues/4201
2021-01-14 03:10:56 +00:00
"microvia_drill_out_of_range": "error",
Fix typo
2020-09-23 21:00:39 +00:00
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
Update QA boards' fills
2023-07-20 19:08:17 +00:00
"padstack": "warning",
Fix typo
2020-09-23 21:00:39 +00:00
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
Update QA boards' fills
2023-07-20 19:08:17 +00:00
"silk_edge_clearance": "warning",
Outline font support.
2022-01-01 01:21:03 +00:00
"silk_over_copper": "warning",
"silk_overlap": "warning",
Allow creating new projects when doing a Save As in eeschema
2020-10-06 02:13:06 +00:00
"skew_out_of_range": "error",
Outline font support.
2022-01-01 01:21:03 +00:00
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
Allow creating new projects when doing a Save As in eeschema
2020-10-06 02:13:06 +00:00
"too_many_vias": "error",
Fix typo
2020-09-23 21:00:39 +00:00
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.0,
Update QA boards' fills
2023-07-20 19:08:17 +00:00
"min_connection": 0.0,
Outline font support.
2022-01-01 01:21:03 +00:00
"min_copper_edge_clearance": 0.1016,
"min_hole_clearance": 0.25,
Fix typo
2020-09-23 21:00:39 +00:00
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.508,
"min_microvia_drill": 0.2032,
Outline font support.
2022-01-01 01:21:03 +00:00
"min_resolved_spokes": 2,
Add testcase for bus junctions problem
2020-10-28 03:02:49 +00:00
"min_silk_clearance": 0.0,
Outline font support.
2022-01-01 01:21:03 +00:00
"min_text_height": 0.7999999999999999,
Update QA boards' fills
2023-07-20 19:08:17 +00:00
"min_text_thickness": 0.08,
Fix typo
2020-09-23 21:00:39 +00:00
"min_through_hole_diameter": 0.508,
"min_track_width": 0.2032,
Update QA boards' fills
2023-07-20 19:08:17 +00:00
"min_via_annular_width": 0.09999999999999999,
Fix typo
2020-09-23 21:00:39 +00:00
"min_via_diameter": 0.889,
Outline font support.
2022-01-01 01:21:03 +00:00
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
Fix typo
2020-09-23 21:00:39 +00:00
},
Emplace_back a bit a in clipper
2022-02-06 02:00:34 +00:00
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
Apply same nettie hack to zone filler The nettie hack is used in DRC but we also need to use it in zone filler to allow zones to be used with netties. We limit this to the appropriate nets in the nettie Fixes https://gitlab.com/kicad/code/kicad/issues/7351
2021-02-01 00:15:24 +00:00
"track_widths": [],
"via_dimensions": [],
Fix typo
2020-09-23 21:00:39 +00:00
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
Outline font support.
2022-01-01 01:21:03 +00:00
"layer_presets": [],
"viewports": []
Adding QA project files
2020-07-28 17:44:51 +00:00
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "complex_hierarchy.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
Update QA boards' fills
2023-07-20 19:08:17 +00:00
"bus_width": 12,
Fix typo
2020-09-23 21:00:39 +00:00
"clearance": 0.2794,
Adding QA project files
2020-07-28 17:44:51 +00:00
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
Fix typo
2020-09-23 21:00:39 +00:00
"microvia_diameter": 0.508,
"microvia_drill": 0.2032,
Adding QA project files
2020-07-28 17:44:51 +00:00
"name": "Default",
Exclude from bill of materials and board netlist to library symbols. ADDED: Support for exclude from bill of materials and board netlist to library symbols. Fixes https://gitlab.com/kicad/code/kicad/issues/4915
2020-09-09 13:03:37 +00:00
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
Fix typo
2020-09-23 21:00:39 +00:00
"track_width": 0.4318,
"via_diameter": 1.651,
"via_drill": 0.635,
Update QA boards' fills
2023-07-20 19:08:17 +00:00
"wire_width": 6
Fix typo
2020-09-23 21:00:39 +00:00
},
{
Update QA boards' fills
2023-07-20 19:08:17 +00:00
"bus_width": 12,
Fix typo
2020-09-23 21:00:39 +00:00
"clearance": 0.381,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.508,
"microvia_drill": 0.2032,
"name": "power",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.6096,
"via_diameter": 1.651,
"via_drill": 0.635,
Update QA boards' fills
2023-07-20 19:08:17 +00:00
"wire_width": 6
Adding QA project files
2020-07-28 17:44:51 +00:00
}
],
"meta": {
Update QA boards' fills
2023-07-20 19:08:17 +00:00
"version": 3
Adding QA project files
2020-07-28 17:44:51 +00:00
},
Update QA boards' fills
2023-07-20 19:08:17 +00:00
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "Default",
"pattern": "+12V"
},
{
"netclass": "Default",
"pattern": "/ampli_h1"
},
{
"netclass": "Default",
"pattern": "/ampli_h2"
},
{
"netclass": "Default",
"pattern": "/ampli_h3"
},
{
"netclass": "Default",
"pattern": "/ampli_h4"
},
{
"netclass": "Default",
"pattern": "/ampli_h5"
},
{
"netclass": "Default",
"pattern": "/ampli_h6"
},
{
"netclass": "Default",
"pattern": "/ampli_h7"
},
{
"netclass": "Default",
"pattern": "/ampli_h8"
},
{
"netclass": "Default",
"pattern": "N-000005"
},
{
"netclass": "Default",
"pattern": "N-000010"
},
{
"netclass": "Default",
"pattern": "N-000011"
},
{
"netclass": "Default",
"pattern": "N-000012"
},
{
"netclass": "Default",
"pattern": "N-000013"
},
{
"netclass": "Default",
"pattern": "N-000014"
},
{
"netclass": "Default",
"pattern": "N-000015"
},
{
"netclass": "Default",
"pattern": "N-000016"
},
{
"netclass": "Default",
"pattern": "N-000017"
},
{
"netclass": "Default",
"pattern": "N-000018"
},
{
"netclass": "Default",
"pattern": "N-000019"
},
{
"netclass": "Default",
"pattern": "N-000020"
},
{
"netclass": "Default",
"pattern": "N-000021"
},
{
"netclass": "Default",
"pattern": "N-000022"
},
{
"netclass": "Default",
"pattern": "N-000023"
},
{
"netclass": "Default",
"pattern": "N-000024"
},
{
"netclass": "Default",
"pattern": "N-000025"
},
{
"netclass": "Default",
"pattern": "N-000026"
},
{
"netclass": "Default",
"pattern": "N-000027"
},
{
"netclass": "Default",
"pattern": "N-000032"
},
{
"netclass": "Default",
"pattern": "N-000033"
},
{
"netclass": "Default",
"pattern": "N-000034"
},
{
"netclass": "Default",
"pattern": "N-000035"
},
{
"netclass": "Default",
"pattern": "N-000036"
},
{
"netclass": "Default",
"pattern": "N-000037"
},
{
"netclass": "Default",
"pattern": "N-000038"
},
{
"netclass": "Default",
"pattern": "N-000039"
},
{
"netclass": "Default",
"pattern": "N-000040"
},
{
"netclass": "Default",
"pattern": "N-000041"
},
{
"netclass": "Default",
"pattern": "N-000042"
},
{
"netclass": "Default",
"pattern": "N-000043"
},
{
"netclass": "Default",
"pattern": "N-000044"
},
{
"netclass": "Default",
"pattern": "N-000045"
},
{
"netclass": "Default",
"pattern": "N-000046"
},
{
"netclass": "Default",
"pattern": "N-000047"
},
{
"netclass": "Default",
"pattern": "N-000048"
},
{
"netclass": "power",
"pattern": "-VAA"
},
{
"netclass": "power",
"pattern": "/12Vext"
},
{
"netclass": "power",
"pattern": "GND"
},
{
"netclass": "power",
"pattern": "HT"
},
{
"netclass": "power",
"pattern": "VCC"
}
]
Adding QA project files
2020-07-28 17:44:51 +00:00
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
Allow creating new projects when doing a Save As in eeschema
2020-10-06 02:13:06 +00:00
"vmrl": "",
"vrml": ""
Adding QA project files
2020-07-28 17:44:51 +00:00
},
"page_layout_descr_file": ""
},
"schematic": {
"legacy_lib_dir": "",
"legacy_lib_list": []
},
"sheets": [],
"text_variables": {}
}