kicad/demos/simulation/pspice/pspice.pro

update=21/11/2017 21:20:51
last_client=kicad
[general]
version=1
RootSch=pspice.sch
BoardNm=pspice.brd
[pcbnew]
version=1
PadDrlX=320
PadDimH=600
PadDimV=600
BoardThickness=630
SgPcb45=1
TxtPcbV=800
TxtPcbH=600
TxtModV=600
TxtModH=600
TxtModW=120
VEgarde=100
DrawLar=150
EdgeLar=150
TxtLar=120
MSegLar=150
LastNetListRead=
[pcbnew/libraries]
LibDir=
LibName1=sockets
LibName2=connect
LibName3=discret
LibName4=pin_array
LibName5=divers
LibName6=libcms
LibName7=display
LibName8=valves
LibName9=led
LibName10=dip_sockets
[eeschema]
version=1
LibDir=
Update demos 2017-11-21 20:26:06 +00:00			`update=21/11/2017 21:20:51`
Update pspice demo 2017-05-29 16:10:25 +00:00			`last_client=kicad`
1) Add "rules" to base of tree for copying into BZR_HOME/rules. File "rules" has instructional text as comments near top. 2) Convert all text files in repo to LF line ending form. Any checkout done with "rules" in play will convert the working tree to native line ending, while keeping repo as LF line ending. 2013-05-26 04:36:44 +00:00			`[general]`
			`version=1`
			`RootSch=pspice.sch`
			`BoardNm=pspice.brd`
			`[pcbnew]`
			`version=1`
			`PadDrlX=320`
			`PadDimH=600`
			`PadDimV=600`
			`BoardThickness=630`
			`SgPcb45=1`
			`TxtPcbV=800`
			`TxtPcbH=600`
			`TxtModV=600`
			`TxtModH=600`
			`TxtModW=120`
			`VEgarde=100`
			`DrawLar=150`
			`EdgeLar=150`
			`TxtLar=120`
			`MSegLar=150`
			`LastNetListRead=`
			`[pcbnew/libraries]`
			`LibDir=`
			`LibName1=sockets`
			`LibName2=connect`
			`LibName3=discret`
			`LibName4=pin_array`
			`LibName5=divers`
			`LibName6=libcms`
			`LibName7=display`
			`LibName8=valves`
			`LibName9=led`
			`LibName10=dip_sockets`
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) . 2014-01-07 19:42:34 +00:00			`[eeschema]`
			`version=1`
			`LibDir=`