56 lines
1.5 KiB
Plaintext
56 lines
1.5 KiB
Plaintext
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* Class D audio amp frontend (to drive a power MOS half bridge)
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* analog input
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* pwm clock generator
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* digital one-shot
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* non-overlapping clock
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* two floating half-bridge drivers
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* Calling the subcircuit
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* Xpwm ain lo+ lo- hi+ hi- DAudioDriver freq = 500k dtime = 100n voutp = 1.4 voutn = 0
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.subckt DAudioDriver ain lo+ lo- hi+ hi- params: freq = 317k dtime = 50n voutp = 12 voutn = 0
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apwm1 ain dfast1 pwm_osc
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.model pwm_osc d_pwm(cntl_array = [-2 -1.99 1.99 2]
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+ dc_array = [0.1 0.1 0.9 0.9]
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+ frequency = {freq} init_phase = 90.0
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a6 dfast1 _d1 inv1
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.model inv1 d_inverter(rise_delay = 0.3e-9 fall_delay = 0.3e-9
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+ input_load = 0.5e-12)
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* equalize d1 and _d1
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abuf2 dfast1 d1 buff2
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.model buff2 d_buffer(rise_delay = 0.3e-9 fall_delay = 0.3e-9
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+ input_load = 0.5e-12)
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*** one-shot ***
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* buffer
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abuf1 dfast1 d2 buff1
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.model buff1 d_buffer(rise_delay = {dtime} fall_delay = {dtime}
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+ input_load = 0.5e-12)
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* one-shot 1->0 output
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a9 [dfast1 d2] dos xnor3
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.model xnor3 d_xnor(rise_delay = 0.2e-9 fall_delay = 0.2e-9
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+ input_load = 0.5e-12)
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***
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* outputs: inverted, non-overlapping
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aand1 [d1 dos] dout1 and1
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aand2 [_d1 dos] dout2 and1
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.model and1 d_and(rise_delay = 0.4e-9 fall_delay = 0.4e-9
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+ input_load = 0.5e-12)
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* analog out, differential
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abridge1 [dout1] [%vd(lo+ lo-)] dac1
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abridge2 [dout2] [%vd(hi+ hi-)] dac1
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.model dac1 dac_bridge(out_low = {voutn} out_high = {voutp} out_undef = 0
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+ input_load = 5.0e-12 t_rise = 20e-9
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+ t_fall = 20e-9)
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* test
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* do we have overlap?
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* aandtest [dout1 dout2] dtest and1
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.ends
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