2020-09-23 21:49:34 +00:00
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/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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2022-03-11 21:16:52 +00:00
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* Copyright (C) 2004-2022 KiCad Developers.
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2020-09-23 21:49:34 +00:00
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*
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2020-09-26 20:42:56 +00:00
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* This program is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation, either version 3 of the License, or (at your
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* option) any later version.
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2020-09-23 21:49:34 +00:00
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*
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2020-09-26 20:42:56 +00:00
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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2020-09-23 21:49:34 +00:00
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*
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2020-09-26 20:42:56 +00:00
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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2020-09-23 21:49:34 +00:00
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*/
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#include <common.h>
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2020-11-12 20:19:22 +00:00
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#include <board.h>
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2021-12-30 14:34:44 +00:00
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#include <board_design_settings.h>
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2020-11-12 20:19:22 +00:00
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#include <pad.h>
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2021-06-11 21:07:02 +00:00
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#include <pcb_track.h>
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2020-09-23 21:49:34 +00:00
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#include <drc/drc_item.h>
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#include <drc/drc_rule.h>
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#include <drc/drc_test_provider.h>
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2020-09-25 18:29:05 +00:00
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#include <drc/drc_length_report.h>
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2020-09-23 21:49:34 +00:00
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#include <connectivity/connectivity_data.h>
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2020-09-25 18:29:05 +00:00
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#include <connectivity/from_to_cache.h>
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2020-09-23 21:49:34 +00:00
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#include <pcb_expr_evaluator.h>
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/*
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2020-09-25 18:29:05 +00:00
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Single-ended matched length + skew + via count test.
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2020-09-23 21:49:34 +00:00
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Errors generated:
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2020-09-25 18:29:05 +00:00
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- DRCE_LENGTH_OUT_OF_RANGE
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- DRCE_SKEW_OUT_OF_RANGE
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- DRCE_TOO_MANY_VIAS
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2020-09-26 20:42:56 +00:00
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Todo: arc support
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2020-09-23 21:49:34 +00:00
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*/
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class DRC_TEST_PROVIDER_MATCHED_LENGTH : public DRC_TEST_PROVIDER
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{
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public:
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2020-10-25 09:02:07 +00:00
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DRC_TEST_PROVIDER_MATCHED_LENGTH () :
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m_board( nullptr )
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2020-09-23 21:49:34 +00:00
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{
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}
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2020-10-01 13:39:34 +00:00
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virtual ~DRC_TEST_PROVIDER_MATCHED_LENGTH()
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2020-09-23 21:49:34 +00:00
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{
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}
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virtual bool Run() override;
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2020-10-01 13:39:34 +00:00
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virtual const wxString GetName() const override
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2020-09-23 21:49:34 +00:00
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{
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2022-03-11 21:16:52 +00:00
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return wxT( "length" );
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2020-09-23 21:49:34 +00:00
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};
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virtual const wxString GetDescription() const override
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{
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2022-03-11 21:16:52 +00:00
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return wxT( "Tests matched track lengths." );
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2020-09-23 21:49:34 +00:00
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}
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2020-09-25 18:29:05 +00:00
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DRC_LENGTH_REPORT BuildLengthReport() const;
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2020-09-23 21:49:34 +00:00
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private:
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2020-09-25 18:29:05 +00:00
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bool runInternal( bool aDelayReportMode = false );
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2020-09-23 21:49:34 +00:00
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2021-07-28 20:04:53 +00:00
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using CONNECTION = DRC_LENGTH_REPORT::ENTRY;
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2020-09-23 21:49:34 +00:00
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2022-03-12 13:34:25 +00:00
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void checkLengths( const DRC_CONSTRAINT& aConstraint,
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const std::vector<CONNECTION>& aMatchedConnections );
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void checkSkews( const DRC_CONSTRAINT& aConstraint,
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const std::vector<CONNECTION>& aMatchedConnections );
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void checkViaCounts( const DRC_CONSTRAINT& aConstraint,
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const std::vector<CONNECTION>& aMatchedConnections );
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2020-09-23 21:49:34 +00:00
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BOARD* m_board;
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2020-09-25 18:29:05 +00:00
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DRC_LENGTH_REPORT m_report;
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2020-09-23 21:49:34 +00:00
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};
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2022-03-12 13:34:25 +00:00
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void DRC_TEST_PROVIDER_MATCHED_LENGTH::checkLengths( const DRC_CONSTRAINT& aConstraint,
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const std::vector<CONNECTION>& aMatchedConnections )
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2020-09-23 21:49:34 +00:00
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{
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2021-07-28 20:04:53 +00:00
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for( const DRC_LENGTH_REPORT::ENTRY& ent : aMatchedConnections )
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2020-09-23 21:49:34 +00:00
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{
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2020-09-25 18:29:05 +00:00
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bool minViolation = false;
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bool maxViolation = false;
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2020-10-01 13:39:34 +00:00
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int minLen = 0;
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int maxLen = 0;
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2020-09-23 21:49:34 +00:00
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2020-09-25 18:29:05 +00:00
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if( aConstraint.GetValue().HasMin() && ent.total < aConstraint.GetValue().Min() )
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2020-09-23 21:49:34 +00:00
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{
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2020-09-25 18:29:05 +00:00
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minViolation = true;
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minLen = aConstraint.GetValue().Min();
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2020-09-23 21:49:34 +00:00
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}
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2020-09-25 18:29:05 +00:00
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else if( aConstraint.GetValue().HasMax() && ent.total > aConstraint.GetValue().Max() )
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2020-09-23 21:49:34 +00:00
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{
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2020-09-25 18:29:05 +00:00
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maxViolation = true;
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maxLen = aConstraint.GetValue().Max();
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}
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2020-09-23 21:49:34 +00:00
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2020-09-25 18:29:05 +00:00
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if( ( minViolation || maxViolation ) )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_LENGTH_OUT_OF_RANGE );
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2022-06-15 23:42:34 +00:00
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wxString msg;
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2020-09-23 21:49:34 +00:00
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2020-09-25 18:29:05 +00:00
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if( minViolation )
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{
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2022-06-15 23:42:34 +00:00
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msg.Printf( _( "(%s min length: %s; actual: %s)" ),
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2020-11-02 16:20:00 +00:00
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aConstraint.GetName(),
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MessageTextFromValue( userUnits(), minLen ),
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MessageTextFromValue( userUnits(), ent.total ) );
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2020-09-25 18:29:05 +00:00
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}
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else if( maxViolation )
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{
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2022-06-15 23:42:34 +00:00
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msg.Printf( _( "(%s max length: %s; actual: %s)" ),
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2020-11-02 16:20:00 +00:00
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aConstraint.GetName(),
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MessageTextFromValue( userUnits(), maxLen ),
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MessageTextFromValue( userUnits(), ent.total ) );
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2020-09-25 18:29:05 +00:00
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}
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2020-09-23 21:49:34 +00:00
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2022-06-15 23:42:34 +00:00
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drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + msg );
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2020-09-23 21:49:34 +00:00
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2020-09-25 18:29:05 +00:00
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for( auto offendingTrack : ent.items )
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2020-09-27 15:51:16 +00:00
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drcItem->AddItem( offendingTrack );
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2020-09-23 21:49:34 +00:00
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2020-09-25 18:29:05 +00:00
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drcItem->SetViolatingRule( aConstraint.GetParentRule() );
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2020-09-23 21:49:34 +00:00
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2021-12-26 13:47:00 +00:00
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reportViolation( drcItem, ( *ent.items.begin() )->GetPosition(),
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( *ent.items.begin() )->GetLayer() );
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2020-09-23 21:49:34 +00:00
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}
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}
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2020-09-25 18:29:05 +00:00
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}
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2020-09-23 21:49:34 +00:00
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2022-03-12 13:34:25 +00:00
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void DRC_TEST_PROVIDER_MATCHED_LENGTH::checkSkews( const DRC_CONSTRAINT& aConstraint,
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const std::vector<CONNECTION>& aMatchedConnections )
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2020-09-25 18:29:05 +00:00
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{
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int avgLength = 0;
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2020-09-23 21:49:34 +00:00
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2021-07-28 20:04:53 +00:00
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for( const DRC_LENGTH_REPORT::ENTRY& ent : aMatchedConnections )
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2020-09-25 18:29:05 +00:00
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avgLength += ent.total;
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2020-09-23 21:49:34 +00:00
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2021-07-28 20:04:53 +00:00
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avgLength /= aMatchedConnections.size();
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2020-09-23 21:49:34 +00:00
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2021-07-28 20:04:53 +00:00
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for( const auto& ent : aMatchedConnections )
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2020-09-25 18:29:05 +00:00
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{
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int skew = ent.total - avgLength;
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if( aConstraint.GetValue().HasMax() && abs( skew ) > aConstraint.GetValue().Max() )
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2020-09-23 21:49:34 +00:00
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{
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2020-09-25 18:29:05 +00:00
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_SKEW_OUT_OF_RANGE );
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2022-06-15 23:42:34 +00:00
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wxString msg;
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2020-09-23 21:49:34 +00:00
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2022-06-15 23:42:34 +00:00
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msg.Printf( _( "(%s max skew: %s; actual: %s; average net length: %s; actual: %s)" ),
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2020-11-02 16:20:00 +00:00
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aConstraint.GetName(),
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MessageTextFromValue( userUnits(), aConstraint.GetValue().Max() ),
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MessageTextFromValue( userUnits(), skew ),
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MessageTextFromValue( userUnits(), avgLength ),
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MessageTextFromValue( userUnits(), ent.total ) );
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2020-09-23 21:49:34 +00:00
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2022-06-15 23:42:34 +00:00
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drcItem->SetErrorMessage( drcItem->GetErrorText() + " " + msg );
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2020-09-23 21:49:34 +00:00
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2020-11-02 16:20:00 +00:00
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for( BOARD_CONNECTED_ITEM* offendingTrack : ent.items )
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2020-09-25 18:29:05 +00:00
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drcItem->SetItems( offendingTrack );
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2020-09-23 21:49:34 +00:00
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2020-09-25 18:29:05 +00:00
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drcItem->SetViolatingRule( aConstraint.GetParentRule() );
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2020-09-23 21:49:34 +00:00
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2021-12-26 13:47:00 +00:00
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reportViolation( drcItem, ( *ent.items.begin() )->GetPosition(),
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( *ent.items.begin() )->GetLayer() );
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2020-09-23 21:49:34 +00:00
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}
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}
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2020-09-25 18:29:05 +00:00
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}
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2020-09-23 21:49:34 +00:00
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2022-03-12 13:34:25 +00:00
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void DRC_TEST_PROVIDER_MATCHED_LENGTH::checkViaCounts( const DRC_CONSTRAINT& aConstraint,
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const std::vector<CONNECTION>& aMatchedConnections )
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2020-09-25 18:29:05 +00:00
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{
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2021-07-28 20:04:53 +00:00
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for( const auto& ent : aMatchedConnections )
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2020-09-23 21:49:34 +00:00
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{
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2020-09-25 18:29:05 +00:00
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if( aConstraint.GetValue().HasMax() && ent.viaCount > aConstraint.GetValue().Max() )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_TOO_MANY_VIAS );
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2022-06-15 23:42:34 +00:00
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wxString msg;
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2020-09-23 21:49:34 +00:00
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2022-06-15 23:42:34 +00:00
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msg.Printf( _( "(%s max count: %d; actual: %d)" ),
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2020-11-02 16:20:00 +00:00
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aConstraint.GetName(),
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aConstraint.GetValue().Max(),
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ent.viaCount );
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2020-09-23 21:49:34 +00:00
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2022-06-15 23:42:34 +00:00
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drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + msg );
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2020-09-23 21:49:34 +00:00
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2020-09-25 18:29:05 +00:00
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for( auto offendingTrack : ent.items )
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drcItem->SetItems( offendingTrack );
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2020-09-23 21:49:34 +00:00
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2020-09-25 18:29:05 +00:00
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drcItem->SetViolatingRule( aConstraint.GetParentRule() );
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2020-09-23 21:49:34 +00:00
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2021-12-26 13:47:00 +00:00
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reportViolation( drcItem, ( *ent.items.begin() )->GetPosition(),
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( *ent.items.begin() )->GetLayer() );
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2020-09-23 21:49:34 +00:00
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}
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}
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}
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2020-11-02 16:20:00 +00:00
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bool DRC_TEST_PROVIDER_MATCHED_LENGTH::Run()
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2020-09-25 18:29:05 +00:00
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{
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return runInternal( false );
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2020-09-23 21:49:34 +00:00
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}
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2020-11-02 16:20:00 +00:00
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bool DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal( bool aDelayReportMode )
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2020-09-23 21:49:34 +00:00
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{
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m_board = m_drcEngine->GetBoard();
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2020-09-25 18:29:05 +00:00
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m_report.Clear();
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2020-09-23 21:49:34 +00:00
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2020-09-25 18:29:05 +00:00
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if( !aDelayReportMode )
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{
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2020-10-05 13:31:10 +00:00
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if( !reportPhase( _( "Gathering length-constrained connections..." ) ) )
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return false;
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2020-09-25 18:29:05 +00:00
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}
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2020-09-23 21:49:34 +00:00
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2021-07-28 20:04:53 +00:00
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std::map<DRC_RULE*, std::set<BOARD_CONNECTED_ITEM*> > itemSets;
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2020-09-23 21:49:34 +00:00
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2022-03-09 00:47:37 +00:00
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std::shared_ptr<FROM_TO_CACHE> ftCache = m_board->GetConnectivity()->GetFromToCache();
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ftCache->Rebuild( m_board );
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2022-03-12 13:34:25 +00:00
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// This is the number of tests between 2 calls to the progress bar
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const size_t delta = 50;
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size_t count = 0;
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size_t ii = 0;
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forEachGeometryItem( { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T }, LSET::AllCuMask(),
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[&]( BOARD_ITEM *item ) -> bool
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{
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count++;
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return true;
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} );
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2022-03-09 00:47:37 +00:00
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forEachGeometryItem( { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T }, LSET::AllCuMask(),
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2020-09-23 21:49:34 +00:00
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[&]( BOARD_ITEM *item ) -> bool
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{
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2022-03-12 13:34:25 +00:00
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if( !reportProgress( ii++, count, delta ) )
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return false;
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2021-01-01 22:29:15 +00:00
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const DRC_CONSTRAINT_T constraintsToCheck[] = {
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2020-11-02 16:20:00 +00:00
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LENGTH_CONSTRAINT,
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SKEW_CONSTRAINT,
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VIA_COUNT_CONSTRAINT,
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2020-09-25 18:29:05 +00:00
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};
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for( int i = 0; i < 3; i++ )
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{
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2021-02-08 14:53:49 +00:00
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auto constraint = m_drcEngine->EvalRules( constraintsToCheck[i], item, nullptr,
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item->GetLayer() );
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2020-09-23 21:49:34 +00:00
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2020-09-25 18:29:05 +00:00
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if( constraint.IsNull() )
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continue;
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2020-09-23 21:49:34 +00:00
|
|
|
|
2020-09-25 18:29:05 +00:00
|
|
|
auto citem = static_cast<BOARD_CONNECTED_ITEM*>( item );
|
2020-09-23 21:49:34 +00:00
|
|
|
|
2020-09-25 18:29:05 +00:00
|
|
|
itemSets[ constraint.GetParentRule() ].insert( citem );
|
|
|
|
}
|
2020-09-23 21:49:34 +00:00
|
|
|
|
|
|
|
return true;
|
2022-03-09 00:47:37 +00:00
|
|
|
} );
|
2020-09-23 21:49:34 +00:00
|
|
|
|
2022-03-12 13:34:25 +00:00
|
|
|
std::map< DRC_RULE*, std::vector<CONNECTION> > matches;
|
2020-09-23 21:49:34 +00:00
|
|
|
|
2022-03-12 13:34:25 +00:00
|
|
|
for( const std::pair< DRC_RULE* const, std::set<BOARD_CONNECTED_ITEM*> >& it : itemSets )
|
2020-09-23 21:49:34 +00:00
|
|
|
{
|
2021-07-28 20:04:53 +00:00
|
|
|
std::map<int, std::set<BOARD_CONNECTED_ITEM*> > netMap;
|
2020-09-23 21:49:34 +00:00
|
|
|
|
2022-03-12 13:34:25 +00:00
|
|
|
for( BOARD_CONNECTED_ITEM* citem : it.second )
|
2020-09-25 18:29:05 +00:00
|
|
|
netMap[ citem->GetNetCode() ].insert( citem );
|
2020-09-23 21:49:34 +00:00
|
|
|
|
2022-03-12 13:34:25 +00:00
|
|
|
for( const std::pair< const int, std::set<BOARD_CONNECTED_ITEM*> >& nitem : netMap )
|
2020-09-23 21:49:34 +00:00
|
|
|
{
|
2021-07-28 20:04:53 +00:00
|
|
|
CONNECTION ent;
|
2020-09-23 21:49:34 +00:00
|
|
|
ent.items = nitem.second;
|
|
|
|
ent.netcode = nitem.first;
|
|
|
|
ent.netname = m_board->GetNetInfo().GetNetItem( ent.netcode )->GetNetname();
|
|
|
|
|
|
|
|
ent.viaCount = 0;
|
|
|
|
ent.totalRoute = 0;
|
|
|
|
ent.totalVia = 0;
|
|
|
|
ent.totalPadToDie = 0;
|
2020-09-25 18:29:05 +00:00
|
|
|
ent.fromItem = nullptr;
|
|
|
|
ent.toItem = nullptr;
|
|
|
|
|
2020-11-24 22:16:41 +00:00
|
|
|
for( BOARD_CONNECTED_ITEM* citem : nitem.second )
|
2020-09-23 21:49:34 +00:00
|
|
|
{
|
2020-11-24 22:16:41 +00:00
|
|
|
if( citem->Type() == PCB_VIA_T )
|
2020-09-23 21:49:34 +00:00
|
|
|
{
|
2021-12-30 14:34:44 +00:00
|
|
|
const BOARD_DESIGN_SETTINGS& ds = m_board->GetDesignSettings();
|
|
|
|
|
2020-09-23 21:49:34 +00:00
|
|
|
ent.viaCount++;
|
2021-12-30 14:34:44 +00:00
|
|
|
|
|
|
|
if( ds.m_UseHeightForLengthCalcs )
|
|
|
|
{
|
|
|
|
const PCB_VIA* v = static_cast<PCB_VIA*>( citem );
|
|
|
|
|
|
|
|
ent.totalVia += ds.GetStackupDescriptor().GetLayerDistance(
|
|
|
|
v->TopLayer(), v->BottomLayer() );
|
|
|
|
}
|
2020-09-23 21:49:34 +00:00
|
|
|
}
|
2020-11-24 22:16:41 +00:00
|
|
|
else if( citem->Type() == PCB_TRACE_T )
|
2020-09-23 21:49:34 +00:00
|
|
|
{
|
2021-06-11 21:07:02 +00:00
|
|
|
ent.totalRoute += static_cast<PCB_TRACK*>( citem )->GetLength();
|
2020-09-23 21:49:34 +00:00
|
|
|
}
|
2020-11-24 22:16:41 +00:00
|
|
|
else if ( citem->Type() == PCB_ARC_T )
|
2020-09-25 18:29:05 +00:00
|
|
|
{
|
2021-06-11 21:07:02 +00:00
|
|
|
ent.totalRoute += static_cast<PCB_ARC*>( citem )->GetLength();
|
2020-11-24 22:16:41 +00:00
|
|
|
}
|
|
|
|
else if( citem->Type() == PCB_PAD_T )
|
|
|
|
{
|
|
|
|
ent.totalPadToDie += static_cast<PAD*>( citem )->GetPadToDieLength();
|
2020-09-25 18:29:05 +00:00
|
|
|
}
|
2020-09-23 21:49:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
ent.total = ent.totalRoute + ent.totalVia + ent.totalPadToDie;
|
2020-09-25 18:29:05 +00:00
|
|
|
ent.matchingRule = it.first;
|
2020-09-23 21:49:34 +00:00
|
|
|
|
2020-09-26 20:42:56 +00:00
|
|
|
// fixme: doesn't seem to work ;-)
|
|
|
|
auto ftPath = ftCache->QueryFromToPath( ent.items );
|
|
|
|
|
|
|
|
if( ftPath )
|
|
|
|
{
|
|
|
|
ent.from = ftPath->fromName;
|
|
|
|
ent.to = ftPath->toName;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2022-04-02 14:08:32 +00:00
|
|
|
ent.from = ent.to = _( "<unconstrained>" );
|
2020-09-26 20:42:56 +00:00
|
|
|
}
|
|
|
|
|
2020-09-25 18:29:05 +00:00
|
|
|
m_report.Add( ent );
|
2020-09-23 21:49:34 +00:00
|
|
|
matches[ it.first ].push_back(ent);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-09-25 18:29:05 +00:00
|
|
|
if( !aDelayReportMode )
|
2020-09-23 21:49:34 +00:00
|
|
|
{
|
2022-03-12 13:34:25 +00:00
|
|
|
if( !reportPhase( _( "Checking length constraints..." ) ) )
|
|
|
|
return false;
|
|
|
|
|
|
|
|
ii = 0;
|
|
|
|
count = matches.size();
|
|
|
|
|
|
|
|
for( std::pair< DRC_RULE* const, std::vector<CONNECTION> > it : matches )
|
2020-09-23 21:49:34 +00:00
|
|
|
{
|
2020-09-25 18:29:05 +00:00
|
|
|
DRC_RULE *rule = it.first;
|
|
|
|
auto& matchedConnections = it.second;
|
2020-09-23 21:49:34 +00:00
|
|
|
|
2022-03-12 13:34:25 +00:00
|
|
|
if( !reportProgress( ii++, count, delta ) )
|
|
|
|
return false;
|
|
|
|
|
2020-09-25 18:29:05 +00:00
|
|
|
std::sort( matchedConnections.begin(), matchedConnections.end(),
|
2021-07-28 20:04:53 +00:00
|
|
|
[] ( const CONNECTION&a, const CONNECTION&b ) -> int
|
2020-11-02 16:20:00 +00:00
|
|
|
{
|
|
|
|
return a.netname < b.netname;
|
|
|
|
} );
|
2020-09-23 21:49:34 +00:00
|
|
|
|
2022-03-11 21:16:52 +00:00
|
|
|
reportAux( wxString::Format( wxT( "Length-constrained traces for rule '%s':" ),
|
2020-11-02 16:20:00 +00:00
|
|
|
it.first->m_Name ) );
|
2020-09-23 21:49:34 +00:00
|
|
|
|
2022-03-12 13:34:25 +00:00
|
|
|
for( const DRC_LENGTH_REPORT::ENTRY& ent : matchedConnections )
|
2020-09-23 21:49:34 +00:00
|
|
|
{
|
2022-03-11 21:16:52 +00:00
|
|
|
reportAux(wxString::Format( wxT( " - net: %s, from: %s, to: %s, "
|
|
|
|
"%d matching items, "
|
|
|
|
"total: %s (tracks: %s, vias: %s, pad-to-die: %s), "
|
|
|
|
"vias: %d" ),
|
2020-11-02 16:20:00 +00:00
|
|
|
ent.netname,
|
|
|
|
ent.from,
|
|
|
|
ent.to,
|
|
|
|
(int) ent.items.size(),
|
|
|
|
MessageTextFromValue( userUnits(), ent.total ),
|
|
|
|
MessageTextFromValue( userUnits(), ent.totalRoute ),
|
|
|
|
MessageTextFromValue( userUnits(), ent.totalVia ),
|
|
|
|
MessageTextFromValue( userUnits(), ent.totalPadToDie ),
|
|
|
|
ent.viaCount ) );
|
2020-09-25 18:29:05 +00:00
|
|
|
}
|
2020-09-23 21:49:34 +00:00
|
|
|
|
|
|
|
|
2020-11-02 16:20:00 +00:00
|
|
|
OPT<DRC_CONSTRAINT> lengthConstraint = rule->FindConstraint( LENGTH_CONSTRAINT );
|
|
|
|
|
2021-09-05 15:06:12 +00:00
|
|
|
if( lengthConstraint && lengthConstraint->GetSeverity() != RPT_SEVERITY_IGNORE )
|
2021-07-28 20:04:53 +00:00
|
|
|
checkLengths( *lengthConstraint, matchedConnections );
|
2020-09-23 21:49:34 +00:00
|
|
|
|
2020-11-02 16:20:00 +00:00
|
|
|
OPT<DRC_CONSTRAINT> skewConstraint = rule->FindConstraint( SKEW_CONSTRAINT );
|
|
|
|
|
2021-09-05 15:06:12 +00:00
|
|
|
if( skewConstraint && skewConstraint->GetSeverity() != RPT_SEVERITY_IGNORE )
|
2021-07-28 20:04:53 +00:00
|
|
|
checkSkews( *skewConstraint, matchedConnections );
|
2020-09-23 21:49:34 +00:00
|
|
|
|
2020-11-02 16:20:00 +00:00
|
|
|
OPT<DRC_CONSTRAINT> viaCountConstraint = rule->FindConstraint( VIA_COUNT_CONSTRAINT );
|
|
|
|
|
2021-09-05 15:06:12 +00:00
|
|
|
if( viaCountConstraint && viaCountConstraint->GetSeverity() != RPT_SEVERITY_IGNORE )
|
2021-07-28 20:04:53 +00:00
|
|
|
checkViaCounts( *viaCountConstraint, matchedConnections );
|
2020-09-23 21:49:34 +00:00
|
|
|
}
|
|
|
|
|
2020-09-25 18:29:05 +00:00
|
|
|
reportRuleStatistics();
|
|
|
|
}
|
2020-09-23 21:49:34 +00:00
|
|
|
|
2022-03-11 21:16:52 +00:00
|
|
|
return !m_drcEngine->IsCancelled();
|
2020-09-23 21:49:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
namespace detail
|
|
|
|
{
|
2020-11-02 16:20:00 +00:00
|
|
|
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_MATCHED_LENGTH> dummy;
|
2020-10-02 20:51:24 +00:00
|
|
|
}
|