126 lines
1.4 KiB
Prolog
126 lines
1.4 KiB
Prolog
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update=13/5/2006-07:55:36
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version=1
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last_client=pcbnew
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[common]
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NetDir=
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[eeschema]
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version=1
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LibDir=
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NetFmt=1
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HPGLSpd=20
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HPGLDm=15
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HPGLNum=1
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offX_A4=0
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offY_A4=0
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offX_A3=0
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offY_A3=0
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offX_A2=0
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offY_A2=0
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offX_A1=0
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offY_A1=0
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offX_A0=0
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offY_A0=0
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offX_A=0
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offY_A=0
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offX_B=0
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offY_B=0
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offX_C=0
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offY_C=0
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offX_D=0
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offY_D=0
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offX_E=0
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offY_E=0
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RptD_X=0
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RptD_Y=100
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RptLab=1
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PenMin=20
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SimCmd=
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UseNetN=0
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[eeschema/libraries]
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LibName1=power
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LibName2=device
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LibName3=conn
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LibName4=linear
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LibName5=regul
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LibName6=74xx
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LibName7=cmos4000
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LibName8=adc-dac
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LibName9=memory
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LibName10=xilinx
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LibName11=special
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[general]
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version=1
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RootSch=interf_u.sch
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BoardNm=interf_u.brd
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[cvpcb]
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version=1
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NetITyp=0
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NetIExt=.net
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PkgIExt=.pkg
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NetType=0
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[cvpcb/libraries]
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EquName1=devcms
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[pcbnew]
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version=1
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PadDril=1200
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PadDimH=1500
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PadDimV=1500
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PadForm=1
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PadMask=14745599
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ViaDiam=600
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ViaDril=250
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Isol=110
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Countlayer=2
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Lpiste=170
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RouteTo=15
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RouteBo=0
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TypeVia=3
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Segm45=1
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Racc45=1
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Unite=0
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SegFill=1
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SegAffG=0
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NewAffG=1
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PadFill=1
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PadAffG=1
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PadSNum=1
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ModAffC=1
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ModAffT=1
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PcbAffT=1
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SgPcb45=1
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TxtPcbV=800
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TxtPcbH=600
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TxtModV=600
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TxtModH=600
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TxtModW=120
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HPGLnum=1
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HPGdiam=15
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HPGLSpd=20
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HPGLrec=2
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HPGLorg=0
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GERBmin=15
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VEgarde=100
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DrawLar=150
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EdgeLar=150
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TxtLar=170
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MSegLar=150
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ForPlot=1
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WpenSer=10
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UserGrX=0,1
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UserGrY=0,1
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UserGrU=0
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DivGrPc=1
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TimeOut=600
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MaxLnkS=3
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ShowRat=0
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ShowMRa=1
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[pcbnew/libraries]
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LibDir=
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LibName1=connect
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LibName2=discret
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LibName3=pin_array
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LibName4=divers
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LibName5=libcms
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LibName6=supports
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LibName7=display
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