diff --git a/pcbnew/kicad_plugin.cpp b/pcbnew/kicad_plugin.cpp
index e90cb8757c..3f98c1058a 100644
--- a/pcbnew/kicad_plugin.cpp
+++ b/pcbnew/kicad_plugin.cpp
@@ -527,7 +527,7 @@ void PCB_IO::formatLayer( const BOARD_ITEM* aItem ) const
         m_out->Print( 0, " (layer %s)", m_out->Quotew( aItem->GetLayerName() ).c_str() );
 }
 
-void PCB_IO::formatHeader( BOARD* aBoard, int aNestLevel ) const throw(IO_ERROR)
+void PCB_IO::formatSetup( BOARD* aBoard, int aNestLevel ) const throw(IO_ERROR)
 {
 
     const BOARD_DESIGN_SETTINGS& dsnSettings = aBoard->GetDesignSettings();
@@ -609,6 +609,7 @@ void PCB_IO::formatHeader( BOARD* aBoard, int aNestLevel ) const throw(IO_ERROR)
     m_out->Print( aNestLevel, ")\n\n" );
 
     // Setup
+    const BOARD_DESIGN_SETTINGS& dsnSettings = aBoard->GetDesignSettings();
     m_out->Print( aNestLevel, "(setup\n" );
 
     // Save current default track width, for compatibility with older Pcbnew version;
@@ -719,8 +720,99 @@ void PCB_IO::formatHeader( BOARD* aBoard, int aNestLevel ) const throw(IO_ERROR)
     aBoard->GetPlotOptions().Format( m_out, aNestLevel+1 );
 
     m_out->Print( aNestLevel, ")\n\n" );
+}
 
-    // Save net codes and names
+void PCB_IO::formatGeneral( BOARD* aBoard, int aNestLevel ) const throw(IO_ERROR)
+{
+    const BOARD_DESIGN_SETTINGS& dsnSettings = aBoard->GetDesignSettings();
+
+    m_out->Print( 0, "\n" );
+    m_out->Print( aNestLevel, "(general\n" );
+    m_out->Print( aNestLevel+1, "(links %d)\n", aBoard->GetRatsnestsCount() );
+    m_out->Print( aNestLevel+1, "(no_connects %d)\n", aBoard->GetUnconnectedNetCount() );
+
+    // Write Bounding box info
+    EDA_RECT bbox = aBoard->GetBoundingBox();
+    m_out->Print( aNestLevel+1,  "(area %s %s %s %s)\n",
+                  FMTIU( bbox.GetX() ).c_str(), FMTIU( bbox.GetY() ).c_str(),
+                  FMTIU( bbox.GetRight() ).c_str(), FMTIU( bbox.GetBottom() ).c_str() );
+    m_out->Print( aNestLevel+1, "(thickness %s)\n",
+                  FMTIU( dsnSettings.GetBoardThickness() ).c_str() );
+
+    m_out->Print( aNestLevel+1, "(drawings %d)\n", aBoard->m_Drawings.GetCount() );
+    m_out->Print( aNestLevel+1, "(tracks %d)\n", aBoard->GetNumSegmTrack() );
+    m_out->Print( aNestLevel+1, "(zones %d)\n", aBoard->GetNumSegmZone() );
+    m_out->Print( aNestLevel+1, "(modules %d)\n", aBoard->m_Modules.GetCount() );
+    m_out->Print( aNestLevel+1, "(nets %d)\n", m_mapping->GetSize() );
+    m_out->Print( aNestLevel, ")\n\n" );
+
+    aBoard->GetPageSettings().Format( m_out, aNestLevel, m_ctl );
+    aBoard->GetTitleBlock().Format( m_out, aNestLevel, m_ctl );
+}
+
+void PCB_IO::formatBoardLayers( BOARD* aBoard, int aNestLevel ) const throw(IO_ERROR)
+{
+    m_out->Print( aNestLevel, "(layers\n" );
+
+    // Save only the used copper layers from front to back.
+    LSET visible_layers = aBoard->GetVisibleLayers();
+
+    for( LSEQ cu = aBoard->GetEnabledLayers().CuStack();  cu;  ++cu )
+    {
+        PCB_LAYER_ID layer = *cu;
+
+        m_out->Print( aNestLevel+1, "(%d %s %s", layer,
+                      m_out->Quotew( aBoard->GetLayerName( layer ) ).c_str(),
+                      LAYER::ShowType( aBoard->GetLayerType( layer ) ) );
+
+        if( !visible_layers[layer] )
+            m_out->Print( 0, " hide" );
+
+        m_out->Print( 0, ")\n" );
+    }
+
+    // Save used non-copper layers in the order they are defined.
+    // desired sequence for non Cu BOARD layers.
+    static const PCB_LAYER_ID non_cu[] = {
+        B_Adhes,        // 32
+        F_Adhes,
+        B_Paste,
+        F_Paste,
+        B_SilkS,
+        F_SilkS,
+        B_Mask,
+        F_Mask,
+        Dwgs_User,
+        Cmts_User,
+        Eco1_User,
+        Eco2_User,
+        Edge_Cuts,
+        Margin,
+        B_CrtYd,
+        F_CrtYd,
+        B_Fab,
+        F_Fab
+    };
+
+    for( LSEQ seq = aBoard->GetEnabledLayers().Seq( non_cu, DIM( non_cu ) );  seq;  ++seq )
+    {
+        PCB_LAYER_ID layer = *seq;
+
+        m_out->Print( aNestLevel+1, "(%d %s user", layer,
+                      m_out->Quotew( aBoard->GetLayerName( layer ) ).c_str() );
+
+        if( !visible_layers[layer] )
+            m_out->Print( 0, " hide" );
+
+        m_out->Print( 0, ")\n" );
+    }
+
+    m_out->Print( aNestLevel, ")\n\n" );
+}
+
+void PCB_IO::formatNetInformation( BOARD* aBoard, int aNestLevel ) const throw(IO_ERROR)
+{
+    const BOARD_DESIGN_SETTINGS& dsnSettings = aBoard->GetDesignSettings();
     for( NETINFO_MAPPING::iterator net = m_mapping->begin(), netEnd = m_mapping->end();
             net != netEnd; ++net )
     {
@@ -747,6 +839,17 @@ void PCB_IO::formatHeader( BOARD* aBoard, int aNestLevel ) const throw(IO_ERROR)
     }
 }
 
+void PCB_IO::formatHeader( BOARD* aBoard, int aNestLevel ) const throw(IO_ERROR)
+{
+    formatGeneral(aBoard);
+    // Layers.
+    formatBoardLayers(aBoard);
+    // Setup
+    formatSetup( aBoard, aNestLevel );
+    // Save net codes and names
+    formatNetInformation( aBoard, aNestLevel );
+}
+
 void PCB_IO::format( BOARD* aBoard, int aNestLevel ) const
     throw( IO_ERROR )
 {
diff --git a/pcbnew/kicad_plugin.h b/pcbnew/kicad_plugin.h
index 9182d5479e..89e038e595 100644
--- a/pcbnew/kicad_plugin.h
+++ b/pcbnew/kicad_plugin.h
@@ -188,6 +188,18 @@ protected:
 
     void init( const PROPERTIES* aProperties );
 
+    void formatSetup( BOARD* aBoard, int aNestLevel = 0 ) const
+        throw( IO_ERROR );
+
+    void formatGeneral( BOARD* aBoard, int aNestLevel = 0 ) const
+        throw( IO_ERROR );
+
+    void formatBoardLayers( BOARD* aBoard, int aNestLevel = 0 ) const
+        throw( IO_ERROR );
+
+    void formatNetInformation( BOARD* aBoard, int aNestLevel = 0 ) const
+        throw( IO_ERROR );
+
     /// writes everything that comes before the board_items, like settings and layers etc
     void formatHeader( BOARD* aBoard, int aNestLevel = 0 ) const
         throw( IO_ERROR );