From 096e34238672ca29dbdec32d8720ee3aeaf304b6 Mon Sep 17 00:00:00 2001 From: Jeff Young Date: Fri, 11 Jun 2021 22:07:02 +0100 Subject: [PATCH] Prefix TRACK, ARC and VIA. --- 3d-viewer/3d_canvas/board_adapter.h | 5 +- .../3d_canvas/create_3Dgraphic_brd_items.cpp | 4 +- 3d-viewer/3d_canvas/create_layer_items.cpp | 40 +-- 3d-viewer/3d_canvas/eda_3d_canvas.cpp | 2 +- .../3d_render_raytracing/create_scene.cpp | 6 +- .../3d_render_raytracing/render_3d_raytrace.h | 2 +- .../3d_rendering/legacy/create_scene.cpp | 4 +- common/CMakeLists.txt | 2 +- gerbview/export_to_pcbnew.h | 2 +- include/core/typeinfo.h | 8 +- include/pcb_base_frame.h | 1 - pcbnew/autorouter/ar_autoplacer.cpp | 1 - pcbnew/autorouter/ar_matrix.h | 1 - pcbnew/board.cpp | 38 +-- pcbnew/board.h | 8 +- pcbnew/board_connected_item.h | 1 - pcbnew/board_design_settings.cpp | 2 +- ...board_items_to_polygon_shape_transform.cpp | 16 +- pcbnew/collectors.cpp | 6 +- pcbnew/connectivity/connectivity_algo.cpp | 14 +- pcbnew/connectivity/connectivity_data.cpp | 16 +- pcbnew/connectivity/connectivity_data.h | 9 +- pcbnew/connectivity/connectivity_items.cpp | 18 +- pcbnew/connectivity/connectivity_items.h | 8 +- pcbnew/connectivity/from_to_cache.cpp | 1 - pcbnew/cross-probing.cpp | 4 +- pcbnew/dialogs/dialog_board_statistics.cpp | 4 +- pcbnew/dialogs/dialog_board_statistics.h | 2 +- pcbnew/dialogs/dialog_gendrill.cpp | 6 +- pcbnew/dialogs/dialog_global_deletion.cpp | 4 +- .../dialog_global_edit_tracks_and_vias.cpp | 11 +- pcbnew/dialogs/dialog_net_inspector.cpp | 12 +- pcbnew/dialogs/dialog_net_inspector.h | 2 +- pcbnew/dialogs/dialog_swap_layers.cpp | 1 - .../dialogs/dialog_track_via_properties.cpp | 14 +- pcbnew/dialogs/dialog_unused_pad_layers.cpp | 8 +- .../dialogs/panel_pcbnew_color_settings.cpp | 1 - pcbnew/drc/drc_engine.cpp | 6 +- pcbnew/drc/drc_rtree.h | 1 - pcbnew/drc/drc_test_provider.cpp | 4 +- pcbnew/drc/drc_test_provider_annulus.cpp | 10 +- pcbnew/drc/drc_test_provider_connectivity.cpp | 2 +- .../drc_test_provider_copper_clearance.cpp | 12 +- .../drc_test_provider_diff_pair_coupling.cpp | 22 +- pcbnew/drc/drc_test_provider_hole_size.cpp | 14 +- pcbnew/drc/drc_test_provider_hole_to_hole.cpp | 10 +- .../drc/drc_test_provider_matched_length.cpp | 11 +- pcbnew/drc/drc_test_provider_track_width.cpp | 8 +- pcbnew/drc/drc_test_provider_via_diameter.cpp | 6 +- pcbnew/edit.cpp | 1 - pcbnew/edit_track_width.cpp | 8 +- pcbnew/exporters/export_d356.cpp | 4 +- pcbnew/exporters/export_gencad.cpp | 28 +-- pcbnew/exporters/export_hyperlynx.cpp | 16 +- pcbnew/exporters/export_vrml.cpp | 6 +- pcbnew/exporters/exporter_vrml.h | 2 +- .../exporters/gendrill_file_writer_base.cpp | 8 +- pcbnew/exporters/gendrill_gerber_writer.cpp | 4 +- pcbnew/exporters/gerber_jobfile_writer.cpp | 4 +- pcbnew/footprint.cpp | 4 +- pcbnew/kicad_clipboard.cpp | 1 - pcbnew/netinfo_item.cpp | 8 +- pcbnew/netinfo_list.cpp | 4 +- .../netlist_reader/board_netlist_updater.cpp | 4 +- pcbnew/pad.h | 1 - pcbnew/pcb_base_frame.cpp | 2 +- pcbnew/pcb_draw_panel_gal.cpp | 6 +- pcbnew/pcb_edit_frame.cpp | 12 +- pcbnew/pcb_edit_frame.h | 6 +- pcbnew/pcb_expr_evaluator.cpp | 12 +- pcbnew/pcb_item_containers.h | 4 +- pcbnew/pcb_painter.cpp | 34 +-- pcbnew/pcb_painter.h | 14 +- pcbnew/{track.cpp => pcb_track.cpp} | 227 +++++++++--------- pcbnew/{track.h => pcb_track.h} | 40 +-- pcbnew/pcbnew_printout.cpp | 2 +- pcbnew/pcbnew_printout.h | 2 +- pcbnew/plot_board_layers.cpp | 24 +- pcbnew/plot_brditems_plotter.cpp | 6 +- pcbnew/plugins/altium/altium_pcb.cpp | 8 +- .../cadstar/cadstar_pcb_archive_loader.cpp | 71 +++--- .../cadstar/cadstar_pcb_archive_loader.h | 10 +- pcbnew/plugins/eagle/eagle_plugin.cpp | 12 +- pcbnew/plugins/fabmaster/import_fabmaster.cpp | 8 +- pcbnew/plugins/kicad/kicad_plugin.cpp | 20 +- pcbnew/plugins/kicad/kicad_plugin.h | 4 +- pcbnew/plugins/kicad/pcb_parser.cpp | 32 +-- pcbnew/plugins/kicad/pcb_parser.h | 12 +- pcbnew/plugins/legacy/legacy_plugin.cpp | 10 +- pcbnew/plugins/legacy/legacy_plugin.h | 2 - pcbnew/plugins/pcad/pcb_line.cpp | 4 +- pcbnew/plugins/pcad/pcb_pad.cpp | 4 +- .../scripting/pcbnew_action_plugins.cpp | 8 +- pcbnew/python/swig/board_item.i | 30 +-- pcbnew/python/swig/track.i | 6 +- pcbnew/ratsnest/ratsnest.cpp | 3 - pcbnew/router/pns_kicad_iface.cpp | 44 ++-- pcbnew/router/pns_kicad_iface.h | 6 +- pcbnew/router/pns_sizes_settings.h | 2 +- pcbnew/router/pns_via.h | 2 +- pcbnew/router/router_tool.cpp | 10 +- pcbnew/router/router_tool.h | 2 +- pcbnew/specctra_import_export/specctra.cpp | 2 +- pcbnew/specctra_import_export/specctra.h | 10 +- .../specctra_export.cpp | 13 +- .../specctra_import.cpp | 33 +-- pcbnew/tools/board_editor_control.cpp | 12 +- pcbnew/tools/convert_tool.cpp | 12 +- pcbnew/tools/drawing_tool.cpp | 46 ++-- pcbnew/tools/drc_tool.h | 1 - pcbnew/tools/edit_tool.cpp | 58 ++--- pcbnew/tools/global_edit_tool.cpp | 6 +- pcbnew/tools/pcb_control.cpp | 4 +- pcbnew/tools/pcb_grid_helper.cpp | 4 +- pcbnew/tools/pcb_selection.cpp | 1 - pcbnew/tools/pcb_selection_tool.cpp | 34 +-- pcbnew/tracks_cleaner.cpp | 34 +-- pcbnew/tracks_cleaner.h | 6 +- pcbnew/undo_redo.cpp | 4 +- pcbnew/zone_filler.cpp | 12 +- qa/libeval_compiler/libeval_compiler_test.cpp | 6 +- qa/pcbnew/test_libeval_compiler.cpp | 6 +- .../polygon_generator/polygon_generator.cpp | 4 +- 123 files changed, 746 insertions(+), 756 deletions(-) rename pcbnew/{track.cpp => pcb_track.cpp} (77%) rename pcbnew/{track.h => pcb_track.h} (94%) diff --git a/3d-viewer/3d_canvas/board_adapter.h b/3d-viewer/3d_canvas/board_adapter.h index b19e3cf459..d7ce10552b 100644 --- a/3d-viewer/3d_canvas/board_adapter.h +++ b/3d-viewer/3d_canvas/board_adapter.h @@ -37,7 +37,7 @@ #include #include -#include +#include #include #include #include @@ -564,7 +564,8 @@ private: void destroyLayers(); // Helper functions to create the board - void createTrack( const TRACK* aTrack, CONTAINER_2D_BASE* aDstContainer, int aClearanceValue ); + void createTrack( const PCB_TRACK* aTrack, CONTAINER_2D_BASE* aDstContainer, + int aClearanceValue ); void createPadWithClearance( const PAD *aPad, CONTAINER_2D_BASE* aDstContainer, PCB_LAYER_ID aLayer, wxSize aClearanceValue ) const; diff --git a/3d-viewer/3d_canvas/create_3Dgraphic_brd_items.cpp b/3d-viewer/3d_canvas/create_3Dgraphic_brd_items.cpp index 9cfee75a0c..ad6b8884ec 100644 --- a/3d-viewer/3d_canvas/create_3Dgraphic_brd_items.cpp +++ b/3d-viewer/3d_canvas/create_3Dgraphic_brd_items.cpp @@ -226,7 +226,7 @@ void BOARD_ADAPTER::addFootprintShapesWithClearance( const FOOTPRINT* aFootprint } -void BOARD_ADAPTER::createTrack( const TRACK* aTrack, CONTAINER_2D_BASE* aDstContainer, +void BOARD_ADAPTER::createTrack( const PCB_TRACK* aTrack, CONTAINER_2D_BASE* aDstContainer, int aClearanceValue ) { SFVEC2F start3DU( aTrack->GetStart().x * m_biuTo3Dunits, @@ -243,7 +243,7 @@ void BOARD_ADAPTER::createTrack( const TRACK* aTrack, CONTAINER_2D_BASE* aDstCon case PCB_ARC_T: { - const ARC* arc = static_cast( aTrack ); + const PCB_ARC* arc = static_cast( aTrack ); VECTOR2D center( arc->GetCenter() ); double arc_angle = arc->GetAngle(); double radius = arc->GetRadius(); diff --git a/3d-viewer/3d_canvas/create_layer_items.cpp b/3d-viewer/3d_canvas/create_layer_items.cpp index d0daf14ab8..6c64a7748b 100644 --- a/3d-viewer/3d_canvas/create_layer_items.cpp +++ b/3d-viewer/3d_canvas/create_layer_items.cpp @@ -149,22 +149,22 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter ) m_averageHoleDiameter = 0; // Prepare track list, convert in a vector. Calc statistic for the holes - std::vector< const TRACK *> trackList; + std::vector trackList; trackList.clear(); trackList.reserve( m_board->Tracks().size() ); - for( TRACK* track : m_board->Tracks() ) + for( PCB_TRACK* track : m_board->Tracks() ) { if( !Is3dLayerEnabled( track->GetLayer() ) ) // Skip non enabled layers continue; - // Note: a TRACK holds normal segment tracks and - // also vias circles (that have also drill values) + // Note: a PCB_TRACK holds normal segment tracks and also vias circles (that have also + // drill values) trackList.push_back( track ); if( track->Type() == PCB_VIA_T ) { - const VIA *via = static_cast< const VIA*>( track ); + const PCB_VIA *via = static_cast< const PCB_VIA*>( track ); m_viaCount++; m_averageViaHoleDiameter += via->GetDrillValue() * m_biuTo3Dunits; } @@ -235,14 +235,14 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter ) for( unsigned int trackIdx = 0; trackIdx < nTracks; ++trackIdx ) { - const TRACK *track = trackList[trackIdx]; + const PCB_TRACK *track = trackList[trackIdx]; // NOTE: Vias can be on multiple layers if( !track->IsOnLayer( curr_layer_id ) ) continue; // Skip vias annulus when not connected on this layer (if removing is enabled) - const VIA *via = dyn_cast< const VIA*>( track ); + const PCB_VIA *via = dyn_cast< const PCB_VIA*>( track ); if( via && !via->FlashLayer( curr_layer_id ) && IsCopperLayer( curr_layer_id ) ) continue; @@ -260,7 +260,7 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter ) for( unsigned int trackIdx = 0; trackIdx < nTracks; ++trackIdx ) { - const TRACK *track = trackList[trackIdx]; + const PCB_TRACK *track = trackList[trackIdx]; if( !track->IsOnLayer( curr_layer_id ) ) continue; @@ -268,14 +268,14 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter ) // ADD VIAS and THT if( track->Type() == PCB_VIA_T ) { - const VIA* via = static_cast( track ); - const VIATYPE viatype = via->GetViaType(); - const float holediameter = via->GetDrillValue() * BiuTo3dUnits(); + const PCB_VIA* via = static_cast( track ); + const VIATYPE viatype = via->GetViaType(); + const float holediameter = via->GetDrillValue() * BiuTo3dUnits(); // holes and layer copper extend half info cylinder wall to hide transition - const float thickness = GetHolePlatingThickness() * BiuTo3dUnits() / 2.0f; - const float hole_inner_radius = ( holediameter / 2.0f ); - const float ring_radius = via->GetWidth() * BiuTo3dUnits() / 2.0f; + const float thickness = GetHolePlatingThickness() * BiuTo3dUnits() / 2.0f; + const float hole_inner_radius = holediameter / 2.0f; + const float ring_radius = via->GetWidth() * BiuTo3dUnits() / 2.0f; const SFVEC2F via_center( via->GetStart().x * m_biuTo3Dunits, -via->GetStart().y * m_biuTo3Dunits ); @@ -337,7 +337,7 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter ) for( unsigned int trackIdx = 0; trackIdx < nTracks; ++trackIdx ) { - const TRACK *track = trackList[trackIdx]; + const PCB_TRACK *track = trackList[trackIdx]; if( !track->IsOnLayer( curr_layer_id ) ) continue; @@ -345,12 +345,12 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter ) // ADD VIAS and THT if( track->Type() == PCB_VIA_T ) { - const VIA *via = static_cast< const VIA*>( track ); - const VIATYPE viatype = via->GetViaType(); + const PCB_VIA* via = static_cast( track ); + const VIATYPE viatype = via->GetViaType(); if( viatype != VIATYPE::THROUGH ) { - // Add VIA hole contours + // Add PCB_VIA hole contours // Add outer holes of VIAs SHAPE_POLY_SET *layerOuterHolesPoly = nullptr; @@ -430,13 +430,13 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter ) for( unsigned int trackIdx = 0; trackIdx < nTracks; ++trackIdx ) { - const TRACK *track = trackList[trackIdx]; + const PCB_TRACK *track = trackList[trackIdx]; if( !track->IsOnLayer( curr_layer_id ) ) continue; // Skip vias annulus when not connected on this layer (if removing is enabled) - const VIA *via = dyn_cast< const VIA*>( track ); + const PCB_VIA *via = dyn_cast( track ); if( via && !via->FlashLayer( curr_layer_id ) && IsCopperLayer( curr_layer_id ) ) continue; diff --git a/3d-viewer/3d_canvas/eda_3d_canvas.cpp b/3d-viewer/3d_canvas/eda_3d_canvas.cpp index 2bb0b14112..22ce09b69e 100644 --- a/3d-viewer/3d_canvas/eda_3d_canvas.cpp +++ b/3d-viewer/3d_canvas/eda_3d_canvas.cpp @@ -742,7 +742,7 @@ void EDA_3D_CANVAS::OnMouseMove( wxMouseEvent& event ) case PCB_VIA_T: case PCB_ARC_T: { - TRACK* track = dynamic_cast( rollOverItem ); + PCB_TRACK* track = dynamic_cast( rollOverItem ); if( track ) { diff --git a/3d-viewer/3d_rendering/3d_render_raytracing/create_scene.cpp b/3d-viewer/3d_rendering/3d_render_raytracing/create_scene.cpp index f04b958080..92fb0ee9ac 100644 --- a/3d-viewer/3d_rendering/3d_render_raytracing/create_scene.cpp +++ b/3d-viewer/3d_rendering/3d_render_raytracing/create_scene.cpp @@ -1023,7 +1023,7 @@ void RENDER_3D_RAYTRACE::Reload( REPORTER* aStatusReporter, REPORTER* aWarningRe } -void RENDER_3D_RAYTRACE::insertHole( const VIA* aVia ) +void RENDER_3D_RAYTRACE::insertHole( const PCB_VIA* aVia ) { PCB_LAYER_ID top_layer, bottom_layer; int radiusBUI = ( aVia->GetDrillValue() / 2 ); @@ -1254,11 +1254,11 @@ void RENDER_3D_RAYTRACE::addPadsAndVias() // Insert plated vertical holes inside the board // Insert vias holes (vertical cylinders) - for( TRACK* track : m_boardAdapter.GetBoard()->Tracks() ) + for( PCB_TRACK* track : m_boardAdapter.GetBoard()->Tracks() ) { if( track->Type() == PCB_VIA_T ) { - const VIA* via = static_cast( track ); + const PCB_VIA* via = static_cast( track ); insertHole( via ); } } diff --git a/3d-viewer/3d_rendering/3d_render_raytracing/render_3d_raytrace.h b/3d-viewer/3d_rendering/3d_render_raytracing/render_3d_raytrace.h index 189f9c561d..e94c38dfb3 100644 --- a/3d-viewer/3d_rendering/3d_render_raytracing/render_3d_raytrace.h +++ b/3d-viewer/3d_rendering/3d_render_raytracing/render_3d_raytrace.h @@ -114,7 +114,7 @@ private: float aZMax, const MATERIAL* aMaterial, const SFVEC3F& aObjColor ); void addPadsAndVias(); - void insertHole( const VIA* aVia ); + void insertHole( const PCB_VIA* aVia ); void insertHole( const PAD* aPad ); void loadModels( CONTAINER_3D& aDstContainer, bool aSkipMaterialInformation ); void addModels( CONTAINER_3D& aDstContainer, const S3DMODEL* a3DModel, diff --git a/3d-viewer/3d_rendering/legacy/create_scene.cpp b/3d-viewer/3d_rendering/legacy/create_scene.cpp index d5bc6baf65..bd5daa7abe 100644 --- a/3d-viewer/3d_rendering/legacy/create_scene.cpp +++ b/3d-viewer/3d_rendering/legacy/create_scene.cpp @@ -737,11 +737,11 @@ void RENDER_3D_LEGACY::generateViasAndPads() // Insert plated vertical holes inside the board // Insert vias holes (vertical cylinders) - for( const TRACK* track : m_boardAdapter.GetBoard()->Tracks() ) + for( const PCB_TRACK* track : m_boardAdapter.GetBoard()->Tracks() ) { if( track->Type() == PCB_VIA_T ) { - const VIA* via = static_cast( track ); + const PCB_VIA* via = static_cast( track ); const float holediameter = via->GetDrillValue() * m_boardAdapter.BiuTo3dUnits(); const int nrSegments = m_boardAdapter.GetCircleSegmentCount( via->GetDrillValue() ); diff --git a/common/CMakeLists.txt b/common/CMakeLists.txt index 7743b60ac8..3498d28c32 100644 --- a/common/CMakeLists.txt +++ b/common/CMakeLists.txt @@ -529,7 +529,7 @@ set( PCB_COMMON_SRCS ${CMAKE_SOURCE_DIR}/pcbnew/pcb_text.cpp ${CMAKE_SOURCE_DIR}/pcbnew/board_stackup_manager/board_stackup.cpp ${CMAKE_SOURCE_DIR}/pcbnew/fp_text.cpp - ${CMAKE_SOURCE_DIR}/pcbnew/track.cpp + ${CMAKE_SOURCE_DIR}/pcbnew/pcb_track.cpp ${CMAKE_SOURCE_DIR}/pcbnew/zone.cpp ${CMAKE_SOURCE_DIR}/pcbnew/collectors.cpp ${CMAKE_SOURCE_DIR}/pcbnew/connectivity/connectivity_algo.cpp diff --git a/gerbview/export_to_pcbnew.h b/gerbview/export_to_pcbnew.h index 05640e75c1..6008cdf450 100644 --- a/gerbview/export_to_pcbnew.h +++ b/gerbview/export_to_pcbnew.h @@ -138,7 +138,7 @@ private: void export_segarc_copper_item( const GERBER_DRAW_ITEM* aGbrItem, LAYER_NUM aLayer ); /** - * Basic write function to write a a #TRACK item to the board file from a non flashed item. + * Basic write function to write a a #PCB_TRACK to the board file from a non flashed item. */ void writeCopperLineItem( const wxPoint& aStart, const wxPoint& aEnd, int aWidth, LAYER_NUM aLayer ); diff --git a/include/core/typeinfo.h b/include/core/typeinfo.h index b5f2bfee14..110df7464b 100644 --- a/include/core/typeinfo.h +++ b/include/core/typeinfo.h @@ -92,10 +92,10 @@ enum KICAD_T PCB_FP_TEXT_T, ///< class FP_TEXT, text in a footprint PCB_FP_SHAPE_T, ///< class FP_SHAPE, a footprint edge PCB_FP_ZONE_T, ///< class ZONE, managed by a footprint - PCB_TRACE_T, ///< class TRACK, a track segment (segment on a copper layer) - PCB_VIA_T, ///< class VIA, a via (like a track segment on a copper layer) - PCB_ARC_T, ///< class ARC, an arc track segment on a copper layer - PCB_MARKER_T, ///< class MARKER_PCB, a marker used to show something + PCB_TRACE_T, ///< class PCB_TRACK, a track segment (segment on a copper layer) + PCB_VIA_T, ///< class PCB_VIA, a via (like a track segment on a copper layer) + PCB_ARC_T, ///< class PCB_ARC, an arc track segment on a copper layer + PCB_MARKER_T, ///< class PCB_MARKER, a marker used to show something PCB_DIMENSION_T, ///< class PCB_DIMENSION_BASE: abstract dimension meta-type PCB_DIM_ALIGNED_T, ///< class PCB_DIM_ALIGNED, a linear dimension (graphic item) PCB_DIM_LEADER_T, ///< class PCB_DIM_LEADER, a leader dimension (graphic item) diff --git a/include/pcb_base_frame.h b/include/pcb_base_frame.h index 0f8eb1bc61..61a2ac03b3 100644 --- a/include/pcb_base_frame.h +++ b/include/pcb_base_frame.h @@ -51,7 +51,6 @@ class BOARD; class BOARD_CONNECTED_ITEM; class COLOR_SETTINGS; class FOOTPRINT; -class TRACK; class PAD; class EDA_3D_VIEWER; class GENERAL_COLLECTOR; diff --git a/pcbnew/autorouter/ar_autoplacer.cpp b/pcbnew/autorouter/ar_autoplacer.cpp index 0614fd5452..30134a5c0f 100644 --- a/pcbnew/autorouter/ar_autoplacer.cpp +++ b/pcbnew/autorouter/ar_autoplacer.cpp @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include diff --git a/pcbnew/autorouter/ar_matrix.h b/pcbnew/autorouter/ar_matrix.h index 03de540418..7cbd8c16b2 100644 --- a/pcbnew/autorouter/ar_matrix.h +++ b/pcbnew/autorouter/ar_matrix.h @@ -33,7 +33,6 @@ #include class PCB_SHAPE; -class TRACK; class PAD; class FOOTPRINT; diff --git a/pcbnew/board.cpp b/pcbnew/board.cpp index 63f38bc263..ecae28db2d 100644 --- a/pcbnew/board.cpp +++ b/pcbnew/board.cpp @@ -34,7 +34,7 @@ #include #include #include -#include +#include #include #include #include @@ -116,7 +116,7 @@ BOARD::~BOARD() m_footprints.clear(); - for( TRACK* t : m_tracks ) + for( PCB_TRACK* t : m_tracks ) delete t; m_tracks.clear(); @@ -307,7 +307,7 @@ TRACKS BOARD::TracksInNet( int aNetCode ) INSPECTOR_FUNC inspector = [aNetCode, &ret]( EDA_ITEM* item, void* testData ) { - TRACK* t = static_cast( item ); + PCB_TRACK* t = static_cast( item ); if( t->GetNetCode() == aNetCode ) ret.push_back( t ); @@ -315,7 +315,7 @@ TRACKS BOARD::TracksInNet( int aNetCode ) return SEARCH_RESULT::CONTINUE; }; - // visit this BOARD's TRACKs and VIAs with above TRACK INSPECTOR which + // visit this BOARD's PCB_TRACKs and PCB_VIAs with above TRACK INSPECTOR which // appends all in aNetCode to ret. Visit( inspector, nullptr, GENERAL_COLLECTOR::Tracks ); @@ -546,7 +546,7 @@ void BOARD::SetElementVisibility( GAL_LAYER_ID aLayer, bool isEnabled ) // because we have a tool to show/hide ratsnest relative to a pad or a footprint // so the hide/show option is a per item selection - for( TRACK* track : Tracks() ) + for( PCB_TRACK* track : Tracks() ) track->SetLocalRatsnestVisible( isEnabled ); for( FOOTPRINT* footprint : Footprints() ) @@ -644,9 +644,9 @@ void BOARD::Add( BOARD_ITEM* aBoardItem, ADD_MODE aMode ) } if( aMode == ADD_MODE::APPEND || aMode == ADD_MODE::BULK_APPEND ) - m_tracks.push_back( static_cast( aBoardItem ) ); + m_tracks.push_back( static_cast( aBoardItem ) ); else - m_tracks.push_front( static_cast( aBoardItem ) ); + m_tracks.push_front( static_cast( aBoardItem ) ); break; @@ -732,7 +732,7 @@ void BOARD::Remove( BOARD_ITEM* aBoardItem, REMOVE_MODE aRemoveMode ) zone->SetNet( unconnected ); } - for( TRACK* track : m_tracks ) + for( PCB_TRACK* track : m_tracks ) { if( track->GetNet() == item ) track->SetNet( unconnected ); @@ -869,7 +869,7 @@ BOARD_ITEM* BOARD::GetItem( const KIID& aID ) const if( aID == niluuid ) return nullptr; - for( TRACK* track : Tracks() ) + for( PCB_TRACK* track : Tracks() ) { if( track->m_Uuid == aID ) return track; @@ -948,7 +948,7 @@ void BOARD::FillItemMap( std::map& aMap ) // the board itself aMap[ m_Uuid ] = this; - for( TRACK* track : Tracks() ) + for( PCB_TRACK* track : Tracks() ) aMap[ track->m_Uuid ] = track; for( FOOTPRINT* footprint : Footprints() ) @@ -1144,7 +1144,7 @@ EDA_RECT BOARD::ComputeBoundingBox( bool aBoardEdgesOnly ) const if( !aBoardEdgesOnly ) { // Check tracks - for( TRACK* track : m_tracks ) + for( PCB_TRACK* track : m_tracks ) { if( ( track->GetLayerSet() & visible ).any() ) area.Merge( track->GetBoundingBox() ); @@ -1168,7 +1168,7 @@ void BOARD::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector int viasCount = 0; int trackSegmentsCount = 0; - for( TRACK* item : m_tracks ) + for( PCB_TRACK* item : m_tracks ) { if( item->Type() == PCB_VIA_T ) viasCount++; @@ -1288,13 +1288,13 @@ SEARCH_RESULT BOARD::Visit( INSPECTOR inspector, void* testData, const KICAD_T s break; case PCB_VIA_T: - result = IterateForward( m_tracks, inspector, testData, p ); + result = IterateForward( m_tracks, inspector, testData, p ); ++p; break; case PCB_TRACE_T: case PCB_ARC_T: - result = IterateForward( m_tracks, inspector, testData, p ); + result = IterateForward( m_tracks, inspector, testData, p ); ++p; break; @@ -1572,7 +1572,7 @@ PAD* BOARD::GetPad( const wxPoint& aPosition, LSET aLayerSet ) const } -PAD* BOARD::GetPad( const TRACK* aTrace, ENDPOINT_T aEndPoint ) const +PAD* BOARD::GetPad( const PCB_TRACK* aTrace, ENDPOINT_T aEndPoint ) const { const wxPoint& aPosition = aTrace->GetEndPoint( aEndPoint ); @@ -1734,7 +1734,7 @@ void BOARD::PadDelete( PAD* aPad ) } -std::tuple BOARD::GetTrackLength( const TRACK& aTrack ) const +std::tuple BOARD::GetTrackLength( const PCB_TRACK& aTrack ) const { int count = 0; double length = 0.0; @@ -1750,11 +1750,11 @@ std::tuple BOARD::GetTrackLength( const TRACK& aTrack ) con { count++; - if( TRACK* track = dynamic_cast( item ) ) + if( PCB_TRACK* track = dynamic_cast( item ) ) { if( track->Type() == PCB_VIA_T && useHeight ) { - VIA* via = static_cast( track ); + PCB_VIA* via = static_cast( track ); length += stackup.GetLayerDistance( via->TopLayer(), via->BottomLayer() ); continue; } @@ -2018,7 +2018,7 @@ const std::vector BOARD::AllConnectedItems() { std::vector items; - for( TRACK* track : Tracks() ) + for( PCB_TRACK* track : Tracks() ) items.push_back( track ); for( FOOTPRINT* footprint : Footprints() ) diff --git a/pcbnew/board.h b/pcbnew/board.h index ce56aacf91..97edde127f 100644 --- a/pcbnew/board.h +++ b/pcbnew/board.h @@ -47,7 +47,7 @@ class PICKED_ITEMS_LIST; class BOARD; class FOOTPRINT; class ZONE; -class TRACK; +class PCB_TRACK; class PAD; class PCB_GROUP; class PCB_MARKER; @@ -927,11 +927,11 @@ public: /** * Find a pad connected to \a aEndPoint of \a aTrace. * - * @param aTrace A pointer to a TRACK object to hit test against. + * @param aTrace A pointer to a PCB_TRACK object to hit test against. * @param aEndPoint The end point of \a aTrace the hit test against. * @return A pointer to a PAD object if found or NULL if not found. */ - PAD* GetPad( const TRACK* aTrace, ENDPOINT_T aEndPoint ) const; + PAD* GetPad( const PCB_TRACK* aTrace, ENDPOINT_T aEndPoint ) const; /** * Return pad found at \a aPosition on \a aLayerMask using the fast search method. @@ -988,7 +988,7 @@ public: * @param aTrack Starting track (can also be a via) to check against for connection. * @return a tuple containing */ - std::tuple GetTrackLength( const TRACK& aTrack ) const; + std::tuple GetTrackLength( const PCB_TRACK& aTrack ) const; /** * Collect all the TRACKs and VIAs that are members of a net given by aNetCode. diff --git a/pcbnew/board_connected_item.h b/pcbnew/board_connected_item.h index 334d81a11f..8faab2fa65 100644 --- a/pcbnew/board_connected_item.h +++ b/pcbnew/board_connected_item.h @@ -30,7 +30,6 @@ class NETCLASS; class NETINFO_ITEM; -class TRACK; class PAD; /** diff --git a/pcbnew/board_design_settings.cpp b/pcbnew/board_design_settings.cpp index f8b19588db..b8e5c3bd90 100644 --- a/pcbnew/board_design_settings.cpp +++ b/pcbnew/board_design_settings.cpp @@ -22,7 +22,7 @@ */ #include -#include +#include #include #include #include diff --git a/pcbnew/board_items_to_polygon_shape_transform.cpp b/pcbnew/board_items_to_polygon_shape_transform.cpp index 22dff403a1..7af9eb5c20 100644 --- a/pcbnew/board_items_to_polygon_shape_transform.cpp +++ b/pcbnew/board_items_to_polygon_shape_transform.cpp @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include #include @@ -72,7 +72,7 @@ void BOARD::ConvertBrdLayerToPolygonalContours( PCB_LAYER_ID aLayer, SHAPE_POLY_ int maxError = GetDesignSettings().m_MaxError; // convert tracks and vias: - for( const TRACK* track : m_tracks ) + for( const PCB_TRACK* track : m_tracks ) { if( !track->IsOnLayer( aLayer ) ) continue; @@ -538,10 +538,10 @@ void PCB_SHAPE::TransformShapeWithClearanceToPolygon( SHAPE_POLY_SET& aCornerBuf } -void TRACK::TransformShapeWithClearanceToPolygon( SHAPE_POLY_SET& aCornerBuffer, - PCB_LAYER_ID aLayer, int aClearanceValue, - int aError, ERROR_LOC aErrorLoc, - bool ignoreLineWidth ) const +void PCB_TRACK::TransformShapeWithClearanceToPolygon( SHAPE_POLY_SET& aCornerBuffer, + PCB_LAYER_ID aLayer, int aClearanceValue, + int aError, ERROR_LOC aErrorLoc, + bool ignoreLineWidth ) const { wxASSERT_MSG( !ignoreLineWidth, "IgnoreLineWidth has no meaning for tracks." ); @@ -557,8 +557,8 @@ void TRACK::TransformShapeWithClearanceToPolygon( SHAPE_POLY_SET& aCornerBuffer, case PCB_ARC_T: { - const ARC* arc = static_cast( this ); - int width = m_Width + ( 2 * aClearanceValue ); + const PCB_ARC* arc = static_cast( this ); + int width = m_Width + ( 2 * aClearanceValue ); TransformArcToPolygon( aCornerBuffer, arc->GetStart(), arc->GetMid(), arc->GetEnd(), width, aError, aErrorLoc ); diff --git a/pcbnew/collectors.cpp b/pcbnew/collectors.cpp index 68a91a656b..dfd6684e92 100644 --- a/pcbnew/collectors.cpp +++ b/pcbnew/collectors.cpp @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include #include #include @@ -161,7 +161,7 @@ SEARCH_RESULT GENERAL_COLLECTOR::Inspect( EDA_ITEM* testItem, void* testData ) PCB_GROUP* group = nullptr; PAD* pad = nullptr; bool pad_through = false; - VIA* via = nullptr; + PCB_VIA* via = nullptr; PCB_MARKER* marker = nullptr; ZONE* zone = nullptr; PCB_SHAPE* shape = nullptr; @@ -258,7 +258,7 @@ SEARCH_RESULT GENERAL_COLLECTOR::Inspect( EDA_ITEM* testItem, void* testData ) break; case PCB_VIA_T: // vias are on many layers, so layer test is specific - via = static_cast( item ); + via = static_cast( item ); break; case PCB_TRACE_T: diff --git a/pcbnew/connectivity/connectivity_algo.cpp b/pcbnew/connectivity/connectivity_algo.cpp index 3bf15db00e..f0d80e79da 100644 --- a/pcbnew/connectivity/connectivity_algo.cpp +++ b/pcbnew/connectivity/connectivity_algo.cpp @@ -148,21 +148,21 @@ bool CN_CONNECTIVITY_ALGO::Add( BOARD_ITEM* aItem ) if( m_itemMap.find( aItem ) != m_itemMap.end() ) return false; - add( m_itemList, static_cast( aItem ) ); + add( m_itemList, static_cast( aItem ) ); break; case PCB_ARC_T: if( m_itemMap.find( aItem ) != m_itemMap.end() ) return false; - add( m_itemList, static_cast( aItem ) ); + add( m_itemList, static_cast( aItem ) ); break; case PCB_VIA_T: if( m_itemMap.find( aItem ) != m_itemMap.end() ) return false; - add( m_itemList, static_cast( aItem ) ); + add( m_itemList, static_cast( aItem ) ); break; case PCB_ZONE_T: @@ -436,7 +436,7 @@ void CN_CONNECTIVITY_ALGO::Build( BOARD* aBoard, PROGRESS_REPORTER* aReporter ) reportProgress( aReporter, ii++, size, delta ); } - for( TRACK* tv : aBoard->Tracks() ) + for( PCB_TRACK* tv : aBoard->Tracks() ) { Add( tv ); reportProgress( aReporter, ii++, size, delta ); @@ -657,7 +657,7 @@ void CN_VISITOR::checkZoneItemConnection( CN_ZONE_LAYER* aZoneLayer, CN_ITEM* aI || aItem->Parent()->Type() == PCB_TRACE_T || aItem->Parent()->Type() == PCB_ARC_T ) { - accuracy = ( static_cast( aItem->Parent() )->GetWidth() + 1 ) / 2; + accuracy = ( static_cast( aItem->Parent() )->GetWidth() + 1 ) / 2; } for( int i = 0; i < aItem->AnchorCount(); ++i ) @@ -776,12 +776,12 @@ bool CN_VISITOR::operator()( CN_ITEM* aCandidate ) if( parentA->Type() == PCB_VIA_T || parentA->Type() == PCB_TRACE_T || parentA->Type() == PCB_ARC_T) - accuracyA = ( static_cast( parentA )->GetWidth() + 1 ) / 2; + accuracyA = ( static_cast( parentA )->GetWidth() + 1 ) / 2; if( parentB->Type() == PCB_VIA_T || parentB->Type() == PCB_TRACE_T || parentB->Type() == PCB_ARC_T ) - accuracyB = ( static_cast( parentB )->GetWidth() + 1 ) / 2; + accuracyB = ( static_cast( parentB )->GetWidth() + 1 ) / 2; // Items do not necessarily have reciprocity as we only check for anchors // therefore, we check HitTest both directions A->B & B->A diff --git a/pcbnew/connectivity/connectivity_data.cpp b/pcbnew/connectivity/connectivity_data.cpp index 42cc46ca71..8f2dfe690c 100644 --- a/pcbnew/connectivity/connectivity_data.cpp +++ b/pcbnew/connectivity/connectivity_data.cpp @@ -484,23 +484,23 @@ bool CONNECTIVITY_DATA::CheckConnectivity( std::vector& a } -const std::vector CONNECTIVITY_DATA::GetConnectedTracks( const BOARD_CONNECTED_ITEM* aItem ) -const +const std::vector CONNECTIVITY_DATA::GetConnectedTracks( + const BOARD_CONNECTED_ITEM* aItem ) const { auto& entry = m_connAlgo->ItemEntry( aItem ); - std::set tracks; - std::vector rv; + std::set tracks; + std::vector rv; - for( auto citem : entry.GetItems() ) + for( CN_ITEM* citem : entry.GetItems() ) { - for( auto connected : citem->ConnectedItems() ) + for( CN_ITEM* connected : citem->ConnectedItems() ) { if( connected->Valid() && ( connected->Parent()->Type() == PCB_TRACE_T || connected->Parent()->Type() == PCB_VIA_T || connected->Parent()->Type() == PCB_ARC_T ) ) - tracks.insert( static_cast ( connected->Parent() ) ); + tracks.insert( static_cast ( connected->Parent() ) ); } } @@ -586,7 +586,7 @@ void CONNECTIVITY_DATA::GetUnconnectedEdges( std::vector& aEdges) const } -bool CONNECTIVITY_DATA::TestTrackEndpointDangling( TRACK* aTrack, wxPoint* aPos ) +bool CONNECTIVITY_DATA::TestTrackEndpointDangling( PCB_TRACK* aTrack, wxPoint* aPos ) { auto items = GetConnectivityAlgo()->ItemEntry( aTrack ).GetItems(); diff --git a/pcbnew/connectivity/connectivity_data.h b/pcbnew/connectivity/connectivity_data.h index ef1adaa50e..c7bf7ec8b5 100644 --- a/pcbnew/connectivity/connectivity_data.h +++ b/pcbnew/connectivity/connectivity_data.h @@ -50,7 +50,7 @@ class BOARD_ITEM; class ZONE; class RN_DATA; class RN_NET; -class TRACK; +class PCB_TRACK; class PAD; class FOOTPRINT; class PROGRESS_REPORTER; @@ -195,13 +195,14 @@ public: */ unsigned int GetUnconnectedCount() const; - bool IsConnectedOnLayer( const BOARD_CONNECTED_ITEM* aItem, int aLayer, std::vector aTypes = {} ) const; + bool IsConnectedOnLayer( const BOARD_CONNECTED_ITEM* aItem, + int aLayer, std::vector aTypes = {} ) const; unsigned int GetNodeCount( int aNet = -1 ) const; unsigned int GetPadCount( int aNet = -1 ) const; - const std::vector GetConnectedTracks( const BOARD_CONNECTED_ITEM* aItem ) const; + const std::vector GetConnectedTracks( const BOARD_CONNECTED_ITEM* aItem ) const; const std::vector GetConnectedPads( const BOARD_CONNECTED_ITEM* aItem ) const; @@ -225,7 +226,7 @@ public: void GetUnconnectedEdges( std::vector& aEdges ) const; - bool TestTrackEndpointDangling( TRACK* aTrack, wxPoint* aPos = nullptr ); + bool TestTrackEndpointDangling( PCB_TRACK* aTrack, wxPoint* aPos = nullptr ); /** * Function ClearDynamicRatsnest() diff --git a/pcbnew/connectivity/connectivity_items.cpp b/pcbnew/connectivity/connectivity_items.cpp index ebef6848e0..1ab4a2c218 100644 --- a/pcbnew/connectivity/connectivity_items.cpp +++ b/pcbnew/connectivity/connectivity_items.cpp @@ -138,12 +138,12 @@ const VECTOR2I CN_ITEM::GetAnchor( int n ) const case PCB_TRACE_T: case PCB_ARC_T: if( n == 0 ) - return static_cast( m_parent )->GetStart(); + return static_cast( m_parent )->GetStart(); else - return static_cast( m_parent )->GetEnd(); + return static_cast( m_parent )->GetEnd(); case PCB_VIA_T: - return static_cast( m_parent )->GetStart(); + return static_cast( m_parent )->GetStart(); default: assert( false ); @@ -158,9 +158,9 @@ void CN_ITEM::Dump() { wxLogDebug(" valid: %d, connected: \n", !!Valid()); - for( auto i : m_connected ) + for( CN_ITEM* i : m_connected ) { - TRACK* t = static_cast( i->Parent() ); + PCB_TRACK* t = static_cast( i->Parent() ); wxLogDebug( " - %p %d\n", t, t->Type() ); } } @@ -239,7 +239,7 @@ CN_ITEM* CN_LIST::Add( PAD* pad ) return item; } -CN_ITEM* CN_LIST::Add( TRACK* track ) +CN_ITEM* CN_LIST::Add( PCB_TRACK* track ) { auto item = new CN_ITEM( track, true ); m_items.push_back( item ); @@ -251,7 +251,7 @@ CN_ITEM* CN_LIST::Add( TRACK* track ) return item; } -CN_ITEM* CN_LIST::Add( ARC* aArc ) +CN_ITEM* CN_LIST::Add( PCB_ARC* aArc ) { auto item = new CN_ITEM( aArc, true ); m_items.push_back( item ); @@ -263,7 +263,7 @@ CN_ITEM* CN_LIST::Add( ARC* aArc ) return item; } - CN_ITEM* CN_LIST::Add( VIA* via ) + CN_ITEM* CN_LIST::Add( PCB_VIA* via ) { auto item = new CN_ITEM( via, !via->GetIsFree(), 1 ); @@ -365,7 +365,7 @@ bool CN_ANCHOR::IsDangling() const return connected_count < minimal_count; if( Parent()->Type() == PCB_TRACE_T || Parent()->Type() == PCB_ARC_T ) - accuracy = ( static_cast( Parent() )->GetWidth() + 1 )/ 2; + accuracy = ( static_cast( Parent() )->GetWidth() + 1 ) / 2; // Items with multiple anchors have usually items connected to each anchor. // We want only the item count of this anchor point diff --git a/pcbnew/connectivity/connectivity_items.h b/pcbnew/connectivity/connectivity_items.h index 67551cb460..c242038eaa 100644 --- a/pcbnew/connectivity/connectivity_items.h +++ b/pcbnew/connectivity/connectivity_items.h @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include #include @@ -432,11 +432,11 @@ public: CN_ITEM* Add( PAD* pad ); - CN_ITEM* Add( TRACK* track ); + CN_ITEM* Add( PCB_TRACK* track ); - CN_ITEM* Add( ARC* track ); + CN_ITEM* Add( PCB_ARC* track ); - CN_ITEM* Add( VIA* via ); + CN_ITEM* Add( PCB_VIA* via ); const std::vector Add( ZONE* zone, PCB_LAYER_ID aLayer ); diff --git a/pcbnew/connectivity/from_to_cache.cpp b/pcbnew/connectivity/from_to_cache.cpp index c84884ac9a..62fb7e830b 100644 --- a/pcbnew/connectivity/from_to_cache.cpp +++ b/pcbnew/connectivity/from_to_cache.cpp @@ -21,7 +21,6 @@ #include #include #include -#include #include #include diff --git a/pcbnew/cross-probing.cpp b/pcbnew/cross-probing.cpp index 477ecfda89..450a8cff82 100644 --- a/pcbnew/cross-probing.cpp +++ b/pcbnew/cross-probing.cpp @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include #include #include @@ -257,7 +257,7 @@ void PCB_EDIT_FRAME::ExecuteRemoteCommand( const char* cmdline ) for( ZONE* zone : pcb->Zones() ) merge_area( zone ); - for( TRACK* track : pcb->Tracks() ) + for( PCB_TRACK* track : pcb->Tracks() ) merge_area( track ); for( FOOTPRINT* fp : pcb->Footprints() ) diff --git a/pcbnew/dialogs/dialog_board_statistics.cpp b/pcbnew/dialogs/dialog_board_statistics.cpp index 9dca8cedb2..883e9faa50 100644 --- a/pcbnew/dialogs/dialog_board_statistics.cpp +++ b/pcbnew/dialogs/dialog_board_statistics.cpp @@ -257,9 +257,9 @@ void DIALOG_BOARD_STATISTICS::getDataFromPCB() } // Get via counts - for( TRACK* track : board->Tracks() ) + for( PCB_TRACK* track : board->Tracks() ) { - if( VIA* via = dyn_cast( track ) ) + if( PCB_VIA* via = dyn_cast( track ) ) { for( auto& type : m_viasTypes ) { diff --git a/pcbnew/dialogs/dialog_board_statistics.h b/pcbnew/dialogs/dialog_board_statistics.h index 363ee12011..ef076bdd5d 100644 --- a/pcbnew/dialogs/dialog_board_statistics.h +++ b/pcbnew/dialogs/dialog_board_statistics.h @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/pcbnew/dialogs/dialog_gendrill.cpp b/pcbnew/dialogs/dialog_gendrill.cpp index 5070c8d953..9977daee82 100644 --- a/pcbnew/dialogs/dialog_gendrill.cpp +++ b/pcbnew/dialogs/dialog_gendrill.cpp @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include #include #include @@ -172,9 +172,9 @@ void DIALOG_GENDRILL::InitDisplayParams() } } - for( TRACK* track : m_board->Tracks() ) + for( PCB_TRACK* track : m_board->Tracks() ) { - const VIA *via = dynamic_cast( track ); + const PCB_VIA *via = dynamic_cast( track ); if( via ) { diff --git a/pcbnew/dialogs/dialog_global_deletion.cpp b/pcbnew/dialogs/dialog_global_deletion.cpp index 23db067db0..b1fb79d70f 100644 --- a/pcbnew/dialogs/dialog_global_deletion.cpp +++ b/pcbnew/dialogs/dialog_global_deletion.cpp @@ -30,7 +30,7 @@ using namespace std::placeholders; #include #include #include -#include +#include #include #include #include @@ -213,7 +213,7 @@ void DIALOG_GLOBAL_DELETION::doGlobalDeletions() if( delete_all || m_delTracks->GetValue() ) { - for( TRACK* track : board->Tracks() ) + for( PCB_TRACK* track : board->Tracks() ) { if( !delete_all ) { diff --git a/pcbnew/dialogs/dialog_global_edit_tracks_and_vias.cpp b/pcbnew/dialogs/dialog_global_edit_tracks_and_vias.cpp index 9d184cd718..6a02f8ae2d 100644 --- a/pcbnew/dialogs/dialog_global_edit_tracks_and_vias.cpp +++ b/pcbnew/dialogs/dialog_global_edit_tracks_and_vias.cpp @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include @@ -85,8 +85,8 @@ protected: } private: - void visitItem( PICKED_ITEMS_LIST* aUndoList, TRACK* aItem ); - void processItem( PICKED_ITEMS_LIST* aUndoList, TRACK* aItem ); + void visitItem( PICKED_ITEMS_LIST* aUndoList, PCB_TRACK* aItem ); + void processItem( PICKED_ITEMS_LIST* aUndoList, PCB_TRACK* aItem ); bool TransferDataToWindow() override; bool TransferDataFromWindow() override; @@ -271,7 +271,8 @@ void DIALOG_GLOBAL_EDIT_TRACKS_AND_VIAS::onSpecifiedValuesUpdateUi( wxUpdateUIEv } -void DIALOG_GLOBAL_EDIT_TRACKS_AND_VIAS::processItem( PICKED_ITEMS_LIST* aUndoList, TRACK* aItem ) +void DIALOG_GLOBAL_EDIT_TRACKS_AND_VIAS::processItem( PICKED_ITEMS_LIST* aUndoList, + PCB_TRACK* aItem ) { BOARD_DESIGN_SETTINGS& brdSettings = m_brd->GetDesignSettings(); bool isTrack = aItem->Type() == PCB_TRACE_T; @@ -320,7 +321,7 @@ void DIALOG_GLOBAL_EDIT_TRACKS_AND_VIAS::processItem( PICKED_ITEMS_LIST* aUndoLi } -void DIALOG_GLOBAL_EDIT_TRACKS_AND_VIAS::visitItem( PICKED_ITEMS_LIST* aUndoList, TRACK* aItem ) +void DIALOG_GLOBAL_EDIT_TRACKS_AND_VIAS::visitItem( PICKED_ITEMS_LIST* aUndoList, PCB_TRACK* aItem ) { if( m_selectedItemsFilter->GetValue() && !m_selection.Contains( aItem ) ) return; diff --git a/pcbnew/dialogs/dialog_net_inspector.cpp b/pcbnew/dialogs/dialog_net_inspector.cpp index 50a46e7c2c..1e354308c4 100644 --- a/pcbnew/dialogs/dialog_net_inspector.cpp +++ b/pcbnew/dialogs/dialog_net_inspector.cpp @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include #include #include @@ -1129,7 +1129,7 @@ void DIALOG_NET_INSPECTOR::OnBoardItemAdded( BOARD& aBoard, BOARD_ITEM* aBoardIt if( r ) { // try to handle frequent operations quickly. - if( TRACK* track = dynamic_cast( i ) ) + if( PCB_TRACK* track = dynamic_cast( i ) ) { const std::unique_ptr& list_item = *r.get(); int len = track->GetLength(); @@ -1228,7 +1228,7 @@ void DIALOG_NET_INSPECTOR::OnBoardItemRemoved( BOARD& aBoard, BOARD_ITEM* aBoard if( r ) { // try to handle frequent operations quickly. - if( TRACK* track = dynamic_cast( i ) ) + if( PCB_TRACK* track = dynamic_cast( i ) ) { const std::unique_ptr& list_item = *r.get(); int len = track->GetLength(); @@ -1370,9 +1370,9 @@ void DIALOG_NET_INSPECTOR::updateNet( NETINFO_ITEM* aNet ) } -unsigned int DIALOG_NET_INSPECTOR::calculateViaLength( const TRACK* aTrack ) const +unsigned int DIALOG_NET_INSPECTOR::calculateViaLength( const PCB_TRACK* aTrack ) const { - const VIA& via = dynamic_cast( *aTrack ); + const PCB_VIA& via = dynamic_cast( *aTrack ); BOARD_DESIGN_SETTINGS& bds = m_brd->GetDesignSettings(); // calculate the via length individually from the board stackup and via's start and end layer. @@ -1417,7 +1417,7 @@ DIALOG_NET_INSPECTOR::buildNewItem( NETINFO_ITEM* aNet, unsigned int aPadCount, if( item->Type() == PCB_PAD_T ) new_item->AddChipWireLength( static_cast( item )->GetPadToDieLength() ); - else if( TRACK* track = dynamic_cast( item ) ) + else if( PCB_TRACK* track = dynamic_cast( item ) ) { new_item->AddBoardWireLength( track->GetLength() ); diff --git a/pcbnew/dialogs/dialog_net_inspector.h b/pcbnew/dialogs/dialog_net_inspector.h index 39a3666c15..00613ffa5f 100644 --- a/pcbnew/dialogs/dialog_net_inspector.h +++ b/pcbnew/dialogs/dialog_net_inspector.h @@ -89,7 +89,7 @@ private: std::vector relevantConnectivityItems() const; bool netFilterMatches( NETINFO_ITEM* aNet ) const; void updateNet( NETINFO_ITEM* aNet ); - unsigned int calculateViaLength( const TRACK* ) const; + unsigned int calculateViaLength( const PCB_TRACK* ) const; void onSelChanged( wxDataViewEvent& event ) override; void onSelChanged(); diff --git a/pcbnew/dialogs/dialog_swap_layers.cpp b/pcbnew/dialogs/dialog_swap_layers.cpp index 3166bd86b8..4f62bb852d 100644 --- a/pcbnew/dialogs/dialog_swap_layers.cpp +++ b/pcbnew/dialogs/dialog_swap_layers.cpp @@ -23,7 +23,6 @@ #include #include -#include #include #include #include diff --git a/pcbnew/dialogs/dialog_track_via_properties.cpp b/pcbnew/dialogs/dialog_track_via_properties.cpp index 682b433be9..3e9773c068 100644 --- a/pcbnew/dialogs/dialog_track_via_properties.cpp +++ b/pcbnew/dialogs/dialog_track_via_properties.cpp @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include #include @@ -108,7 +108,7 @@ DIALOG_TRACK_VIA_PROPERTIES::DIALOG_TRACK_VIA_PROPERTIES( PCB_BASE_FRAME* aParen case PCB_TRACE_T: case PCB_ARC_T: { - const TRACK* t = static_cast( item ); + const PCB_TRACK* t = static_cast( item ); if( !m_tracks ) // first track in the list { @@ -155,7 +155,7 @@ DIALOG_TRACK_VIA_PROPERTIES::DIALOG_TRACK_VIA_PROPERTIES( PCB_BASE_FRAME* aParen case PCB_VIA_T: { - const VIA* v = static_cast( item ); + const PCB_VIA* v = static_cast( item ); if( !m_vias ) // first via in the list { @@ -426,7 +426,7 @@ bool DIALOG_TRACK_VIA_PROPERTIES::TransferDataFromWindow() case PCB_ARC_T: { wxASSERT( m_tracks ); - TRACK* t = static_cast( item ); + PCB_TRACK* t = static_cast( item ); if( !m_trackStartX.IsIndeterminate() ) t->SetStart( wxPoint( m_trackStartX.GetValue(), t->GetStart().y ) ); @@ -459,7 +459,7 @@ bool DIALOG_TRACK_VIA_PROPERTIES::TransferDataFromWindow() case PCB_VIA_T: { wxASSERT( m_vias ); - VIA* v = static_cast( item ); + PCB_VIA* v = static_cast( item ); if( !m_viaX.IsIndeterminate() ) v->SetPosition( wxPoint( m_viaX.GetValue(), v->GetPosition().y ) ); @@ -584,11 +584,11 @@ bool DIALOG_TRACK_VIA_PROPERTIES::TransferDataFromWindow() { case PCB_TRACE_T: case PCB_ARC_T: - static_cast( item )->SetNetCode( newNetCode ); + static_cast( item )->SetNetCode( newNetCode ); break; case PCB_VIA_T: - static_cast( item )->SetNetCode( newNetCode ); + static_cast( item )->SetNetCode( newNetCode ); break; default: diff --git a/pcbnew/dialogs/dialog_unused_pad_layers.cpp b/pcbnew/dialogs/dialog_unused_pad_layers.cpp index 616b3d4de4..9824b24151 100644 --- a/pcbnew/dialogs/dialog_unused_pad_layers.cpp +++ b/pcbnew/dialogs/dialog_unused_pad_layers.cpp @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include #include @@ -88,7 +88,7 @@ bool DIALOG_UNUSED_PAD_LAYERS::TransferDataFromWindow() if( item->Type() == PCB_VIA_T && m_rbScope->GetSelection() == SCOPE_VIAS ) { - VIA* via = static_cast( item ); + PCB_VIA* via = static_cast( item ); via->SetRemoveUnconnected( m_rbAction->GetSelection() == PAD_ACTION_REMOVE ); via->SetKeepTopBottom( m_cbPreservePads->IsChecked() ); } @@ -130,13 +130,13 @@ bool DIALOG_UNUSED_PAD_LAYERS::TransferDataFromWindow() } else { - for( TRACK* item : m_frame->GetBoard()->Tracks() ) + for( PCB_TRACK* item : m_frame->GetBoard()->Tracks() ) { if( item->Type() != PCB_VIA_T ) continue; m_commit.Modify( item ); - VIA* via = static_cast( item ); + PCB_VIA* via = static_cast( item ); via->SetRemoveUnconnected( m_rbAction->GetSelection() == PAD_ACTION_REMOVE ); via->SetKeepTopBottom( m_cbPreservePads->IsChecked() ); } diff --git a/pcbnew/dialogs/panel_pcbnew_color_settings.cpp b/pcbnew/dialogs/panel_pcbnew_color_settings.cpp index 57a2f3bd72..b297d8a254 100644 --- a/pcbnew/dialogs/panel_pcbnew_color_settings.cpp +++ b/pcbnew/dialogs/panel_pcbnew_color_settings.cpp @@ -31,7 +31,6 @@ #include #include #include -#include #include #include diff --git a/pcbnew/drc/drc_engine.cpp b/pcbnew/drc/drc_engine.cpp index 4320985b06..c44c1c643d 100644 --- a/pcbnew/drc/drc_engine.cpp +++ b/pcbnew/drc/drc_engine.cpp @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include #include #include @@ -895,9 +895,9 @@ DRC_CONSTRAINT DRC_ENGINE::EvalRules( DRC_CONSTRAINT_T aConstraintId, const BOAR } else if( a->Type() == PCB_VIA_T ) { - if( static_cast( a )->GetViaType() == VIATYPE::BLIND_BURIED ) + if( static_cast( a )->GetViaType() == VIATYPE::BLIND_BURIED ) mask = DRC_DISALLOW_VIAS | DRC_DISALLOW_BB_VIAS; - else if( static_cast( a )->GetViaType() == VIATYPE::MICROVIA ) + else if( static_cast( a )->GetViaType() == VIATYPE::MICROVIA ) mask = DRC_DISALLOW_VIAS | DRC_DISALLOW_MICRO_VIAS; else mask = DRC_DISALLOW_VIAS; diff --git a/pcbnew/drc/drc_rtree.h b/pcbnew/drc/drc_rtree.h index 87114548ac..2fa9306103 100644 --- a/pcbnew/drc/drc_rtree.h +++ b/pcbnew/drc/drc_rtree.h @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include diff --git a/pcbnew/drc/drc_test_provider.cpp b/pcbnew/drc/drc_test_provider.cpp index 634985f2bf..9d5fcc1728 100644 --- a/pcbnew/drc/drc_test_provider.cpp +++ b/pcbnew/drc/drc_test_provider.cpp @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include #include @@ -167,7 +167,7 @@ int DRC_TEST_PROVIDER::forEachGeometryItem( const std::vector& aTypes, typeMask[ aType ] = true; } - for( TRACK* item : brd->Tracks() ) + for( PCB_TRACK* item : brd->Tracks() ) { if( (item->GetLayerSet() & aLayers).any() ) { diff --git a/pcbnew/drc/drc_test_provider_annulus.cpp b/pcbnew/drc/drc_test_provider_annulus.cpp index e58ae4835d..4095f7f8d0 100644 --- a/pcbnew/drc/drc_test_provider_annulus.cpp +++ b/pcbnew/drc/drc_test_provider_annulus.cpp @@ -22,7 +22,7 @@ */ #include -#include +#include #include #include #include @@ -93,9 +93,9 @@ bool DRC_TEST_PROVIDER_ANNULUS::Run() if( m_drcEngine->IsErrorLimitExceeded( DRCE_ANNULAR_WIDTH ) ) return false; - int v_min = 0; - int v_max = 0; - VIA* via = dyn_cast( item ); + int v_min = 0; + int v_max = 0; + PCB_VIA* via = dyn_cast( item ); // fixme: check minimum IAR/OAR ring for THT pads too if( !via ) @@ -149,7 +149,7 @@ bool DRC_TEST_PROVIDER_ANNULUS::Run() BOARD* board = m_drcEngine->GetBoard(); int ii = 0; - for( TRACK* item : board->Tracks() ) + for( PCB_TRACK* item : board->Tracks() ) { if( !reportProgress( ii++, board->Tracks().size(), delta ) ) break; diff --git a/pcbnew/drc/drc_test_provider_connectivity.cpp b/pcbnew/drc/drc_test_provider_connectivity.cpp index 62b51a63d9..329d162716 100644 --- a/pcbnew/drc/drc_test_provider_connectivity.cpp +++ b/pcbnew/drc/drc_test_provider_connectivity.cpp @@ -90,7 +90,7 @@ bool DRC_TEST_PROVIDER_CONNECTIVITY::Run() ii += count; // We gave half of this phase to CONNECTIVITY_DATA::Build() count += count; - for( TRACK* track : board->Tracks() ) + for( PCB_TRACK* track : board->Tracks() ) { bool exceedT = m_drcEngine->IsErrorLimitExceeded( DRCE_DANGLING_TRACK ); bool exceedV = m_drcEngine->IsErrorLimitExceeded( DRCE_DANGLING_VIA ); diff --git a/pcbnew/drc/drc_test_provider_copper_clearance.cpp b/pcbnew/drc/drc_test_provider_copper_clearance.cpp index b4c2650fbc..7678f34888 100644 --- a/pcbnew/drc/drc_test_provider_copper_clearance.cpp +++ b/pcbnew/drc/drc_test_provider_copper_clearance.cpp @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include @@ -81,7 +81,7 @@ public: int GetNumPhases() const override; private: - bool testTrackAgainstItem( TRACK* track, SHAPE* trackShape, PCB_LAYER_ID layer, + bool testTrackAgainstItem( PCB_TRACK* track, SHAPE* trackShape, PCB_LAYER_ID layer, BOARD_ITEM* other ); void testTrackClearances(); @@ -255,7 +255,7 @@ bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::Run() } -bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackAgainstItem( TRACK* track, SHAPE* trackShape, +bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackAgainstItem( PCB_TRACK* track, SHAPE* trackShape, PCB_LAYER_ID layer, BOARD_ITEM* other ) { @@ -328,7 +328,7 @@ bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackAgainstItem( TRACK* track, SHA if( other->Type() == PCB_VIA_T ) { - VIA* via = static_cast( other ); + PCB_VIA* via = static_cast( other ); pos = via->GetPosition(); if( via->GetLayerSet().Contains( layer ) ) @@ -458,7 +458,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackClearances() std::map< std::pair, int> checkedPairs; - for( TRACK* track : m_board->Tracks() ) + for( PCB_TRACK* track : m_board->Tracks() ) { if( !reportProgress( ii++, m_board->Tracks().size(), delta ) ) break; @@ -541,7 +541,7 @@ bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadAgainstItem( PAD* pad, SHAPE* pa testClearance = false; // Track clearances are tested in testTrackClearances() - if( dynamic_cast( other) ) + if( dynamic_cast( other) ) testClearance = false; if( !testClearance && !testShorting && !testHoles ) diff --git a/pcbnew/drc/drc_test_provider_diff_pair_coupling.cpp b/pcbnew/drc/drc_test_provider_diff_pair_coupling.cpp index 88d0763eb7..634cf7cafa 100644 --- a/pcbnew/drc/drc_test_provider_diff_pair_coupling.cpp +++ b/pcbnew/drc/drc_test_provider_diff_pair_coupling.cpp @@ -20,7 +20,7 @@ #include #include -#include +#include #include #include @@ -162,8 +162,8 @@ struct DIFF_PAIR_COUPLED_SEGMENTS { SEG coupledN; SEG coupledP; - TRACK* parentN; - TRACK* parentP; + PCB_TRACK* parentN; + PCB_TRACK* parentP; int computedGap; PCB_LAYER_ID layer; bool couplingOK; @@ -190,18 +190,18 @@ static void extractDiffPairCoupledItems( DIFF_PAIR_ITEMS& aDp, DRC_RTREE& aTree { for( BOARD_CONNECTED_ITEM* itemP : aDp.itemsP ) { - TRACK* sp = dyn_cast( itemP ); + PCB_TRACK* sp = dyn_cast( itemP ); OPT bestCoupled; int bestGap = std::numeric_limits::max(); - if(!sp) + if( !sp ) continue; for ( BOARD_CONNECTED_ITEM* itemN : aDp.itemsN ) { - auto sn = dyn_cast ( itemN ); + PCB_TRACK* sn = dyn_cast ( itemN ); - if(!sn) + if( !sn ) continue; if( ( sn->GetLayerSet() & sp->GetLayerSet() ).none() ) @@ -374,17 +374,17 @@ bool test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run() OPT maxUncoupledConstraint = it.first.parentRule->FindConstraint( DIFF_PAIR_MAX_UNCOUPLED_CONSTRAINT ); - for( auto& item : it.second.itemsN ) + for( BOARD_CONNECTED_ITEM* item : it.second.itemsN ) { // fixme: include vias - if( auto track = dyn_cast( item ) ) + if( PCB_TRACK* track = dyn_cast( item ) ) it.second.totalLengthN += track->GetLength(); } - for( auto& item : it.second.itemsP ) + for( BOARD_CONNECTED_ITEM* item : it.second.itemsP ) { // fixme: include vias - if( auto track = dyn_cast( item ) ) + if( PCB_TRACK* track = dyn_cast( item ) ) it.second.totalLengthP += track->GetLength(); } diff --git a/pcbnew/drc/drc_test_provider_hole_size.cpp b/pcbnew/drc/drc_test_provider_hole_size.cpp index 8e5ee5566c..d63a973665 100644 --- a/pcbnew/drc/drc_test_provider_hole_size.cpp +++ b/pcbnew/drc/drc_test_provider_hole_size.cpp @@ -23,7 +23,7 @@ #include #include -#include +#include #include #include #include @@ -66,7 +66,7 @@ public: int GetNumPhases() const override; private: - void checkVia( VIA* via, bool aExceedMicro, bool aExceedStd ); + void checkVia( PCB_VIA* via, bool aExceedMicro, bool aExceedStd ); void checkPad( PAD* aPad ); BOARD* m_board; @@ -111,15 +111,15 @@ bool DRC_TEST_PROVIDER_HOLE_SIZE::Run() return false; // DRC cancelled } - std::vector vias; + std::vector vias; - for( TRACK* track : m_board->Tracks() ) + for( PCB_TRACK* track : m_board->Tracks() ) { if( track->Type() == PCB_VIA_T ) - vias.push_back( static_cast( track ) ); + vias.push_back( static_cast( track ) ); } - for( VIA* via : vias ) + for( PCB_VIA* via : vias ) { bool exceedMicro = m_drcEngine->IsErrorLimitExceeded( DRCE_MICROVIA_DRILL_OUT_OF_RANGE ); bool exceedStd = m_drcEngine->IsErrorLimitExceeded( DRCE_DRILL_OUT_OF_RANGE ); @@ -191,7 +191,7 @@ void DRC_TEST_PROVIDER_HOLE_SIZE::checkPad( PAD* aPad ) } -void DRC_TEST_PROVIDER_HOLE_SIZE::checkVia( VIA* via, bool aExceedMicro, bool aExceedStd ) +void DRC_TEST_PROVIDER_HOLE_SIZE::checkVia( PCB_VIA* via, bool aExceedMicro, bool aExceedStd ) { int errorCode; diff --git a/pcbnew/drc/drc_test_provider_hole_to_hole.cpp b/pcbnew/drc/drc_test_provider_hole_to_hole.cpp index 4abecc0bc7..fa9800369b 100644 --- a/pcbnew/drc/drc_test_provider_hole_to_hole.cpp +++ b/pcbnew/drc/drc_test_provider_hole_to_hole.cpp @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include @@ -84,7 +84,7 @@ static std::shared_ptr getDrilledHoleShape( BOARD_ITEM* aItem ) { if( aItem->Type() == PCB_VIA_T ) { - VIA* via = static_cast( aItem ); + PCB_VIA* via = static_cast( aItem ); return std::make_shared( via->GetCenter(), via->GetDrillValue() / 2 ); } else if( aItem->Type() == PCB_PAD_T ) @@ -158,7 +158,7 @@ bool DRC_TEST_PROVIDER_HOLE_TO_HOLE::Run() } else if( item->Type() == PCB_VIA_T ) { - VIA* via = static_cast( item ); + PCB_VIA* via = static_cast( item ); // We only care about mechanically drilled (ie: non-laser) holes if( via->GetViaType() == VIATYPE::THROUGH ) @@ -176,12 +176,12 @@ bool DRC_TEST_PROVIDER_HOLE_TO_HOLE::Run() std::map< std::pair, int> checkedPairs; - for( TRACK* track : m_board->Tracks() ) + for( PCB_TRACK* track : m_board->Tracks() ) { if( track->Type() != PCB_VIA_T ) continue; - VIA* via = static_cast( track ); + PCB_VIA* via = static_cast( track ); if( !reportProgress( ii++, count, delta ) ) return false; // DRC cancelled diff --git a/pcbnew/drc/drc_test_provider_matched_length.cpp b/pcbnew/drc/drc_test_provider_matched_length.cpp index f5ae0df588..cd325f74fd 100644 --- a/pcbnew/drc/drc_test_provider_matched_length.cpp +++ b/pcbnew/drc/drc_test_provider_matched_length.cpp @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include @@ -92,7 +92,7 @@ private: }; -static int computeViaThruLength( VIA *aVia, const std::set &conns ) +static int computeViaThruLength( PCB_VIA *aVia, const std::set &conns ) { return 0; // fixme: not yet there... } @@ -294,15 +294,16 @@ bool DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal( bool aDelayReportMode ) if( citem->Type() == PCB_VIA_T ) { ent.viaCount++; - ent.totalVia += computeViaThruLength( static_cast( citem ), nitem.second ); + ent.totalVia += computeViaThruLength( static_cast( citem ), + nitem.second ); } else if( citem->Type() == PCB_TRACE_T ) { - ent.totalRoute += static_cast( citem )->GetLength(); + ent.totalRoute += static_cast( citem )->GetLength(); } else if ( citem->Type() == PCB_ARC_T ) { - ent.totalRoute += static_cast( citem )->GetLength(); + ent.totalRoute += static_cast( citem )->GetLength(); } else if( citem->Type() == PCB_PAD_T ) { diff --git a/pcbnew/drc/drc_test_provider_track_width.cpp b/pcbnew/drc/drc_test_provider_track_width.cpp index 2df7ed0c28..19c1be6c0c 100644 --- a/pcbnew/drc/drc_test_provider_track_width.cpp +++ b/pcbnew/drc/drc_test_provider_track_width.cpp @@ -22,7 +22,7 @@ */ //#include -#include +#include #include #include #include @@ -92,12 +92,12 @@ bool DRC_TEST_PROVIDER_TRACK_WIDTH::Run() int actual; wxPoint p0; - if( ARC* arc = dyn_cast( item ) ) + if( PCB_ARC* arc = dyn_cast( item ) ) { actual = arc->GetWidth(); p0 = arc->GetStart(); } - else if( TRACK* trk = dyn_cast( item ) ) + else if( PCB_TRACK* trk = dyn_cast( item ) ) { actual = trk->GetWidth(); p0 = ( trk->GetStart() + trk->GetEnd() ) / 2; @@ -156,7 +156,7 @@ bool DRC_TEST_PROVIDER_TRACK_WIDTH::Run() int ii = 0; - for( TRACK* item : m_drcEngine->GetBoard()->Tracks() ) + for( PCB_TRACK* item : m_drcEngine->GetBoard()->Tracks() ) { if( !reportProgress( ii++, m_drcEngine->GetBoard()->Tracks().size(), delta ) ) break; diff --git a/pcbnew/drc/drc_test_provider_via_diameter.cpp b/pcbnew/drc/drc_test_provider_via_diameter.cpp index 9c7f002654..c4a884894b 100644 --- a/pcbnew/drc/drc_test_provider_via_diameter.cpp +++ b/pcbnew/drc/drc_test_provider_via_diameter.cpp @@ -21,7 +21,7 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA */ -#include +#include #include #include #include @@ -88,7 +88,7 @@ bool DRC_TEST_PROVIDER_VIA_DIAMETER::Run() if( m_drcEngine->IsErrorLimitExceeded( DRCE_VIA_DIAMETER ) ) return false; - VIA* via = dyn_cast( item ); + PCB_VIA* via = dyn_cast( item ); // fixme: move to pad stack check? if( !via ) @@ -145,7 +145,7 @@ bool DRC_TEST_PROVIDER_VIA_DIAMETER::Run() int ii = 0; - for( TRACK* item : m_drcEngine->GetBoard()->Tracks() ) + for( PCB_TRACK* item : m_drcEngine->GetBoard()->Tracks() ) { if( !reportProgress( ii++, m_drcEngine->GetBoard()->Tracks().size(), delta ) ) break; diff --git a/pcbnew/edit.cpp b/pcbnew/edit.cpp index 7472c0e3bf..f476a617f0 100644 --- a/pcbnew/edit.cpp +++ b/pcbnew/edit.cpp @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include diff --git a/pcbnew/edit_track_width.cpp b/pcbnew/edit_track_width.cpp index 6f39ba6f7b..375df9ce15 100644 --- a/pcbnew/edit_track_width.cpp +++ b/pcbnew/edit_track_width.cpp @@ -25,12 +25,12 @@ #include #include #include -#include +#include #include #include #include -void PCB_EDIT_FRAME::SetTrackSegmentWidth( TRACK* aTrackItem, +void PCB_EDIT_FRAME::SetTrackSegmentWidth( PCB_TRACK* aTrackItem, PICKED_ITEMS_LIST* aItemsListPicker, bool aUseNetclassValue ) { @@ -48,7 +48,7 @@ void PCB_EDIT_FRAME::SetTrackSegmentWidth( TRACK* aTrackItem, if( aTrackItem->Type() == PCB_VIA_T ) { - const VIA *via = static_cast( aTrackItem ); + const PCB_VIA *via = static_cast( aTrackItem ); // Get the drill value, regardless it is default or specific initial_drill = via->GetDrillValue(); @@ -89,7 +89,7 @@ void PCB_EDIT_FRAME::SetTrackSegmentWidth( TRACK* aTrackItem, if( aTrackItem->Type() == PCB_VIA_T ) { // Set new drill value. Note: currently microvias have only a default drill value - VIA *via = static_cast( aTrackItem ); + PCB_VIA *via = static_cast( aTrackItem ); if( new_drill > 0 ) via->SetDrill( new_drill ); diff --git a/pcbnew/exporters/export_d356.cpp b/pcbnew/exporters/export_d356.cpp index fbb953498b..c62640e526 100644 --- a/pcbnew/exporters/export_d356.cpp +++ b/pcbnew/exporters/export_d356.cpp @@ -41,7 +41,7 @@ #include #include #include -#include +#include #include #include #include // for KiROUND @@ -175,7 +175,7 @@ static void build_via_testpoints( BOARD *aPcb, std::vector & aRecor { if( track->Type() == PCB_VIA_T ) { - VIA *via = (VIA*) track; + PCB_VIA *via = static_cast( track ); NETINFO_ITEM *net = track->GetNet(); D356_RECORD rk; diff --git a/pcbnew/exporters/export_gencad.cpp b/pcbnew/exporters/export_gencad.cpp index 0818a23069..415c3bd653 100644 --- a/pcbnew/exporters/export_gencad.cpp +++ b/pcbnew/exporters/export_gencad.cpp @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include #include #include @@ -333,7 +333,7 @@ void PCB_EDIT_FRAME::ExportToGenCAD( wxCommandEvent& aEvent ) // Sort vias for uniqueness -static bool ViaSort( const VIA* aPadref, const VIA* aPadcmp ) +static bool ViaSort( const PCB_VIA* aPadref, const PCB_VIA* aPadcmp ) { if( aPadref->GetWidth() != aPadcmp->GetWidth() ) return aPadref->GetWidth() < aPadcmp->GetWidth(); @@ -361,9 +361,9 @@ static void CreateArtworksSection( FILE* aFile ) // Via name is synthesized from their attributes, pads are numbered static void CreatePadsShapesSection( FILE* aFile, BOARD* aPcb ) { - std::vector padstacks; - std::vector vias; - std::vector viastacks; + std::vector padstacks; + std::vector vias; + std::vector viastacks; padstacks.resize( 1 ); // We count pads from 1 @@ -383,14 +383,14 @@ static void CreatePadsShapesSection( FILE* aFile, BOARD* aPcb ) // The same for vias - for( TRACK* track : aPcb->Tracks() ) + for( PCB_TRACK* track : aPcb->Tracks() ) { - if( VIA* via = dyn_cast( track ) ) + if( PCB_VIA* via = dyn_cast( track ) ) vias.push_back( via ); } std::sort( vias.begin(), vias.end(), ViaSort ); - vias.erase( std::unique( vias.begin(), vias.end(), []( const VIA* a, const VIA* b ) + vias.erase( std::unique( vias.begin(), vias.end(), []( const PCB_VIA* a, const PCB_VIA* b ) { return ViaSort( a, b ) == false; } ), @@ -398,7 +398,7 @@ static void CreatePadsShapesSection( FILE* aFile, BOARD* aPcb ) // Emit vias pads - for( VIA* via : vias ) + for( PCB_VIA* via : vias ) { viastacks.push_back( via ); fprintf( aFile, "PAD V%d.%d.%s ROUND %g\nCIRCLE 0 0 %g\n", @@ -608,7 +608,7 @@ static void CreatePadsShapesSection( FILE* aFile, BOARD* aPcb ) // Via padstacks for( unsigned i = 0; i < viastacks.size(); i++ ) { - VIA* via = viastacks[i]; + PCB_VIA* via = viastacks[i]; LSET mask = via->GetLayerSet() & master_layermask; @@ -982,7 +982,7 @@ static void CreateRoutesSection( FILE* aFile, BOARD* aPcb ) TRACKS tracks( aPcb->Tracks() ); std::sort( tracks.begin(), tracks.end(), - []( const TRACK* a, const TRACK* b ) + []( const PCB_TRACK* a, const PCB_TRACK* b ) { if( a->GetNetCode() == b->GetNetCode() ) { @@ -999,7 +999,7 @@ static void CreateRoutesSection( FILE* aFile, BOARD* aPcb ) old_netcode = -1; old_width = -1; old_layer = -1; - for( TRACK* track : tracks ) + for( PCB_TRACK* track : tracks ) { if( old_netcode != track->GetNetCode() ) { @@ -1037,7 +1037,7 @@ static void CreateRoutesSection( FILE* aFile, BOARD* aPcb ) if( track->Type() == PCB_VIA_T ) { - const VIA* via = static_cast(track); + const PCB_VIA* via = static_cast(track); LSET vset = via->GetLayerSet() & master_layermask; @@ -1130,7 +1130,7 @@ static void CreateTracksInfoData( FILE* aFile, BOARD* aPcb ) std::set trackinfo; - for( TRACK* track : aPcb->Tracks() ) + for( PCB_TRACK* track : aPcb->Tracks() ) trackinfo.insert( track->GetWidth() ); // Write data diff --git a/pcbnew/exporters/export_hyperlynx.cpp b/pcbnew/exporters/export_hyperlynx.cpp index e61d7e3204..032ad7a086 100644 --- a/pcbnew/exporters/export_hyperlynx.cpp +++ b/pcbnew/exporters/export_hyperlynx.cpp @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include #include @@ -54,7 +54,7 @@ public: friend class HYPERLYNX_EXPORTER; HYPERLYNX_PAD_STACK( BOARD* aBoard, const PAD* aPad ); - HYPERLYNX_PAD_STACK( BOARD* aBoard, const VIA* aVia ); + HYPERLYNX_PAD_STACK( BOARD* aBoard, const PCB_VIA* aVia ); ~HYPERLYNX_PAD_STACK(){}; bool isThrough() const @@ -246,7 +246,7 @@ HYPERLYNX_PAD_STACK::HYPERLYNX_PAD_STACK( BOARD* aBoard, const PAD* aPad ) } -HYPERLYNX_PAD_STACK::HYPERLYNX_PAD_STACK( BOARD* aBoard, const VIA* aVia ) +HYPERLYNX_PAD_STACK::HYPERLYNX_PAD_STACK( BOARD* aBoard, const PCB_VIA* aVia ) { m_board = aBoard; m_sx = aVia->GetWidth(); @@ -416,9 +416,9 @@ bool HYPERLYNX_EXPORTER::writePadStacks() } } - for( TRACK* trk : m_board->Tracks() ) + for( PCB_TRACK* track : m_board->Tracks() ) { - if( VIA* via = dyn_cast( trk ) ) + if( PCB_VIA* via = dyn_cast( track ) ) { HYPERLYNX_PAD_STACK* ps = addPadStack( HYPERLYNX_PAD_STACK( m_board, via ) ); m_padMap[via] = ps; @@ -459,7 +459,7 @@ bool HYPERLYNX_EXPORTER::writeNetObjects( const std::vector& aObjec pstackIter->second->GetId() ); } } - else if( VIA* via = dyn_cast( item ) ) + else if( PCB_VIA* via = dyn_cast( item ) ) { auto pstackIter = m_padMap.find( via ); @@ -469,7 +469,7 @@ bool HYPERLYNX_EXPORTER::writeNetObjects( const std::vector& aObjec iu2hyp( via->GetPosition().y ), pstackIter->second->GetId() ); } } - else if( TRACK* track = dyn_cast( item ) ) + else if( PCB_TRACK* track = dyn_cast( item ) ) { const wxString layerName = m_board->GetLayerName( track->GetLayer() ); @@ -560,7 +560,7 @@ const std::vector HYPERLYNX_EXPORTER::collectNetObjects( int netcod } } - for( TRACK* item : m_board->Tracks() ) + for( PCB_TRACK* item : m_board->Tracks() ) { if( check( item ) ) rv.push_back( item ); diff --git a/pcbnew/exporters/export_vrml.cpp b/pcbnew/exporters/export_vrml.cpp index aadaa7bf23..8e08f979a9 100644 --- a/pcbnew/exporters/export_vrml.cpp +++ b/pcbnew/exporters/export_vrml.cpp @@ -39,7 +39,7 @@ #include "footprint.h" #include "pad.h" #include "pcb_text.h" -#include "track.h" +#include "pcb_track.h" #include "convert_to_biu.h" #include #include @@ -615,12 +615,12 @@ void EXPORTER_PCB_VRML::ExportVrmlViaHoles() { PCB_LAYER_ID top_layer, bottom_layer; - for( TRACK* track : m_Pcb->Tracks() ) + for( PCB_TRACK* track : m_Pcb->Tracks() ) { if( track->Type() != PCB_VIA_T ) continue; - const VIA* via = (const VIA*) track; + const PCB_VIA* via = static_cast( track ); via->LayerPair( &top_layer, &bottom_layer ); diff --git a/pcbnew/exporters/exporter_vrml.h b/pcbnew/exporters/exporter_vrml.h index 23f6a9ec25..96fe4abe63 100644 --- a/pcbnew/exporters/exporter_vrml.h +++ b/pcbnew/exporters/exporter_vrml.h @@ -140,7 +140,7 @@ public: // Build and exports the board outlines (board body) void ExportVrmlBoard(); - void ExportVrmlVia( const VIA* aVia ); + void ExportVrmlVia( const PCB_VIA* aVia ); // Export all via holes void ExportVrmlViaHoles(); diff --git a/pcbnew/exporters/gendrill_file_writer_base.cpp b/pcbnew/exporters/gendrill_file_writer_base.cpp index 9164e77d2f..62cc6896dd 100644 --- a/pcbnew/exporters/gendrill_file_writer_base.cpp +++ b/pcbnew/exporters/gendrill_file_writer_base.cpp @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include @@ -81,8 +81,8 @@ void GENDRILL_WRITER_BASE::buildHolesList( DRILL_LAYER_PAIR aLayerPair, if( track->Type() != PCB_VIA_T ) continue; - auto via = static_cast( track ); - int hole_sz = via->GetDrillValue(); + PCB_VIA* via = static_cast( track ); + int hole_sz = via->GetDrillValue(); if( hole_sz == 0 ) // Should not occur. continue; @@ -222,7 +222,7 @@ std::vector GENDRILL_WRITER_BASE::getUniqueLayerPairs() const for( int i = 0; i < vias.GetCount(); ++i ) { - VIA* v = (VIA*) vias[i]; + PCB_VIA* v = static_cast( vias[i] ); v->LayerPair( &layer_pair.first, &layer_pair.second ); diff --git a/pcbnew/exporters/gendrill_gerber_writer.cpp b/pcbnew/exporters/gendrill_gerber_writer.cpp index cadb95856b..ac13ecfbbb 100644 --- a/pcbnew/exporters/gendrill_gerber_writer.cpp +++ b/pcbnew/exporters/gendrill_gerber_writer.cpp @@ -36,7 +36,7 @@ #include #include #include -#include +#include #include #include #include @@ -182,7 +182,7 @@ int GERBER_WRITER::createDrillFile( wxString& aFullFilename, bool aIsNpth, // "Slot" for oblong holes; GBR_METADATA gbr_metadata; - if( dyn_cast(hole_descr.m_ItemParent ) ) + if( dyn_cast( hole_descr.m_ItemParent ) ) { gbr_metadata.SetApertureAttrib( GBR_APERTURE_METADATA::GBR_APERTURE_ATTRIB_VIADRILL ); diff --git a/pcbnew/exporters/gerber_jobfile_writer.cpp b/pcbnew/exporters/gerber_jobfile_writer.cpp index 89e38a7486..38b2408e95 100644 --- a/pcbnew/exporters/gerber_jobfile_writer.cpp +++ b/pcbnew/exporters/gerber_jobfile_writer.cpp @@ -40,7 +40,7 @@ #include #include #include -#include +#include #include #include @@ -496,7 +496,7 @@ void GERBER_JOBFILE_WRITER::addJSONDesignRules() int mintrackWidthOuter = INT_MAX; int mintrackWidthInner = INT_MAX; - for( TRACK* track : m_pcb->Tracks() ) + for( PCB_TRACK* track : m_pcb->Tracks() ) { if( track->Type() == PCB_VIA_T ) continue; diff --git a/pcbnew/footprint.cpp b/pcbnew/footprint.cpp index cec8bb4bf4..a94f06e61b 100644 --- a/pcbnew/footprint.cpp +++ b/pcbnew/footprint.cpp @@ -39,7 +39,7 @@ #include #include #include -#include +#include #include #include #include @@ -1817,7 +1817,7 @@ double FOOTPRINT::GetCoverageArea( const BOARD_ITEM* aItem, const GENERAL_COLLEC } else if( aItem->Type() == PCB_TRACE_T || aItem->Type() == PCB_ARC_T ) { - double width = static_cast( aItem )->GetWidth(); + double width = static_cast( aItem )->GetWidth(); return width * width; } else diff --git a/pcbnew/kicad_clipboard.cpp b/pcbnew/kicad_clipboard.cpp index 437ce959eb..efbfef00cc 100644 --- a/pcbnew/kicad_clipboard.cpp +++ b/pcbnew/kicad_clipboard.cpp @@ -27,7 +27,6 @@ #include #include -#include #include #include #include diff --git a/pcbnew/netinfo_item.cpp b/pcbnew/netinfo_item.cpp index 2b14d5c02b..7b71b523b8 100644 --- a/pcbnew/netinfo_item.cpp +++ b/pcbnew/netinfo_item.cpp @@ -34,7 +34,7 @@ #include #include #include -#include +#include #include @@ -84,8 +84,8 @@ void NETINFO_ITEM::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vectorFootprints() ) { @@ -100,7 +100,7 @@ void NETINFO_ITEM::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vectorTracks() ) + for( PCB_TRACK* track : board->Tracks() ) { if( track->GetNetCode() == GetNetCode() ) { diff --git a/pcbnew/netinfo_list.cpp b/pcbnew/netinfo_list.cpp index 18d2e0b850..a7f30ca945 100644 --- a/pcbnew/netinfo_list.cpp +++ b/pcbnew/netinfo_list.cpp @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include @@ -223,7 +223,7 @@ void NETINFO_MAPPING::Update() nets.insert( zone->GetNetCode() ); // Tracks - for( TRACK* track : m_board->Tracks() ) + for( PCB_TRACK* track : m_board->Tracks() ) nets.insert( track->GetNetCode() ); // footprints/pads diff --git a/pcbnew/netlist_reader/board_netlist_updater.cpp b/pcbnew/netlist_reader/board_netlist_updater.cpp index 0df4727d68..9de050eb3d 100644 --- a/pcbnew/netlist_reader/board_netlist_updater.cpp +++ b/pcbnew/netlist_reader/board_netlist_updater.cpp @@ -33,7 +33,7 @@ #include #include #include -#include +#include #include #include #include @@ -608,7 +608,7 @@ bool BOARD_NETLIST_UPDATER::updateCopperZoneNets( NETLIST& aNetlist ) } } - for( TRACK* via : m_board->Tracks() ) + for( PCB_TRACK* via : m_board->Tracks() ) { if( via->Type() != PCB_VIA_T ) continue; diff --git a/pcbnew/pad.h b/pcbnew/pad.h index 9167dd5c79..0e2f35bdee 100644 --- a/pcbnew/pad.h +++ b/pcbnew/pad.h @@ -48,7 +48,6 @@ class LINE_READER; class EDA_3D_CANVAS; class FOOTPRINT; class FP_SHAPE; -class TRACK; namespace KIGFX { diff --git a/pcbnew/pcb_base_frame.cpp b/pcbnew/pcb_base_frame.cpp index 8a41b76b1a..fc2655f26b 100644 --- a/pcbnew/pcb_base_frame.cpp +++ b/pcbnew/pcb_base_frame.cpp @@ -751,7 +751,7 @@ void PCB_BASE_FRAME::SetDisplayOptions( const PCB_DISPLAY_OPTIONS& aOptions, boo GetCanvas()->GetView()->UpdateAllItemsConditionally( KIGFX::REPAINT, []( KIGFX::VIEW_ITEM* aItem ) -> bool { - if( VIA* via = dynamic_cast( aItem ) ) + if( PCB_VIA* via = dynamic_cast( aItem ) ) { return via->GetViaType() == VIATYPE::BLIND_BURIED || via->GetViaType() == VIATYPE::MICROVIA; diff --git a/pcbnew/pcb_draw_panel_gal.cpp b/pcbnew/pcb_draw_panel_gal.cpp index 7ba004d8a6..912a053138 100644 --- a/pcbnew/pcb_draw_panel_gal.cpp +++ b/pcbnew/pcb_draw_panel_gal.cpp @@ -31,7 +31,7 @@ #include #include -#include +#include #include #include #include @@ -207,7 +207,7 @@ void PCB_DRAW_PANEL_GAL::DisplayBoard( BOARD* aBoard ) m_view->Add( drawing ); // Load tracks - for( TRACK* track : aBoard->Tracks() ) + for( PCB_TRACK* track : aBoard->Tracks() ) m_view->Add( track ); // Load footprints and its additional elements @@ -442,7 +442,7 @@ void PCB_DRAW_PANEL_GAL::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, int viasCount = 0; int trackSegmentsCount = 0; - for( TRACK* item : board->Tracks() ) + for( PCB_TRACK* item : board->Tracks() ) { if( item->Type() == PCB_VIA_T ) viasCount++; diff --git a/pcbnew/pcb_edit_frame.cpp b/pcbnew/pcb_edit_frame.cpp index 1e664e9838..ecff4feaa5 100644 --- a/pcbnew/pcb_edit_frame.cpp +++ b/pcbnew/pcb_edit_frame.cpp @@ -936,11 +936,11 @@ void PCB_EDIT_FRAME::ShowBoardSetupDialog( const wxString& aInitialPage ) GetCanvas()->GetView()->UpdateAllItemsConditionally( KIGFX::REPAINT, [&]( KIGFX::VIEW_ITEM* aItem ) -> bool { - TRACK* track = dynamic_cast( aItem ); - PAD* pad = dynamic_cast( aItem ); + PCB_TRACK* track = dynamic_cast( aItem ); + PAD* pad = dynamic_cast( aItem ); - // TRACK is the base class of VIA and ARC so we don't need to - // check them independently + // PCB_TRACK is the base class of PCB_VIA and PCB_ARC so we don't need + // to check them independently return ( track && opts.m_ShowTrackClearanceMode ) || ( pad && opts.m_DisplayPadClearance ); @@ -1031,7 +1031,7 @@ void PCB_EDIT_FRAME::SetActiveLayer( PCB_LAYER_ID aLayer ) GetCanvas()->GetView()->UpdateAllItemsConditionally( KIGFX::REPAINT, [&]( KIGFX::VIEW_ITEM* aItem ) -> bool { - if( VIA* via = dynamic_cast( aItem ) ) + if( PCB_VIA* via = dynamic_cast( aItem ) ) { // Vias on a restricted layer set must be redrawn when the active layer // is changed @@ -1059,7 +1059,7 @@ void PCB_EDIT_FRAME::SetActiveLayer( PCB_LAYER_ID aLayer ) return true; } } - else if( TRACK* track = dynamic_cast( aItem ) ) + else if( PCB_TRACK* track = dynamic_cast( aItem ) ) { // Clearances could be layer-dependent so redraw them when the active layer // is changed diff --git a/pcbnew/pcb_edit_frame.h b/pcbnew/pcb_edit_frame.h index 41fd9fbb70..d8e83b49a7 100644 --- a/pcbnew/pcb_edit_frame.h +++ b/pcbnew/pcb_edit_frame.h @@ -33,8 +33,8 @@ class BOARD; class BOARD_COMMIT; class BOARD_ITEM_CONTAINER; class FOOTPRINT; -class TRACK; -class VIA; +class PCB_TRACK; +class PCB_VIA; class PAD; class PCB_TARGET; class PCB_GROUP; @@ -544,7 +544,7 @@ public: * @param aUseNetclassValue true to use NetClass value, false to use current designSettings * value. */ - void SetTrackSegmentWidth( TRACK* aTrackItem, PICKED_ITEMS_LIST* aItemsListPicker, + void SetTrackSegmentWidth( PCB_TRACK* aTrackItem, PICKED_ITEMS_LIST* aItemsListPicker, bool aUseNetclassValue ); diff --git a/pcbnew/pcb_expr_evaluator.cpp b/pcbnew/pcb_expr_evaluator.cpp index ddb3b93c9b..81c4ad5a50 100644 --- a/pcbnew/pcb_expr_evaluator.cpp +++ b/pcbnew/pcb_expr_evaluator.cpp @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include #include @@ -476,7 +476,7 @@ static void insideArea( LIBEVAL::CONTEXT* aCtx, void* self ) } else if( item->Type() == PCB_VIA_T ) { - VIA* via = static_cast( item ); + PCB_VIA* via = static_cast( item ); const SHAPE_CIRCLE holeShape( via->GetPosition(), via->GetDrillValue() ); return areaOutline.Collide( &holeShape ); @@ -712,12 +712,10 @@ static void isMicroVia( LIBEVAL::CONTEXT* aCtx, void* self ) result->Set( 0.0 ); aCtx->Push( result ); - auto via = dyn_cast( item ); + PCB_VIA* via = dyn_cast( item ); if( via && via->GetViaType() == VIATYPE::MICROVIA ) - { result->Set ( 1.0 ); - } } @@ -730,12 +728,10 @@ static void isBlindBuriedVia( LIBEVAL::CONTEXT* aCtx, void* self ) result->Set( 0.0 ); aCtx->Push( result ); - auto via = dyn_cast( item ); + PCB_VIA* via = dyn_cast( item ); if( via && via->GetViaType() == VIATYPE::BLIND_BURIED ) - { result->Set ( 1.0 ); - } } diff --git a/pcbnew/pcb_item_containers.h b/pcbnew/pcb_item_containers.h index 3404470ecb..0c7bf7f05e 100644 --- a/pcbnew/pcb_item_containers.h +++ b/pcbnew/pcb_item_containers.h @@ -28,14 +28,14 @@ // Board-level items class FOOTPRINT; -class TRACK; +class PCB_TRACK; class PCB_GROUP; class PCB_MARKER; class ZONE; DECL_VEC_FOR_SWIG( MARKERS, PCB_MARKER* ) DECL_VEC_FOR_SWIG( ZONES, ZONE* ) -DECL_DEQ_FOR_SWIG( TRACKS, TRACK* ) +DECL_DEQ_FOR_SWIG( TRACKS, PCB_TRACK* ) DECL_DEQ_FOR_SWIG( FOOTPRINTS, FOOTPRINT* ) // Dequeue rather than Vector just so we can use moveUnflaggedItems in pcbnew_control.cpp DECL_DEQ_FOR_SWIG( GROUPS, PCB_GROUP* ) diff --git a/pcbnew/pcb_painter.cpp b/pcbnew/pcb_painter.cpp index 126140948d..6ba1b08b92 100644 --- a/pcbnew/pcb_painter.cpp +++ b/pcbnew/pcb_painter.cpp @@ -25,7 +25,7 @@ #include #include -#include +#include #include #include #include @@ -233,10 +233,10 @@ COLOR4D PCB_RENDER_SETTINGS::GetColor( const VIEW_ITEM* aItem, int aLayer ) cons { // Careful that we don't end up with the same colour for the annular ring and the hole // when printing in B&W. - const PAD* pad = dynamic_cast( item ); - const VIA* via = dynamic_cast( item ); - int holeLayer = aLayer; - int annularRingLayer = UNDEFINED_LAYER; + const PAD* pad = dynamic_cast( item ); + const PCB_VIA* via = dynamic_cast( item ); + int holeLayer = aLayer; + int annularRingLayer = UNDEFINED_LAYER; if( pad && pad->GetAttribute() == PAD_ATTRIB::PTH ) annularRingLayer = LAYER_PADS_TH; @@ -349,13 +349,13 @@ COLOR4D PCB_RENDER_SETTINGS::GetColor( const VIEW_ITEM* aItem, int aLayer ) cons case LAYER_VIA_BBLIND: case LAYER_VIA_MICROVIA: // Target graphic is active if the via crosses the primary layer - if( static_cast( item )->GetLayerSet().test( primary ) == 0 ) + if( static_cast( item )->GetLayerSet().test( primary ) == 0 ) isActive = false; break; case LAYER_VIA_THROUGH: - if( !static_cast( item )->FlashLayer( primary ) ) + if( !static_cast( item )->FlashLayer( primary ) ) isActive = false; break; @@ -371,11 +371,11 @@ COLOR4D PCB_RENDER_SETTINGS::GetColor( const VIEW_ITEM* aItem, int aLayer ) cons case LAYER_VIA_HOLES: case LAYER_VIA_HOLEWALLS: - if( static_cast( item )->GetViaType() == VIATYPE::BLIND_BURIED - || static_cast( item )->GetViaType() == VIATYPE::MICROVIA ) + if( static_cast( item )->GetViaType() == VIATYPE::BLIND_BURIED + || static_cast( item )->GetViaType() == VIATYPE::MICROVIA ) { // A blind or micro via's hole is active if it crosses the primary layer - if( static_cast( item )->GetLayerSet().test( primary ) == 0 ) + if( static_cast( item )->GetLayerSet().test( primary ) == 0 ) isActive = false; } else @@ -445,7 +445,7 @@ VECTOR2D PCB_PAINTER::getDrillSize( const PAD* aPad ) const } -int PCB_PAINTER::getDrillSize( const VIA* aVia ) const +int PCB_PAINTER::getDrillSize( const PCB_VIA* aVia ) const { return aVia->GetDrillValue(); } @@ -474,15 +474,15 @@ bool PCB_PAINTER::Draw( const VIEW_ITEM* aItem, int aLayer ) switch( item->Type() ) { case PCB_TRACE_T: - draw( static_cast( item ), aLayer ); + draw( static_cast( item ), aLayer ); break; case PCB_ARC_T: - draw( static_cast( item ), aLayer ); + draw( static_cast( item ), aLayer ); break; case PCB_VIA_T: - draw( static_cast( item ), aLayer ); + draw( static_cast( item ), aLayer ); break; case PCB_PAD_T: @@ -542,7 +542,7 @@ bool PCB_PAINTER::Draw( const VIEW_ITEM* aItem, int aLayer ) } -void PCB_PAINTER::draw( const TRACK* aTrack, int aLayer ) +void PCB_PAINTER::draw( const PCB_TRACK* aTrack, int aLayer ) { VECTOR2D start( aTrack->GetStart() ); VECTOR2D end( aTrack->GetEnd() ); @@ -633,7 +633,7 @@ void PCB_PAINTER::draw( const TRACK* aTrack, int aLayer ) } -void PCB_PAINTER::draw( const ARC* aArc, int aLayer ) +void PCB_PAINTER::draw( const PCB_ARC* aArc, int aLayer ) { VECTOR2D center( aArc->GetCenter() ); int width = aArc->GetWidth(); @@ -679,7 +679,7 @@ void PCB_PAINTER::draw( const ARC* aArc, int aLayer ) } -void PCB_PAINTER::draw( const VIA* aVia, int aLayer ) +void PCB_PAINTER::draw( const PCB_VIA* aVia, int aLayer ) { BOARD* board = aVia->GetBoard(); BOARD_DESIGN_SETTINGS& bds = board->GetDesignSettings(); diff --git a/pcbnew/pcb_painter.h b/pcbnew/pcb_painter.h index 6277314050..e930b2e8b6 100644 --- a/pcbnew/pcb_painter.h +++ b/pcbnew/pcb_painter.h @@ -37,10 +37,10 @@ class EDA_ITEM; class PCB_DISPLAY_OPTIONS; class BOARD_ITEM; -class ARC; +class PCB_ARC; class BOARD; -class VIA; -class TRACK; +class PCB_VIA; +class PCB_TRACK; class PAD; class PCB_SHAPE; class PCB_GROUP; @@ -254,9 +254,9 @@ public: protected: // Drawing functions for various types of PCB-specific items - void draw( const TRACK* aTrack, int aLayer ); - void draw( const ARC* aArc, int aLayer ); - void draw( const VIA* aVia, int aLayer ); + void draw( const PCB_TRACK* aTrack, int aLayer ); + void draw( const PCB_ARC* aArc, int aLayer ); + void draw( const PCB_VIA* aVia, int aLayer ); void draw( const PAD* aPad, int aLayer ); void draw( const PCB_SHAPE* aSegment, int aLayer ); void draw( const PCB_TEXT* aText, int aLayer ); @@ -289,7 +289,7 @@ protected: /** * Return drill diameter for a via (internal units). */ - virtual int getDrillSize( const VIA* aVia ) const; + virtual int getDrillSize( const PCB_VIA* aVia ) const; protected: PCB_RENDER_SETTINGS m_pcbSettings; diff --git a/pcbnew/track.cpp b/pcbnew/pcb_track.cpp similarity index 77% rename from pcbnew/track.cpp rename to pcbnew/pcb_track.cpp index f9e04613a5..d836b3e2bf 100644 --- a/pcbnew/track.cpp +++ b/pcbnew/pcb_track.cpp @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include #include #include @@ -47,20 +47,21 @@ using KIGFX::PCB_PAINTER; using KIGFX::PCB_RENDER_SETTINGS; -TRACK::TRACK( BOARD_ITEM* aParent, KICAD_T idtype ) : +PCB_TRACK::PCB_TRACK( BOARD_ITEM* aParent, KICAD_T idtype ) : BOARD_CONNECTED_ITEM( aParent, idtype ) { m_Width = Millimeter2iu( 0.2 ); // Gives a reasonable default width } -EDA_ITEM* TRACK::Clone() const +EDA_ITEM* PCB_TRACK::Clone() const { - return new TRACK( *this ); + return new PCB_TRACK( *this ); } -ARC::ARC( BOARD_ITEM* aParent, const SHAPE_ARC* aArc ) : TRACK( aParent, PCB_ARC_T ) +PCB_ARC::PCB_ARC( BOARD_ITEM* aParent, const SHAPE_ARC* aArc ) : + PCB_TRACK( aParent, PCB_ARC_T ) { m_Start = wxPoint( aArc->GetP0() ); m_End = wxPoint( aArc->GetP1() ); @@ -68,14 +69,14 @@ ARC::ARC( BOARD_ITEM* aParent, const SHAPE_ARC* aArc ) : TRACK( aParent, PCB_ARC } -EDA_ITEM* ARC::Clone() const +EDA_ITEM* PCB_ARC::Clone() const { - return new ARC( *this ); + return new PCB_ARC( *this ); } -VIA::VIA( BOARD_ITEM* aParent ) : - TRACK( aParent, PCB_VIA_T ) +PCB_VIA::PCB_VIA( BOARD_ITEM* aParent ) : + PCB_TRACK( aParent, PCB_VIA_T ) { SetViaType( VIATYPE::THROUGH ); m_bottomLayer = B_Cu; @@ -86,13 +87,13 @@ VIA::VIA( BOARD_ITEM* aParent ) : } -EDA_ITEM* VIA::Clone() const +EDA_ITEM* PCB_VIA::Clone() const { - return new VIA( *this ); + return new PCB_VIA( *this ); } -wxString VIA::GetSelectMenuText( EDA_UNITS aUnits ) const +wxString PCB_VIA::GetSelectMenuText( EDA_UNITS aUnits ) const { wxString formatStr; @@ -109,13 +110,13 @@ wxString VIA::GetSelectMenuText( EDA_UNITS aUnits ) const } -BITMAPS VIA::GetMenuImage() const +BITMAPS PCB_VIA::GetMenuImage() const { return BITMAPS::via; } -bool TRACK::ApproxCollinear( const TRACK& aTrack ) +bool PCB_TRACK::ApproxCollinear( const PCB_TRACK& aTrack ) { SEG a( m_Start, m_End ); SEG b( aTrack.GetStart(), aTrack.GetEnd() ); @@ -123,14 +124,14 @@ bool TRACK::ApproxCollinear( const TRACK& aTrack ) } -int TRACK::GetLocalClearance( wxString* aSource ) const +int PCB_TRACK::GetLocalClearance( wxString* aSource ) const { // Not currently implemented return 0; } -void TRACK::GetWidthConstraints( int* aMin, int* aMax, wxString* aSource ) const +void PCB_TRACK::GetWidthConstraints( int* aMin, int* aMax, wxString* aSource ) const { *aMin = 0; *aMax = INT_MAX; @@ -158,7 +159,7 @@ void TRACK::GetWidthConstraints( int* aMin, int* aMax, wxString* aSource ) const } -int VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const +int PCB_VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const { if( !FlashLayer( aLayer ) ) { @@ -189,7 +190,7 @@ int VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const } -int VIA::GetDrillValue() const +int PCB_VIA::GetDrillValue() const { if( m_drill > 0 ) // Use the specific value. return m_drill; @@ -204,7 +205,7 @@ int VIA::GetDrillValue() const } -EDA_ITEM_FLAGS TRACK::IsPointOnEnds( const wxPoint& point, int min_dist ) const +EDA_ITEM_FLAGS PCB_TRACK::IsPointOnEnds( const wxPoint& point, int min_dist ) const { EDA_ITEM_FLAGS result = 0; @@ -236,7 +237,7 @@ EDA_ITEM_FLAGS TRACK::IsPointOnEnds( const wxPoint& point, int min_dist ) const } -const EDA_RECT TRACK::GetBoundingBox() const +const EDA_RECT PCB_TRACK::GetBoundingBox() const { // end of track is round, this is its radius, rounded up int radius = ( m_Width + 1 ) / 2; @@ -282,20 +283,20 @@ const EDA_RECT TRACK::GetBoundingBox() const } -double TRACK::GetLength() const +double PCB_TRACK::GetLength() const { return GetLineLength( m_Start, m_End ); } -void TRACK::Rotate( const wxPoint& aRotCentre, double aAngle ) +void PCB_TRACK::Rotate( const wxPoint& aRotCentre, double aAngle ) { RotatePoint( &m_Start, aRotCentre, aAngle ); RotatePoint( &m_End, aRotCentre, aAngle ); } -void ARC::Rotate( const wxPoint& aRotCentre, double aAngle ) +void PCB_ARC::Rotate( const wxPoint& aRotCentre, double aAngle ) { RotatePoint( &m_Start, aRotCentre, aAngle ); RotatePoint( &m_End, aRotCentre, aAngle ); @@ -303,7 +304,7 @@ void ARC::Rotate( const wxPoint& aRotCentre, double aAngle ) } -void TRACK::Flip( const wxPoint& aCentre, bool aFlipLeftRight ) +void PCB_TRACK::Flip( const wxPoint& aCentre, bool aFlipLeftRight ) { if( aFlipLeftRight ) { @@ -321,7 +322,7 @@ void TRACK::Flip( const wxPoint& aCentre, bool aFlipLeftRight ) } -void ARC::Flip( const wxPoint& aCentre, bool aFlipLeftRight ) +void PCB_ARC::Flip( const wxPoint& aCentre, bool aFlipLeftRight ) { if( aFlipLeftRight ) { @@ -341,7 +342,7 @@ void ARC::Flip( const wxPoint& aCentre, bool aFlipLeftRight ) } -void VIA::Flip( const wxPoint& aCentre, bool aFlipLeftRight ) +void PCB_VIA::Flip( const wxPoint& aCentre, bool aFlipLeftRight ) { if( aFlipLeftRight ) { @@ -368,7 +369,7 @@ void VIA::Flip( const wxPoint& aCentre, bool aFlipLeftRight ) // see class_track.h -SEARCH_RESULT TRACK::Visit( INSPECTOR inspector, void* testData, const KICAD_T scanTypes[] ) +SEARCH_RESULT PCB_TRACK::Visit( INSPECTOR inspector, void* testData, const KICAD_T scanTypes[] ) { KICAD_T stype = *scanTypes; @@ -383,7 +384,7 @@ SEARCH_RESULT TRACK::Visit( INSPECTOR inspector, void* testData, const KICAD_T s } -bool VIA::IsOnLayer( PCB_LAYER_ID layer_number ) const +bool PCB_VIA::IsOnLayer( PCB_LAYER_ID layer_number ) const { PCB_LAYER_ID bottom_layer, top_layer; @@ -398,7 +399,7 @@ bool VIA::IsOnLayer( PCB_LAYER_ID layer_number ) const } -LSET VIA::GetLayerSet() const +LSET PCB_VIA::GetLayerSet() const { if( GetViaType() == VIATYPE::THROUGH ) return LSET::AllCuMask(); @@ -419,7 +420,7 @@ LSET VIA::GetLayerSet() const } -void VIA::SetLayerSet( LSET aLayerSet ) +void PCB_VIA::SetLayerSet( LSET aLayerSet ) { bool first = true; @@ -436,7 +437,7 @@ void VIA::SetLayerSet( LSET aLayerSet ) } -void VIA::SetLayerPair( PCB_LAYER_ID aTopLayer, PCB_LAYER_ID aBottomLayer ) +void PCB_VIA::SetLayerPair( PCB_LAYER_ID aTopLayer, PCB_LAYER_ID aBottomLayer ) { m_layer = aTopLayer; @@ -445,19 +446,19 @@ void VIA::SetLayerPair( PCB_LAYER_ID aTopLayer, PCB_LAYER_ID aBottomLayer ) } -void VIA::SetTopLayer( PCB_LAYER_ID aLayer ) +void PCB_VIA::SetTopLayer( PCB_LAYER_ID aLayer ) { m_layer = aLayer; } -void VIA::SetBottomLayer( PCB_LAYER_ID aLayer ) +void PCB_VIA::SetBottomLayer( PCB_LAYER_ID aLayer ) { m_bottomLayer = aLayer; } -void VIA::LayerPair( PCB_LAYER_ID* top_layer, PCB_LAYER_ID* bottom_layer ) const +void PCB_VIA::LayerPair( PCB_LAYER_ID* top_layer, PCB_LAYER_ID* bottom_layer ) const { PCB_LAYER_ID t_layer = F_Cu; PCB_LAYER_ID b_layer = B_Cu; @@ -479,19 +480,19 @@ void VIA::LayerPair( PCB_LAYER_ID* top_layer, PCB_LAYER_ID* bottom_layer ) const } -PCB_LAYER_ID VIA::TopLayer() const +PCB_LAYER_ID PCB_VIA::TopLayer() const { return m_layer; } -PCB_LAYER_ID VIA::BottomLayer() const +PCB_LAYER_ID PCB_VIA::BottomLayer() const { return m_bottomLayer; } -void VIA::SanitizeLayers() +void PCB_VIA::SanitizeLayers() { if( GetViaType() == VIATYPE::THROUGH ) { @@ -504,7 +505,7 @@ void VIA::SanitizeLayers() } -bool VIA::FlashLayer( LSET aLayers ) const +bool PCB_VIA::FlashLayer( LSET aLayers ) const { for( auto layer : aLayers.Seq() ) { @@ -516,7 +517,7 @@ bool VIA::FlashLayer( LSET aLayers ) const } -bool VIA::FlashLayer( int aLayer ) const +bool PCB_VIA::FlashLayer( int aLayer ) const { std::vector types { PCB_TRACE_T, PCB_ARC_T, PCB_PAD_T, PCB_ZONE_T, PCB_FP_ZONE_T }; @@ -544,7 +545,7 @@ bool VIA::FlashLayer( int aLayer ) const } -void TRACK::ViewGetLayers( int aLayers[], int& aCount ) const +void PCB_TRACK::ViewGetLayers( int aLayers[], int& aCount ) const { // Show the track and its netname on different layers aLayers[0] = GetLayer(); @@ -553,7 +554,7 @@ void TRACK::ViewGetLayers( int aLayers[], int& aCount ) const } -double TRACK::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const +double PCB_TRACK::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const { constexpr double HIDE = std::numeric_limits::max(); @@ -581,7 +582,7 @@ double TRACK::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const } -const BOX2I TRACK::ViewBBox() const +const BOX2I PCB_TRACK::ViewBBox() const { BOX2I bbox = GetBoundingBox(); @@ -594,7 +595,7 @@ const BOX2I TRACK::ViewBBox() const } -void VIA::ViewGetLayers( int aLayers[], int& aCount ) const +void PCB_VIA::ViewGetLayers( int aLayers[], int& aCount ) const { aLayers[0] = LAYER_VIA_HOLES; aLayers[1] = LAYER_VIA_HOLEWALLS; @@ -613,7 +614,7 @@ void VIA::ViewGetLayers( int aLayers[], int& aCount ) const } -double VIA::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const +double PCB_VIA::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const { constexpr double HIDE = (double)std::numeric_limits::max(); @@ -675,7 +676,7 @@ double VIA::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const // see class_track.h -void TRACK::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector& aList ) +void PCB_TRACK::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector& aList ) { EDA_UNITS units = aFrame->GetUserUnits(); wxString msg; @@ -693,7 +694,7 @@ void TRACK::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector if( Type() == PCB_ARC_T ) { - double radius = static_cast( this )->GetRadius(); + double radius = static_cast( this )->GetRadius(); aList.emplace_back( _( "Radius" ), MessageTextFromValue( units, radius ) ); } @@ -736,7 +737,7 @@ void TRACK::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector } -void VIA::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector& aList ) +void PCB_VIA::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector& aList ) { EDA_UNITS units = aFrame->GetUserUnits(); wxString msg; @@ -778,7 +779,8 @@ void VIA::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector& } -void TRACK::GetMsgPanelInfoBase_Common( EDA_DRAW_FRAME* aFrame, std::vector& aList ) const +void PCB_TRACK::GetMsgPanelInfoBase_Common( EDA_DRAW_FRAME* aFrame, + std::vector& aList ) const { wxString msg; @@ -810,7 +812,7 @@ void TRACK::GetMsgPanelInfoBase_Common( EDA_DRAW_FRAME* aFrame, std::vectorType() == PCB_TRACE_T ); - std::swap( *((TRACK*) this), *((TRACK*) aImage) ); + std::swap( *((PCB_TRACK*) this), *((PCB_TRACK*) aImage) ); } -void ARC::SwapData( BOARD_ITEM* aImage ) +void PCB_ARC::SwapData( BOARD_ITEM* aImage ) { assert( aImage->Type() == PCB_ARC_T ); - std::swap( *this, *static_cast( aImage ) ); + std::swap( *this, *static_cast( aImage ) ); } -void VIA::SwapData( BOARD_ITEM* aImage ) +void PCB_VIA::SwapData( BOARD_ITEM* aImage ) { assert( aImage->Type() == PCB_VIA_T ); - std::swap( *((VIA*) this), *((VIA*) aImage) ); + std::swap( *((PCB_VIA*) this), *((PCB_VIA*) aImage) ); } -wxPoint ARC::GetPosition() const +wxPoint PCB_ARC::GetPosition() const { auto center = GetArcCenter( VECTOR2I( m_Start ), VECTOR2I( m_Mid ), VECTOR2I( m_End ) ); return wxPoint( center.x, center.y ); } -double ARC::GetRadius() const +double PCB_ARC::GetRadius() const { auto center = GetArcCenter( VECTOR2I( m_Start ), VECTOR2I( m_Mid ), VECTOR2I( m_End ) ); return GetLineLength( wxPoint( center ), m_Start ); } -double ARC::GetAngle() const +double PCB_ARC::GetAngle() const { wxPoint center = GetPosition(); wxPoint p0 = m_Start - center; @@ -984,7 +985,7 @@ double ARC::GetAngle() const return NormalizeAngle180( angle1 ) + NormalizeAngle180( angle2 ); } -double ARC::GetArcAngleStart() const +double PCB_ARC::GetArcAngleStart() const { wxPoint center = GetPosition(); @@ -993,7 +994,7 @@ double ARC::GetArcAngleStart() const return NormalizeAnglePos( angleStart ); } -double ARC::GetArcAngleEnd() const +double PCB_ARC::GetArcAngleEnd() const { wxPoint center = GetPosition(); @@ -1003,7 +1004,7 @@ double ARC::GetArcAngleEnd() const } -bool TRACK::cmp_tracks::operator() ( const TRACK* a, const TRACK* b ) const +bool PCB_TRACK::cmp_tracks::operator() ( const PCB_TRACK* a, const PCB_TRACK* b ) const { if( a->GetNetCode() != b->GetNetCode() ) return a->GetNetCode() < b->GetNetCode(); @@ -1021,13 +1022,13 @@ bool TRACK::cmp_tracks::operator() ( const TRACK* a, const TRACK* b ) const } -std::shared_ptr TRACK::GetEffectiveShape( PCB_LAYER_ID aLayer ) const +std::shared_ptr PCB_TRACK::GetEffectiveShape( PCB_LAYER_ID aLayer ) const { return std::make_shared( m_Start, m_End, m_Width ); } -std::shared_ptr VIA::GetEffectiveShape( PCB_LAYER_ID aLayer ) const +std::shared_ptr PCB_VIA::GetEffectiveShape( PCB_LAYER_ID aLayer ) const { if( FlashLayer( aLayer ) ) return std::make_shared( m_Start, m_Width / 2 ); @@ -1036,7 +1037,7 @@ std::shared_ptr VIA::GetEffectiveShape( PCB_LAYER_ID aLayer ) const } -std::shared_ptr ARC::GetEffectiveShape( PCB_LAYER_ID aLayer ) const +std::shared_ptr PCB_ARC::GetEffectiveShape( PCB_LAYER_ID aLayer ) const { return std::make_shared( GetStart(), GetMid(), GetEnd(), GetWidth() ); } @@ -1045,7 +1046,7 @@ std::shared_ptr ARC::GetEffectiveShape( PCB_LAYER_ID aLayer ) const #if defined(DEBUG) -wxString TRACK::ShowState( int stateBits ) +wxString PCB_TRACK::ShowState( int stateBits ) { wxString ret; @@ -1102,57 +1103,57 @@ static struct TRACK_VIA_DESC PROPERTY_MANAGER& propMgr = PROPERTY_MANAGER::Instance(); // Track - REGISTER_TYPE( TRACK ); - propMgr.InheritsAfter( TYPE_HASH( TRACK ), TYPE_HASH( BOARD_CONNECTED_ITEM ) ); + REGISTER_TYPE( PCB_TRACK ); + propMgr.InheritsAfter( TYPE_HASH( PCB_TRACK ), TYPE_HASH( BOARD_CONNECTED_ITEM ) ); - propMgr.AddProperty( new PROPERTY( _HKI( "Width" ), - &TRACK::SetWidth, &TRACK::GetWidth, PROPERTY_DISPLAY::DISTANCE ) ); + propMgr.AddProperty( new PROPERTY( _HKI( "Width" ), + &PCB_TRACK::SetWidth, &PCB_TRACK::GetWidth, PROPERTY_DISPLAY::DISTANCE ) ); propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position X" ), - new PROPERTY( _HKI( "Origin X" ), - &TRACK::SetX, &TRACK::GetX, PROPERTY_DISPLAY::DISTANCE ) ); + new PROPERTY( _HKI( "Origin X" ), + &PCB_TRACK::SetX, &PCB_TRACK::GetX, PROPERTY_DISPLAY::DISTANCE ) ); propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position Y" ), - new PROPERTY( _HKI( "Origin Y" ), - &TRACK::SetY, &TRACK::GetY, PROPERTY_DISPLAY::DISTANCE ) ); - propMgr.AddProperty( new PROPERTY( _HKI( "End X" ), - &TRACK::SetEndX, &TRACK::GetEndX, PROPERTY_DISPLAY::DISTANCE ) ); - propMgr.AddProperty( new PROPERTY( _HKI( "End Y" ), - &TRACK::SetEndY, &TRACK::GetEndY, PROPERTY_DISPLAY::DISTANCE ) ); + new PROPERTY( _HKI( "Origin Y" ), + &PCB_TRACK::SetY, &PCB_TRACK::GetY, PROPERTY_DISPLAY::DISTANCE ) ); + propMgr.AddProperty( new PROPERTY( _HKI( "End X" ), + &PCB_TRACK::SetEndX, &PCB_TRACK::GetEndX, PROPERTY_DISPLAY::DISTANCE ) ); + propMgr.AddProperty( new PROPERTY( _HKI( "End Y" ), + &PCB_TRACK::SetEndY, &PCB_TRACK::GetEndY, PROPERTY_DISPLAY::DISTANCE ) ); // Arc - REGISTER_TYPE( ARC ); - propMgr.InheritsAfter( TYPE_HASH( ARC ), TYPE_HASH( BOARD_CONNECTED_ITEM ) ); + REGISTER_TYPE( PCB_ARC ); + propMgr.InheritsAfter( TYPE_HASH( PCB_ARC ), TYPE_HASH( BOARD_CONNECTED_ITEM ) ); - propMgr.AddProperty( new PROPERTY( _HKI( "Width" ), - &ARC::SetWidth, &ARC::GetWidth, PROPERTY_DISPLAY::DISTANCE ) ); + propMgr.AddProperty( new PROPERTY( _HKI( "Width" ), + &PCB_ARC::SetWidth, &PCB_ARC::GetWidth, PROPERTY_DISPLAY::DISTANCE ) ); propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position X" ), - new PROPERTY( _HKI( "Origin X" ), - &TRACK::SetX, &ARC::GetX, PROPERTY_DISPLAY::DISTANCE ) ); + new PROPERTY( _HKI( "Origin X" ), + &PCB_TRACK::SetX, &PCB_ARC::GetX, PROPERTY_DISPLAY::DISTANCE ) ); propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Position Y" ), - new PROPERTY( _HKI( "Origin Y" ), - &TRACK::SetY, &ARC::GetY, PROPERTY_DISPLAY::DISTANCE ) ); - propMgr.AddProperty( new PROPERTY( _HKI( "End X" ), - &TRACK::SetEndX, &ARC::GetEndX, PROPERTY_DISPLAY::DISTANCE ) ); - propMgr.AddProperty( new PROPERTY( _HKI( "End Y" ), - &TRACK::SetEndY, &ARC::GetEndY, PROPERTY_DISPLAY::DISTANCE ) ); + new PROPERTY( _HKI( "Origin Y" ), + &PCB_TRACK::SetY, &PCB_ARC::GetY, PROPERTY_DISPLAY::DISTANCE ) ); + propMgr.AddProperty( new PROPERTY( _HKI( "End X" ), + &PCB_TRACK::SetEndX, &PCB_ARC::GetEndX, PROPERTY_DISPLAY::DISTANCE ) ); + propMgr.AddProperty( new PROPERTY( _HKI( "End Y" ), + &PCB_TRACK::SetEndY, &PCB_ARC::GetEndY, PROPERTY_DISPLAY::DISTANCE ) ); // Via - REGISTER_TYPE( VIA ); - propMgr.InheritsAfter( TYPE_HASH( VIA ), TYPE_HASH( BOARD_CONNECTED_ITEM ) ); + REGISTER_TYPE( PCB_VIA ); + propMgr.InheritsAfter( TYPE_HASH( PCB_VIA ), TYPE_HASH( BOARD_CONNECTED_ITEM ) ); // TODO layerset for vias? // TODO test drill, use getdrillvalue? - propMgr.ReplaceProperty( TYPE_HASH( TRACK ), _HKI( "Width" ), - new PROPERTY( _HKI( "Diameter" ), - &VIA::SetWidth, &VIA::GetWidth, PROPERTY_DISPLAY::DISTANCE ) ); - propMgr.AddProperty( new PROPERTY( _HKI( "Drill" ), - &VIA::SetDrill, &VIA::GetDrillValue, PROPERTY_DISPLAY::DISTANCE ) ); + propMgr.ReplaceProperty( TYPE_HASH( PCB_TRACK ), _HKI( "Width" ), + new PROPERTY( _HKI( "Diameter" ), + &PCB_VIA::SetWidth, &PCB_VIA::GetWidth, PROPERTY_DISPLAY::DISTANCE ) ); + propMgr.AddProperty( new PROPERTY( _HKI( "Drill" ), + &PCB_VIA::SetDrill, &PCB_VIA::GetDrillValue, PROPERTY_DISPLAY::DISTANCE ) ); propMgr.ReplaceProperty( TYPE_HASH( BOARD_ITEM ), _HKI( "Layer" ), - new PROPERTY_ENUM( _HKI( "Layer Top" ), - &VIA::SetLayer, &VIA::GetLayer ) ); - propMgr.AddProperty( new PROPERTY_ENUM( _HKI( "Layer Bottom" ), - &VIA::SetBottomLayer, &VIA::BottomLayer ) ); - propMgr.AddProperty( new PROPERTY_ENUM( _HKI( "Via Type" ), - &VIA::SetViaType, &VIA::GetViaType ) ); + new PROPERTY_ENUM( _HKI( "Layer Top" ), + &PCB_VIA::SetLayer, &PCB_VIA::GetLayer ) ); + propMgr.AddProperty( new PROPERTY_ENUM( _HKI( "Layer Bottom" ), + &PCB_VIA::SetBottomLayer, &PCB_VIA::BottomLayer ) ); + propMgr.AddProperty( new PROPERTY_ENUM( _HKI( "Via Type" ), + &PCB_VIA::SetViaType, &PCB_VIA::GetViaType ) ); } } _TRACK_VIA_DESC; diff --git a/pcbnew/track.h b/pcbnew/pcb_track.h similarity index 94% rename from pcbnew/track.h rename to pcbnew/pcb_track.h index 6ae4dff66c..a5a8fd30f3 100644 --- a/pcbnew/track.h +++ b/pcbnew/pcb_track.h @@ -2,7 +2,7 @@ * This program source code file is part of KiCad, a free EDA CAD application. * * Copyright (C) 2004 Jean-Pierre Charras, jaen-pierre.charras@gipsa-lab.inpg.com - * Copyright (C) 1992-2020 KiCad Developers, see AUTHORS.txt for contributors. + * Copyright (C) 1992-2021 KiCad Developers, see AUTHORS.txt for contributors. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -23,9 +23,8 @@ */ /** - * @file class_track.h - * @brief A single base class (TRACK) represents both tracks and vias, with subclasses - * for curved tracks (ARC) and vias (VIA). All told there are three KICAD_Ts: + * @brief A single base class (PCB_TRACK) represents both tracks and vias, with subclasses + * for curved tracks (PCB_ARC) and vias (PCB_VIA). All told there are three KICAD_Ts: * PCB_TRACK_T, PCB_ARC_T, and PCB_VIA_T. * * For vias there is a further VIATYPE which indicates THROUGH, BLIND_BURIED, or @@ -41,8 +40,8 @@ #include -class TRACK; -class VIA; +class PCB_TRACK; +class PCB_VIA; class PAD; class MSG_PANEL_ITEM; class SHAPE_POLY_SET; @@ -73,7 +72,7 @@ enum class VIATYPE : int #define GEOMETRY_MIN_SIZE ( int )( 0.001 * IU_PER_MM ) -class TRACK : public BOARD_CONNECTED_ITEM +class PCB_TRACK : public BOARD_CONNECTED_ITEM { public: static inline bool ClassOf( const EDA_ITEM* aItem ) @@ -81,7 +80,7 @@ public: return aItem && PCB_TRACE_T == aItem->Type(); } - TRACK( BOARD_ITEM* aParent, KICAD_T idtype = PCB_TRACE_T ); + PCB_TRACK( BOARD_ITEM* aParent, KICAD_T idtype = PCB_TRACE_T ); // Do not create a copy constructor. The one generated by the compiler is adequate. @@ -177,11 +176,11 @@ public: bool HitTest( const wxPoint& aPosition, int aAccuracy = 0 ) const override; bool HitTest( const EDA_RECT& aRect, bool aContained, int aAccuracy = 0 ) const override; - bool ApproxCollinear( const TRACK& aTrack ); + bool ApproxCollinear( const PCB_TRACK& aTrack ); wxString GetClass() const override { - return wxT( "TRACK" ); + return wxT( "PCB_TRACK" ); } /** @@ -218,7 +217,7 @@ public: struct cmp_tracks { - bool operator()( const TRACK* aFirst, const TRACK* aSecond ) const; + bool operator()( const PCB_TRACK* aFirst, const PCB_TRACK* aSecond ) const; }; #if defined (DEBUG) @@ -244,12 +243,15 @@ protected: }; -class ARC : public TRACK +class PCB_ARC : public PCB_TRACK { public: - ARC( BOARD_ITEM* aParent ) : TRACK( aParent, PCB_ARC_T ){}; + PCB_ARC( BOARD_ITEM* aParent ) : + PCB_TRACK( aParent, PCB_ARC_T ) + { + }; - ARC( BOARD_ITEM* aParent, const SHAPE_ARC* aArc ); + PCB_ARC( BOARD_ITEM* aParent, const SHAPE_ARC* aArc ); static inline bool ClassOf( const EDA_ITEM *aItem ) { @@ -289,7 +291,7 @@ public: wxString GetClass() const override { - return wxT( "ARC" ); + return wxT( "PCB_ARC" ); } // @copydoc BOARD_ITEM::GetEffectiveShape @@ -319,10 +321,10 @@ private: }; -class VIA : public TRACK +class PCB_VIA : public PCB_TRACK { public: - VIA( BOARD_ITEM* aParent ); + PCB_VIA( BOARD_ITEM* aParent ); static inline bool ClassOf( const EDA_ITEM *aItem ) { @@ -397,7 +399,7 @@ public: wxString GetClass() const override { - return wxT( "VIA" ); + return wxT( "PCB_VIA" ); } wxString GetSelectMenuText( EDA_UNITS aUnits ) const override; @@ -454,7 +456,7 @@ public: /** * Function GetDrill - * returns the local drill setting for this VIA. If you want the calculated value, + * returns the local drill setting for this PCB_VIA. If you want the calculated value, * use GetDrillValue() instead. */ int GetDrill() const { return m_drill; } diff --git a/pcbnew/pcbnew_printout.cpp b/pcbnew/pcbnew_printout.cpp index a9e89bbdf7..7d287f08d7 100644 --- a/pcbnew/pcbnew_printout.cpp +++ b/pcbnew/pcbnew_printout.cpp @@ -309,7 +309,7 @@ VECTOR2D KIGFX::PCB_PRINT_PAINTER::getDrillSize( const PAD* aPad ) const } -int KIGFX::PCB_PRINT_PAINTER::getDrillSize( const VIA* aVia ) const +int KIGFX::PCB_PRINT_PAINTER::getDrillSize( const PCB_VIA* aVia ) const { // TODO should it depend on the via size? return m_drillMarkReal ? KIGFX::PCB_PAINTER::getDrillSize( aVia ) : m_drillMarkSize; diff --git a/pcbnew/pcbnew_printout.h b/pcbnew/pcbnew_printout.h index 04371623c1..b45761194e 100644 --- a/pcbnew/pcbnew_printout.h +++ b/pcbnew/pcbnew_printout.h @@ -105,7 +105,7 @@ protected: VECTOR2D getDrillSize( const PAD* aPad ) const override; - int getDrillSize( const VIA* aVia ) const override; + int getDrillSize( const PCB_VIA* aVia ) const override; ///< Flag deciding whether use the actual hole size or user-specified size for drill marks bool m_drillMarkReal; diff --git a/pcbnew/plot_board_layers.cpp b/pcbnew/plot_board_layers.cpp index dab2b7af2a..f14f084d00 100644 --- a/pcbnew/plot_board_layers.cpp +++ b/pcbnew/plot_board_layers.cpp @@ -39,7 +39,7 @@ #include #include #include -#include +#include #include #include #include @@ -426,9 +426,9 @@ void PlotStandardLayer( BOARD *aBoard, PLOTTER* aPlotter, LSET aLayerMask, aPlotter->StartBlock( NULL ); - for( const TRACK* track : aBoard->Tracks() ) + for( const PCB_TRACK* track : aBoard->Tracks() ) { - const VIA* via = dyn_cast( track ); + const PCB_VIA* via = dyn_cast( track ); if( !via ) continue; @@ -489,7 +489,7 @@ void PlotStandardLayer( BOARD *aBoard, PLOTTER* aPlotter, LSET aLayerMask, gbr_metadata.SetApertureAttrib( GBR_APERTURE_METADATA::GBR_APERTURE_ATTRIB_CONDUCTOR ); // Plot tracks (not vias) : - for( const TRACK* track : aBoard->Tracks() ) + for( const PCB_TRACK* track : aBoard->Tracks() ) { if( track->Type() == PCB_VIA_T ) continue; @@ -507,11 +507,11 @@ void PlotStandardLayer( BOARD *aBoard, PLOTTER* aPlotter, LSET aLayerMask, if( track->Type() == PCB_ARC_T ) { - const ARC* arc = static_cast( track ); + const PCB_ARC* arc = static_cast( track ); VECTOR2D center( arc->GetCenter() ); - int radius = arc->GetRadius(); - double start_angle = arc->GetArcAngleStart(); - double end_angle = start_angle + arc->GetAngle(); + int radius = arc->GetRadius(); + double start_angle = arc->GetArcAngleStart(); + double end_angle = start_angle + arc->GetAngle(); aPlotter->ThickArc( wxPoint( center.x, center.y ), -end_angle, -start_angle, radius, width, plotMode, &gbr_metadata ); @@ -696,9 +696,9 @@ void PlotLayerOutlines( BOARD* aBoard, PLOTTER* aPlotter, LSET aLayerMask, } // Plot vias holes - for( TRACK* track : aBoard->Tracks() ) + for( PCB_TRACK* track : aBoard->Tracks() ) { - const VIA* via = dyn_cast( track ); + const PCB_VIA* via = dyn_cast( track ); if( via && via->IsOnLayer( layer ) ) // via holes can be not through holes { @@ -811,9 +811,9 @@ void PlotSolderMaskLayer( BOARD *aBoard, PLOTTER* aPlotter, LSET aLayerMask, int via_clearance = aBoard->GetDesignSettings().m_SolderMaskMargin; int via_margin = via_clearance + inflate; - for( TRACK* track : aBoard->Tracks() ) + for( PCB_TRACK* track : aBoard->Tracks() ) { - const VIA* via = dyn_cast( track ); + const PCB_VIA* via = dyn_cast( track ); if( !via ) continue; diff --git a/pcbnew/plot_brditems_plotter.cpp b/pcbnew/plot_brditems_plotter.cpp index ae78a1f958..864325f58a 100644 --- a/pcbnew/plot_brditems_plotter.cpp +++ b/pcbnew/plot_brditems_plotter.cpp @@ -59,7 +59,7 @@ #include #include #include -#include +#include #include #include #include @@ -1016,9 +1016,9 @@ void BRDITEMS_PLOTTER::PlotDrillMarks() if( GetPlotMode() == FILLED ) m_plotter->SetColor( WHITE ); - for( TRACK* tracks : m_board->Tracks() ) + for( PCB_TRACK* tracks : m_board->Tracks() ) { - const VIA* via = dyn_cast( tracks ); + const PCB_VIA* via = dyn_cast( tracks ); if( via ) { diff --git a/pcbnew/plugins/altium/altium_pcb.cpp b/pcbnew/plugins/altium/altium_pcb.cpp index 2641d821f2..38cd1fd0bc 100644 --- a/pcbnew/plugins/altium/altium_pcb.cpp +++ b/pcbnew/plugins/altium/altium_pcb.cpp @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include #include @@ -1707,7 +1707,7 @@ void ALTIUM_PCB::ParseArcs6Data( const CFB::CompoundFileReader& aReader, -KiROUND( std::sin( startradiant ) * elem.radius ) ); SHAPE_ARC shapeArc( elem.center, elem.center + arcStartOffset, angle, elem.width ); - ARC* arc = new ARC( m_board, &shapeArc ); + PCB_ARC* arc = new PCB_ARC( m_board, &shapeArc ); m_board->Add( arc, ADD_MODE::APPEND ); arc->SetWidth( elem.width ); @@ -2166,7 +2166,7 @@ void ALTIUM_PCB::ParseVias6Data( const CFB::CompoundFileReader& aReader, { AVIA6 elem( reader ); - VIA* via = new VIA( m_board ); + PCB_VIA* via = new PCB_VIA( m_board ); m_board->Add( via, ADD_MODE::APPEND ); via->SetPosition( elem.position ); @@ -2286,7 +2286,7 @@ void ALTIUM_PCB::ParseTracks6Data( const CFB::CompoundFileReader& aReader, if( klayer >= F_Cu && klayer <= B_Cu ) { - TRACK* track = new TRACK( m_board ); + PCB_TRACK* track = new PCB_TRACK( m_board ); m_board->Add( track, ADD_MODE::APPEND ); track->SetStart( elem.start ); diff --git a/pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp b/pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp index b876a18d22..25b5d3c0e5 100644 --- a/pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp +++ b/pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp @@ -37,7 +37,7 @@ #include #include #include -#include +#include #include #include #include @@ -2032,8 +2032,9 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadCoppers() std::vector outlineSegments = getDrawSegmentsFromVertices( csCopper.Shape.Vertices ); - std::vector outlineTracks = makeTracksFromDrawsegments( outlineSegments, m_board, - getKiCadNet( csCopper.NetRef.NetID ), getKiCadLayer( csCopper.LayerID ), + std::vector outlineTracks = makeTracksFromDrawsegments( outlineSegments, + m_board, getKiCadNet( csCopper.NetRef.NetID ), + getKiCadLayer( csCopper.LayerID ), getKiCadLength( getCopperCode( csCopper.CopperCodeID ).CopperWidth ) ); //cleanup @@ -2045,8 +2046,9 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadCoppers() std::vector cutoutSeg = getDrawSegmentsFromVertices( cutout.Vertices ); - std::vector cutoutTracks = makeTracksFromDrawsegments( cutoutSeg, m_board, - getKiCadNet( csCopper.NetRef.NetID ), getKiCadLayer( csCopper.LayerID ), + std::vector cutoutTracks = makeTracksFromDrawsegments( cutoutSeg, + m_board, getKiCadNet( csCopper.NetRef.NetID ), + getKiCadLayer( csCopper.LayerID ), getKiCadLength( getCopperCode( csCopper.CopperCodeID ).CopperWidth ) ); //cleanup @@ -2362,8 +2364,8 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadNetTracks( const NET_ID& aCadstarNe prevEnd = v.Vertex.End; } - NETINFO_ITEM* net = getKiCadNet( aCadstarNetID ); - std::vector tracks = makeTracksFromDrawsegments( shapes, m_board, net ); + NETINFO_ITEM* net = getKiCadNet( aCadstarNetID ); + std::vector tracks = makeTracksFromDrawsegments( shapes, m_board, net ); //cleanup for( PCB_SHAPE* shape : shapes ) @@ -2374,7 +2376,7 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadNetTracks( const NET_ID& aCadstarNe int CADSTAR_PCB_ARCHIVE_LOADER::loadNetVia( const NET_ID& aCadstarNetID, const NET_PCB::VIA& aCadstarVia ) { - VIA* via = new VIA( m_board ); + PCB_VIA* via = new PCB_VIA( m_board ); m_board->Add( via, ADD_MODE::APPEND ); VIACODE csViaCode = getViaCode( aCadstarVia.ViaCodeID ); @@ -2958,33 +2960,34 @@ SHAPE_LINE_CHAIN CADSTAR_PCB_ARCHIVE_LOADER::getLineChainFromDrawsegments( const } -std::vector CADSTAR_PCB_ARCHIVE_LOADER::makeTracksFromDrawsegments( +std::vector CADSTAR_PCB_ARCHIVE_LOADER::makeTracksFromDrawsegments( const std::vector aDrawsegments, BOARD_ITEM_CONTAINER* aParentContainer, NETINFO_ITEM* aNet, PCB_LAYER_ID aLayerOverride, int aWidthOverride ) { - std::vector tracks; - TRACK* prevTrack = nullptr; - TRACK* track = nullptr; + std::vector tracks; + PCB_TRACK* prevTrack = nullptr; + PCB_TRACK* track = nullptr; - auto addTrack = [&]( TRACK* aTrack ) - { - // Ignore zero length tracks in the same way as the CADSTAR postprocessor - // does when generating gerbers. Note that CADSTAR reports these as "Route - // offset errors" when running a DRC within CADSTAR, so we shouldn't be - // getting this in general, however it is used to remove any synthetic - // points added to aDrawSegments by the caller of this function. - if( aTrack->GetLength() != 0 ) - { - tracks.push_back( aTrack ); - aParentContainer->Add( aTrack, ADD_MODE::APPEND ); - } - else - { - delete aTrack; - } - }; + auto addTrack = + [&]( PCB_TRACK* aTrack ) + { + // Ignore zero length tracks in the same way as the CADSTAR postprocessor does + // when generating gerbers. Note that CADSTAR reports these as "Route offset + // errors" when running a DRC within CADSTAR, so we shouldn't be getting this in + // general, however it is used to remove any synthetic points added to + // aDrawSegments by the caller of this function. + if( aTrack->GetLength() != 0 ) + { + tracks.push_back( aTrack ); + aParentContainer->Add( aTrack, ADD_MODE::APPEND ); + } + else + { + delete aTrack; + } + }; for( PCB_SHAPE* ds : aDrawsegments ) { @@ -2995,25 +2998,25 @@ std::vector CADSTAR_PCB_ARCHIVE_LOADER::makeTracksFromDrawsegments( { FP_SHAPE* em = (FP_SHAPE*) ds; SHAPE_ARC arc( em->GetStart0(), em->GetEnd0(), (double) em->GetAngle() / 10.0 ); - track = new ARC( aParentContainer, &arc ); + track = new PCB_ARC( aParentContainer, &arc ); } else { SHAPE_ARC arc( ds->GetCenter(), ds->GetArcStart(), (double) ds->GetAngle() / 10.0 ); - track = new ARC( aParentContainer, &arc ); + track = new PCB_ARC( aParentContainer, &arc ); } break; case PCB_SHAPE_TYPE::SEGMENT: if( ds->GetClass() == wxT( "MGRAPHIC" ) ) { FP_SHAPE* em = (FP_SHAPE*) ds; - track = new TRACK( aParentContainer ); + track = new PCB_TRACK( aParentContainer ); track->SetStart( em->GetStart0() ); track->SetEnd( em->GetEnd0() ); } else { - track = new TRACK( aParentContainer ); + track = new PCB_TRACK( aParentContainer ); track->SetStart( ds->GetStart() ); track->SetEnd( ds->GetEnd() ); } @@ -3067,7 +3070,7 @@ std::vector CADSTAR_PCB_ARCHIVE_LOADER::makeTracksFromDrawsegments( if( track->GetStart() != prevTrack->GetEnd() ) { int minWidth = std::min( track->GetWidth(), prevTrack->GetWidth() ); - TRACK* synthTrack = new TRACK( aParentContainer ); + PCB_TRACK* synthTrack = new PCB_TRACK( aParentContainer ); synthTrack->SetStart( prevTrack->GetEnd() ); synthTrack->SetEnd( track->GetStart() ); synthTrack->SetWidth( minWidth ); diff --git a/pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.h b/pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.h index 8875020a0d..42773b4cf1 100644 --- a/pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.h +++ b/pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.h @@ -363,11 +363,11 @@ private: * in the DrawSegments * @return */ - std::vector makeTracksFromDrawsegments( const std::vector aDrawsegments, - BOARD_ITEM_CONTAINER* aParentContainer, - NETINFO_ITEM* aNet = nullptr, - PCB_LAYER_ID aLayerOverride = UNDEFINED_LAYER, - int aWidthOverride = -1 ); + std::vector makeTracksFromDrawsegments( const std::vector aDrawsegments, + BOARD_ITEM_CONTAINER* aParentContainer, + NETINFO_ITEM* aNet = nullptr, + PCB_LAYER_ID aLayerOverride = UNDEFINED_LAYER, + int aWidthOverride = -1 ); /** * @brief Adds a CADSTAR Attribute to a KiCad footprint diff --git a/pcbnew/plugins/eagle/eagle_plugin.cpp b/pcbnew/plugins/eagle/eagle_plugin.cpp index 978bc70035..d6477f8525 100644 --- a/pcbnew/plugins/eagle/eagle_plugin.cpp +++ b/pcbnew/plugins/eagle/eagle_plugin.cpp @@ -72,7 +72,7 @@ Load() TODO's #include #include #include -#include +#include #include #include #include @@ -2366,7 +2366,7 @@ void EAGLE_PLUGIN::loadSignals( wxXmlNode* aSignals ) wxPoint end( KiROUND( radius * cos( end_angle + angle ) + center.x ), KiROUND( radius * sin( end_angle + angle ) + center.y ) ); - TRACK* t = new TRACK( m_board ); + PCB_TRACK* t = new PCB_TRACK( m_board ); t->SetPosition( start ); t->SetEnd( end ); @@ -2380,7 +2380,7 @@ void EAGLE_PLUGIN::loadSignals( wxXmlNode* aSignals ) angle -= delta_angle; } - TRACK* t = new TRACK( m_board ); + PCB_TRACK* t = new PCB_TRACK( m_board ); t->SetPosition( start ); t->SetEnd( wxPoint( kicad_x( w.x2 ), kicad_y( w.y2 ) ) ); @@ -2409,9 +2409,9 @@ void EAGLE_PLUGIN::loadSignals( wxXmlNode* aSignals ) if( IsCopperLayer( layer_front_most ) && IsCopperLayer( layer_back_most ) ) { - int kidiam; - int drillz = v.drill.ToPcbUnits(); - VIA* via = new VIA( m_board ); + int kidiam; + int drillz = v.drill.ToPcbUnits(); + PCB_VIA* via = new PCB_VIA( m_board ); m_board->Add( via ); via->SetLayerPair( layer_front_most, layer_back_most ); diff --git a/pcbnew/plugins/fabmaster/import_fabmaster.cpp b/pcbnew/plugins/fabmaster/import_fabmaster.cpp index 1b365e92d7..2eb1fdf6ec 100644 --- a/pcbnew/plugins/fabmaster/import_fabmaster.cpp +++ b/pcbnew/plugins/fabmaster/import_fabmaster.cpp @@ -48,7 +48,7 @@ #include #include #include -#include +#include #include #include #include @@ -2391,7 +2391,7 @@ bool FABMASTER::loadVias( BOARD* aBoard ) auto net_it = netinfo.find( via->net ); auto padstack = pads.find( via->padstack ); - VIA* new_via = new VIA( aBoard ); + PCB_VIA* new_via = new PCB_VIA( aBoard ); new_via->SetPosition( wxPoint( via->x, via->y ) ); @@ -2456,7 +2456,7 @@ bool FABMASTER::loadEtch( BOARD* aBoard, const std::unique_ptr { const GRAPHIC_LINE* src = static_cast( seg.get() ); - TRACK* trk = new TRACK( aBoard ); + PCB_TRACK* trk = new PCB_TRACK( aBoard ); trk->SetLayer( layer ); trk->SetStart( wxPoint( src->start_x, src->start_y ) ); @@ -2472,7 +2472,7 @@ bool FABMASTER::loadEtch( BOARD* aBoard, const std::unique_ptr { const GRAPHIC_ARC* src = static_cast( seg.get() ); - ARC* trk = new ARC( aBoard, &src->result ); + PCB_ARC* trk = new PCB_ARC( aBoard, &src->result ); trk->SetLayer( layer ); trk->SetWidth( src->width ); diff --git a/pcbnew/plugins/kicad/kicad_plugin.cpp b/pcbnew/plugins/kicad/kicad_plugin.cpp index 17ed5d4f49..b6680e20ac 100644 --- a/pcbnew/plugins/kicad/kicad_plugin.cpp +++ b/pcbnew/plugins/kicad/kicad_plugin.cpp @@ -46,7 +46,7 @@ #include #include #include -#include +#include #include #include #include @@ -444,7 +444,7 @@ void PCB_IO::Format( const BOARD_ITEM* aItem, int aNestLevel ) const case PCB_TRACE_T: case PCB_ARC_T: case PCB_VIA_T: - format( static_cast( aItem ), aNestLevel ); + format( static_cast( aItem ), aNestLevel ); break; case PCB_FP_ZONE_T: @@ -650,8 +650,8 @@ void PCB_IO::format( const BOARD* aBoard, int aNestLevel ) const aBoard->Footprints().end() ); std::set sorted_drawings( aBoard->Drawings().begin(), aBoard->Drawings().end() ); - std::set sorted_tracks( aBoard->Tracks().begin(), - aBoard->Tracks().end() ); + std::set sorted_tracks( aBoard->Tracks().begin(), + aBoard->Tracks().end() ); std::set sorted_zones( aBoard->Zones().begin(), aBoard->Zones().end() ); std::set sorted_groups( aBoard->Groups().begin(), @@ -675,7 +675,7 @@ void PCB_IO::format( const BOARD* aBoard, int aNestLevel ) const // Do not save PCB_MARKERs, they can be regenerated easily. // Save the tracks and vias. - for( TRACK* track : sorted_tracks ) + for( PCB_TRACK* track : sorted_tracks ) Format( track, aNestLevel ); if( sorted_tracks.size() ) @@ -1759,14 +1759,14 @@ void PCB_IO::format( const FP_TEXT* aText, int aNestLevel ) const } -void PCB_IO::format( const TRACK* aTrack, int aNestLevel ) const +void PCB_IO::format( const PCB_TRACK* aTrack, int aNestLevel ) const { if( aTrack->Type() == PCB_VIA_T ) { PCB_LAYER_ID layer1, layer2; - const VIA* via = static_cast( aTrack ); - BOARD* board = (BOARD*) via->GetParent(); + const PCB_VIA* via = static_cast( aTrack ); + BOARD* board = (BOARD*) via->GetParent(); wxCHECK_RET( board != nullptr, wxT( "Via " ) + via->GetSelectMenuText( EDA_UNITS::MILLIMETRES ) + wxT( " has no parent." ) ); @@ -1826,8 +1826,8 @@ void PCB_IO::format( const TRACK* aTrack, int aNestLevel ) const } else if( aTrack->Type() == PCB_ARC_T ) { - const ARC* arc = static_cast( aTrack ); - std::string locked = arc->IsLocked() ? " locked" : ""; + const PCB_ARC* arc = static_cast( aTrack ); + std::string locked = arc->IsLocked() ? " locked" : ""; m_out->Print( aNestLevel, "(arc%s (start %s) (mid %s) (end %s) (width %s)", locked.c_str(), diff --git a/pcbnew/plugins/kicad/kicad_plugin.h b/pcbnew/plugins/kicad/kicad_plugin.h index 63517dbce9..8095afbf56 100644 --- a/pcbnew/plugins/kicad/kicad_plugin.h +++ b/pcbnew/plugins/kicad/kicad_plugin.h @@ -42,7 +42,7 @@ class PCB_TARGET; class PAD; class FP_TEXT; class PCB_GROUP; -class TRACK; +class PCB_TRACK; class ZONE; class PCB_TEXT; @@ -261,7 +261,7 @@ private: void format( const FP_TEXT* aText, int aNestLevel = 0 ) const; - void format( const TRACK* aTrack, int aNestLevel = 0 ) const; + void format( const PCB_TRACK* aTrack, int aNestLevel = 0 ) const; void format( const ZONE* aZone, int aNestLevel = 0 ) const; diff --git a/pcbnew/plugins/kicad/pcb_parser.cpp b/pcbnew/plugins/kicad/pcb_parser.cpp index 20895ccd1e..80d73d45c4 100644 --- a/pcbnew/plugins/kicad/pcb_parser.cpp +++ b/pcbnew/plugins/kicad/pcb_parser.cpp @@ -45,7 +45,7 @@ #include #include #include -#include +#include #include #include #include @@ -679,7 +679,7 @@ BOARD* PCB_PARSER::parseBOARD_unchecked() break; case T_segment: - item = parseTRACK(); + item = parsePCB_TRACK(); m_board->Add( item, ADD_MODE::BULK_APPEND ); bulkAddedItems.push_back( item ); break; @@ -695,7 +695,7 @@ BOARD* PCB_PARSER::parseBOARD_unchecked() break; case T_via: - item = parseVIA(); + item = parsePCB_VIA(); m_board->Add( item, ADD_MODE::BULK_APPEND ); bulkAddedItems.push_back( item ); break; @@ -759,11 +759,11 @@ BOARD* PCB_PARSER::parseBOARD_unchecked() } }; - for( auto segm : m_board->Tracks() ) + for( PCB_TRACK* track : m_board->Tracks() ) { - if( segm->Type() == PCB_VIA_T ) + if( track->Type() == PCB_VIA_T ) { - VIA* via = (VIA*) segm; + PCB_VIA* via = static_cast( track ); PCB_LAYER_ID top_layer, bottom_layer; if( via->GetViaType() == VIATYPE::THROUGH ) @@ -788,7 +788,9 @@ BOARD* PCB_PARSER::parseBOARD_unchecked() } } else - visitItem( segm ); + { + visitItem( track ); + } } for( BOARD_ITEM* zone : m_board->Zones() ) @@ -4370,7 +4372,7 @@ void PCB_PARSER::parseGROUP( BOARD_ITEM* aParent ) } -ARC* PCB_PARSER::parseARC() +PCB_ARC* PCB_PARSER::parseARC() { wxCHECK_MSG( CurTok() == T_arc, NULL, wxT( "Cannot parse " ) + GetTokenString( CurTok() ) + wxT( " as ARC." ) ); @@ -4378,7 +4380,7 @@ ARC* PCB_PARSER::parseARC() wxPoint pt; T token; - std::unique_ptr arc = std::make_unique( m_board ); + std::unique_ptr arc = std::make_unique( m_board ); for( token = NextTok(); token != T_RIGHT; token = NextTok() ) { @@ -4454,15 +4456,15 @@ ARC* PCB_PARSER::parseARC() } -TRACK* PCB_PARSER::parseTRACK() +PCB_TRACK* PCB_PARSER::parsePCB_TRACK() { wxCHECK_MSG( CurTok() == T_segment, NULL, - wxT( "Cannot parse " ) + GetTokenString( CurTok() ) + wxT( " as TRACK." ) ); + wxT( "Cannot parse " ) + GetTokenString( CurTok() ) + wxT( " as PCB_TRACK." ) ); wxPoint pt; T token; - std::unique_ptr track = std::make_unique( m_board ); + std::unique_ptr track = std::make_unique( m_board ); for( token = NextTok(); token != T_RIGHT; token = NextTok() ) { @@ -4532,15 +4534,15 @@ TRACK* PCB_PARSER::parseTRACK() } -VIA* PCB_PARSER::parseVIA() +PCB_VIA* PCB_PARSER::parsePCB_VIA() { wxCHECK_MSG( CurTok() == T_via, NULL, - wxT( "Cannot parse " ) + GetTokenString( CurTok() ) + wxT( " as VIA." ) ); + wxT( "Cannot parse " ) + GetTokenString( CurTok() ) + wxT( " as PCB_VIA." ) ); wxPoint pt; T token; - std::unique_ptr via = std::make_unique( m_board ); + std::unique_ptr via = std::make_unique( m_board ); for( token = NextTok(); token != T_RIGHT; token = NextTok() ) { diff --git a/pcbnew/plugins/kicad/pcb_parser.h b/pcbnew/plugins/kicad/pcb_parser.h index 56bacf94d4..23938765ee 100644 --- a/pcbnew/plugins/kicad/pcb_parser.h +++ b/pcbnew/plugins/kicad/pcb_parser.h @@ -40,7 +40,7 @@ #include -class ARC; +class PCB_ARC; class BOARD; class BOARD_ITEM; class BOARD_ITEM_CONTAINER; @@ -52,11 +52,11 @@ class EDA_TEXT; class FP_SHAPE; class FP_TEXT; class PCB_TEXT; -class TRACK; +class PCB_TRACK; class FOOTPRINT; class PCB_GROUP; class PCB_TARGET; -class VIA; +class PCB_VIA; class ZONE; class FP_3DMODEL; struct LAYER; @@ -199,9 +199,9 @@ private: // Parse only the (option ...) inside a pad description bool parsePAD_option( PAD* aPad ); - ARC* parseARC(); - TRACK* parseTRACK(); - VIA* parseVIA(); + PCB_ARC* parseARC(); + PCB_TRACK* parsePCB_TRACK(); + PCB_VIA* parsePCB_VIA(); ZONE* parseZONE( BOARD_ITEM_CONTAINER* aParent ); PCB_TARGET* parsePCB_TARGET(); BOARD* parseBOARD(); diff --git a/pcbnew/plugins/legacy/legacy_plugin.cpp b/pcbnew/plugins/legacy/legacy_plugin.cpp index 6b9bbaec96..d0f07642b7 100644 --- a/pcbnew/plugins/legacy/legacy_plugin.cpp +++ b/pcbnew/plugins/legacy/legacy_plugin.cpp @@ -75,7 +75,7 @@ #include #include #include -#include +#include #include #include #include @@ -2265,13 +2265,13 @@ void LEGACY_PLUGIN::loadTrackList( int aStructType ) continue; } - TRACK* newTrack; + PCB_TRACK* newTrack; switch( makeType ) { default: - case PCB_TRACE_T: newTrack = new TRACK( m_board ); break; - case PCB_VIA_T: newTrack = new VIA( m_board ); break; + case PCB_TRACE_T: newTrack = new PCB_TRACK( m_board ); break; + case PCB_VIA_T: newTrack = new PCB_VIA( m_board ); break; } const_cast( newTrack->m_Uuid ) = KIID( uuid ); @@ -2282,7 +2282,7 @@ void LEGACY_PLUGIN::loadTrackList( int aStructType ) if( makeType == PCB_VIA_T ) // Ensure layers are OK when possible: { - VIA *via = static_cast( newTrack ); + PCB_VIA *via = static_cast( newTrack ); via->SetViaType( viatype ); if( drill < 0 ) diff --git a/pcbnew/plugins/legacy/legacy_plugin.h b/pcbnew/plugins/legacy/legacy_plugin.h index 0dc010a0b6..2a28b7b2e7 100644 --- a/pcbnew/plugins/legacy/legacy_plugin.h +++ b/pcbnew/plugins/legacy/legacy_plugin.h @@ -40,14 +40,12 @@ class PCB_TARGET; class FOOTPRINT; -class TRACK; class NETCLASS; class NETCLASSES; class ZONE; class PCB_DIMENSION_BASE; class NETINFO_ITEM; class FP_TEXT; -class TRACK; class PAD; struct LP_CACHE; diff --git a/pcbnew/plugins/pcad/pcb_line.cpp b/pcbnew/plugins/pcad/pcb_line.cpp index 05edd4f441..f0a6d2f20a 100644 --- a/pcbnew/plugins/pcad/pcb_line.cpp +++ b/pcbnew/plugins/pcad/pcb_line.cpp @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include @@ -138,7 +138,7 @@ void PCB_LINE::AddToBoard() { if( IsCopperLayer( m_KiCadLayer ) ) { - TRACK* track = new TRACK( m_board ); + PCB_TRACK* track = new PCB_TRACK( m_board ); m_board->Add( track ); track->SetPosition( wxPoint( m_positionX, m_positionY ) ); diff --git a/pcbnew/plugins/pcad/pcb_pad.cpp b/pcbnew/plugins/pcad/pcb_pad.cpp index 22d37b54e5..30f4a1d929 100644 --- a/pcbnew/plugins/pcad/pcb_pad.cpp +++ b/pcbnew/plugins/pcad/pcb_pad.cpp @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include @@ -346,7 +346,7 @@ void PCB_PAD::AddToBoard() if( IsCopperLayer( m_KiCadLayer ) ) { - VIA* via = new VIA( m_board ); + PCB_VIA* via = new PCB_VIA( m_board ); m_board->Add( via ); via->SetPosition( wxPoint( m_positionX, m_positionY ) ); diff --git a/pcbnew/python/scripting/pcbnew_action_plugins.cpp b/pcbnew/python/scripting/pcbnew_action_plugins.cpp index eb1466f918..2987d534f4 100644 --- a/pcbnew/python/scripting/pcbnew_action_plugins.cpp +++ b/pcbnew/python/scripting/pcbnew_action_plugins.cpp @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include #include @@ -216,7 +216,7 @@ void PCB_EDIT_FRAME::RunActionPlugin( ACTION_PLUGIN* aActionPlugin ) bool fromEmpty = false; // Append tracks: - for( TRACK* item : currentPcb->Tracks() ) + for( PCB_TRACK* item : currentPcb->Tracks() ) { ITEM_PICKER picker( nullptr, item, UNDO_REDO::CHANGED ); itemsList.PushItem( picker ); @@ -277,7 +277,7 @@ void PCB_EDIT_FRAME::RunActionPlugin( ACTION_PLUGIN* aActionPlugin ) std::set currItemList; // Append tracks: - for( TRACK* item : currentPcb->Tracks() ) + for( PCB_TRACK* item : currentPcb->Tracks() ) currItemList.insert( item ); // Append footprints: @@ -324,7 +324,7 @@ void PCB_EDIT_FRAME::RunActionPlugin( ACTION_PLUGIN* aActionPlugin ) } } - for( TRACK* item : currentPcb->Tracks() ) + for( PCB_TRACK* item : currentPcb->Tracks() ) { if( !oldBuffer->ContainsItem( item ) ) { diff --git a/pcbnew/python/swig/board_item.i b/pcbnew/python/swig/board_item.i index a8fa7c91c3..d9c5b8bed0 100644 --- a/pcbnew/python/swig/board_item.i +++ b/pcbnew/python/swig/board_item.i @@ -74,9 +74,9 @@ class MARKER_PCB; class BOARD; class FP_SHAPE; class PAD; -class TRACK; -class VIA; -class ARC; +class PCB_TRACK; +class PCB_VIA; +class PCB_ARC; class ZONE; class FP_ZONE; class PCB_TARGET; @@ -100,9 +100,9 @@ static PCB_MARKER* Cast_to_PCB_MARKER( BOARD_ITEM* ); static BOARD* Cast_to_BOARD( BOARD_ITEM* ); static FP_SHAPE* Cast_to_FP_SHAPE( BOARD_ITEM* ); static PAD* Cast_to_PAD( BOARD_ITEM* ); -static TRACK* Cast_to_TRACK( BOARD_ITEM* ); -static VIA* Cast_to_VIA( BOARD_ITEM* ); -static ARC* Cast_to_ARC( BOARD_ITEM* ); +static PCB_TRACK* Cast_to_PCB_TRACK( BOARD_ITEM* ); +static PCB_VIA* Cast_to_PCB_VIA( BOARD_ITEM* ); +static PCB_ARC* Cast_to_PCB_ARC( BOARD_ITEM* ); static ZONE* Cast_to_ZONE( BOARD_ITEM* ); static FP_ZONE* Cast_to_FP_ZONE( BOARD_ITEM* ); static PCB_TARGET* Cast_to_PCB_TARGET( BOARD_ITEM* ); @@ -126,9 +126,9 @@ static PCB_MARKER* Cast_to_PCB_MARKER( BOARD_ITEM* ); static BOARD* Cast_to_BOARD( BOARD_ITEM* ); static FP_SHAPE* Cast_to_FP_SHAPE( BOARD_ITEM* ); static PAD* Cast_to_PAD( BOARD_ITEM* ); -static TRACK* Cast_to_TRACK( BOARD_ITEM* ); -static VIA* Cast_to_VIA( BOARD_ITEM* ); -static ARC* Cast_to_ARC( BOARD_ITEM* ); +static PCB_TRACK* Cast_to_PCB_TRACK( BOARD_ITEM* ); +static PCB_VIA* Cast_to_PCB_VIA( BOARD_ITEM* ); +static PCB_ARC* Cast_to_PCB_ARC( BOARD_ITEM* ); static ZONE* Cast_to_ZONE( BOARD_ITEM* ); static FP_ZONE* Cast_to_FP_ZONE( BOARD_ITEM* ); static PCB_TARGET* Cast_to_PCB_TARGET( BOARD_ITEM* ); @@ -167,11 +167,11 @@ static PCB_TARGET* Cast_to_PCB_TARGET( BOARD_ITEM* ); elif ct=="MTEXT": return Cast_to_FP_TEXT(self) elif ct=="VIA": - return Cast_to_VIA(self) + return Cast_to_PCB_VIA(self) elif ct=="TRACK": - return Cast_to_TRACK(self) + return Cast_to_PCB_TRACK(self) elif ct=="ARC": - return Cast_to_ARC(self) + return Cast_to_PCB_ARC(self) elif ct=="PCB_TARGET": return Cast_to_PCB_TARGET(self) elif ct=="ZONE": @@ -217,9 +217,9 @@ static PCB_MARKER* Cast_to_PCB_MARKER( BOARD_ITEM* self ) { static BOARD* Cast_to_BOARD( BOARD_ITEM* self ) { return dynamic_cast(self); } static FP_SHAPE* Cast_to_FP_SHAPE( BOARD_ITEM* self ) { return dynamic_cast(self); } static PAD* Cast_to_PAD( BOARD_ITEM* self ) { return dynamic_cast(self); } -static TRACK* Cast_to_TRACK( BOARD_ITEM* self ) { return dynamic_cast(self); } -static VIA* Cast_to_VIA( BOARD_ITEM* self ) { return dynamic_cast(self); } -static ARC* Cast_to_ARC( BOARD_ITEM* self ) { return dynamic_cast(self); } +static PCB_TRACK* Cast_to_PCB_TRACK( BOARD_ITEM* self ) { return dynamic_cast(self); } +static PCB_VIA* Cast_to_PCB_VIA( BOARD_ITEM* self ) { return dynamic_cast(self); } +static PCB_ARC* Cast_to_PCB_ARC( BOARD_ITEM* self ) { return dynamic_cast(self); } static ZONE* Cast_to_ZONE( BOARD_ITEM* self ) { return dynamic_cast(self); } static FP_ZONE* Cast_to_FP_ZONE( BOARD_ITEM* self ) { return dynamic_cast(self); } static PCB_TARGET* Cast_to_PCB_TARGET( BOARD_ITEM* self ) { return dynamic_cast(self); } diff --git a/pcbnew/python/swig/track.i b/pcbnew/python/swig/track.i index 42d7c23e6b..b642d6e5a9 100644 --- a/pcbnew/python/swig/track.i +++ b/pcbnew/python/swig/track.i @@ -1,8 +1,8 @@ -%include track.h -%rename(Get) operator TRACK*; +%include pcb_track.h +%rename(Get) operator PCB_TRACK*; %{ -#include +#include %} diff --git a/pcbnew/ratsnest/ratsnest.cpp b/pcbnew/ratsnest/ratsnest.cpp index 7a1fe908ac..7c3367cfd9 100644 --- a/pcbnew/ratsnest/ratsnest.cpp +++ b/pcbnew/ratsnest/ratsnest.cpp @@ -26,7 +26,6 @@ #include #include #include -#include #include #include @@ -43,8 +42,6 @@ void PCB_BASE_FRAME::Compile_Ratsnest( bool aDisplayStatus ) GetBoard()->GetConnectivity()->RecalculateRatsnest(); if( aDisplayStatus ) - { SetMsgPanel( m_pcb ); - } } diff --git a/pcbnew/router/pns_kicad_iface.cpp b/pcbnew/router/pns_kicad_iface.cpp index 5dac8b4a55..e99d8508a6 100644 --- a/pcbnew/router/pns_kicad_iface.cpp +++ b/pcbnew/router/pns_kicad_iface.cpp @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include @@ -94,9 +94,9 @@ private: private: PNS::ROUTER_IFACE* m_routerIface; BOARD* m_board; - TRACK m_dummyTracks[2]; - ARC m_dummyArcs[2]; - VIA m_dummyVias[2]; + PCB_TRACK m_dummyTracks[2]; + PCB_ARC m_dummyArcs[2]; + PCB_VIA m_dummyVias[2]; int m_clearanceEpsilon; std::map, int> m_clearanceCache; @@ -136,7 +136,7 @@ int PNS_PCBNEW_RULE_RESOLVER::holeRadius( const PNS::ITEM* aItem ) const } else if( aItem->Kind() == PNS::ITEM::VIA_T ) { - const ::VIA* via = dynamic_cast( aItem->Parent() ); + const PCB_VIA* via = dynamic_cast( aItem->Parent() ); if( via ) return via->GetDrillValue() / 2; @@ -963,7 +963,7 @@ std::unique_ptr PNS_KICAD_IFACE_BASE::syncPad( PAD* aPad ) } -std::unique_ptr PNS_KICAD_IFACE_BASE::syncTrack( TRACK* aTrack ) +std::unique_ptr PNS_KICAD_IFACE_BASE::syncTrack( PCB_TRACK* aTrack ) { auto segment = std::make_unique( SEG( aTrack->GetStart(), aTrack->GetEnd() ), aTrack->GetNetCode() ); @@ -979,7 +979,7 @@ std::unique_ptr PNS_KICAD_IFACE_BASE::syncTrack( TRACK* aTrack ) } -std::unique_ptr PNS_KICAD_IFACE_BASE::syncArc( ARC* aArc ) +std::unique_ptr PNS_KICAD_IFACE_BASE::syncArc( PCB_ARC* aArc ) { auto arc = std::make_unique( SHAPE_ARC( aArc->GetStart(), aArc->GetMid(), aArc->GetEnd(), aArc->GetWidth() ), @@ -995,7 +995,7 @@ std::unique_ptr PNS_KICAD_IFACE_BASE::syncArc( ARC* aArc ) } -std::unique_ptr PNS_KICAD_IFACE_BASE::syncVia( VIA* aVia ) +std::unique_ptr PNS_KICAD_IFACE_BASE::syncVia( PCB_VIA* aVia ) { PCB_LAYER_ID top, bottom; aVia->LayerPair( &top, &bottom ); @@ -1220,7 +1220,7 @@ bool PNS_KICAD_IFACE::IsFlashedOnLayer( const PNS::ITEM* aItem, int aLayer ) con { case PCB_VIA_T: { - const VIA* via = static_cast( aItem->Parent() ); + const PCB_VIA* via = static_cast( aItem->Parent() ); return via->FlashLayer( static_cast( aLayer ) ); } @@ -1336,7 +1336,7 @@ void PNS_KICAD_IFACE_BASE::SyncWorld( PNS::NODE *aWorld ) } } - for( TRACK* t : m_board->Tracks() ) + for( PCB_TRACK* t : m_board->Tracks() ) { KICAD_T type = t->Type(); @@ -1347,12 +1347,12 @@ void PNS_KICAD_IFACE_BASE::SyncWorld( PNS::NODE *aWorld ) } else if( type == PCB_ARC_T ) { - if( auto arc = syncArc( static_cast( t ) ) ) + if( auto arc = syncArc( static_cast( t ) ) ) aWorld->Add( std::move( arc ) ); } else if( type == PCB_VIA_T ) { - if( auto via = syncVia( static_cast( t ) ) ) + if( auto via = syncVia( static_cast( t ) ) ) aWorld->Add( std::move( via ) ); } } @@ -1493,8 +1493,8 @@ void PNS_KICAD_IFACE::UpdateItem( PNS::ITEM* aItem ) { case PNS::ITEM::ARC_T: { - PNS::ARC* arc = static_cast( aItem ); - ARC* arc_board = static_cast( board_item ); + PNS::ARC* arc = static_cast( aItem ); + PCB_ARC* arc_board = static_cast( board_item ); const SHAPE_ARC* arc_shape = static_cast( arc->Shape() ); arc_board->SetStart( wxPoint( arc_shape->GetP0() ) ); arc_board->SetEnd( wxPoint( arc_shape->GetP1() ) ); @@ -1506,8 +1506,8 @@ void PNS_KICAD_IFACE::UpdateItem( PNS::ITEM* aItem ) case PNS::ITEM::SEGMENT_T: { PNS::SEGMENT* seg = static_cast( aItem ); - TRACK* track = static_cast( board_item ); - const SEG& s = seg->Seg(); + PCB_TRACK* track = static_cast( board_item ); + const SEG& s = seg->Seg(); track->SetStart( wxPoint( s.A.x, s.A.y ) ); track->SetEnd( wxPoint( s.B.x, s.B.y ) ); track->SetWidth( seg->Width() ); @@ -1516,7 +1516,7 @@ void PNS_KICAD_IFACE::UpdateItem( PNS::ITEM* aItem ) case PNS::ITEM::VIA_T: { - VIA* via_board = static_cast( board_item ); + PCB_VIA* via_board = static_cast( board_item ); PNS::VIA* via = static_cast( aItem ); via_board->SetPosition( wxPoint( via->Pos().x, via->Pos().y ) ); via_board->SetWidth( via->Diameter() ); @@ -1531,7 +1531,7 @@ void PNS_KICAD_IFACE::UpdateItem( PNS::ITEM* aItem ) case PNS::ITEM::SOLID_T: { - PAD* pad = static_cast( aItem->Parent() ); + PAD* pad = static_cast( aItem->Parent() ); VECTOR2I pos = static_cast( aItem )->Pos(); m_fpOffsets[ pad ].p_old = pad->GetPosition(); @@ -1559,8 +1559,8 @@ void PNS_KICAD_IFACE::AddItem( PNS::ITEM* aItem ) { case PNS::ITEM::ARC_T: { - auto arc = static_cast( aItem ); - ARC* new_arc = new ARC( m_board, static_cast( arc->Shape() ) ); + PNS::ARC* arc = static_cast( aItem ); + PCB_ARC* new_arc = new PCB_ARC( m_board, static_cast( arc->Shape() ) ); new_arc->SetWidth( arc->Width() ); new_arc->SetLayer( ToLAYER_ID( arc->Layers().Start() ) ); new_arc->SetNetCode( std::max( 0, arc->Net() ) ); @@ -1571,7 +1571,7 @@ void PNS_KICAD_IFACE::AddItem( PNS::ITEM* aItem ) case PNS::ITEM::SEGMENT_T: { PNS::SEGMENT* seg = static_cast( aItem ); - TRACK* track = new TRACK( m_board ); + PCB_TRACK* track = new PCB_TRACK( m_board ); const SEG& s = seg->Seg(); track->SetStart( wxPoint( s.A.x, s.A.y ) ); track->SetEnd( wxPoint( s.B.x, s.B.y ) ); @@ -1584,7 +1584,7 @@ void PNS_KICAD_IFACE::AddItem( PNS::ITEM* aItem ) case PNS::ITEM::VIA_T: { - VIA* via_board = new VIA( m_board ); + PCB_VIA* via_board = new PCB_VIA( m_board ); PNS::VIA* via = static_cast( aItem ); via_board->SetPosition( wxPoint( via->Pos().x, via->Pos().y ) ); via_board->SetWidth( via->Diameter() ); diff --git a/pcbnew/router/pns_kicad_iface.h b/pcbnew/router/pns_kicad_iface.h index 4a6c987752..8fc68dc6f4 100644 --- a/pcbnew/router/pns_kicad_iface.h +++ b/pcbnew/router/pns_kicad_iface.h @@ -90,9 +90,9 @@ protected: PNS::DEBUG_DECORATOR* m_debugDecorator; std::unique_ptr syncPad( PAD* aPad ); - std::unique_ptr syncTrack( TRACK* aTrack ); - std::unique_ptr syncArc( ARC* aArc ); - std::unique_ptr syncVia( VIA* aVia ); + std::unique_ptr syncTrack( PCB_TRACK* aTrack ); + std::unique_ptr syncArc( PCB_ARC* aArc ); + std::unique_ptr syncVia( PCB_VIA* aVia ); bool syncTextItem( PNS::NODE* aWorld, EDA_TEXT* aText, PCB_LAYER_ID aLayer ); bool syncGraphicalItem( PNS::NODE* aWorld, PCB_SHAPE* aItem ); bool syncZone( PNS::NODE* aWorld, ZONE* aZone, SHAPE_POLY_SET* aBoardOutline ); diff --git a/pcbnew/router/pns_sizes_settings.h b/pcbnew/router/pns_sizes_settings.h index 0ec6ad609f..5092d61865 100644 --- a/pcbnew/router/pns_sizes_settings.h +++ b/pcbnew/router/pns_sizes_settings.h @@ -25,7 +25,7 @@ #include #include -#include "track.h" // for VIATYPE_T +#include "pcb_track.h" // for VIATYPE_T class BOARD; class BOARD_DESIGN_SETTINGS; diff --git a/pcbnew/router/pns_via.h b/pcbnew/router/pns_via.h index 5f214ca011..669a1ae1c6 100644 --- a/pcbnew/router/pns_via.h +++ b/pcbnew/router/pns_via.h @@ -26,7 +26,7 @@ #include #include -#include "track.h" +#include "pcb_track.h" #include "pns_item.h" diff --git a/pcbnew/router/router_tool.cpp b/pcbnew/router/router_tool.cpp index 3be43b5f7b..c6bb5a3472 100644 --- a/pcbnew/router/router_tool.cpp +++ b/pcbnew/router/router_tool.cpp @@ -948,7 +948,7 @@ int ROUTER_TOOL::handleLayerSwitch( const TOOL_EVENT& aEvent, bool aForceVia ) if( bds.UseNetClassVia() || viaType == VIATYPE::MICROVIA ) { - class VIA dummyVia( board() ); + PCB_VIA dummyVia( board() ); dummyVia.SetViaType( viaType ); dummyVia.SetLayerPair( currentLayer, targetLayer ); @@ -1495,11 +1495,11 @@ void ROUTER_TOOL::NeighboringSegmentFilter( const VECTOR2I& aPt, GENERAL_COLLECT if( arcs > 0 || vias > 1 || traces > 2 || vias + traces < 1 ) return; - // Fetch first TRACK (via or trace) as our reference - TRACK* reference = nullptr; + // Fetch first PCB_TRACK (via or trace) as our reference + PCB_TRACK* reference = nullptr; for( int i = 0; !reference && i < aCollector.GetCount(); i++ ) - reference = dynamic_cast( aCollector[i] ); + reference = dynamic_cast( aCollector[i] ); int refNet = reference->GetNetCode(); @@ -1515,7 +1515,7 @@ void ROUTER_TOOL::NeighboringSegmentFilter( const VECTOR2I& aPt, GENERAL_COLLECT // the same net. for( int i = 0; i < aCollector.GetCount(); i++ ) { - TRACK* neighbor = dynamic_cast( aCollector[i] ); + PCB_TRACK* neighbor = dynamic_cast( aCollector[i] ); if( neighbor && neighbor != reference ) { diff --git a/pcbnew/router/router_tool.h b/pcbnew/router/router_tool.h index a9c31733de..e5ecfccb8b 100644 --- a/pcbnew/router/router_tool.h +++ b/pcbnew/router/router_tool.h @@ -51,7 +51,7 @@ public: void setTransitions() override; // A filter for narrowing a collection representing a simple corner - // or a non-fanout-via to a single TRACK item. + // or a non-fanout-via to a single PCB_TRACK item. static void NeighboringSegmentFilter( const VECTOR2I& aPt, GENERAL_COLLECTOR& aCollector ); private: diff --git a/pcbnew/specctra_import_export/specctra.cpp b/pcbnew/specctra_import_export/specctra.cpp index a380680e0e..c6e12ede04 100644 --- a/pcbnew/specctra_import_export/specctra.cpp +++ b/pcbnew/specctra_import_export/specctra.cpp @@ -53,7 +53,7 @@ #include #include -#include +#include #include "specctra.h" #include diff --git a/pcbnew/specctra_import_export/specctra.h b/pcbnew/specctra_import_export/specctra.h index 526e6241f5..1b8496461a 100644 --- a/pcbnew/specctra_import_export/specctra.h +++ b/pcbnew/specctra_import_export/specctra.h @@ -38,8 +38,8 @@ // all outside the DSN namespace: class BOARD; -class TRACK; -class VIA; +class PCB_TRACK; +class PCB_VIA; class NETCLASS; class FOOTPRINT; class SHAPE_POLY_SET; @@ -3820,7 +3820,7 @@ class SPECCTRA_DB : public SPECCTRA_LEXER * @return PADSTACK* - The padstack, which is on the heap only, user must save * or delete it. */ - PADSTACK* makeVia( const ::VIA* aVia ); + PADSTACK* makeVia( const ::PCB_VIA* aVia ); /** * Function deleteNETs @@ -3848,14 +3848,14 @@ class SPECCTRA_DB : public SPECCTRA_LEXER * Function makeTRACK * creates a TRACK form the PATH and BOARD info. */ - TRACK* makeTRACK( PATH* aPath, int aPointIndex, int aNetcode ); + PCB_TRACK* makeTRACK( PATH* aPath, int aPointIndex, int aNetcode ); /** * Function makeVIA * instantiates a KiCad VIA on the heap and initializes it with internal * values consistent with the given PADSTACK, POINT, and netcode. */ - ::VIA* makeVIA( PADSTACK* aPadstack, const POINT& aPoint, int aNetCode, int aViaDrillDefault ); + PCB_VIA* makeVIA( PADSTACK* aPadstack, const POINT& aPoint, int aNetCode, int aViaDrillDefault ); //--------------------------------------------------------- diff --git a/pcbnew/specctra_import_export/specctra_export.cpp b/pcbnew/specctra_import_export/specctra_export.cpp index 37d5ec5435..1779114271 100644 --- a/pcbnew/specctra_import_export/specctra_export.cpp +++ b/pcbnew/specctra_import_export/specctra_export.cpp @@ -46,7 +46,7 @@ #include #include #include -#include +#include #include #include #include @@ -930,7 +930,7 @@ PADSTACK* SPECCTRA_DB::makeVia( int aCopperDiameter, int aDrillDiameter, } -PADSTACK* SPECCTRA_DB::makeVia( const ::VIA* aVia ) +PADSTACK* SPECCTRA_DB::makeVia( const PCB_VIA* aVia ) { PCB_LAYER_ID topLayerNum; PCB_LAYER_ID botLayerNum; @@ -1580,9 +1580,8 @@ void SPECCTRA_DB::FromBOARD( BOARD* aBoard ) for( int i=0; iGetNetCode(); + PCB_TRACK* track = static_cast( items[i] ); + int netcode = track->GetNetCode(); if( netcode == 0 ) continue; @@ -1636,10 +1635,10 @@ void SPECCTRA_DB::FromBOARD( BOARD* aBoard ) for( int i = 0; i( items[i] ); wxASSERT( via->Type() == PCB_VIA_T ); - int netcode = via->GetNetCode(); + int netcode = via->GetNetCode(); if( netcode == 0 ) continue; diff --git a/pcbnew/specctra_import_export/specctra_import.cpp b/pcbnew/specctra_import_export/specctra_import.cpp index 17b21e8fce..8726cd66af 100644 --- a/pcbnew/specctra_import_export/specctra_import.cpp +++ b/pcbnew/specctra_import_export/specctra_import.cpp @@ -40,7 +40,7 @@ #include #include #include -#include +#include #include #include #include "specctra.h" @@ -157,7 +157,7 @@ static wxPoint mapPt( const POINT& aPoint, UNIT_RES* aResolution ) } -TRACK* SPECCTRA_DB::makeTRACK( PATH* aPath, int aPointIndex, int aNetcode ) +PCB_TRACK* SPECCTRA_DB::makeTRACK( PATH* aPath, int aPointIndex, int aNetcode ) { int layerNdx = findLayerName( aPath->layer_id ); @@ -168,7 +168,7 @@ TRACK* SPECCTRA_DB::makeTRACK( PATH* aPath, int aPointIndex, int aNetcode ) wxString::Format( _( "Session file uses invalid layer id \"%s\"" ), layerName ) ); } - TRACK* track = new TRACK( m_sessionBoard ); + PCB_TRACK* track = new PCB_TRACK( m_sessionBoard ); track->SetStart( mapPt( aPath->points[aPointIndex+0], m_routeResolution ) ); track->SetEnd( mapPt( aPath->points[aPointIndex+1], m_routeResolution ) ); @@ -180,15 +180,14 @@ TRACK* SPECCTRA_DB::makeTRACK( PATH* aPath, int aPointIndex, int aNetcode ) } -::VIA* SPECCTRA_DB::makeVIA( PADSTACK* aPadstack, const POINT& aPoint, - int aNetCode, int aViaDrillDefault ) +PCB_VIA* SPECCTRA_DB::makeVIA( PADSTACK* aPadstack, const POINT& aPoint, int aNetCode, + int aViaDrillDefault ) { - ::VIA* via = 0; - SHAPE* shape; - - int shapeCount = aPadstack->Length(); - int drill_diam_iu = -1; - int copperLayerCount = m_sessionBoard->GetCopperLayerCount(); + PCB_VIA* via = 0; + SHAPE* shape; + int shapeCount = aPadstack->Length(); + int drill_diam_iu = -1; + int copperLayerCount = m_sessionBoard->GetCopperLayerCount(); // The drill diameter is encoded in the padstack name if Pcbnew did the DSN export. @@ -229,7 +228,7 @@ TRACK* SPECCTRA_DB::makeTRACK( PATH* aPath, int aPointIndex, int aNetcode ) CIRCLE* circle = (CIRCLE*) shape->shape; int viaDiam = scale( circle->diameter, m_routeResolution ); - via = new ::VIA( m_sessionBoard ); + via = new PCB_VIA( m_sessionBoard ); via->SetPosition( mapPt( aPoint, m_routeResolution ) ); via->SetDrill( drill_diam_iu ); via->SetViaType( VIATYPE::THROUGH ); @@ -247,7 +246,7 @@ TRACK* SPECCTRA_DB::makeTRACK( PATH* aPath, int aPointIndex, int aNetcode ) CIRCLE* circle = (CIRCLE*) shape->shape; int viaDiam = scale( circle->diameter, m_routeResolution ); - via = new ::VIA( m_sessionBoard ); + via = new PCB_VIA( m_sessionBoard ); via->SetPosition( mapPt( aPoint, m_routeResolution ) ); via->SetDrill( drill_diam_iu ); via->SetViaType( VIATYPE::THROUGH ); @@ -289,7 +288,7 @@ TRACK* SPECCTRA_DB::makeTRACK( PATH* aPath, int aPointIndex, int aNetcode ) viaDiam = scale( circle->diameter, m_routeResolution ); } - via = new ::VIA( m_sessionBoard ); + via = new PCB_VIA( m_sessionBoard ); via->SetPosition( mapPt( aPoint, m_routeResolution ) ); via->SetDrill( drill_diam_iu ); @@ -450,9 +449,10 @@ void SPECCTRA_DB::FromSESSION( BOARD* aBoard ) else { PATH* path = (PATH*) wire->shape; + for( unsigned pt=0; ptpoints.size()-1; ++pt ) { - TRACK* track = makeTRACK( path, pt, netoutCode ); + PCB_TRACK* track = makeTRACK( path, pt, netoutCode ); aBoard->Add( track ); } } @@ -506,7 +506,8 @@ void SPECCTRA_DB::FromSESSION( BOARD* aBoard ) for( unsigned v=0; vvertexes.size(); ++v ) { - ::VIA* via = makeVIA( padstack, wire_via->vertexes[v], netCode, via_drill_default ); + PCB_VIA* via = makeVIA( padstack, wire_via->vertexes[v], netCode, + via_drill_default ); aBoard->Add( via ); } } diff --git a/pcbnew/tools/board_editor_control.cpp b/pcbnew/tools/board_editor_control.cpp index 273117d403..d7a48cb31b 100644 --- a/pcbnew/tools/board_editor_control.cpp +++ b/pcbnew/tools/board_editor_control.cpp @@ -38,7 +38,7 @@ #include #include #include -#include +#include #include #include #include @@ -551,7 +551,7 @@ int BOARD_EDITOR_CONTROL::RepairBoard( const TOOL_EVENT& aEvent ) processItem( pad ); } - for( TRACK* track : board()->Tracks() ) + for( PCB_TRACK* track : board()->Tracks() ) processItem( track ); // From here out I don't think order matters much. @@ -688,7 +688,7 @@ int BOARD_EDITOR_CONTROL::TrackWidthInc( const TOOL_EVENT& aEvent ) { if( item->Type() == PCB_TRACE_T ) { - TRACK* track = (TRACK*) item; + PCB_TRACK* track = static_cast( item ); for( int candidate : designSettings.m_TrackWidthList ) { @@ -754,7 +754,7 @@ int BOARD_EDITOR_CONTROL::TrackWidthDec( const TOOL_EVENT& aEvent ) { if( item->Type() == PCB_TRACE_T ) { - TRACK* track = (TRACK*) item; + PCB_TRACK* track = static_cast( item ); for( int i = designSettings.m_TrackWidthList.size() - 1; i >= 0; --i ) { @@ -822,7 +822,7 @@ int BOARD_EDITOR_CONTROL::ViaSizeInc( const TOOL_EVENT& aEvent ) { if( item->Type() == PCB_VIA_T ) { - VIA* via = (VIA*) item; + PCB_VIA* via = static_cast( item ); for( VIA_DIMENSION candidate : designSettings.m_ViasDimensionsList ) { @@ -871,7 +871,7 @@ int BOARD_EDITOR_CONTROL::ViaSizeDec( const TOOL_EVENT& aEvent ) { if( item->Type() == PCB_VIA_T ) { - VIA* via = (VIA*) item; + PCB_VIA* via = static_cast( item ); for( int i = designSettings.m_ViasDimensionsList.size() - 1; i >= 0; --i ) { diff --git a/pcbnew/tools/convert_tool.cpp b/pcbnew/tools/convert_tool.cpp index 8684d153b8..7468afba9f 100644 --- a/pcbnew/tools/convert_tool.cpp +++ b/pcbnew/tools/convert_tool.cpp @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include #include #include @@ -571,7 +571,7 @@ int CONVERT_TOOL::PolyToLines( const TOOL_EVENT& aEvent ) // Creating tracks for( SEG& seg : segs ) { - TRACK* track = new TRACK( parent ); + PCB_TRACK* track = new PCB_TRACK( parent ); track->SetLayer( layer ); track->SetStart( wxPoint( seg.A ) ); @@ -660,8 +660,8 @@ int CONVERT_TOOL::SegmentToArc( const TOOL_EVENT& aEvent ) else { wxASSERT( source->Type() == PCB_TRACE_T ); - TRACK* line = static_cast( source ); - ARC* arc = new ARC( parent ); + PCB_TRACK* line = static_cast( source ); + PCB_ARC* arc = new PCB_ARC( parent ); arc->SetLayer( layer ); arc->SetWidth( line->GetWidth() ); @@ -696,7 +696,7 @@ OPT CONVERT_TOOL::getStartEndPoints( EDA_ITEM* aItem, int* aWidth ) case PCB_TRACE_T: { - TRACK* line = static_cast( aItem ); + PCB_TRACK* line = static_cast( aItem ); if( aWidth ) *aWidth = line->GetWidth(); @@ -707,7 +707,7 @@ OPT CONVERT_TOOL::getStartEndPoints( EDA_ITEM* aItem, int* aWidth ) case PCB_ARC_T: { - ARC* arc = static_cast( aItem ); + PCB_ARC* arc = static_cast( aItem ); if( aWidth ) *aWidth = arc->GetWidth(); diff --git a/pcbnew/tools/drawing_tool.cpp b/pcbnew/tools/drawing_tool.cpp index 31c29852d2..be13913d66 100644 --- a/pcbnew/tools/drawing_tool.cpp +++ b/pcbnew/tools/drawing_tool.cpp @@ -2265,7 +2265,7 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent ) { } - TRACK* findTrack( VIA* aVia ) + PCB_TRACK* findTrack( PCB_VIA* aVia ) { const LSET lset = aVia->GetLayerSet(); wxPoint position = aVia->GetPosition(); @@ -2273,7 +2273,7 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent ) std::vector items; auto view = m_frame->GetCanvas()->GetView(); - std::vector possible_tracks; + std::vector possible_tracks; view->Query( bbox, items ); @@ -2284,7 +2284,7 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent ) if( !(item->GetLayerSet() & lset ).any() ) continue; - if( TRACK* track = dyn_cast( item ) ) + if( PCB_TRACK* track = dyn_cast( item ) ) { if( TestSegmentHit( position, track->GetStart(), track->GetEnd(), ( track->GetWidth() + aVia->GetWidth() ) / 2 ) ) @@ -2292,10 +2292,10 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent ) } } - TRACK* return_track = nullptr; + PCB_TRACK* return_track = nullptr; int min_d = std::numeric_limits::max(); - for( TRACK* track : possible_tracks ) + for( PCB_TRACK* track : possible_tracks ) { SEG test( track->GetStart(), track->GetEnd() ); int dist = ( test.NearestPoint( position ) - position ).EuclideanNorm(); @@ -2310,7 +2310,7 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent ) return return_track; } - bool hasDRCViolation( VIA* aVia, BOARD_ITEM* aOther ) + bool hasDRCViolation( PCB_VIA* aVia, BOARD_ITEM* aOther ) { // It would really be better to know what particular nets a nettie should allow, // but for now it is what it is. @@ -2347,8 +2347,8 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent ) if( aOther->Type() == PCB_VIA_T ) { - VIA* via = static_cast( aOther ); - wxPoint pos = via->GetPosition(); + PCB_VIA* via = static_cast( aOther ); + wxPoint pos = via->GetPosition(); holeShape.reset( new SHAPE_SEGMENT( pos, pos, via->GetDrill() ) ); } @@ -2378,7 +2378,7 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent ) return false; } - bool checkDRCViolation( VIA* aVia ) + bool checkDRCViolation( PCB_VIA* aVia ) { std::vector items; std::set checkedItems; @@ -2415,7 +2415,7 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent ) return false; } - PAD* findPad( VIA* aVia ) + PAD* findPad( PCB_VIA* aVia ) { const wxPoint position = aVia->GetPosition(); const LSET lset = aVia->GetLayerSet(); @@ -2433,7 +2433,7 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent ) return nullptr; } - int findStitchedZoneNet( VIA* aVia ) + int findStitchedZoneNet( PCB_VIA* aVia ) { const wxPoint position = aVia->GetPosition(); const LSET lset = aVia->GetLayerSet(); @@ -2481,9 +2481,9 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent ) // this situation. m_gridHelper.SetSnap( !( m_modifiers & MD_SHIFT ) ); - auto via = static_cast( aItem ); - wxPoint position = via->GetPosition(); - TRACK* track = findTrack( via ); + PCB_VIA* via = static_cast( aItem ); + wxPoint position = via->GetPosition(); + PCB_TRACK* track = findTrack( via ); if( track ) { @@ -2496,9 +2496,9 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent ) bool PlaceItem( BOARD_ITEM* aItem, BOARD_COMMIT& aCommit ) override { - VIA* via = static_cast( aItem ); - wxPoint viaPos = via->GetPosition(); - TRACK* track = findTrack( via ); + PCB_VIA* via = static_cast( aItem ); + wxPoint viaPos = via->GetPosition(); + PCB_TRACK* track = findTrack( via ); PAD * pad = findPad( via ); if( track ) @@ -2524,7 +2524,7 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent ) { aCommit.Modify( track ); - TRACK* newTrack = dynamic_cast( track->Clone() ); + PCB_TRACK* newTrack = dynamic_cast( track->Clone() ); const_cast( newTrack->m_Uuid ) = KIID(); track->SetEnd( viaPos ); @@ -2544,15 +2544,15 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent ) std::unique_ptr CreateItem() override { - auto& ds = m_board->GetDesignSettings(); - VIA* via = new VIA( m_board ); + BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings(); + PCB_VIA* via = new PCB_VIA( m_board ); via->SetNetCode( 0 ); - via->SetViaType( ds.m_CurrentViaType ); + via->SetViaType( bds.m_CurrentViaType ); // for microvias, the size and hole will be changed later. - via->SetWidth( ds.GetCurrentViaSize() ); - via->SetDrill( ds.GetCurrentViaDrill() ); + via->SetWidth( bds.GetCurrentViaSize() ); + via->SetDrill( bds.GetCurrentViaDrill() ); // Usual via is from copper to component. // layer pair is B_Cu and F_Cu. diff --git a/pcbnew/tools/drc_tool.h b/pcbnew/tools/drc_tool.h index a23932ed6c..b5793779f3 100644 --- a/pcbnew/tools/drc_tool.h +++ b/pcbnew/tools/drc_tool.h @@ -26,7 +26,6 @@ #include #include -#include #include #include #include diff --git a/pcbnew/tools/edit_tool.cpp b/pcbnew/tools/edit_tool.cpp index 28e875057f..428eb93aa8 100644 --- a/pcbnew/tools/edit_tool.cpp +++ b/pcbnew/tools/edit_tool.cpp @@ -127,7 +127,7 @@ bool EDIT_TOOL::Init() for( EDA_ITEM* item : aSel ) { - if( !dynamic_cast( item ) ) + if( !dynamic_cast( item ) ) return false; } @@ -335,8 +335,8 @@ int EDIT_TOOL::DragArcTrack( const TOOL_EVENT& aEvent ) Activate(); - ARC* theArc = static_cast( selection.Front() ); - double arcAngleDegrees = std::abs( theArc->GetAngle() ) / 10.0; + PCB_ARC* theArc = static_cast( selection.Front() ); + double arcAngleDegrees = std::abs( theArc->GetAngle() ) / 10.0; if( arcAngleDegrees + ADVANCED_CFG::GetCfg().m_MaxTangentAngleDeviation >= 180.0 ) { @@ -366,7 +366,7 @@ int EDIT_TOOL::DragArcTrack( const TOOL_EVENT& aEvent ) KICAD_T track_types[] = { PCB_PAD_T, PCB_VIA_T, PCB_TRACE_T, PCB_ARC_T, EOT }; auto getUniqueTrackAtAnchorCollinear = - [&]( const VECTOR2I& aAnchor, const SEG& aCollinearSeg ) -> TRACK* + [&]( const VECTOR2I& aAnchor, const SEG& aCollinearSeg ) -> PCB_TRACK* { auto conn = board()->GetConnectivity(); @@ -385,11 +385,11 @@ int EDIT_TOOL::DragArcTrack( const TOOL_EVENT& aEvent ) break; } - TRACK* retval = nullptr; + PCB_TRACK* retval = nullptr; if( itemsOnAnchor.size() == 1 && itemsOnAnchor.front()->Type() == PCB_TRACE_T ) { - retval = static_cast( itemsOnAnchor.front() ); + retval = static_cast( itemsOnAnchor.front() ); SEG trackSeg( retval->GetStart(), retval->GetEnd() ); // Allow deviations in colinearity as defined in ADVANCED_CFG @@ -402,7 +402,7 @@ int EDIT_TOOL::DragArcTrack( const TOOL_EVENT& aEvent ) if( !retval ) { - retval = new TRACK( theArc->GetParent() ); + retval = new PCB_TRACK( theArc->GetParent() ); retval->SetStart( (wxPoint) aAnchor ); retval->SetEnd( (wxPoint) aAnchor ); retval->SetNet( theArc->GetNet() ); @@ -415,13 +415,13 @@ int EDIT_TOOL::DragArcTrack( const TOOL_EVENT& aEvent ) return retval; }; - TRACK* trackOnStart = getUniqueTrackAtAnchorCollinear( theArc->GetStart(), tanStart); - TRACK* trackOnEnd = getUniqueTrackAtAnchorCollinear( theArc->GetEnd(), tanEnd ); + PCB_TRACK* trackOnStart = getUniqueTrackAtAnchorCollinear( theArc->GetStart(), tanStart); + PCB_TRACK* trackOnEnd = getUniqueTrackAtAnchorCollinear( theArc->GetEnd(), tanEnd ); // Make copies of items to be edited - ARC* theArcCopy = new ARC( *theArc ); - TRACK* trackOnStartCopy = new TRACK( *trackOnStart ); - TRACK* trackOnEndCopy = new TRACK( *trackOnEnd ); + PCB_ARC* theArcCopy = new PCB_ARC( *theArc ); + PCB_TRACK* trackOnStartCopy = new PCB_TRACK( *trackOnStart ); + PCB_TRACK* trackOnEndCopy = new PCB_TRACK( *trackOnEnd ); if( trackOnStart->GetLength() != 0 ) { @@ -439,7 +439,7 @@ int EDIT_TOOL::DragArcTrack( const TOOL_EVENT& aEvent ) tanIntersect = tanStart.IntersectLines( tanEnd ).get(); auto isTrackStartClosestToArcStart = - [&]( TRACK* aPointA ) -> bool + [&]( PCB_TRACK* aPointA ) -> bool { return GetLineLength( aPointA->GetStart(), theArc->GetStart() ) < GetLineLength( aPointA->GetEnd(), theArc->GetStart() ); @@ -595,7 +595,7 @@ int EDIT_TOOL::DragArcTrack( const TOOL_EVENT& aEvent ) // Ensure we only do one commit operation on each object auto processTrack = - [&]( TRACK* aTrack, TRACK* aTrackCopy, int aMaxLengthIU ) -> bool + [&]( PCB_TRACK* aTrack, PCB_TRACK* aTrackCopy, int aMaxLengthIU ) -> bool { if( aTrack->IsNew() ) { @@ -1101,7 +1101,7 @@ int EDIT_TOOL::ChangeTrackWidth( const TOOL_EVENT& aEvent ) { BOARD_ITEM* item = aCollector[ i ]; - if( !dynamic_cast( item ) ) + if( !dynamic_cast( item ) ) aCollector.Remove( item ); } }, @@ -1111,7 +1111,7 @@ int EDIT_TOOL::ChangeTrackWidth( const TOOL_EVENT& aEvent ) { if( item->Type() == PCB_VIA_T ) { - VIA* via = static_cast( item ); + PCB_VIA* via = static_cast( item ); m_commit->Modify( via ); @@ -1136,7 +1136,7 @@ int EDIT_TOOL::ChangeTrackWidth( const TOOL_EVENT& aEvent ) } else if( item->Type() == PCB_TRACE_T || item->Type() == PCB_ARC_T ) { - TRACK* track = dynamic_cast( item ); + PCB_TRACK* track = dynamic_cast( item ); wxCHECK( track, 0 ); @@ -1174,7 +1174,7 @@ int EDIT_TOOL::FilletTracks( const TOOL_EVENT& aEvent ) { BOARD_ITEM* item = aCollector[i]; - if( !dynamic_cast( item ) ) + if( !dynamic_cast( item ) ) aCollector.Remove( item ); } }, @@ -1204,22 +1204,22 @@ int EDIT_TOOL::FilletTracks( const TOOL_EVENT& aEvent ) struct FILLET_OP { - TRACK* t1; - TRACK* t2; - //If true, start point of track is modified after ARC is added, otherwise the end point: - bool t1Start = true; - bool t2Start = true; + PCB_TRACK* t1; + PCB_TRACK* t2; + // Start point of track is modified after PCB_ARC is added, otherwise the end point: + bool t1Start = true; + bool t2Start = true; }; std::vector filletOperations; KICAD_T track_types[] = { PCB_PAD_T, PCB_VIA_T, PCB_TRACE_T, PCB_ARC_T, EOT }; bool operationPerformedOnAtLeastOne = false; bool didOneAttemptFail = false; - std::set processedTracks; + std::set processedTracks; for( auto it = selection.begin(); it != selection.end(); it++ ) { - TRACK* track = dyn_cast( *it ); + PCB_TRACK* track = dyn_cast( *it ); if( !track || track->Type() != PCB_TRACE_T || track->IsLocked() || track->GetLength() == 0 ) @@ -1239,7 +1239,7 @@ int EDIT_TOOL::FilletTracks( const TOOL_EVENT& aEvent ) && selection.Contains( itemsOnAnchor.at( 0 ) ) && itemsOnAnchor.at( 0 )->Type() == PCB_TRACE_T ) { - TRACK* trackOther = dyn_cast( itemsOnAnchor.at( 0 ) ); + PCB_TRACK* trackOther = dyn_cast( itemsOnAnchor.at( 0 ) ); // Make sure we don't fillet the same pair of tracks twice if( processedTracks.find( trackOther ) == processedTracks.end() ) @@ -1273,8 +1273,8 @@ int EDIT_TOOL::FilletTracks( const TOOL_EVENT& aEvent ) for( FILLET_OP filletOp : filletOperations ) { - TRACK* track1 = filletOp.t1; - TRACK* track2 = filletOp.t2; + PCB_TRACK* track1 = filletOp.t1; + PCB_TRACK* track2 = filletOp.t2; bool trackOnStart = track1->IsPointOnEnds( track2->GetStart() ); bool trackOnEnd = track1->IsPointOnEnds( track2->GetEnd() ); @@ -1325,7 +1325,7 @@ int EDIT_TOOL::FilletTracks( const TOOL_EVENT& aEvent ) continue; } - ARC* tArc = new ARC( frame()->GetBoard(), &sArc ); + PCB_ARC* tArc = new PCB_ARC( frame()->GetBoard(), &sArc ); tArc->SetLayer( track1->GetLayer() ); tArc->SetWidth( track1->GetWidth() ); tArc->SetNet( track1->GetNet() ); diff --git a/pcbnew/tools/global_edit_tool.cpp b/pcbnew/tools/global_edit_tool.cpp index 3078eb5e70..dde81fd7b2 100644 --- a/pcbnew/tools/global_edit_tool.cpp +++ b/pcbnew/tools/global_edit_tool.cpp @@ -22,7 +22,7 @@ */ #include -#include +#include #include #include #include @@ -135,11 +135,11 @@ int GLOBAL_EDIT_TOOL::SwapLayers( const TOOL_EVENT& aEvent ) bool hasChanges = false; // Change tracks. - for( TRACK* segm : frame()->GetBoard()->Tracks() ) + for( PCB_TRACK* segm : frame()->GetBoard()->Tracks() ) { if( segm->Type() == PCB_VIA_T ) { - VIA* via = (VIA*) segm; + PCB_VIA* via = static_cast( segm ); PCB_LAYER_ID top_layer, bottom_layer; if( via->GetViaType() == VIATYPE::THROUGH ) diff --git a/pcbnew/tools/pcb_control.cpp b/pcbnew/tools/pcb_control.cpp index 56729aba57..a6fb1763b6 100644 --- a/pcbnew/tools/pcb_control.cpp +++ b/pcbnew/tools/pcb_control.cpp @@ -39,7 +39,7 @@ #include #include #include -#include +#include #include #include #include @@ -982,7 +982,7 @@ int PCB_CONTROL::AppendBoard( PLUGIN& pi, wxString& fileName ) // Mark existing items, in order to know what are the new items so we can select only // the new items after loading - for( TRACK* track : brd->Tracks() ) + for( PCB_TRACK* track : brd->Tracks() ) track->SetFlags( SKIP_STRUCT ); for( FOOTPRINT* footprint : brd->Footprints() ) diff --git a/pcbnew/tools/pcb_grid_helper.cpp b/pcbnew/tools/pcb_grid_helper.cpp index 3e6202ef18..71cf8db640 100644 --- a/pcbnew/tools/pcb_grid_helper.cpp +++ b/pcbnew/tools/pcb_grid_helper.cpp @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include #include @@ -599,7 +599,7 @@ void PCB_GRID_HELPER::computeAnchors( BOARD_ITEM* aItem, const VECTOR2I& aRefPos { if( aFrom || m_magneticSettings->tracks == MAGNETIC_OPTIONS::CAPTURE_ALWAYS ) { - TRACK* track = static_cast( aItem ); + PCB_TRACK* track = static_cast( aItem ); addAnchor( track->GetStart(), CORNER | SNAPPABLE, track ); addAnchor( track->GetEnd(), CORNER | SNAPPABLE, track ); diff --git a/pcbnew/tools/pcb_selection.cpp b/pcbnew/tools/pcb_selection.cpp index 8c50c51758..04c0056469 100644 --- a/pcbnew/tools/pcb_selection.cpp +++ b/pcbnew/tools/pcb_selection.cpp @@ -31,7 +31,6 @@ using namespace std::placeholders; #include #include -#include #include #include #include diff --git a/pcbnew/tools/pcb_selection_tool.cpp b/pcbnew/tools/pcb_selection_tool.cpp index 04127cba1e..e2c1da6306 100644 --- a/pcbnew/tools/pcb_selection_tool.cpp +++ b/pcbnew/tools/pcb_selection_tool.cpp @@ -32,7 +32,7 @@ using namespace std::placeholders; #include #include #include -#include +#include #include #include #include @@ -417,7 +417,7 @@ int PCB_SELECTION_TOOL::Main( const TOOL_EVENT& aEvent ) if( evt->HasPosition() && selectionContains( evt->Position() ) ) { // Yes -> run the move tool and wait till it finishes - TRACK* track = dynamic_cast( m_selection.GetItem( 0 ) ); + PCB_TRACK* track = dynamic_cast( m_selection.GetItem( 0 ) ); // If there is only item in the selection and it's a track, then we need to route it bool doRouting = ( track && ( 1 == m_selection.GetSize() ) ); @@ -1101,7 +1101,7 @@ int PCB_SELECTION_TOOL::expandConnection( const TOOL_EVENT& aEvent ) for( EDA_ITEM* item : selectedItems ) { - TRACK* trackItem = dynamic_cast( item ); + PCB_TRACK* trackItem = dynamic_cast( item ); // Track items marked SKIP_STRUCT have already been visited if( trackItem && !( trackItem->GetFlags() & SKIP_STRUCT ) ) @@ -1128,9 +1128,9 @@ void PCB_SELECTION_TOOL::selectConnectedTracks( BOARD_CONNECTED_ITEM& aStartItem auto connectivity = board()->GetConnectivity(); auto connectedItems = connectivity->GetConnectedItems( &aStartItem, types, true ); - std::map> trackMap; - std::map viaMap; - std::map padMap; + std::map> trackMap; + std::map viaMap; + std::map padMap; // Build maps of connected items for( BOARD_CONNECTED_ITEM* item : connectedItems ) @@ -1140,7 +1140,7 @@ void PCB_SELECTION_TOOL::selectConnectedTracks( BOARD_CONNECTED_ITEM& aStartItem case PCB_ARC_T: case PCB_TRACE_T: { - TRACK* track = static_cast( item ); + PCB_TRACK* track = static_cast( item ); trackMap[ track->GetStart() ].push_back( track ); trackMap[ track->GetEnd() ].push_back( track ); } @@ -1148,7 +1148,7 @@ void PCB_SELECTION_TOOL::selectConnectedTracks( BOARD_CONNECTED_ITEM& aStartItem case PCB_VIA_T: { - VIA* via = static_cast( item ); + PCB_VIA* via = static_cast( item ); viaMap[ via->GetStart() ] = via; } break; @@ -1174,12 +1174,12 @@ void PCB_SELECTION_TOOL::selectConnectedTracks( BOARD_CONNECTED_ITEM& aStartItem { case PCB_ARC_T: case PCB_TRACE_T: - activePts.push_back( static_cast( &aStartItem )->GetStart() ); - activePts.push_back( static_cast( &aStartItem )->GetEnd() ); + activePts.push_back( static_cast( &aStartItem )->GetStart() ); + activePts.push_back( static_cast( &aStartItem )->GetEnd() ); break; case PCB_VIA_T: - activePts.push_back( static_cast( &aStartItem )->GetStart() ); + activePts.push_back( static_cast( &aStartItem )->GetStart() ); break; case PCB_PAD_T: @@ -1214,7 +1214,7 @@ void PCB_SELECTION_TOOL::selectConnectedTracks( BOARD_CONNECTED_ITEM& aStartItem continue; } - for( TRACK* track : trackMap[ pt ] ) + for( PCB_TRACK* track : trackMap[ pt ] ) { if( track->GetState( SKIP_STRUCT ) ) continue; @@ -1980,9 +1980,9 @@ bool PCB_SELECTION_TOOL::Selectable( const BOARD_ITEM* aItem, bool checkVisibili return false; } - const ZONE* zone = nullptr; - const VIA* via = nullptr; - const PAD* pad = nullptr; + const ZONE* zone = nullptr; + const PCB_VIA* via = nullptr; + const PAD* pad = nullptr; switch( aItem->Type() ) { @@ -2030,7 +2030,7 @@ bool PCB_SELECTION_TOOL::Selectable( const BOARD_ITEM* aItem, bool checkVisibili if( !board()->IsElementVisible( LAYER_VIAS ) ) return false; - via = static_cast( aItem ); + via = static_cast( aItem ); // For vias it is enough if only one of its layers is visible if( !( board()->GetVisibleLayers() & via->GetLayerSet() ).any() ) @@ -2443,7 +2443,7 @@ void PCB_SELECTION_TOOL::GuessSelectionCandidates( GENERAL_COLLECTOR& aCollector { // Vias rarely hide other things, and we don't want them deferring to short track // segments -- so make them artificially small by dropping the π from πr². - area = SEG::Square( static_cast( item )->GetDrill() / 2 ); + area = SEG::Square( static_cast( item )->GetDrill() / 2 ); } else { diff --git a/pcbnew/tracks_cleaner.cpp b/pcbnew/tracks_cleaner.cpp index b471dbed4f..a6fe5f8a7c 100644 --- a/pcbnew/tracks_cleaner.cpp +++ b/pcbnew/tracks_cleaner.cpp @@ -79,7 +79,7 @@ void TRACKS_CLEANER::removeShortingTrackSegments() std::set toRemove; - for( TRACK* segment : m_brd->Tracks() ) + for( PCB_TRACK* segment : m_brd->Tracks() ) { // Assume that the user knows what they are doing if( segment->IsLocked() ) @@ -103,7 +103,7 @@ void TRACKS_CLEANER::removeShortingTrackSegments() } } - for( TRACK* testedTrack : connectivity->GetConnectedTracks( segment ) ) + for( PCB_TRACK* testedTrack : connectivity->GetConnectedTracks( segment ) ) { if( segment->GetNetCode() != testedTrack->GetNetCode() ) { @@ -127,7 +127,7 @@ void TRACKS_CLEANER::removeShortingTrackSegments() } -bool TRACKS_CLEANER::testTrackEndpointIsNode( TRACK* aTrack, bool aTstStart ) +bool TRACKS_CLEANER::testTrackEndpointIsNode( PCB_TRACK* aTrack, bool aTstStart ) { // A node is a point where more than 2 items are connected. @@ -175,9 +175,9 @@ bool TRACKS_CLEANER::deleteDanglingTracks( bool aTrack, bool aVia ) m_brd->BuildConnectivity(); // Keep a duplicate deque to all deleting in the primary - std::deque temp_tracks( m_brd->Tracks() ); + std::deque temp_tracks( m_brd->Tracks() ); - for( TRACK* track : temp_tracks ) + for( PCB_TRACK* track : temp_tracks ) { if( track->IsLocked() ) continue; @@ -228,7 +228,7 @@ void TRACKS_CLEANER::deleteTracksInPads() // Delete tracks that start and end on the same pad std::shared_ptr connectivity = m_brd->GetConnectivity(); - for( TRACK* track : m_brd->Tracks() ) + for( PCB_TRACK* track : m_brd->Tracks() ) { if( track->IsLocked() ) continue; @@ -272,7 +272,7 @@ void TRACKS_CLEANER::cleanup( bool aDeleteDuplicateVias, bool aDeleteNullSegment { DRC_RTREE rtree; - for( TRACK* track : m_brd->Tracks() ) + for( PCB_TRACK* track : m_brd->Tracks() ) { track->ClearFlags( IS_DELETED | SKIP_STRUCT ); rtree.Insert( track, track->GetLayer() ); @@ -280,14 +280,14 @@ void TRACKS_CLEANER::cleanup( bool aDeleteDuplicateVias, bool aDeleteNullSegment std::set toRemove; - for( TRACK* track : m_brd->Tracks() ) + for( PCB_TRACK* track : m_brd->Tracks() ) { if( track->HasFlag( IS_DELETED ) || track->IsLocked() ) continue; if( aDeleteDuplicateVias && track->Type() == PCB_VIA_T ) { - VIA* via = static_cast( track ); + PCB_VIA* via = static_cast( track ); if( via->GetStart() != via->GetEnd() ) via->SetEnd( via->GetStart() ); @@ -303,7 +303,7 @@ void TRACKS_CLEANER::cleanup( bool aDeleteDuplicateVias, bool aDeleteNullSegment // Visitor: [&]( BOARD_ITEM* aItem ) -> bool { - VIA* other = static_cast( aItem ); + PCB_VIA* other = static_cast( aItem ); if( via->GetPosition() == other->GetPosition() && via->GetViaType() == other->GetViaType() @@ -367,7 +367,7 @@ void TRACKS_CLEANER::cleanup( bool aDeleteDuplicateVias, bool aDeleteNullSegment // Visitor: [&]( BOARD_ITEM* aItem ) -> bool { - TRACK* other = static_cast( aItem ); + PCB_TRACK* other = static_cast( aItem ); if( track->IsPointOnEnds( other->GetStart() ) && track->IsPointOnEnds( other->GetEnd() ) @@ -402,10 +402,10 @@ void TRACKS_CLEANER::cleanup( bool aDeleteDuplicateVias, bool aDeleteNullSegment m_brd->BuildConnectivity(); // Keep a duplicate deque to all deleting in the primary - std::deque temp_segments( m_brd->Tracks() ); + std::deque temp_segments( m_brd->Tracks() ); // merge collinear segments: - for( TRACK* segment : temp_segments ) + for( PCB_TRACK* segment : temp_segments ) { if( segment->Type() != PCB_TRACE_T ) // one can merge only track collinear segments, not vias. continue; @@ -428,7 +428,7 @@ void TRACKS_CLEANER::cleanup( bool aDeleteDuplicateVias, bool aDeleteNullSegment if( candidateItem->Type() == PCB_TRACE_T && !candidateItem->HasFlag( IS_DELETED ) ) { - TRACK* candidateSegment = static_cast( candidateItem ); + PCB_TRACK* candidateSegment = static_cast( candidateItem ); // Do not merge segments having different widths: it is a frequent case // to draw a track between 2 pads: @@ -444,12 +444,12 @@ void TRACKS_CLEANER::cleanup( bool aDeleteDuplicateVias, bool aDeleteNullSegment } while( merged ); } - for( TRACK* track : m_brd->Tracks() ) + for( PCB_TRACK* track : m_brd->Tracks() ) track->ClearFlags( IS_DELETED | SKIP_STRUCT ); } -bool TRACKS_CLEANER::mergeCollinearSegments( TRACK* aSeg1, TRACK* aSeg2 ) +bool TRACKS_CLEANER::mergeCollinearSegments( PCB_TRACK* aSeg1, PCB_TRACK* aSeg2 ) { if( aSeg1->IsLocked() || aSeg2->IsLocked() ) return false; @@ -458,7 +458,7 @@ bool TRACKS_CLEANER::mergeCollinearSegments( TRACK* aSeg1, TRACK* aSeg2 ) // Verify the removed point after merging is not a node. // If it is a node (i.e. if more than one other item is connected, the segments cannot be merged - TRACK dummy_seg( *aSeg1 ); + PCB_TRACK dummy_seg( *aSeg1 ); // Calculate the new ends of the segment to merge, and store them to dummy_seg: int min_x = std::min( aSeg1->GetStart().x, diff --git a/pcbnew/tracks_cleaner.h b/pcbnew/tracks_cleaner.h index 71c18af4e8..31d007ad8c 100644 --- a/pcbnew/tracks_cleaner.h +++ b/pcbnew/tracks_cleaner.h @@ -24,7 +24,7 @@ #ifndef KICAD_TRACKS_CLEANER_H #define KICAD_TRACKS_CLEANER_H -#include +#include #include class BOARD_COMMIT; @@ -81,7 +81,7 @@ private: * @param aSeg1 is the reference * @param aSeg2 is the candidate, and after merging, the removed segment */ - bool mergeCollinearSegments( TRACK* aSeg1, TRACK* aSeg2 ); + bool mergeCollinearSegments( PCB_TRACK* aSeg1, PCB_TRACK* aSeg2 ); /** * @return true if a track end position is a node, i.e. a end connected @@ -89,7 +89,7 @@ private: * @param aTrack is the track to test. * @param aTstStart = true ot test the start point of the track or false for end point */ - bool testTrackEndpointIsNode( TRACK* aTrack, bool aTstStart ); + bool testTrackEndpointIsNode( PCB_TRACK* aTrack, bool aTstStart ); void removeItems( std::set& aItems ); diff --git a/pcbnew/undo_redo.cpp b/pcbnew/undo_redo.cpp index 48e89b037b..35962ab1e6 100644 --- a/pcbnew/undo_redo.cpp +++ b/pcbnew/undo_redo.cpp @@ -30,7 +30,7 @@ using namespace std::placeholders; #include #include #include -#include +#include #include #include #include @@ -113,7 +113,7 @@ using namespace std::placeholders; static bool TestForExistingItem( BOARD* aPcb, BOARD_ITEM* aItem ) { - for( TRACK* item : aPcb->Tracks() ) + for( PCB_TRACK* item : aPcb->Tracks() ) { if( aItem == static_cast( item ) ) return true; diff --git a/pcbnew/zone_filler.cpp b/pcbnew/zone_filler.cpp index 1b561e04b5..70aaf8a3ee 100644 --- a/pcbnew/zone_filler.cpp +++ b/pcbnew/zone_filler.cpp @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include #include #include @@ -742,7 +742,7 @@ void ZONE_FILLER::buildCopperItemClearances( const ZONE* aZone, PCB_LAYER_ID aLa // Add non-connected track clearances // auto knockoutTrackClearance = - [&]( TRACK* aTrack ) + [&]( PCB_TRACK* aTrack ) { if( aTrack->GetBoundingBox().Intersects( zone_boundingbox ) ) { @@ -752,7 +752,7 @@ void ZONE_FILLER::buildCopperItemClearances( const ZONE* aZone, PCB_LAYER_ID aLa if( aTrack->Type() == PCB_VIA_T ) { - VIA* via = static_cast( aTrack ); + PCB_VIA* via = static_cast( aTrack ); if( !via->FlashLayer( aLayer ) && via->GetNetCode() != aZone->GetNetCode() ) { @@ -774,7 +774,7 @@ void ZONE_FILLER::buildCopperItemClearances( const ZONE* aZone, PCB_LAYER_ID aLa } }; - for( TRACK* track : m_board->Tracks() ) + for( PCB_TRACK* track : m_board->Tracks() ) { if( !track->IsOnLayer( aLayer ) ) continue; @@ -1529,11 +1529,11 @@ bool ZONE_FILLER::addHatchFillTypeOnZone( const ZONE* aZone, PCB_LAYER_ID aLayer SHAPE_POLY_SET aprons; int min_apron_radius = ( aZone->GetHatchGap() * 10 ) / 19; - for( TRACK* track : m_board->Tracks() ) + for( PCB_TRACK* track : m_board->Tracks() ) { if( track->Type() == PCB_VIA_T ) { - VIA* via = static_cast( track ); + PCB_VIA* via = static_cast( track ); if( via->GetNetCode() == aZone->GetNetCode() && via->IsOnLayer( aLayer ) diff --git a/qa/libeval_compiler/libeval_compiler_test.cpp b/qa/libeval_compiler/libeval_compiler_test.cpp index a37a9d597e..1a8602da42 100644 --- a/qa/libeval_compiler/libeval_compiler_test.cpp +++ b/qa/libeval_compiler/libeval_compiler_test.cpp @@ -2,7 +2,7 @@ #include #include "board.h" -#include "track.h" +#include "pcb_track.h" #include @@ -81,8 +81,8 @@ int main( int argc, char *argv[] ) net1info->SetClass( netclass1 ); net2info->SetClass( netclass2 ); - TRACK trackA(&brd); - TRACK trackB(&brd); + PCB_TRACK trackA( &brd ); + PCB_TRACK trackB( &brd ); trackA.SetNet( net1info ); trackB.SetNet( net2info ); diff --git a/qa/pcbnew/test_libeval_compiler.cpp b/qa/pcbnew/test_libeval_compiler.cpp index 0872762ad1..ac2e81b6b5 100644 --- a/qa/pcbnew/test_libeval_compiler.cpp +++ b/qa/pcbnew/test_libeval_compiler.cpp @@ -29,7 +29,7 @@ #include #include -#include +#include BOOST_AUTO_TEST_SUITE( Libeval_Compiler ) @@ -162,8 +162,8 @@ BOOST_AUTO_TEST_CASE( IntrospectedProperties ) net1info->SetNetClass( netclass1 ); net2info->SetNetClass( netclass2 ); - TRACK trackA( &brd ); - TRACK trackB( &brd ); + PCB_TRACK trackA( &brd ); + PCB_TRACK trackB( &brd ); trackA.SetNet( net1info ); trackB.SetNet( net2info ); diff --git a/qa/pcbnew_tools/tools/polygon_generator/polygon_generator.cpp b/qa/pcbnew_tools/tools/polygon_generator/polygon_generator.cpp index 59d3ebc5d8..699ee5de95 100644 --- a/qa/pcbnew_tools/tools/polygon_generator/polygon_generator.cpp +++ b/qa/pcbnew_tools/tools/polygon_generator/polygon_generator.cpp @@ -34,7 +34,7 @@ #include #include #include -#include +#include #include @@ -76,7 +76,7 @@ int polygon_gererator_main( int argc, char* argv[] ) for( unsigned net = 0; net < brd->GetNetCount(); net++ ) { - for( TRACK* track : brd->Tracks() ) + for( PCB_TRACK* track : brd->Tracks() ) process( track, net ); for( FOOTPRINT* fp : brd->Footprints() )