diff --git a/change_log.txt b/change_log.txt
index 2c950e63e9..e6194c471b 100644
--- a/change_log.txt
+++ b/change_log.txt
@@ -5,6 +5,12 @@ Started 2007-June-11
 Please add newer entries at the top, list the date and your name with
 email address.
 
+2008-Mar-3 UPDATE   Dick Hollenbeck <dick@softplc.com>
+================================================================================
++pcbnew
+	Solved problem in fill zone calculations when using buried or blind vias (like micro vias)
+
+
 2008-Feb-18 UPDATE Igor Plyatov <plyatov@mail.ru>
 ================================================================================
 +common
diff --git a/pcbnew/board.cpp b/pcbnew/board.cpp
index 5bc4cc3f1c..e1270a3b84 100644
--- a/pcbnew/board.cpp
+++ b/pcbnew/board.cpp
@@ -288,7 +288,7 @@ void PlaceCells( BOARD* Pcb, int net_code, int flag )
             dx = PtText->Pitch() * PtText->GetLength();
             dy = PtText->m_Size.y + PtText->m_Width;
 
-            /* Calcul du rectangle d'encadrement */
+            /* Put bounding box (rectangle) on matrix */
             dx  /= 2; dy /= 2;    /* dx et dy = demi dimensionx X et Y */
             ux1  = ux0 + dx; uy1 = uy0 + dy;
             ux0 -= dx; uy0 -= dy;
@@ -309,17 +309,18 @@ void PlaceCells( BOARD* Pcb, int net_code, int flag )
         }
     }
 
-    /* Placement des PISTES */
+    /* Put tracks and vias on matrix */
     pt_segm = Pcb->m_Track;
     for( ; pt_segm != NULL; pt_segm = (TRACK*) pt_segm->Pnext )
     {
         if( net_code == pt_segm->GetNet() )
             continue;
-        TraceSegmentPcb( Pcb, pt_segm, HOLE, marge, WRITE_CELL );
-        TraceSegmentPcb( Pcb, pt_segm, VIA_IMPOSSIBLE, via_marge, WRITE_OR_CELL );
+				
+		TraceSegmentPcb( Pcb, pt_segm, HOLE, marge, WRITE_CELL );
+		TraceSegmentPcb( Pcb, pt_segm, VIA_IMPOSSIBLE, via_marge, WRITE_OR_CELL );
     }
 
-    /* Placement des ZONES */
+    /* Put zone filling on matrix */
     pt_segm = (TRACK*) Pcb->m_Zone;
     for( ; pt_segm != NULL; pt_segm = (TRACK*) pt_segm->Pnext )
     {
diff --git a/pcbnew/graphpcb.cpp b/pcbnew/graphpcb.cpp
index c4c1982732..f3a7d39f42 100644
--- a/pcbnew/graphpcb.cpp
+++ b/pcbnew/graphpcb.cpp
@@ -251,7 +251,6 @@ void TraceSegmentPcb( BOARD* Pcb, TRACK* pt_segm, int color, int marge, int op_l
 {
     int demi_pas, demi_largeur;
     int ux0, uy0, ux1, uy1;
-    int layer = pt_segm->GetLayer();
 
 
     demi_pas     = g_GridRoutingSize / 2;
@@ -262,17 +261,32 @@ void TraceSegmentPcb( BOARD* Pcb, TRACK* pt_segm, int color, int marge, int op_l
     ux1 = pt_segm->m_End.x - Pcb->m_BoundaryBox.m_Pos.x;
     uy1 = pt_segm->m_End.y - Pcb->m_BoundaryBox.m_Pos.y;
 
-    if( color == VIA_IMPOSSIBLE )
-        layer = -1;
-
     /* Test si VIA (cercle plein a tracer) */
     if( pt_segm->Type() == TYPEVIA )
     {
-        TraceFilledCercle( Pcb, pt_segm->m_Start.x, pt_segm->m_Start.y, demi_largeur,
-                           0x0000FFFF, color, op_logique );
+		int mask_layer = 0;
+		if ( pt_segm->IsOnLayer(Route_Layer_BOTTOM) )
+			mask_layer = 1 << Route_Layer_BOTTOM;
+		if ( pt_segm->IsOnLayer(Route_Layer_TOP) )
+		{
+			if ( mask_layer == 0 )
+				mask_layer = 1 << Route_Layer_TOP;
+			else mask_layer = -1;
+		}
+	
+		if( color == VIA_IMPOSSIBLE )
+			mask_layer = -1;
+
+		if ( mask_layer )
+			TraceFilledCercle( Pcb, pt_segm->m_Start.x, pt_segm->m_Start.y, demi_largeur,
+                           mask_layer, color, op_logique );
         return;
     }
 
+    int layer = pt_segm->GetLayer();
+    if( color == VIA_IMPOSSIBLE )
+        layer = -1;
+
     /* Le segment est ici un segment de droite ou un cercle ou un arc: */
     if( pt_segm->m_Shape == S_CIRCLE )
     {
diff --git a/pcbnew/makefile.include b/pcbnew/makefile.include
index f3ad50831b..fc1c29d565 100644
--- a/pcbnew/makefile.include
+++ b/pcbnew/makefile.include
@@ -116,9 +116,7 @@ OBJECTS=	$(TARGET).o classpcb.o\
 		modedit.o\
 		export_gencad.o\
 		hotkeys.o \
-        collectors.o \
-		set_color.o
-		
+        collectors.o
 
 
 PolyLine.o: ../polygon/PolyLine.cpp ../polygon/PolyLine.h $(COMMON)