diff --git a/pcbnew/drc/drc_test_provider_matched_length.cpp b/pcbnew/drc/drc_test_provider_matched_length.cpp
index 81639ebda7..7be3664a30 100644
--- a/pcbnew/drc/drc_test_provider_matched_length.cpp
+++ b/pcbnew/drc/drc_test_provider_matched_length.cpp
@@ -19,6 +19,7 @@
 
 #include <common.h>
 #include <board.h>
+#include <board_design_settings.h>
 #include <pad.h>
 #include <pcb_track.h>
 
@@ -89,13 +90,6 @@ private:
     DRC_LENGTH_REPORT m_report;
 };
 
-
-static int computeViaThruLength( PCB_VIA *aVia, const std::set<BOARD_CONNECTED_ITEM*> &conns )
-{
-    return 0; // fixme: not yet there...
-}
-
-
 void DRC_TEST_PROVIDER_MATCHED_LENGTH::checkLengths( DRC_CONSTRAINT& aConstraint,
                                                      std::vector<CONNECTION>& aMatchedConnections )
 {
@@ -291,9 +285,17 @@ bool DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal( bool aDelayReportMode )
             {
                 if( citem->Type() == PCB_VIA_T )
                 {
+                    const BOARD_DESIGN_SETTINGS& ds = m_board->GetDesignSettings();
+
                     ent.viaCount++;
-                    ent.totalVia += computeViaThruLength( static_cast<PCB_VIA*>( citem ),
-                                                          nitem.second );
+
+                    if( ds.m_UseHeightForLengthCalcs )
+                    {
+                        const PCB_VIA* v = static_cast<PCB_VIA*>( citem );
+
+                        ent.totalVia += ds.GetStackupDescriptor().GetLayerDistance(
+                                v->TopLayer(), v->BottomLayer() );
+                    }
                 }
                 else if( citem->Type() == PCB_TRACE_T )
                 {