From 1757631652c89ce28714ec819d81ba9b099bcadc Mon Sep 17 00:00:00 2001 From: Rigo Ligo Date: Wed, 16 Jun 2021 14:36:46 +0000 Subject: [PATCH] Translated using Weblate (Chinese (Simplified)) Currently translated at 99.9% (6989 of 6990 strings) Translation: KiCad EDA/master source Translate-URL: https://hosted.weblate.org/projects/kicad/master-source/zh_Hans/ --- translation/pofiles/zh_CN.po | 177 +++++++++++++++++------------------ 1 file changed, 87 insertions(+), 90 deletions(-) diff --git a/translation/pofiles/zh_CN.po b/translation/pofiles/zh_CN.po index 1335bfd477..698adbfdef 100644 --- a/translation/pofiles/zh_CN.po +++ b/translation/pofiles/zh_CN.po @@ -11,7 +11,7 @@ msgstr "" "Report-Msgid-Bugs-To: \n" "POT-Creation-Date: 2021-06-10 13:22-0700\n" "PO-Revision-Date: 2021-06-18 13:11+0000\n" -"Last-Translator: taotieren \n" +"Last-Translator: Rigo Ligo \n" "Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" @@ -20231,7 +20231,7 @@ msgstr "锁定" #: pcbnew/board_stackup_manager/board_stackup.cpp:306 #, c-format msgid "Dielectric %d" -msgstr "Dielectric %d" +msgstr "电介质层 %d" #: pcbnew/board_stackup_manager/board_stackup.cpp:526 msgid "Top Silk Screen" @@ -26507,7 +26507,7 @@ msgstr "如果选中，区域将在使用区域属性对话框编辑区域的属 #: pcbnew/dialogs/panel_fp_editor_color_settings.cpp:130 msgid "Internal Layers" -msgstr "Internal Layers" +msgstr "内层" #: pcbnew/dialogs/panel_fp_editor_defaults.cpp:325 msgid "" @@ -27491,6 +27491,7 @@ msgid "Check rule syntax" msgstr "检查规则语法" #: pcbnew/dialogs/panel_setup_rules_help_md.h:2 +#, fuzzy msgid "" "### Top-level Clauses\n" "\n" @@ -27698,209 +27699,205 @@ msgid "" " (constraint clearance (min \"1.5mm\"))\n" " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" msgstr "" -"### Top-level Clauses\n" +"### 顶层语句\n" "\n" -" (version )\n" +" 版本语句：(version <版本号>)\n" "\n" -" (rule ...)\n" +" 规则语句：(rule <规则名> <规则语句> ...)\n" "\n" "\n" "

\n" "\n" -"### Rule Clauses\n" +"### 规则语句\n" "\n" -" (constraint ...)\n" +" 约束语句：(constraint <约束类型> ...)\n" "\n" -" (condition \"\")\n" +" 条件语句：(condition \"<条件表达式>\")\n" "\n" -" (layer \"\")\n" +" 层语句：(layer \"<层名>\")\n" "\n" "\n" "

\n" "\n" -"### Constraint Types\n" +"### 约束类型\n" "\n" -" * annular_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" +" * annular_width （孔铜环宽度）\n" +" * clearance （间隙）\n" +" * courtyard_clearance （封装外框之间的间隙）\n" +" * diff\\_pair\\_gap （差分对间隙）\n" " * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge_clearance\n" -" * length\n" -" * hole\n" -" * hole_clearance\n" -" * silk_clearance\n" -" * skew\n" -" * track_width\n" -" * via_count\n" +" * disallow （不允许）\n" +" * edge_clearance （与板边的间隙）\n" +" * length （长度）\n" +" * hole （孔）\n" +" * hole_clearance （与孔的间隙）\n" +" * silk_clearance （与丝印的间隙）\n" +" * skew （偏移）\n" +" * track_width （线宽）\n" +" * via_count （过孔个数）\n" "\n" "\n" "

\n" "\n" -"### Item Types\n" +"### 电路板元素类型\n" "\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" +" * buried_via （埋孔）\n" +" * graphic （图形）\n" +" * hole （孔）\n" +" * micro_via （微孔）\n" +" * pad （焊盘）\n" +" * text （文字）\n" +" * track （布线）\n" +" * via （过孔）\n" +" * zone （区域）\n" "\n" "
\n" "\n" -"### Examples\n" +"### 范例\n" "\n" " (version 1)\n" "\n" -" (rule HV\n" +" (rule 高压间距\n" " (constraint clearance (min 1.5mm))\n" " (condition \"A.NetClass == 'HV'\"))\n" "\n" "\n" -" (rule HV\n" +" (rule 外层高压间距\n" " (layer outer)\n" " (constraint clearance (min 1.5mm))\n" " (condition \"A.NetClass == 'HV'\"))\n" "\n" "\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" +" (rule 高压之间间距\n" +" # 高压线路之间间距应该更大\n" " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" "\n" "\n" -" (rule HV_unshielded\n" +" (rule 无护罩高压线路\n" " (constraint clearance (min 2mm))\n" " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" "

\n" "\n" -"### Notes\n" +"### \n" "\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" +"版本语句标志着文件的语法版本，所以版本语句必须是第一个语句，\n" +"以便将来的 KiCad 解析新版本的规则文件。版本应设为“1”。\n" "\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" +"规则应该以优先级排序。后面的规则优先于前面的规则；\n" +"且一旦检测到某个规则成功匹配，则其余的规则均被忽略。\n" "\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" +"使用 Ctrl+/ 来对选中的行添加或取消注释。\n" "


\n" "\n" -"### Expression functions\n" +"### 表达式函数\n" "\n" -"All function parameters support simple wildcards (`*` and `?`).\n" +"函数的参数均支持简单的通配符（`*` 和 `?`）。\n" "

\n" "\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" +" A.insideCourtyard('<封装标号>')\n" +"若 `A` 的任何部分落在指定封装的主要外框中，则为真。\n" "

\n" "\n" " A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" +"若 `A` 的任何部分落在指定封装的顶层外框中，则为真。\n" "

\n" "\n" " A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" +"若 `A` 的任何部分落在指定封装的底层外框中，则为真。\n" "

\n" "\n" " A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" +"若 `A` 的任何部分落在指定区域中，则为真。\n" "

\n" "\n" " A.isPlated()\n" -"True if `A` has a hole which is plated.\n" +"若 `A` 含/是铜孔，则为真。\n" "

\n" "\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('CLK')`\n" +" A.inDiffPair('<网络名>')\n" +"若 `A` 含有指定差分对的网络，则为真。\n" +"`<网络名>` 是指定差分对的基础名称。例如， `inDiffPair('CLK')`\n" "matches items in the `CLK_P` and `CLK_N` nets.\n" "

\n" "\n" " AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" +"若 `A` 和 `B` 分别具有同一差分对的两个网络，则为真。\n" "

\n" "\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" +" A.memberOf('<组名>')\n" +"若 `A` 是指定组中的成员，则为真。组内嵌套的组也包括在内。\n" "

\n" "\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" +" A.existsOnLayer('<层名>')\n" +"若 `A` 在指定的层中，则为真。层名可以是“电路板设置 >\n" +"电路板编辑图层”菜单中指定的名称，也可以是内部最简名称\n" +"（如 `F.Cu`）。\n" +"\n" +"注：不论是否正在检查指定的层，只要 `A` 在该层上，\n" +"此条件即为真。对这样的使用场景，请在规则中使用\n" +"`(layer \"层名\")`。\n" "\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" "


\n" "\n" -"### More Examples\n" +"### 更多的范例\n" "\n" -" (rule \"copper keepout\"\n" +" (rule \"禁止铜区\"\n" " (constraint disallow track via zone)\n" " (condition \"A.insideArea('zone3')\"))\n" "\n" "\n" -" (rule \"BGA neckdown\"\n" +" (rule \"BGA加粗\"\n" " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" " (condition \"A.insideCourtyard('U3')\"))\n" "\n" "\n" -" # prevent silk over tented vias\n" +" # 禁止盖油过孔上印字\n" " (rule silk_over_via\n" " (constraint silk_clearance (min 0.2mm))\n" " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" "\n" "\n" -" (rule \"Distance between Vias of Different Nets\" \n" +" (rule \"不同网络的过孔的间距\" \n" " (constraint hole_to_hole (min 0.254mm))\n" " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" "\n" -" (rule \"Clearance between Pads of Different Nets\" \n" +" (rule \"不同网络的焊盘的间距\" \n" " (constraint clearance (min 3.0mm))\n" " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" "\n" "\n" -" (rule \"Via Hole to Track Clearance\" \n" +" (rule \"过孔到焊盘的间距\" \n" " (constraint hole_clearance (min 0.254mm))\n" " (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" " \n" -" (rule \"Pad to Track Clearance\" \n" +" (rule \"焊盘到导线的间距\" \n" " (constraint clearance (min 0.2mm))\n" " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" "\n" "\n" -" (rule \"clearance-to-1mm-cutout\"\n" +" (rule \"1mm宽开槽周围的间距\"\n" " (constraint clearance (min 0.8mm))\n" " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" "\n" "\n" -" (rule \"Max Drill Hole Size Mechanical\" \n" +" (rule \"最大机械孔孔径\" \n" " (constraint hole (max 6.3mm))\n" " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" " \n" -" (rule \"Max Drill Hole Size PTH\" \n" +" (rule \"最大铜孔孔径\" \n" " (constraint hole (max 6.35mm))\n" " (condition \"A.Pad_Type == 'Through-hole'\"))\n" "\n" "\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" +" # 给单独的差分对设置最优（opt）间距\n" +" (rule \"CLK信号间距\"\n" " (constraint diff_pair_gap (opt \"0.8mm\"))\n" " (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" "\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" +" # 给任意差分对周围扩大间距\n" +" (rule \"差分对外间距\"\n" " (constraint clearance (min \"1.5mm\"))\n" " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" @@ -28653,7 +28650,7 @@ msgstr "正在测试 %d 丝印功能针对 %d 个电路板项目。" #: pcbnew/drc/drc_test_provider_silk_to_mask.cpp:100 msgid "Checking silkscreen for potential soldermask clipping..." -msgstr "正在检查丝网印是否存在潜在的阻焊裁剪..." +msgstr "正在检查丝印是否可能与开窗区相交..." #: pcbnew/drc/drc_test_provider_silk_to_mask.cpp:182 #, c-format @@ -29519,7 +29516,7 @@ msgstr "未知(%d)" #: pcbnew/kicad_clipboard.cpp:406 msgid "Clipboard content is not KiCad compatible" -msgstr "剪贴板内容不兼容 KiCad" +msgstr "剪贴板内容与 KiCad 不兼容" #: pcbnew/load_select_footprint.cpp:265 #, c-format @@ -32945,7 +32942,7 @@ msgstr "带位号复制" #: pcbnew/tools/pcb_actions.cpp:265 msgid "Copy selected item(s) to clipboard with a specified starting point" -msgstr "将选定项目复制到具有指定起始点的剪贴板" +msgstr "将选定项目及指定的起始点复制到剪贴板" #: pcbnew/tools/pcb_actions.cpp:271 msgid "Duplicate and Increment"