From 18ad58cf4cac29bdff246e164ef08a03d5011af1 Mon Sep 17 00:00:00 2001
From: Jeff Young <jeff@rokeby.ie>
Date: Thu, 19 Nov 2020 13:25:30 +0000
Subject: [PATCH] Replace legacy copper edge heuristics.

Fixes https://gitlab.com/kicad/code/kicad/issues/6435
---
 pcbnew/board.cpp                    |  1 +
 pcbnew/board.h                      |  1 +
 pcbnew/files.cpp                    | 54 ++++++++++++++++++++++++++++-
 pcbnew/pcb_edit_frame.h             |  2 ++
 pcbnew/plugins/kicad/pcb_parser.cpp |  1 +
 5 files changed, 58 insertions(+), 1 deletion(-)

diff --git a/pcbnew/board.cpp b/pcbnew/board.cpp
index 08bfd5ae4c..0ad76b0339 100644
--- a/pcbnew/board.cpp
+++ b/pcbnew/board.cpp
@@ -65,6 +65,7 @@ BOARD::BOARD() :
         m_designSettings( new BOARD_DESIGN_SETTINGS( nullptr, "board.design_settings" ) ),
         m_NetInfo( this ),
         m_LegacyDesignSettingsLoaded( false ),
+        m_LegacyCopperEdgeClearanceLoaded( false ),
         m_LegacyNetclassesLoaded( false )
 {
     // we have not loaded a board yet, assume latest until then.
diff --git a/pcbnew/board.h b/pcbnew/board.h
index 5b59383eaf..41ba1aaae9 100644
--- a/pcbnew/board.h
+++ b/pcbnew/board.h
@@ -314,6 +314,7 @@ public:
 
     /// True if the legacy board design settings were loaded from a file
     bool m_LegacyDesignSettingsLoaded;
+    bool m_LegacyCopperEdgeClearanceLoaded;
 
     /// True if netclasses were loaded from the file
     bool m_LegacyNetclassesLoaded;
diff --git a/pcbnew/files.cpp b/pcbnew/files.cpp
index 6c76061eb4..b9f0ae76da 100644
--- a/pcbnew/files.cpp
+++ b/pcbnew/files.cpp
@@ -476,6 +476,48 @@ IO_MGR::PCB_FILE_T plugin_type( const wxString& aFileName, int aCtl )
 }
 
 
+int PCB_EDIT_FRAME::inferLegacyEdgeClearance( BOARD* aBoard )
+{
+    PCB_LAYER_COLLECTOR collector;
+
+    collector.SetLayerId( Edge_Cuts );
+    collector.Collect( aBoard, GENERAL_COLLECTOR::AllBoardItems );
+
+    int  edgeWidth = -1;
+    bool mixed = false;
+
+    for( int i = 0; i < collector.GetCount(); i++ )
+    {
+        if( collector[i]->Type() == PCB_SHAPE_T )
+        {
+            int itemWidth = static_cast<PCB_SHAPE*>( collector[i] )->GetWidth();
+
+            if( edgeWidth != -1 && edgeWidth != itemWidth )
+            {
+                mixed = true;
+                edgeWidth = std::max( edgeWidth, itemWidth );
+            }
+            else
+            {
+                edgeWidth = itemWidth;
+            }
+        }
+    }
+
+    if( mixed )
+    {
+        // If they had different widths then we can't ensure that fills will be the same.
+        wxMessageBox( _( "If the zones on this board are refilled the Copper Edge Clearance "
+                         "setting will be used (see Board Setup > Design Rules).\n"
+                         "This may result in different fills from previous Kicad versions which "
+                         "used the line thicknesses of the board boundary on the Edge Cuts layer." ),
+                      _( "Edge Clearance Warning" ), wxOK|wxICON_WARNING, this );
+    }
+
+    return std::max( 0, edgeWidth / 2 );
+}
+
+
 bool PCB_EDIT_FRAME::OpenProjectFiles( const std::vector<wxString>& aFileSet, int aCtl )
 {
     // This is for python:
@@ -623,7 +665,8 @@ bool PCB_EDIT_FRAME::OpenProjectFiles( const std::vector<wxString>& aFileSet, in
         {
             if( ioe.Problem() != wxT( "CANCEL" ) )
             {
-                wxString msg = wxString::Format( _( "Error loading board file:\n%s" ), fullFileName );
+                wxString msg = wxString::Format( _( "Error loading board file:\n%s" ),
+                                                 fullFileName );
                 DisplayErrorMessage( this, msg, ioe.What() );
             }
 
@@ -639,6 +682,15 @@ bool PCB_EDIT_FRAME::OpenProjectFiles( const std::vector<wxString>& aFileSet, in
         {
             Prj().GetProjectFile().NetSettings().ResolveNetClassAssignments( true );
 
+            // Before we had a copper edge clearance setting, the edge line widths could be used
+            // as a kludge to control them.  So if there's no setting then infer it from the
+            // edge widths.
+            if( !loadedBoard->m_LegacyCopperEdgeClearanceLoaded )
+            {
+                int edgeClearance = inferLegacyEdgeClearance( loadedBoard );
+                loadedBoard->GetDesignSettings().SetCopperEdgeClearance( edgeClearance );
+            }
+
             // On save; design settings will be removed from the board
             loadedBoard->SetModified();
         }
diff --git a/pcbnew/pcb_edit_frame.h b/pcbnew/pcb_edit_frame.h
index 30fa90d2b9..65a75ddb19 100644
--- a/pcbnew/pcb_edit_frame.h
+++ b/pcbnew/pcb_edit_frame.h
@@ -225,6 +225,8 @@ protected:
 
     void onSize( wxSizeEvent& aEvent );
 
+    int inferLegacyEdgeClearance( BOARD* aBoard );
+
 public:
     PCB_LAYER_BOX_SELECTOR* m_SelLayerBox;  // a combo box to display and select active layer
     wxChoice* m_SelTrackWidthBox;           // a choice box to display and select current track width
diff --git a/pcbnew/plugins/kicad/pcb_parser.cpp b/pcbnew/plugins/kicad/pcb_parser.cpp
index 04e9ba19ff..3cfb09c12a 100644
--- a/pcbnew/plugins/kicad/pcb_parser.cpp
+++ b/pcbnew/plugins/kicad/pcb_parser.cpp
@@ -1864,6 +1864,7 @@ void PCB_PARSER::parseDefaults( BOARD_DESIGN_SETTINGS& designSettings )
         {
         case T_edge_clearance:
             designSettings.m_CopperEdgeClearance = parseBoardUnits( T_edge_clearance );
+            m_board->m_LegacyCopperEdgeClearanceLoaded = true;
             NeedRIGHT();
             break;