diff --git a/pcbnew/drc/drc_engine.cpp b/pcbnew/drc/drc_engine.cpp index 6ac88a3782..29c9775024 100644 --- a/pcbnew/drc/drc_engine.cpp +++ b/pcbnew/drc/drc_engine.cpp @@ -1189,16 +1189,11 @@ DRC_CONSTRAINT DRC_ENGINE::EvalRules( DRC_CONSTRAINT_T aConstraintType, const BO } } else if( c->constraint.m_Type == HOLE_TO_HOLE_CONSTRAINT - && ( !a->HasDrilledHole() || !b->HasDrilledHole() ) ) + && ( !a->HasDrilledHole() && !b->HasDrilledHole() ) ) { // Report non-drilled-holes as an implicit condition - if( aReporter ) - { - const BOARD_ITEM* x = !a->HasDrilledHole() ? a : b; - - REPORT( wxString::Format( _( "%s is not a drilled hole; rule ignored." ), - x->GetItemDescription( this ) ) ) - } + REPORT( wxString::Format( _( "%s is not a drilled hole; rule ignored." ), + a->GetItemDescription( this ) ) ) } else if( !c->condition || c->condition->GetExpression().IsEmpty() ) { diff --git a/pcbnew/drc/drc_item.cpp b/pcbnew/drc/drc_item.cpp index 73c25e0052..0f2ce3f51a 100644 --- a/pcbnew/drc/drc_item.cpp +++ b/pcbnew/drc/drc_item.cpp @@ -102,7 +102,7 @@ DRC_ITEM DRC_ITEM::holeClearance( DRCE_HOLE_CLEARANCE, wxT( "hole_clearance" ) ); DRC_ITEM DRC_ITEM::holeNearHole( DRCE_DRILLED_HOLES_TOO_CLOSE, - _( "Drilled holes too close together" ), + _( "Drilled hole too close to other hole" ), wxT( "hole_to_hole" ) ); DRC_ITEM DRC_ITEM::holesCoLocated( DRCE_DRILLED_HOLES_COLOCATED, diff --git a/pcbnew/drc/drc_test_provider_hole_to_hole.cpp b/pcbnew/drc/drc_test_provider_hole_to_hole.cpp index 796b4ea365..34ef9a592b 100644 --- a/pcbnew/drc/drc_test_provider_hole_to_hole.cpp +++ b/pcbnew/drc/drc_test_provider_hole_to_hole.cpp @@ -76,20 +76,17 @@ private: }; -static std::shared_ptr getDrilledHoleShape( BOARD_ITEM* aItem ) +static std::shared_ptr getHoleShape( BOARD_ITEM* aItem ) { - if( aItem->HasDrilledHole() ) + if( aItem->Type() == PCB_VIA_T ) { - if( aItem->Type() == PCB_VIA_T ) - { - PCB_VIA* via = static_cast( aItem ); - return std::make_shared( via->GetCenter(), via->GetDrillValue() / 2 ); - } - else if( aItem->Type() == PCB_PAD_T ) - { - PAD* pad = static_cast( aItem ); - return std::make_shared( pad->GetPosition(), pad->GetDrillSize().x / 2 ); - } + PCB_VIA* via = static_cast( aItem ); + return std::make_shared( via->GetCenter(), via->GetDrillValue() / 2 ); + } + else if( aItem->Type() == PCB_PAD_T ) + { + PAD* pad = static_cast( aItem ); + return std::make_shared( pad->GetPosition(), pad->GetDrillSize().x / 2 ); } return std::make_shared( VECTOR2I( 0, 0 ), 0 ); @@ -179,7 +176,7 @@ bool DRC_TEST_PROVIDER_HOLE_TO_HOLE::Run() // holes (which are generally drilled post laminataion). if( via->GetViaType() != VIATYPE::MICROVIA ) { - std::shared_ptr holeShape = getDrilledHoleShape( via ); + std::shared_ptr holeShape = getHoleShape( via ); m_holeTree.QueryColliding( via, Edge_Cuts, Edge_Cuts, // Filter: @@ -221,10 +218,10 @@ bool DRC_TEST_PROVIDER_HOLE_TO_HOLE::Run() if( !reportProgress( ii++, count, progressDelta ) ) return false; // DRC cancelled - // We only care about drilled (ie: round) holes + // We only care about drilled (ie: round) pad holes if( pad->HasDrilledHole() ) { - std::shared_ptr holeShape = getDrilledHoleShape( pad ); + std::shared_ptr holeShape = getHoleShape( pad ); m_holeTree.QueryColliding( pad, Edge_Cuts, Edge_Cuts, // Filter: @@ -276,11 +273,11 @@ bool DRC_TEST_PROVIDER_HOLE_TO_HOLE::testHoleAgainstHole( BOARD_ITEM* aItem, SHA if( !reportCoLocation && !reportHole2Hole ) return false; - std::shared_ptr otherHole = getDrilledHoleShape( aOther ); + std::shared_ptr otherHole = getHoleShape( aOther ); int epsilon = m_board->GetDesignSettings().GetDRCEpsilon(); SEG::ecoord epsilon_sq = SEG::Square( epsilon ); - // Blind-buried or microvias that don't overlap layers aren't an issue. + // Blind-buried vias are drilled prior to stackup; they're only an issue if they share layers if( aItem->Type() == PCB_VIA_T && aOther->Type() == PCB_VIA_T ) { LSET viaHoleLayers = static_cast( aItem )->GetLayerSet() & LSET::AllCuMask(); @@ -306,7 +303,7 @@ bool DRC_TEST_PROVIDER_HOLE_TO_HOLE::testHoleAgainstHole( BOARD_ITEM* aItem, SHA auto constraint = m_drcEngine->EvalRules( HOLE_TO_HOLE_CONSTRAINT, aItem, aOther, UNDEFINED_LAYER /* holes pierce all layers */ ); - int minClearance = constraint.GetValue().Min() - epsilon; + int minClearance = std::max( 0, constraint.GetValue().Min() - epsilon ); if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && minClearance >= 0 diff --git a/pcbnew/pcb_track.h b/pcbnew/pcb_track.h index 15bcf3aa3d..79543edfeb 100644 --- a/pcbnew/pcb_track.h +++ b/pcbnew/pcb_track.h @@ -422,7 +422,7 @@ public: bool HasDrilledHole() const override { - return m_viaType == VIATYPE::THROUGH; + return m_viaType == VIATYPE::THROUGH || m_viaType == VIATYPE::BLIND_BURIED; } std::shared_ptr GetEffectiveHoleShape() const override; diff --git a/pcbnew/tools/board_inspection_tool.cpp b/pcbnew/tools/board_inspection_tool.cpp index 424322a686..3053b3f55d 100644 --- a/pcbnew/tools/board_inspection_tool.cpp +++ b/pcbnew/tools/board_inspection_tool.cpp @@ -1112,7 +1112,7 @@ int BOARD_INSPECTION_TOOL::InspectClearance( const TOOL_EVENT& aEvent ) r->Flush(); } - if( a->HasDrilledHole() && b->HasDrilledHole() ) + if( a->HasDrilledHole() || b->HasDrilledHole() ) { if( !pageAdded ) {