From 32ff242157d4696f2e11f961e6378847dd07a03b Mon Sep 17 00:00:00 2001 From: charras Date: Thu, 8 Apr 2010 11:33:43 +0000 Subject: [PATCH 1/4] Pcbnew: fixed an inconsistency in DRC. (see changelog) fixed others very minor bugs. --- CHANGELOG.txt | 9 ++++++ common/build_version.cpp | 4 +-- gerbview/class_gerbview_layer_widget.cpp | 36 +++++++----------------- packaging/windows/nsis/install.nsi | 2 +- pcbnew/class_board_connected_item.cpp | 20 ++++--------- pcbnew/class_pad.cpp | 25 ++++++++-------- pcbnew/class_pad.h | 8 +++--- pcbnew/class_track.cpp | 16 +++++++++++ pcbnew/class_track.h | 11 ++++++++ pcbnew/dialog_drc.cpp | 1 + pcbnew/drc.cpp | 13 ++++----- 11 files changed, 78 insertions(+), 67 deletions(-) diff --git a/CHANGELOG.txt b/CHANGELOG.txt index b35f1158f5..35eda0bc43 100644 --- a/CHANGELOG.txt +++ b/CHANGELOG.txt @@ -4,6 +4,15 @@ KiCad ChangeLog 2010 Please add newer entries at the top, list the date and your name with email address. +2010-apr-08, UPDATE Jean-Pierre Charras +================================================================================ +++Pcbnew: + Drc: take in account the clearance "local parameters" for pads that have local parameters. + Until now, only NETCLASS clearance values were used. + (local parameters are used in zone filling) + But because a pad (or a footprint) can have a specific clearance value + Drc used now this value, and NETCLASS value only if no local value specified. + 2010-mar-31, UPDATE Jean-Pierre Charras ================================================================================ ++Pcbnew diff --git a/common/build_version.cpp b/common/build_version.cpp index 1c02a3715d..0b6e20f0b4 100644 --- a/common/build_version.cpp +++ b/common/build_version.cpp @@ -6,10 +6,10 @@ #endif #ifndef KICAD_BUILD_VERSION -#define KICAD_BUILD_VERSION "(2010-03-30 SVN 2479)" +#define KICAD_BUILD_VERSION "(2010-04-08 SVN 25xx)" #endif -#define VERSION_STABILITY "final" +#define VERSION_STABILITY "unstable" /** Function GetBuildVersion() * Return the build date and version diff --git a/gerbview/class_gerbview_layer_widget.cpp b/gerbview/class_gerbview_layer_widget.cpp index ffa7d1f9da..5f4e29654f 100644 --- a/gerbview/class_gerbview_layer_widget.cpp +++ b/gerbview/class_gerbview_layer_widget.cpp @@ -76,7 +76,7 @@ GERBER_LAYER_WIDGET::GERBER_LAYER_WIDGET( WinEDA_GerberFrame* aParent, wxWindow* } AppendRenderRows( renderRows, DIM(renderRows) ); - + // Update default tabs labels for gerbview SetLayersManagerTabsText( ); @@ -143,6 +143,7 @@ void GERBER_LAYER_WIDGET::onPopupSelection( wxCommandEvent& event ) int rowCount; int menuId = event.GetId(); bool visible; + int visibleLayers = 0; switch( menuId ) { @@ -153,36 +154,19 @@ void GERBER_LAYER_WIDGET::onPopupSelection( wxCommandEvent& event ) case ID_SHOW_NO_COPPERS: visible = false; L_change_coppers: - int lastCu = -1; rowCount = GetLayerRowCount(); - for( int row=rowCount-1; row>=0; --row ) + for( int row=0; row < rowCount; ++row ) { wxCheckBox* cb = (wxCheckBox*) getLayerComp( row, 3 ); - int layer = getDecodedId( cb->GetId() ); - if( IsValidCopperLayerIndex( layer ) ) - { - lastCu = row; - break; - } + cb->SetValue( visible ); + if( visible ) + visibleLayers |= (1 << row); + else + visibleLayers &= ~(1 << row); } - for( int row=0; rowGetId() ); - - if( IsValidCopperLayerIndex( layer ) ) - { - cb->SetValue( visible ); - - bool isLastCopperLayer = (row==lastCu); - - OnLayerVisible( layer, visible, isLastCopperLayer ); - - if( isLastCopperLayer ) - break; - } - } + myframe->GetBoard()->SetVisibleLayers( visibleLayers ); + myframe->DrawPanel->Refresh(); break; } } diff --git a/packaging/windows/nsis/install.nsi b/packaging/windows/nsis/install.nsi index 8fb0b8363a..975bfaf94d 100644 --- a/packaging/windows/nsis/install.nsi +++ b/packaging/windows/nsis/install.nsi @@ -25,7 +25,7 @@ !define COPYRIGHT "Kicad Team (Jean-Pierre Charras et all)" !define COMMENTS "" !define HELP_WEB_SITE "http://groups.yahoo.com/group/kicad-users/" -!define DEVEL_WEB_SITE "http://groups.yahoo.com/group/kicad-devel/" +!define DEVEL_WEB_SITE "https://launchpad.net/~kicad-developers/" !define WINGS3D_WEB_SITE "http://www.wings3d.com" !define PRODUCT_UNINST_KEY "Software\Microsoft\Windows\CurrentVersion\Uninstall\${PRODUCT_NAME}" diff --git a/pcbnew/class_board_connected_item.cpp b/pcbnew/class_board_connected_item.cpp index 0fc73f42cc..ae89f5f9cd 100644 --- a/pcbnew/class_board_connected_item.cpp +++ b/pcbnew/class_board_connected_item.cpp @@ -78,27 +78,17 @@ int BOARD_CONNECTED_ITEM::GetClearance( BOARD_CONNECTED_ITEM* aItem ) const // and a call to wxASSERT can crash the application. if( myclass ) { + int myClearance = myclass->GetClearance(); // @todo : after GetNetClass() is reliably not returning NULL, remove the - // tests for if( myclass ) and if( hisclass ) + // tests for if( myclass ) if( aItem ) { - NETCLASS* hisclass = aItem->GetNetClass(); - if( hisclass ) - { - int hisClearance = hisclass->GetClearance(); - int myClearance = myclass->GetClearance(); - return max( hisClearance, myClearance ); - } - else - { -#ifdef __WXDEBUG__ - wxLogWarning(wxT("BOARD_CONNECTED_ITEM::GetClearance(): NULL hisclass") ); -#endif - } + int hisClearance = aItem->GetClearance(); + return max( hisClearance, myClearance ); } - return myclass->GetClearance(); + return myClearance; } else { diff --git a/pcbnew/class_pad.cpp b/pcbnew/class_pad.cpp index 042295752e..8eecf909d5 100644 --- a/pcbnew/class_pad.cpp +++ b/pcbnew/class_pad.cpp @@ -201,37 +201,38 @@ void D_PAD::Copy( D_PAD* source ) /** Virtual function GetClearance - * returns the clearance in 1/10000 inches. If \a aItem is not NULL then the - * returned clearance is the greater of this object's NETCLASS clearance and - * aItem's NETCLASS clearance. If \a aItem is NULL, then this objects + * returns the clearance in internal units. If \a aItem is not NULL then the + * returned clearance is the greater of this object's clearance and + * aItem's clearance. If \a aItem is NULL, then this objects * clearance * is returned. * @param aItem is another BOARD_CONNECTED_ITEM or NULL - * @return int - the clearance in 1/10000 inches. + * @return int - the clearance in internal units. */ int D_PAD::GetClearance( BOARD_CONNECTED_ITEM* aItem ) const { + // A pad can have specific clearance parameters that + // overrides its NETCLASS clearance value int clearance = m_LocalClearance; if( clearance == 0 ) - { + { // If local clearance is 0, use the parent footprint clearance value if( GetParent() && ( (MODULE*) GetParent() )->m_LocalClearance ) clearance = ( (MODULE*) GetParent() )->m_LocalClearance; } - if( clearance == 0 ) + if( clearance == 0 ) // If the parent footprint clearance value = 0, use NETCLASS value return BOARD_CONNECTED_ITEM::GetClearance( aItem ); + // We have a specific clearance. + // if aItem, return the biggest clearance if( aItem ) { - NETCLASS* hisclass = aItem->GetNetClass(); - if( hisclass ) - { - int hisClearance = hisclass->GetClearance(); - return max( hisClearance, clearance ); - } + int hisClearance = aItem->GetClearance(); + return max( hisClearance, clearance ); } + // Return the specific clearance. return clearance; } diff --git a/pcbnew/class_pad.h b/pcbnew/class_pad.h index fef7e2b733..d599161c87 100644 --- a/pcbnew/class_pad.h +++ b/pcbnew/class_pad.h @@ -160,12 +160,12 @@ public: /** * Function GetClearance - * returns the clearance in 1/10000 inches. If \a aItem is not NULL then the - * returned clearance is the greater of this object's NETCLASS clearance and - * aItem's NETCLASS clearance. If \a aItem is NULL, then this objects clearance + * returns the clearance in internal units. If \a aItem is not NULL then the + * returned clearance is the greater of this object's clearance and + * aItem's clearance. If \a aItem is NULL, then this objects clearance * is returned. * @param aItem is another BOARD_CONNECTED_ITEM or NULL - * @return int - the clearance in 1/10000 inches. + * @return int - the clearance in internal units. */ virtual int GetClearance( BOARD_CONNECTED_ITEM* aItem = NULL ) const; diff --git a/pcbnew/class_track.cpp b/pcbnew/class_track.cpp index cfff496a3f..9890bb922f 100644 --- a/pcbnew/class_track.cpp +++ b/pcbnew/class_track.cpp @@ -107,6 +107,22 @@ TRACK* TRACK::Copy() const return NULL; // should never happen } +/** Virtual function GetClearance + * returns the clearance in internal units. If \a aItem is not NULL then the + * returned clearance is the greater of this object's clearance and + * aItem's clearance. If \a aItem is NULL, then this objects + * clearance + * is returned. + * @param aItem is another BOARD_CONNECTED_ITEM or NULL + * @return int - the clearance in internal units. + */ +int TRACK::GetClearance( BOARD_CONNECTED_ITEM* aItem ) const +{ + // Currently tracks have no specific clearance parameter + // on a per track or per segment basis. + // the NETCLASS clearance is used + return BOARD_CONNECTED_ITEM::GetClearance( aItem ); +} /** * Function GetDrillValue diff --git a/pcbnew/class_track.h b/pcbnew/class_track.h index 59ce3c3daa..364b8a9264 100644 --- a/pcbnew/class_track.h +++ b/pcbnew/class_track.h @@ -275,6 +275,17 @@ public: return wxT( "TRACK" ); } + /** + * Function GetClearance + * returns the clearance in internal units. If \a aItem is not NULL then the + * returned clearance is the greater of this object's clearance and + * aItem's clearance. If \a aItem is NULL, then this objects clearance + * is returned. + * @param aItem is another BOARD_CONNECTED_ITEM or NULL + * @return int - the clearance in internal units. + */ + virtual int GetClearance( BOARD_CONNECTED_ITEM* aItem = NULL ) const; + #if defined (DEBUG) diff --git a/pcbnew/dialog_drc.cpp b/pcbnew/dialog_drc.cpp index 64e5f3b31c..32819f24f6 100644 --- a/pcbnew/dialog_drc.cpp +++ b/pcbnew/dialog_drc.cpp @@ -551,6 +551,7 @@ void DIALOG_DRC_CONTROL::RedrawDrawPanel() void DIALOG_DRC_CONTROL::DelDRCMarkers() /*********************************************************/ { + m_Parent->SetCurItem( NULL ); // clear curr item, because it could be a DRC marker m_ClearanceListBox->DeleteAllItems(); m_UnconnectedListBox->DeleteAllItems(); } diff --git a/pcbnew/drc.cpp b/pcbnew/drc.cpp index 3d07c84534..8078b32dfc 100644 --- a/pcbnew/drc.cpp +++ b/pcbnew/drc.cpp @@ -704,7 +704,6 @@ bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads ) { TRACK* track; int dx, dy; // utilise pour calcul des dim x et dim y des segments - int w_dist; int layerMask; int net_code_ref; wxPoint shape_pos; @@ -813,7 +812,7 @@ bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads ) D_PAD pseudo_pad( (MODULE*) NULL ); // construct this once outside following loop // Compute the min distance to pads - w_dist = aRefSeg->m_Width >> 1; + int refsegm_half_width = aRefSeg->m_Width >> 1; if( testPads ) { @@ -842,7 +841,7 @@ bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads ) m_spotcx = pseudo_pad.GetPosition().x - org_X; m_spotcy = pseudo_pad.GetPosition().y - org_Y; - if( !checkClearanceSegmToPad( &pseudo_pad, w_dist, netclass->GetClearance() )) + if( !checkClearanceSegmToPad( &pseudo_pad, refsegm_half_width, netclass->GetClearance() )) { m_currentMarker = fillMarker( aRefSeg, pad, DRCE_TRACK_NEAR_THROUGH_HOLE, m_currentMarker ); @@ -863,7 +862,7 @@ bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads ) m_spotcx = shape_pos.x - org_X; m_spotcy = shape_pos.y - org_Y; - if( !checkClearanceSegmToPad( pad, w_dist, aRefSeg->GetClearance( pad ) ) ) + if( !checkClearanceSegmToPad( pad, refsegm_half_width, aRefSeg->GetClearance( pad ) ) ) { m_currentMarker = fillMarker( aRefSeg, pad, DRCE_TRACK_NEAR_PAD, m_currentMarker ); @@ -897,7 +896,7 @@ bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads ) // the minimum distance = clearance plus half the reference track // width plus half the other track's width - w_dist = aRefSeg->GetClearance( track ); + int w_dist = aRefSeg->GetClearance( track ); w_dist += (aRefSeg->m_Width + track->m_Width)/2; // If the reference segment is a via, we test it here @@ -1423,7 +1422,7 @@ exit: // the only way out (hopefully) for simpler debugging } -bool DRC::checkClearanceSegmToPad( const D_PAD* pad_to_test, int w_segm, int dist_min ) +bool DRC::checkClearanceSegmToPad( const D_PAD* pad_to_test, int w_segm, int aMinDist ) { int p_dimx; int p_dimy; // half the dimension of the pad @@ -1432,7 +1431,7 @@ bool DRC::checkClearanceSegmToPad( const D_PAD* pad_to_test, int w_segm, int dis int seuil; int deltay; - seuil = w_segm + dist_min; + seuil = w_segm + aMinDist; p_dimx = pad_to_test->m_Size.x >> 1; p_dimy = pad_to_test->m_Size.y >> 1; From d5775f0d93a7f27bea1133589ba92087ce1826bc Mon Sep 17 00:00:00 2001 From: dickelbeck Date: Fri, 9 Apr 2010 13:06:28 +0000 Subject: [PATCH 2/4] This file, kicad_export.xml, was a snapshot made today of the entire sourceforge website. It includes the tracker items: Bugs, Feature Requests, etc. And it includes the forum items. We have it here as a historical record, and bits and pieces should migrate into appropriate storage resources on the new launcpad site. --- Documentation/kicad_export.xml | 32286 +++++++++++++++++++++++++++++++ 1 file changed, 32286 insertions(+) create mode 100644 Documentation/kicad_export.xml diff --git a/Documentation/kicad_export.xml b/Documentation/kicad_export.xml new file mode 100644 index 0000000000..88dfdf9356 --- /dev/null +++ b/Documentation/kicad_export.xml @@ -0,0 +1,32286 @@ + + + + + + + + + + +145591 +kicad +dickelbeck + + +http://sourceforge.net/projects/kicad/ +145591 +kicad +Kicad EDA +Kicad EDA is an open source (GPL) software for the creation of electronic schematic diagrams and printed circuit board artwork. +gpl +http://kicad.sourceforge.net +This software (using WXWIDGETS) is MULTI-PLATFORM. It is running under LINUX, Windows (XP or 2000), FreeBSD and Solaris. +Kicad written on C++ using Gcc, wxWidgets (wxwidgets.org), GTK (www.gtk.org) and Mesa (www.mesa3d.org). +Documentation maked in OpenOfficeOrg. +3D shapes of Pcbnew footprints maked in Wings3D (www.wings3d.com). +Kicad can solve problems of electronic hardware designers as free CAD package, complete and with a professional standard. +Kicad is a sofware suite which consists from + Eeschema :Schematic entry. + Pcbnew :Board editor. + Gerbview :GERBER viewer (photoplotter documents). + Cvpcb :footprint selector for components used in the circuit design. + Kicad: project manager. + +The original homepage of software is http://www.lis.inpg.fr/realise_au_lis/kicad/ +plyatov +1123423800 + + +http://sourceforge.net/users/kintel/ +145718 +kintel +Marius Kintel +kintel@users.sourceforge.net +No + + +http://sourceforge.net/users/diemer/ +154672 +diemer +Jonas Diemer +diemer@users.sourceforge.net +No + + +http://sourceforge.net/users/bennett78/ +464167 +bennett78 +Frank Bennett +bennett78@users.sourceforge.net +No + + +http://sourceforge.net/users/manneveru/ +639576 +manneveru +Michał Fita +manneveru@users.sourceforge.net +No + + +http://sourceforge.net/users/strangeril/ +1196510 +strangeril +Milan Horák +strangeril@users.sourceforge.net +No + + +http://sourceforge.net/users/vesa_solonen/ +1207241 +vesa_solonen +Vesa Solonen +vesa_solonen@users.sourceforge.net +No + + +http://sourceforge.net/users/raburton/ +1213654 +raburton +rab +raburton@users.sourceforge.net +No + + +http://sourceforge.net/users/dickelbeck/ +1222857 +dickelbeck +Dick Hollenbeck +dickelbeck@users.sourceforge.net +Yes + + +http://sourceforge.net/users/goutnet/ +1283799 +goutnet +Florian Delizy +goutnet@users.sourceforge.net +No + + +http://sourceforge.net/users/charras/ +1293228 +charras +jp-charras +charras@users.sourceforge.net +No + + +http://sourceforge.net/users/plyatov/ +1325376 +plyatov +Igor Plyatov +plyatov@users.sourceforge.net +Yes + + +http://sourceforge.net/users/f3nix/ +1459455 +f3nix +Mateusz Skowroński +f3nix@users.sourceforge.net +No + + +http://sourceforge.net/users/aircraft/ +1777188 +aircraft +aircraft +aircraft@users.sourceforge.net +No + + +http://sourceforge.net/users/faa/ +1805271 +faa +faa +faa@users.sourceforge.net +Yes + + +http://sourceforge.net/users/messo/ +1810278 +messo +Messo +messo@users.sourceforge.net +No + + +http://sourceforge.net/users/lifekidyeaa/ +1811176 +lifekidyeaa +Tim Hanson +lifekidyeaa@users.sourceforge.net +No + + +http://sourceforge.net/users/g_harland/ +1848371 +g_harland +Geoff Harland +g_harland@users.sourceforge.net +No + + +http://sourceforge.net/users/reniemarquet/ +1894170 +reniemarquet +Renie S. Marquet +reniemarquet@users.sourceforge.net +No + + +http://sourceforge.net/users/a-lunev/ +1930733 +a-lunev +Alexander Lunev +a-lunev@users.sourceforge.net +No + + +http://sourceforge.net/users/kajtek1/ +1935577 +kajtek1 +Kajtek1 +kajtek1@users.sourceforge.net +No + + +http://sourceforge.net/users/stambaughw/ +1994912 +stambaughw +Wayne Stambaugh +stambaughw@users.sourceforge.net +No + + +http://sourceforge.net/users/klui_/ +2007962 +klui_ +Vladimir Kalyaev +klui_@users.sourceforge.net +No + + +http://sourceforge.net/users/george_han/ +2010903 +george_han +George Han +george_han@users.sourceforge.net +No + + +http://sourceforge.net/users/peud/ +2031753 +peud +Per Uddén +peud@users.sourceforge.net +No + + +http://sourceforge.net/users/jerryjacobs/ +2066563 +jerryjacobs +Jerry Jacobs +jerryjacobs@users.sourceforge.net +No + + +http://sourceforge.net/users/drannou/ +2488236 +drannou +Damien RANNOU +drannou@users.sourceforge.net +No + + +http://sourceforge.net/users/vovanium/ +2728450 +vovanium +Vladimir Uryvaev +vovanium@users.sourceforge.net +No + + +http://sourceforge.net/users/viknn/ +2800567 +viknn +Yuri Vikulov +viknn@users.sourceforge.net +No + + +http://sourceforge.net/users/emmedics4/ +2808437 +emmedics4 +Marco Serantoni +emmedics4@users.sourceforge.net +No + + + + +No +Yes +No +Yes +No +No + + +487027 +Open Discussion + +Yes + + +487028 +Help + +Yes + + +487029 +Developers + +No + + + + +762476 +Bugs +Bug Tracking System +All site users +Yes + + +762477 +Support Requests +Tech Support Tracking System +All site users +Yes + + +762478 +Patches +Patch Tracking System +All site users +Yes + + +762479 +Feature Requests +Feature Request Tracking System +All site users +Yes + + + + +57666 +kicad-svnnotify +Yes + + + + + +Translations :: Slovene +Translations :: Dutch +Translations :: Korean +Translations :: Hungarian +Translations :: German +Translations :: Czech +Translations :: Catalan +Intended Audience :: by Industry or Sector :: Engineering +User Interface :: Toolkits/Libraries :: wxWidgets +Translations :: English +Translations :: French +Translations :: Russian +Translations :: Spanish +Translations :: Portuguese +Programming Language :: C++ +Development Status :: 5 - Production/Stable +License :: OSI-Approved Open Source :: GNU General Public License (GPL) +Topic :: Scientific/Engineering :: Electronic Design Automation (EDA) +Operating System :: Grouping and Descriptive Categories :: 32-bit MS Windows (NT/2000/XP) +Operating System :: Grouping and Descriptive Categories :: All POSIX (Linux/BSD/UNIX-like OSes) +Translations :: Italian +Translations :: Croatian +Translations :: Chinese (Simplified) +Translations :: Polish +Programming Language :: C++ +Development Status :: 2 - Pre-Alpha +Programming Language :: Lua +Topic :: Games/Entertainment :: Real Time Strategy +User Interface :: Toolkits/Libraries :: SDL +License :: OSI-Approved Open Source :: GNU General Public License (GPL) + + + + + + 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+http://sourceforge.net/projects/kicad/forums/forum/487027 +487027 +Open Discussion +Yes + + +No + + +http://sourceforge.net/projects/kicad/forums/forum/487027/topic/3242243?message=7283516 +7283516 +broran +bror eriksson +autorouter to KiCAD +3242243 +0 +0 +1240665685 +No +what about a Opensource auto router to KiCAD? Like Wat's available at http://web.ift.uib.no/~bruce/eda1.htm#nevin + + +http://sourceforge.net/projects/kicad/forums/forum/487027/topic/3170961?message=7068720 +7068720 +beerslayer +The Beerslayer +Import from OrCAD? +3170961 +0 +0 +1238824114 +No +Hi - I'm not personally a CAD user so I don't know the technical details, but my father uses OrCAD (v9, I believe) at his job. I'd like to see if perhaps Kicad will do the job he needs to do, but he has a LOT of old files in OrCAD format that he needs to be able to access and, in some cases, edit or modify. I believe the extension on these files is .prj, but I'm not 100% sure. + +Is there currently any way within Kicad to import these files directly? If not, is there another open source app that can do this? Or is there possibly some intermediate format that this version of OrCAD can export that Kicad (or other open source converter) can read? + +Failing all of that, does Kicad support any kind of add-on structure (other than hacking its own sources) for producing some sort of plugin that might offer this functionality? + + +http://sourceforge.net/projects/kicad/forums/forum/487027/topic/1332066?message=4944948 +4944948 +xcskier +skier +How to get wxmsw28u_gcc_custom.dll ? +1332066 +3285326 +0 +1209954241 +No +I've downloaded kicad-20080504-41027-win32.zip, +& unzipped it. + +Please tell me where I can find + +wxmsw28u_gcc_custom.dll + +Thank you +Dave +mcquate (at) sonic (dot) net + + +http://sourceforge.net/projects/kicad/forums/forum/487027/topic/1332066?message=3285326 +3285326 +nobody +Nobody/Anonymous +Welcome to Open Discussion +1332066 +0 +1 +1123520471 +No +Welcome to Open Discussion + + + + +http://sourceforge.net/projects/kicad/forums/forum/487028 +487028 +Help +Yes + + +No + + +http://sourceforge.net/projects/kicad/forums/forum/487028/topic/3480879?message=7801578 +7801578 +stefanl38 +Stefan L38 +most efficient way to add devices +3480879 +0 +0 +1260103227 +No +Hello, + +I would like to know what is the most efficient way to add devices to a schematic + +right now I know only of + +1) click on schematic: window choose opens +2) Click on librarybrowser +3) Click on device name +4) Click on add to schematic +5) place device on schematic + +five clicks that's 3 clicks too much. +How can I do this in that way ? + +Doubleclick for choose - leftclick for placing +Doubleclick for choose - leftclick for placing + +Or is there only the workaoriund of having a template where all important devices are placed in one edge and then copy and paste them ? + +best regards + +Stefan + + +http://sourceforge.net/projects/kicad/forums/forum/487028/topic/3334371?message=7503044 +7503044 +jenningsthecat +jenningsthecat +Net names display in PcbNew +3334371 +0 +0 +1247615452 +No +Is there a way to turn off the net names display in PcbNew? I've looked through all of the config menus and have been unable to find it. If I can't turn this 'feature' off I'll have to go back to an earlier version! + + +http://sourceforge.net/projects/kicad/forums/forum/487028/topic/3334254?message=7502873 +7502873 +jerryjacobs +Jerry Jacobs +RE: Net names display in PcbNew +3334254 +7502829 +0 +1247607325 +No +In last SVN version it is no problem to turn this off, +Look at Preferences -> Display -> Netnames. + + +http://sourceforge.net/projects/kicad/forums/forum/487028/topic/3334254?message=7502829 +7502829 +jenningsthecat +jenningsthecat +Net names display in PcbNew +3334254 +0 +1 +1247606519 +No +Is there a way to turn off the net names display in PcbNew? I've looked through all of the config menus and have been unable to find it. If I can't turn this 'feature' off I'll have to go back to an earlier version! + + +http://sourceforge.net/projects/kicad/forums/forum/487028/topic/3066958?message=6631783 +6631783 +jgmejiah +juan +Adding rats from pcbnew +3066958 +0 +0 +1236194765 +No +Hi, + +Is there any way to add rats from PCBnew? Do I always have to make a schematic (or a netlist) before using PCBnew? For some designs it could be faster to design just the PCB and I see no tool for adding rats. + +Thanks a lot + + +http://sourceforge.net/projects/kicad/forums/forum/487028/topic/2156310?message=5152057 +5152057 +cablik +Jan Cablik +Same length of the bus nets +2156310 +0 +0 +1218098684 +No +Hi, I'm new to KiCAD. At this moment I'm looking for an alternative to OrCAD 9.2. +I make designs with DDR2 memories and I need their bus signals to be aligned to the same length (with a small allowed tolerance). Is it possible with KiCAD to set a rule that autorouted and/or hand-drawn nets should be aligned to the same length (automatically, or notify me of the current and desired length}. I searched through the manuals but was not able to find anything about this. + +Jan + + +http://sourceforge.net/projects/kicad/forums/forum/487028/topic/1882263?message=4652136 +4652136 +di2 +di2 +fiducials +1882263 +0 +0 +1196442067 +No +Hi, +how do I make fiducials? +I need to make the clearance for the soldermask bigger than standard. +Thanks, +di2 + + +http://sourceforge.net/projects/kicad/forums/forum/487028/topic/1332067?message=3285327 +3285327 +nobody +Nobody/Anonymous +Welcome to Help +1332067 +0 +0 +1123520472 +No +Welcome to Help + + + + +http://sourceforge.net/projects/kicad/forums/forum/487029 +487029 +Developers +No + + +No + + +http://sourceforge.net/projects/kicad/forums/forum/487029/topic/1332068?message=3285328 +3285328 +nobody +Nobody/Anonymous +Welcome to Developers +1332068 +0 +0 +1123520472 +No +Welcome to Developers + + + + + + +http://sourceforge.net/?group_id=145591&atid=762476 +762476 +Bugs +Bug Tracking System +All site users +Yes +No +2592000 + + +1209600 +0 +0 +0 + + +5497 +Bug Fixed +This bug has been fixed +Active + + + + + + + +516020 +Windows XP + + +755196 +Linux + + +755197 +Mac + + +755198 +Any + + +1083286 + + + +1083307 +Windows Vista + + +1083308 +Windows 7 + + + + +761682 +PCBnew +nobody + + +1015285 +EESchema +nobody + + +1015286 +KiCad +nobody + + +1015287 +GerbView +nobody + + +1015288 +CVpcb +nobody + + + + +1 +Fixed + + +2 +Invalid + + +3 +Wont Fix + + +4 +Later + + +5 +Remind + + +6 +Works For Me + + +100 +None + + +101 +Duplicate + + +102 +Accepted + + +103 +Out of Date + + +104 +Postponed + + +105 +Rejected + + + + +1 +Open + + +2 +Closed + + +3 +Deleted + + +4 +Pending + + + + +http://sourceforge.net/support/tracker.php?aid=1635789 +1635789 +3 +761682 +100 +100 +cyrilbuttay +nobody +dickelbeck +1168860204 +1188591390 +5 +naming problem in EEschema +
Hi, + +I'm running kicad RC2 2007-01-03, and I noted the following (strange behaviour). I'm not a regular user of Kicad, so maybe it is not related to this version: + +When I add a resistor (R), if I click on "edit component/edit", I have a Chip Name field "R" and a value "R?" (in the "component properties" window). But if I click on "edit component/value", the windows that opens returns "R", and "edit component/reference" returns "R". + +Furthermore, in "edit component/edit", if I change the value from R? to, for example 1k, the reference of the component changes on the schematic, not its value, and if I change the "chip name" from "R" to 1k, I have an error message ("component [1k] not found"). + +Also, if I right click exactly in the middle of the resistor, the only choice I have under "edit component" is "edit", nothing else. Is that normal? + +Thank you for your work + +Regards + +Cyril
+0 + + +2466685 +dickelbeck +1187413511 +
Logged In: YES +user_id=1222857 +Originator: NO + +This seems to be fixed now. Please re-submit if still present in latest software.
+ + +2469757 +dickelbeck +1187708591 +
Logged In: YES +user_id=1222857 +Originator: NO + +This seems to be fixed in later releases. Re-submit if its still a problem.
+ + + + + + +4936480 +IP +Comment Added: 67.64.64.34 +1187413511 +dickelbeck + + +4947886 +IP +Comment Added: 67.64.64.34 +1187708591 +dickelbeck + + +4947900 +status_id +1 +1187708697 +dickelbeck + + +4947901 +close_date +0 +1187708697 +dickelbeck + + +4990238 +status_id +2 +1188591390 +dickelbeck + + +4990239 +close_date +1187708697 +1188591390 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=1786007 +1786007 +3 +761682 +755198 +100 +dickelbeck +nobody +dickelbeck +1188591968 +1228758316 +5 +Grid color change not working +
You can change the grid color on the Colors Preferences panel and it has no effect on the grid color. + +share/drawpanel.cpp is using g_GridColor and not g_PcbGridColor. + +
+0 + + +2511928 +dickelbeck +1191349907 +
Logged In: YES +user_id=1222857 +Originator: YES + +This bug has been fixed
+ + + + + + +4990288 +IP +Artifact Created: 67.64.64.34 +1188591968 +dickelbeck + + +5114086 +status_id +1 +1191349742 +dickelbeck + + +5114087 +close_date +0 +1191349742 +dickelbeck + + +5114097 +IP +Comment Added: 67.64.64.34 +1191349907 +dickelbeck + + +7157900 +status_id +2 +1228758316 +dickelbeck + + +7157901 +close_date +1191349742 +1228758316 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=1798419 +1798419 +2 +1015288 +755198 +100 +bennett78 +nobody +sf-robot +1190237318 +1231208426 +5 +editor munges long pin names +
Netlist editor munges pin names +greater than 4 characters. + +to Reproduce: + read bugin.net - note name COLLECTOR, CATHODE, etc + write out.net + +Attached bug.zip +bugin.net +bugout.net
+0 + + +2502326 +dickelbeck +1190516244 +
Logged In: YES +user_id=1222857 +Originator: NO + +The data structures which hold the pin names only allow for 4 characters. Would you be happy if you could not input longer names, thus you would get an early warning that names are limited to 4 characters? Or should the data structure be expanded to handle longer names, and if so how long? + +As it stands, this is probably not a bug, but a feature request. +
+ + +2503755 +bennett78 +1190655724 +
Logged In: YES +user_id=464167 +Originator: YES + +The long name should probably be truncated. It also seems to stomp +on the Reference Designator. + +This doesn't look like a problem in EEschem or pcbnew? (I didn't +check pcbnew) + +I did notice that a footprint can be assigned (backannotated?) in +EEschem, although not a nice as the footprint viewer in CVPCB. + +I think some users would prefer that the CVPCB function exist in EEschem.
+ + +3285867 +sf-robot +1231208426 +
This Tracker item was closed automatically by the system. It was +previously set to a Pending status, and the original submitter +did not respond within 14 days (the time period specified by +the administrator of this Tracker).
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=246370&aid= +246370 +bug.zip +netlist in, out +649 +application/x-zip-compressed +1190237319 +bennett78 + + + + +5064071 +IP +Artifact Created: 199.3.246.231 +1190237319 +bennett78 + + +5064072 +File Added +246370: bug.zip +1190237319 +bennett78 + + +5077381 +IP +Comment Added: 67.64.64.34 +1190516244 +dickelbeck + + +5082760 +IP +Comment Added: 199.3.246.231 +1190655724 +bennett78 + + +7157875 +status_id +1 +1228758211 +dickelbeck + + +7157876 +close_date +0 +1228758211 +dickelbeck + + +7157892 +status_id +2 +1228758271 +dickelbeck + + +7157893 +close_date +1228758211 +1228758271 +dickelbeck + + +7368962 +IP +Comment Added: +1231208426 +sf-robot + + +7368963 +status_id +4 +1231208426 +sf-robot + + +7368964 +close_date +1228758271 +1231208426 +sf-robot + + + + +http://sourceforge.net/support/tracker.php?aid=1800438 +1800438 +1 +761682 +100 +100 +dickelbeck +nobody +nobody +1190516361 +0 +4 +Block copy is moving footprints on an invisible layer +
The block copy command is grabbing footprints from a layer which is currently set to invisible. This is a seriously dangerous bug, because it can wipe out hours of work. +
+0 + + +2582021 +nobody +1196925024 +
Logged In: NO + +Track, via and text can be move too.
+ + + + + + +5077383 +IP +Artifact Created: 67.64.64.34 +1190516361 +dickelbeck + + +5354187 +priority +9 +1196875472 +dickelbeck + + +5356089 +IP +Comment Added: 217.150.32.243 +1196925024 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1812554 +1812554 +2 +1015285 +755198 +100 +sfabris +nobody +sf-robot +1192223155 +1208139613 +5 +Erc reports warnings about non connected wires +
Erc check report pins as non connected. +Netlist and Pcbnew show the pins as regolary connected. + +Tried both with win and Linux version, SVN build and last stable release. + +If necessary I can give more help to try to find the bug (if any). + +Thanks, + +Simone
+0 + + +2723115 +diemer +1206891097 +
Logged In: YES +user_id=154672 +Originator: NO + +Please provide a complete schematic or at least the exact output of ERC.
+ + +2739523 +sf-robot +1208139613 +
Logged In: YES +user_id=1312539 +Originator: NO + +This Tracker item was closed automatically by the system. It was +previously set to a Pending status, and the original submitter +did not respond within 14 days (the time period specified by +the administrator of this Tracker).
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=249438&aid= +249438 +example.jpg +Example of what described. +68567 +image/jpeg +1192223155 +sfabris + + + + +5152236 +IP +Artifact Created: 151.65.2.75 +1192223155 +sfabris + + +5152237 +File Added +249438: example.jpg +1192223155 +sfabris + + +5833726 +IP +Comment Added: 82.83.232.41 +1206891097 +diemer + + +5833727 +status_id +1 +1206891097 +diemer + + +5833728 +close_date +0 +1206891097 +diemer + + +5895185 +IP +Comment Added: +1208139613 +sf-robot + + +5895186 +status_id +4 +1208139613 +sf-robot + + +5895187 +close_date +1206891097 +1208139613 +sf-robot + + + + +http://sourceforge.net/support/tracker.php?aid=1817455 +1817455 +2 +100 +516020 +100 +djsbriscoe +nobody +dickelbeck +1192994631 +1194011858 +5 +Tooltips and status bar info not displayed. +
Tooltips and status bar info is not displayed in EEschema ,CVPCB, PCBnew or gerbview. +I'm using the latest SVN snapshot in Windows 2000 sp4.
+0 + + +2537603 +djsbriscoe +1193571098 +
Logged In: YES +user_id=1047261 +Originator: YES + +Problem appears to have gone away in latest snapshots.
+ + + + + + +5183404 +IP +Artifact Created: 82.18.200.240 +1192994631 +djsbriscoe + + +5207376 +IP +Comment Added: 82.18.206.122 +1193571098 +djsbriscoe + + +5229275 +status_id +1 +1194011858 +dickelbeck + + +5229276 +close_date +0 +1194011858 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=1820057 +1820057 +3 +1015288 +100 +100 +ckgrier2 +nobody +ckgrier2 +1193326522 +1193327717 +5 +Viewing Modules from Footprint list +
When using CVPCB to select footprints it is helpful to see the modules in the "View Selected Part" window. + +However, if the cursor is placed on the footprint list, and the user attempts to cursor through the available footprints, the window "focus" shifts to each new footprint as it is displayed. This is counter-intuitive, since the up and down cursor action doesn't seem to warrant a change in window "focus". + +I don't know if this is an wxWidgets thing... but telling the "view" window to update with a new footprint shouldn't cause the CVPCB window to loose focus. Pressing the down arrow three times should move the cursor down three lines.
+0 + + + + + + +5198599 +IP +Artifact Created: 74.160.34.198 +1193326522 +ckgrier2 + + +5198701 +status_id +1 +1193327717 +ckgrier2 + + +5198702 +close_date +0 +1193327717 +ckgrier2 + + + + +http://sourceforge.net/support/tracker.php?aid=1820072 +1820072 +2 +1015288 +100 +100 +ckgrier2 +nobody +strangeril +1193327535 +1193610551 +5 +Viewing Modules from Footprint list +
When using CVPCB to select footprints it is helpful to see the modules in the "View Selected Part" window. + +However, if the cursor is placed on the footprint list, and the user attempts to cursor through the available footprints, the window "focus" shifts to each new footprint as it is displayed. This is counter-intuitive, since the up and down cursor action doesn't seem to warrant a change in window "focus". + +I don't know if this is an wxWidgets thing... but telling the "view" window to update with a new footprint shouldn't cause the CVPCB window to loose focus. Pressing the down arrow three times should move the cursor down three lines.
+0 + + +2535325 +nobody +1193363773 +
Logged In: NO + +It happens on the Windos build from September 22. I don't see the same problem with the Linux build from Jan. 15th
+ + +2535968 +strangeril +1193405929 +
Logged In: YES +user_id=1196510 +Originator: NO + +There is no official svn-snapshot from September 22th. + +Can you please test it with latest svn-snapshot (20071015-r336). + +I'll also test it on my computer at home so please be patient.
+ + +2538007 +ckgrier2 +1193603868 +
Logged In: YES +user_id=1921682 +Originator: YES + +No issues now. It works. Thanks.
+ + + + + + +5198680 +IP +Artifact Created: 74.160.34.198 +1193327535 +ckgrier2 + + +5200216 +IP +Comment Added: 68.158.5.158 +1193363773 +nobody + + +5202061 +IP +Comment Added: 194.108.201.110 +1193405929 +strangeril + + +5208799 +IP +Comment Added: 68.158.5.158 +1193603868 +ckgrier2 + + +5208991 +status_id +1 +1193610551 +strangeril + + +5208992 +close_date +0 +1193610551 +strangeril + + + + +http://sourceforge.net/support/tracker.php?aid=1823001 +1823001 +2 +1015288 +100 +100 +plyatov +charras +dickelbeck +1193774372 +1194011980 +5 +cvpcb closed when Netlist and Cmp files saved. +
The cvpcb program closed accidentally when user save the NetList and Components files. +The files saved successfully, but the program closed for unknown reason.
+0 + + +2541259 +charras +1193830078 +
Logged In: YES +user_id=1293228 +Originator: NO + +This is not a bug, this is a feature ... + +J-P. Charras
+ + +2544149 +dickelbeck +1194011980 +
Logged In: YES +user_id=1222857 +Originator: NO + +Seems to be a difference of opinion, I'm closing the bug for now. It can be moved by reporter to the enhancement list if he wants, but it looks like nothing will be done about it.
+ + + + + + +5217212 +IP +Artifact Created: 217.106.91.42 +1193774372 +plyatov + + +5219639 +IP +Comment Added: 86.193.9.209 +1193830078 +charras + + +5229278 +IP +Comment Added: 67.64.64.34 +1194011980 +dickelbeck + + +5229279 +status_id +1 +1194011980 +dickelbeck + + +5229280 +close_date +0 +1194011980 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=1828485 +1828485 +2 +1015286 +755198 +1 +lainal +dickelbeck +dickelbeck +1194551507 +1196874372 +1 +makefile.include: bad compiler directive +
Some rules refer to the compiler $(CC) instead of $(CXX). +With non-GCC compilers, this prevents C++ code to be built. +Same occurs in makefile.include files of the others targets, i.e. PCBNEW, EESCHEMA, CVPCB and GERBVIEW
+0 + + +2581362 +dickelbeck +1196874372 +
Logged In: YES +user_id=1222857 +Originator: NO + +I think I fixed this two weeks ago.
+ + + + + + +5252962 +IP +Artifact Created: 217.226.73.94 +1194551507 +lainal + + +5253071 +priority +5 +1194553071 +lainal + + +5354058 +IP +Comment Added: 67.64.64.34 +1196874372 +dickelbeck + + +5354059 +status_id +1 +1196874372 +dickelbeck + + +5354060 +resolution_id +100 +1196874372 +dickelbeck + + +5354061 +assigned_to +100 +1196874372 +dickelbeck + + +5354062 +close_date +0 +1196874372 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=1828487 +1828487 +2 +761682 +100 +3 +lainal +nobody +dickelbeck +1194551771 +1196875751 +1 +3D-viewer ANSI C++ code boken +
In source file 3d_canvas.cpp, the constructor Pcb3D_GLCanvas::Pcb3D_GLCanvas should have a "const wxWindowsID id parameter". +The missing "const" prevents the compilation to succeeds on non-GCC C++ compilers
+0 + + +2551700 +nobody +1194596144 +
Logged In: NO + +Actioned in Revision 439
+ + +2551702 +g_harland +1194596480 +
Logged In: YES +user_id=1848371 +Originator: NO + +Actioned in Revision 439
+ + +2581402 +dickelbeck +1196875750 +
Logged In: YES +user_id=1222857 +Originator: NO + +submit a diff generated patch to the developers list and if it does not break the g++ compile, we will use it. Generally there's no commitment to support any non g++ compiler. Unless that person steps up, he is no where to be found currently.
+ + + + + + +5252980 +IP +Artifact Created: 217.226.73.94 +1194551771 +lainal + + +5254740 +IP +Comment Added: 58.106.1.84 +1194596144 +nobody + + +5254744 +IP +Comment Added: 58.106.1.84 +1194596480 +g_harland + + +5354196 +IP +Comment Added: 67.64.64.34 +1196875750 +dickelbeck + + +5354197 +status_id +1 +1196875750 +dickelbeck + + +5354198 +resolution_id +100 +1196875751 +dickelbeck + + +5354199 +priority +5 +1196875751 +dickelbeck + + +5354200 +close_date +0 +1196875751 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=1828499 +1828499 +2 +1015286 +755198 +3 +lainal +nobody +dickelbeck +1194553011 +1196874162 +5 +EXCHG macro dedicated to GCC +
In include/macros.h, the definition of EXCHG(a,b) is not valid in other compilers than G++ which don't have the GCC's "typeof" extension. + +A small update I use is the following: + +#ifdef __GNUC__ +#define EXCHG(a,b) { typeof(a) __temp__ = (a); (a) = (b); (b) = __temp__; } +#else +/* --Dom: typeof not always existing outside gcc world */ +#define EXCHG(a,b) { \ +size_t __nb__ = sizeof( (a) ); \ +void *__temp__ = malloc( __nb__ ); \ +memcpy( __temp__ , (void*)&(b), __nb__ ); \ +memcpy( (void*)&(b), (void*)&(a), __nb__ ); \ +memcpy( (void*)&(a), __temp__ , __nb__ ); \ +free (__temp__); \ +} +#endif
+0 + + +2581355 +dickelbeck +1196874038 +
Logged In: YES +user_id=1222857 +Originator: NO + +duplicate of 1844285 +
+ + + + + + +5253066 +IP +Artifact Created: 217.226.73.94 +1194553011 +lainal + + +5354013 +IP +Comment Added: 67.64.64.34 +1196874038 +dickelbeck + + +5354014 +resolution_id +100 +1196874038 +dickelbeck + + +5354033 +status_id +1 +1196874162 +dickelbeck + + +5354034 +close_date +0 +1196874162 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=1829931 +1829931 +2 +1015285 +755198 +1 +plyatov +diemer +diemer +1194788228 +1207252172 +5 +Incorrect area zooming in eeschema +
If user try to zoom an area (by middle mouse button dragging or from a context menu), then zoomed area displayed only partially. +If eeschema window is maximized then correct area zooming occurs more often. +This problem can be easy investigated on a rectangular objects, which user want to zoom. + +My system is: + Gentoo Linux + wxWidgets 2.6.4 + KiCad SVN r454
+0 + + +2728551 +diemer +1207252172 +
Logged In: YES +user_id=154672 +Originator: NO + +I just improved that behavior in r969, so the area shown after zooming includes at least the selected rectangle (rather than zooming too far in as it was the case in earlier versions). Zooming more accurately is not possible (currently), because we can only zoom in fixed steps. + +-> Bug fixed.
+ + + + + + +5261211 +IP +Artifact Created: 217.106.91.42 +1194788228 +plyatov + + +5856067 +IP +Comment Added: 82.83.174.232 +1207252172 +diemer + + +5856068 +status_id +1 +1207252172 +diemer + + +5856069 +resolution_id +100 +1207252172 +diemer + + +5856070 +artifact_group_id +755196 +1207252172 +diemer + + +5856071 +assigned_to +1293228 +1207252172 +diemer + + +5856072 +close_date +0 +1207252172 +diemer + + + + +http://sourceforge.net/support/tracker.php?aid=1830005 +1830005 +1 +100 +100 +100 +plyatov +charras +nobody +1194799913 +0 +5 +Duplicate pins was not detected in LibEdit +
If user makes a component with identical pins without enabled property "Common to parts" in different parts, then function "Test duplicate pins" always reports "Pins test OK!". + +This function must reports error if component contains pins with identical "Pin Number" and without enabled property "Common to parts".
+0 + + + + + + +5261621 +IP +Artifact Created: 217.106.91.42 +1194799914 +plyatov + + +5261672 +assigned_to +100 +1194800726 +plyatov + + + + +http://sourceforge.net/support/tracker.php?aid=1831005 +1831005 +2 +1015285 +755196 +6 +sunnysan +diemer +diemer +1194951225 +1206890913 +5 +ERC error to well connected grd +
When I do the erc test I got the ground connected to a wire which gives me a error. +ERC shows/thinks that the ground (GND) of the circuit is not connected, although I rewired it many times and even to deleted the ground to put a new one. +But the ERC still shows me the arrow (on the GND) thinking that it is not connected + +Sunny San + +My version of KiCad +Build Version: +KiCad (2007-05-25) - Unicode version +under Ubuntu 7.10 + +erc file content below + +ERC control (13/11/2007-10:37:36) + +***** Sheet 1 (Root) +ERC: Warning Pin power_in not driven (Net 1) (X= 7.750 inches, Y= 2.400 inches + + >> Errors ERC: 1
+0 + + +2636524 +nobody +1200571735 +
Logged In: NO + +I confirm the above behaviour, exactly the same problem. + +I have a GND power pin in three places (they are in the same net) and the are grouped by this three GND power items. + +I noticed in ERC that always warned the first one to be disconnected. Well I cleared wire and power and replaced both wire and power. Then ERC warned in one of the other two power items: there's always one power with warning. +
+ + +2723112 +diemer +1206890913 +
Logged In: YES +user_id=154672 +Originator: NO + +That behavior is normal. ERC requires Power pins to be driven by something (e.g. a voltage regulator). If your circuit does not include such a device, you need to add a Power_Flag to the corresponding net, see attached file. This is also in the Manual (chapter 7 - ERC).
+ + +2723114 +diemer +1206890952 +
Logged In: YES +user_id=154672 +Originator: NO + +That behavior is normal. ERC requires Power pins to be driven by something (e.g. a voltage regulator). If your circuit does not include such a device, you need to add a Power_Flag to the corresponding net, see attached file. This is also in the Manual (chapter 7 - ERC). +File Added: test003-fixed.sch
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=254078&aid= +254078 +test003.sch +schematic file +3351 +application/x-extension-sch +1194951225 +sunnysan + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=272502&aid= +272502 +test003-fixed.sch +schematic with power flag. +3874 +application/octet-stream +1206890952 +diemer + + + + +5268453 +IP +Artifact Created: 81.137.78.73 +1194951225 +sunnysan + + +5268454 +File Added +254078: test003.sch +1194951226 +sunnysan + + +5523226 +IP +Comment Added: 87.235.48.116 +1200571735 +nobody + + +5833705 +IP +Comment Added: 82.83.232.41 +1206890913 +diemer + + +5833706 +status_id +1 +1206890913 +diemer + + +5833707 +resolution_id +100 +1206890913 +diemer + + +5833708 +assigned_to +100 +1206890913 +diemer + + +5833709 +close_date +0 +1206890913 +diemer + + +5833715 +File Added +272502: test003-fixed.sch +1206890952 +diemer + + +5833716 +IP +Comment Added: 82.83.232.41 +1206890953 +diemer + + + + +http://sourceforge.net/support/tracker.php?aid=1832187 +1832187 +2 +761682 +100 +102 +ckgrier2 +dickelbeck +ckgrier2 +1195092530 +1200507454 +5 +Module Editor asks twice for Selection Clarification +
Using module Editor on Windows 10-29-07 version. + +Erasing graphic lines near pads, left-click pops up a Selection Clarification window (as expected). Selecting the line brings up a duplicate Clarifcation window, and requires a second selection. + +I don't know why it is asking twice, but it shouldn't. :) + +(Have not tested on Linux version yet.)
+0 + + +2581387 +dickelbeck +1196875114 +
Logged In: YES +user_id=1222857 +Originator: NO + +I added a fix so that if your mouse does not move, between the two clicks, (left mouse, then right mouse for popup menu) then it will not prompt you the 2nd time. + +Is this working for you? +
+ + +2584396 +ckgrier2 +1197082665 +
Logged In: YES +user_id=1921682 +Originator: YES + +Sorry, but I can't build from source. :-( + +I'll check as soon as there's a new W32 build available.
+ + +2635169 +ckgrier2 +1200507454 +
Logged In: YES +user_id=1921682 +Originator: YES + +This bug has been fixed
+ + +2635170 +ckgrier2 +1200507454 +
Logged In: YES +user_id=1921682 +Originator: YES + +I tested it on Win32 with the 12/22 version and the double confirmation is resolved.
+ + + + + + +5276109 +IP +Artifact Created: 64.132.121.34 +1195092530 +ckgrier2 + + +5354153 +IP +Comment Added: 67.64.64.34 +1196875114 +dickelbeck + + +5354154 +status_id +1 +1196875114 +dickelbeck + + +5354155 +resolution_id +100 +1196875114 +dickelbeck + + +5354156 +assigned_to +100 +1196875114 +dickelbeck + + +5354157 +close_date +0 +1196875114 +dickelbeck + + +5364056 +IP +Comment Added: 68.158.1.69 +1197082665 +ckgrier2 + + +5364057 +status_id +4 +1197082665 +ckgrier2 + + +5364058 +close_date +1196875114 +1197082665 +ckgrier2 + + +5519707 +IP +Comment Added: 68.217.12.91 +1200507454 +ckgrier2 + + +5519708 +IP +Comment Added: 68.217.12.91 +1200507454 +ckgrier2 + + +5519709 +status_id +1 +1200507454 +ckgrier2 + + +5519710 +close_date +0 +1200507454 +ckgrier2 + + + + +http://sourceforge.net/support/tracker.php?aid=1834473 +1834473 +2 +100 +100 +102 +whitis +charras +dickelbeck +1195471051 +1228757739 +9 +Fill zones a mess +
There are a lot of problems with fill zones. + + - Filling with traces is not a good way to do it. + You get crappy edges on diagonal edges, + around pads, etc. Even the program pcb does a + better job of this. + + - No thermals that I can see, even though "thermals" + is an option on fill. But how does the program + know what pads should get connected? And if you + draw thermals manually using traces (very tedious), + the program will probably avoid them next time + you zap and recrate the fill. Apparently, from + looking at the pic programmer, it does this via + the netlist. But it doesn't let you tell it what + net the plane belongs to (how does it guess or does + it just assume incorrectly it is ground). And + just because + a pad connects to ground does not mean you want a + thermal there. You may need to connect particular + pins to the ground system in very particular ways. + And what happens if the pad is so close to a trace that the normal thermal pattern would intersect the trace? + + - The program non-consensually creates an imaginary + fill zone line around its misconceived notion of the + board extents. It fails to include manually drawn + fill zones in this notion of the board extent. + If you have drawn a board edge, however, it + functions ok so it is Pins necessary to create a board + outline even if you don't know what the outline + is yet. + + - Fill zone does not fill up to and including zone + boundaries. Sometimes it draws outside the lines + but usually it leaves a gap based on the + "clearance" as if the zone margin was a trace. + You can set the clearance to zero but then you + get inadequate clearance around traces. + + - Fill zone avoids imaginary objects that only it + can see. You can't see or edit these objects. + They are apparently stray fill zone boundary + segments from fill zones that were drawn but never + closed. They do sometimes appear temporarily + while you are drawing a new fill boundary, if + you trigger a redraw with the scroll wheel + (zoom). They go away when you answer yes to + "delete current edge zone" but that deletes + all the useful edges as well. It is really easy + to end up with a dozen of these imaginary + edge zones in a few minutes by aborting drawing + a zone boundary or segment. You get them by + drawing one too many edges before you hit + "end zone". You get them by clicking the mouse + not realizing you are in zone mode. Even when + you trick the program into displaying them, they + can't be deleted? + + + - The program is way to cavalier about deleting + zone edges. It constantly asks you if you + want to delete them. And sometimes you have to + delete them to clean up the mess left behind. + This is REALLY BAD. Those edges could have taken + hours to draw on a decent board with lots of fill. + Would you consider it acceptable for the program + to delete all your traces, or worse yet force you + to delete them to clean up the programs mess, + so easily? + + - Is there any documentation on fill zones? The + broken help viewer with no search function makes + it very hard to tell. + + - sometimes delete zone deletes the zone edge + instead of the fill. Well, it doesn't completely + go away, it just becomes one of the invisable + phantom edges. The rectangular cutout between + the two SSOP28 modules in the attached file is one + example. + + - Even when you say yes to delete zone edges, it doesn't get rid of some of the bad ones even though it does get rid of some of the good ones. + + - If I delete the "zone" on the pic programmer, and try to refill it, it deletes the thermals and doesn't put them back. And furthermore, it only fills in +one small area, not the whole board. It treats the +existing ground traces as boundaries. + +The attached file has at least 7 phantom edge segments that aren't supposed to be plus one phantom rectangle that is supposed to be there but is invisible. + +Warning: I am going to critique some of the sample board layouts. Disengage ego. I was looking at them to figure out if you had somehow managed to do any decent ground/power/signal planes with the software. Well, the boards look like they were laid out by a technician, not an engineer. Some cleverness in playing connect the dots but from a signal integrity perspective, they suck. Lots of copper in ground planes but not where it needs to be. Ground planes as an afterthought, not designed in. It is "would you believe its a ground plane? No? Well would you believe I am saving a lot of etchant by leaving copper on the board?". The program apparently is unusable for serious ground plane (or other fill work) because the programmers haven't done ground right. They look impressive to the untrained eye. + +A lot of real boards can have multiple power planes for different nets on the same layer along with signals that are drawn like planes for better impedence. And sometimes the planes are joined in certain specific locations. They aren't simple (from a zone perspective) like interf_u.brd. In fact, the "ground plane" on interf_u is a joke. It doesn't actually connect to anything as far as I can tell. It might actually create crosstalk and make the board worse off. +Ground is carried by traces that are too small. And the decoupling capacitors are likely to have to high high frequency impedence. Is this a real board? Does it actually work? sonde_xilinx contains another ground plane that is connected to a few pins without thermals. +Aha, you "select net", then fill. That sort of works but it also fills in the left D connector. And now I can't find a way to unselect the net. test_xil_95108 contains, again, only one net as a plane. And ground distrubution to the CPLD is not so good. VCC and ground should be planes on opposite layers. Was this a non-plated through hole board? If so, maybe a few jumpers under the CPLD socket are in order. Or better yet, use machined pin socket and solder the VCC pins on the top. Pretend you are an electron trying to get from the ground pin on the RAM to the CPLD. It is a 6" journey through two vias or a 4" journey though two throughholes (the regulator pin). You are on shaky ground (no pun intended) with a JEDEC ram pinout that only has one ground pin for two dozen signal pins (bouncy bouncy bouncy). And ground on the TDA8702 which should have run 0.4" to pin 60 (where is the via to the red ground trace next to pin 60????) has to travel half the circumference of the board to get to pin 16 on the CPLD or through two vias and a skinny red trace and squeeze between two pins before it can get to pin 42. Why wasn't the red trace from U2:49 to U1:6 not fattened? And why does it detour around a via that could have been moved instead of cutting the corner? Just because you flood a lot of copper on the board doesn't mean you have a decent ground. Pins 14,15,17,18,19,20, 21, 23, and 57 are all unused. If they had been tied to ground, you would have more channels to route ground through. Better yet, distribute them more evenly around the chip so you can make channels where you need them, like pins 30 and 29 where you desperately need one. Since the outdated JEDEC RAM pinout won't let you run ground traces between the pins, fat ground traces should have +hugged the top and bottom signal traces. And you +had lots of room on the component side to run ground. +Especially to pins 49 and 42, even if you have to +stitch across the TDO line. And, shit, the TDO line should not have been routed between the CPLD and the RAM at all. Run TDO around the periphery of the +board, not ground. And you might have avoided breaking ground in a critical place for the jtag signals - via those over ground. And a ground trace could have been squeezed between pins 15, 16, and 17 of the RAM. Better yet, you should have put the ground plane on the component side of the board where it would have done some good. Also, when you break a ground plane to run a long trace through it, you are supposed to stitch the two broken pieces together with a traces on the opposite side (that red trace from pin 59 is problematic). Pin 49 is on stich, you need another near pin 42 and one near pin 32. Fill the area on the bottom layer under the CPLD with VCC and fill the top (entire board) with GND and stitch. If you don't have through hole plating when prototyping, use individual screw machine IC socket pins (use the IC as a carrier while you are soldering the bottom and flatten out the leads of a dip and use it to hold pins in place while you solder the top or get a socket that has no fill in the middle. + +Some grounding tips: + - Ground is usually the most important signal on + the board and often neglected. + + - High speed logic needs good ground layouts even + when clocked at 1hz. It isn't the frequency + that matters, it is the edge rate. + + - Program CPLDs and FPGAs for the slowest edge rate + you can use. Many micros let you do this too. + If the chip won't let you do this, consider + series resistors on long traces, when driving + cables, etc. Use a slow logic family to get + slow edge rates. + + - At high frequencies, ground currents returning + from a signal do not take the shortest route, they + take the route that most nearly follows the path + of the original signal. This is one reason + ground planes directly under the signal really + help. If you can't run a ground plane there, + run some individual grounds between the signals. + Think like an electron; electrons do. + + - For every signal, pretend you are an electron + traveling in a loop through the signal traces and + back through ground. How many inches did you + have to travel? How far did you have to deviate + from your original path on the return trip? How + many vias? How many tight squeezes? The + bigger the area between the two paths the more EMI + you generate, the more you are susceptible to + external EMI, the more ground bounce you have, + and signal integrity is poorer. + + - FPGAs and CPLDs are great. They let you move pins + to facilitate PCB layout. Use this not just for + signals but to improve ground as well. + Where possible, tie unused signals on ICs to + ground and use that to create a channel to route + ground under that pin. Also, on some CPLD/FPGA you + can configure that pin as an extra ground or + at least drive a 0 onto the pin so ground + currents have an extra path through the output FET. + Move signals on your CPLD/FPGA to make room for + ground. + + - consider using a physical layout schematic symbol + for your programmable logic. It will help you + choose signal pins that are easy to route and it + is easier to plan for extra ground routes. + + - When you break a ground plane to run a trace + perpendicular to high speed signals, stitch + the two pieces together with traces across the + break and multiple parallel vias (for example, + two vias on each side of the break). + + - VCC and ground on opposite planes work great. + You get a lot of distributed capacitance. Ideally, + the whole board would be like this is one reason + why people pay for 4 layer boards. But if you + are using a two sided board, you can still do + this under your micros and programmable logic + and other high speed ICs. It isn't just your + external signals to be concerned about, ground + currents from internal logic needs help, too. + + + - Loopback testing from one port on a FPGA, CPLDs, + and micros isn't a good way to test ground + networks. When the signal gets to it's + destination, ground is already home. Use two + boards so ground currents flow the way they + will in the real world. + + - Cables to the outside world: alternate ground + and signal leads. + + - I have seen some crappy microboards that have + only 1 ground pin for all the I/O signals on + each I/O connector or worse, 1 ground pin + for the whole board. My last micro had one + ground for every signal. + + - If you are driving a long cable, make sure + your driver chip has enough ground pins + near the signals you are drivings. If you + drive 8 data lines across a 10ft cable with an + HC245, the ground bounce on the cable will + kill you. Use two separate chips or series + resistors. + + - Program micros (or CPLDs or FPGAs) to toggle + a whole bunch of pins in the same direction + at the same time to stress test your board. + Hang long cables off your I/O ports to stress + test it. When you aren't trying to stress + test your board, do the opposite. Program + the pins to not change at the same time if you + can. You can, for example, update every other + pin on an 8 bit data bus in two separate + operations instead of updating all 8 bits at + once if you are driving a cable and have + time to spare. Try to balance the number + of signals changing high to low and low to high. + Alternating 0xFF and 0x00 is worse than alternating + 0x55 and 0xAA. + + - Pros use differential signaling, for high speed + logic, long cables, and analog signals that + travel any distance. That is part of the + reason SATA is replacing ATA (IDE). Skew is the + another big part. Those are a big part of + why they can run SATA at 1.5, 3, and 6 megabits + per second over a single pair when they have + trouble pumping that same data at 133 mhz over + 16 parallel lines, even after adding 40 ground + wires. Likewise for PCI express replacing + PCI and AGP. + + - Just connecting everything together with + a ground plane or fat ground traces isn't + always good. Sometimes you need to deliberately + create gaps in your ground. You don't want + your digital signals returning through your + analog ground pins, for example. In some + cases, you stitch together with capacitors + to let AC through while blocking DC. + Single point grounds are often used, for example, + on A/D converters. + + - Murphy's law dictates that on a 1 or 2 layer board, + you will end up with the least fill in ground + plane where you need it the most. + + - On solderless or soldered breadboard patterns, + cross connect the ground buses with jumper wires + between the ICs. + + - Termination, characteristic impedence, and + transmission line effects for needs to be + looked at for fast edge rate signals. + + - clock skew and signal skew needs to be looked at + for high speed logic, especially synchronous logic + (where data is updated on the active clock edge). + For bush league designs, update your data and + clock your data on opposite edges of the clock. + Much easier on the signal routing. But you + lose 50% speed. PCB software should be + able to measure, and match trace length. + + - Lazy techs and junior engineers think this stuff + doesn't matter. You see lots of failed + prototypes as a result. + + + +Maybe you should borrow some code from PCB. It does +a much better job at handling solid copper fill.
+0 + + +2581380 +dickelbeck +1196874952 +
Logged In: YES +user_id=1222857 +Originator: NO + +Your title would have been enough. + +This bug report is a mess. It is 100 times too long + +This verbose text should have been posted to the user's list, with an http reference to a concise bug report. + +I agree fully (1000,000%) that zone support is inadequate. I am trying to find a way to improve it immediately, my highest priority. Jean-Pierre said it was at the top of his list, but I see no progress to date. So I am giving him a little more time to do it or give it up. + + +
+ + +2891530 +manneveru +1219588432 +
Logged In: YES +user_id=639576 +Originator: NO + +The pcb.sourceforge.net has nice support for zones, you can adjust clearance between zone and track on-the-fly by K and Shift-K key. But tracks drawing is much better in pcbnew.
+ + +3204260 +dickelbeck +1228757739 +
Maybe the newest code improves zones, so many of your issues are fixed. + +Don't know that anyone here needs to spend volunteer time taking the criticism however, so I am closing this. If there are still issues with zone, please submit them in smaller finer granularity without criticism. + +No one will read a 300 line bug report, especially one filled with criticism. + +
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=254934&aid= +254934 +junk1.brd + +97191 +application/octet-stream +1195471051 +whitis + + + + +5291683 +IP +Artifact Created: 67.76.175.5 +1195471051 +whitis + + +5291684 +File Added +254934: junk1.brd +1195471051 +whitis + + +5354131 +IP +Comment Added: 67.64.64.34 +1196874952 +dickelbeck + + +5354132 +resolution_id +100 +1196874952 +dickelbeck + + +5354133 +assigned_to +100 +1196874952 +dickelbeck + + +5354188 +priority +5 +1196875537 +dickelbeck + + +6413506 +IP +Comment Added: 213.134.171.113 +1219588432 +manneveru + + +7157813 +IP +Comment Added: 67.64.64.34 +1228757739 +dickelbeck + + +7157814 +status_id +1 +1228757739 +dickelbeck + + +7157815 +close_date +0 +1228757739 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=1834766 +1834766 +2 +100 +100 +102 +whitis +nobody +dickelbeck +1195504839 +1196875262 +5 +Fill zones a mess +
There are a lot of problems with fill zones. + + - Filling with traces is not a good way to do it. + You get crappy edges on diagonal edges, + around pads, etc. Even the program pcb does a + better job of this. + + - No thermals that I can see, even though "thermals" + is an option on fill. But how does the program + know what pads should get connected? And if you + draw thermals manually using traces (very tedious), + the program will probably avoid them next time + you zap and recrate the fill. Apparently, from + looking at the pic programmer, it does this via + the netlist. But it doesn't let you tell it what + net the plane belongs to (how does it guess or does + it just assume incorrectly it is ground). And + just because + a pad connects to ground does not mean you want a + thermal there. You may need to connect particular + pins to the ground system in very particular ways. + And what happens if the pad is so close to a trace that the normal thermal pattern would intersect the trace? + + - The program non-consensually creates an imaginary + fill zone line around its misconceived notion of the + board extents. It fails to include manually drawn + fill zones in this notion of the board extent. + If you have drawn a board edge, however, it + functions ok so it is Pins necessary to create a board + outline even if you don't know what the outline + is yet. + + - Fill zone does not fill up to and including zone + boundaries. Sometimes it draws outside the lines + but usually it leaves a gap based on the + "clearance" as if the zone margin was a trace. + You can set the clearance to zero but then you + get inadequate clearance around traces. + + - Fill zone avoids imaginary objects that only it + can see. You can't see or edit these objects. + They are apparently stray fill zone boundary + segments from fill zones that were drawn but never + closed. They do sometimes appear temporarily + while you are drawing a new fill boundary, if + you trigger a redraw with the scroll wheel + (zoom). They go away when you answer yes to + "delete current edge zone" but that deletes + all the useful edges as well. It is really easy + to end up with a dozen of these imaginary + edge zones in a few minutes by aborting drawing + a zone boundary or segment. You get them by + drawing one too many edges before you hit + "end zone". You get them by clicking the mouse + not realizing you are in zone mode. Even when + you trick the program into displaying them, they + can't be deleted? + + + - The program is way to cavalier about deleting + zone edges. It constantly asks you if you + want to delete them. And sometimes you have to + delete them to clean up the mess left behind. + This is REALLY BAD. Those edges could have taken + hours to draw on a decent board with lots of fill. + Would you consider it acceptable for the program + to delete all your traces, or worse yet force you + to delete them to clean up the programs mess, + so easily? + + - Is there any documentation on fill zones? The + broken help viewer with no search function makes + it very hard to tell. + + - sometimes delete zone deletes the zone edge + instead of the fill. Well, it doesn't completely + go away, it just becomes one of the invisable + phantom edges. The rectangular cutout between + the two SSOP28 modules in the attached file is one + example. + + - Even when you say yes to delete zone edges, it doesn't get rid of some of the bad ones even though it does get rid of some of the good ones. + + - If I delete the "zone" on the pic programmer, and try to refill it, it deletes the thermals and doesn't put them back. And furthermore, it only fills in +one small area, not the whole board. It treats the +existing ground traces as boundaries. + +The attached file has at least 7 phantom edge segments that aren't supposed to be plus one phantom rectangle that is supposed to be there but is invisible. + +Warning: I am going to critique some of the sample board layouts. Disengage ego. I was looking at them to figure out if you had somehow managed to do any decent ground/power/signal planes with the software. Well, the boards look like they were laid out by a technician, not an engineer. Some cleverness in playing connect the dots but from a signal integrity perspective, they suck. Lots of copper in ground planes but not where it needs to be. Ground planes as an afterthought, not designed in. It is "would you believe its a ground plane? No? Well would you believe I am saving a lot of etchant by leaving copper on the board?". The program apparently is unusable for serious ground plane (or other fill work) because the programmers haven't done ground right. They look impressive to the untrained eye. + +A lot of real boards can have multiple power planes for different nets on the same layer along with signals that are drawn like planes for better impedence. And sometimes the planes are joined in certain specific locations. They aren't simple (from a zone perspective) like interf_u.brd. In fact, the "ground plane" on interf_u is a joke. It doesn't actually connect to anything as far as I can tell. It might actually create crosstalk and make the board worse off. +Ground is carried by traces that are too small. And the decoupling capacitors are likely to have to high high frequency impedence. Is this a real board? Does it actually work? sonde_xilinx contains another ground plane that is connected to a few pins without thermals. +Aha, you "select net", then fill. That sort of works but it also fills in the left D connector. And now I can't find a way to unselect the net. test_xil_95108 contains, again, only one net as a plane. And ground distrubution to the CPLD is not so good. VCC and ground should be planes on opposite layers. Was this a non-plated through hole board? If so, maybe a few jumpers under the CPLD socket are in order. Or better yet, use machined pin socket and solder the VCC pins on the top. Pretend you are an electron trying to get from the ground pin on the RAM to the CPLD. It is a 6" journey through two vias or a 4" journey though two throughholes (the regulator pin). You are on shaky ground (no pun intended) with a JEDEC ram pinout that only has one ground pin for two dozen signal pins (bouncy bouncy bouncy). And ground on the TDA8702 which should have run 0.4" to pin 60 (where is the via to the red ground trace next to pin 60????) has to travel half the circumference of the board to get to pin 16 on the CPLD or through two vias and a skinny red trace and squeeze between two pins before it can get to pin 42. Why wasn't the red trace from U2:49 to U1:6 not fattened? And why does it detour around a via that could have been moved instead of cutting the corner? Just because you flood a lot of copper on the board doesn't mean you have a decent ground. Pins 14,15,17,18,19,20, 21, 23, and 57 are all unused. If they had been tied to ground, you would have more channels to route ground through. Better yet, distribute them more evenly around the chip so you can make channels where you need them, like pins 30 and 29 where you desperately need one. Since the outdated JEDEC RAM pinout won't let you run ground traces between the pins, fat ground traces should have +hugged the top and bottom signal traces. And you +had lots of room on the component side to run ground. +Especially to pins 49 and 42, even if you have to +stitch across the TDO line. And, shit, the TDO line should not have been routed between the CPLD and the RAM at all. Run TDO around the periphery of the +board, not ground. And you might have avoided breaking ground in a critical place for the jtag signals - via those over ground. And a ground trace could have been squeezed between pins 15, 16, and 17 of the RAM. Better yet, you should have put the ground plane on the component side of the board where it would have done some good. Also, when you break a ground plane to run a long trace through it, you are supposed to stitch the two broken pieces together with a traces on the opposite side (that red trace from pin 59 is problematic). Pin 49 is on stich, you need another near pin 42 and one near pin 32. Fill the area on the bottom layer under the CPLD with VCC and fill the top (entire board) with GND and stitch. If you don't have through hole plating when prototyping, use individual screw machine IC socket pins (use the IC as a carrier while you are soldering the bottom and flatten out the leads of a dip and use it to hold pins in place while you solder the top or get a socket that has no fill in the middle. + +Some grounding tips: + - Ground is usually the most important signal on + the board and often neglected. + + - High speed logic needs good ground layouts even + when clocked at 1hz. It isn't the frequency + that matters, it is the edge rate. + + - Program CPLDs and FPGAs for the slowest edge rate + you can use. Many micros let you do this too. + If the chip won't let you do this, consider + series resistors on long traces, when driving + cables, etc. Use a slow logic family to get + slow edge rates. + + - At high frequencies, ground currents returning + from a signal do not take the shortest route, they + take the route that most nearly follows the path + of the original signal. This is one reason + ground planes directly under the signal really + help. If you can't run a ground plane there, + run some individual grounds between the signals. + Think like an electron; electrons do. + + - For every signal, pretend you are an electron + traveling in a loop through the signal traces and + back through ground. How many inches did you + have to travel? How far did you have to deviate + from your original path on the return trip? How + many vias? How many tight squeezes? The + bigger the area between the two paths the more EMI + you generate, the more you are susceptible to + external EMI, the more ground bounce you have, + and signal integrity is poorer. + + - FPGAs and CPLDs are great. They let you move pins + to facilitate PCB layout. Use this not just for + signals but to improve ground as well. + Where possible, tie unused signals on ICs to + ground and use that to create a channel to route + ground under that pin. Also, on some CPLD/FPGA you + can configure that pin as an extra ground or + at least drive a 0 onto the pin so ground + currents have an extra path through the output FET. + Move signals on your CPLD/FPGA to make room for + ground. + + - consider using a physical layout schematic symbol + for your programmable logic. It will help you + choose signal pins that are easy to route and it + is easier to plan for extra ground routes. + + - When you break a ground plane to run a trace + perpendicular to high speed signals, stitch + the two pieces together with traces across the + break and multiple parallel vias (for example, + two vias on each side of the break). + + - VCC and ground on opposite planes work great. + You get a lot of distributed capacitance. Ideally, + the whole board would be like this is one reason + why people pay for 4 layer boards. But if you + are using a two sided board, you can still do + this under your micros and programmable logic + and other high speed ICs. It isn't just your + external signals to be concerned about, ground + currents from internal logic needs help, too. + + + - Loopback testing from one port on a FPGA, CPLDs, + and micros isn't a good way to test ground + networks. When the signal gets to it's + destination, ground is already home. Use two + boards so ground currents flow the way they + will in the real world. + + - Cables to the outside world: alternate ground + and signal leads. + + - I have seen some crappy microboards that have + only 1 ground pin for all the I/O signals on + each I/O connector or worse, 1 ground pin + for the whole board. My last micro had one + ground for every signal. + + - If you are driving a long cable, make sure + your driver chip has enough ground pins + near the signals you are drivings. If you + drive 8 data lines across a 10ft cable with an + HC245, the ground bounce on the cable will + kill you. Use two separate chips or series + resistors. + + - Program micros (or CPLDs or FPGAs) to toggle + a whole bunch of pins in the same direction + at the same time to stress test your board. + Hang long cables off your I/O ports to stress + test it. When you aren't trying to stress + test your board, do the opposite. Program + the pins to not change at the same time if you + can. You can, for example, update every other + pin on an 8 bit data bus in two separate + operations instead of updating all 8 bits at + once if you are driving a cable and have + time to spare. Try to balance the number + of signals changing high to low and low to high. + Alternating 0xFF and 0x00 is worse than alternating + 0x55 and 0xAA. + + - Pros use differential signaling, for high speed + logic, long cables, and analog signals that + travel any distance. That is part of the + reason SATA is replacing ATA (IDE). Skew is the + another big part. Those are a big part of + why they can run SATA at 1.5, 3, and 6 megabits + per second over a single pair when they have + trouble pumping that same data at 133 mhz over + 16 parallel lines, even after adding 40 ground + wires. Likewise for PCI express replacing + PCI and AGP. + + - Just connecting everything together with + a ground plane or fat ground traces isn't + always good. Sometimes you need to deliberately + create gaps in your ground. You don't want + your digital signals returning through your + analog ground pins, for example. In some + cases, you stitch together with capacitors + to let AC through while blocking DC. + Single point grounds are often used, for example, + on A/D converters. + + - Murphy's law dictates that on a 1 or 2 layer board, + you will end up with the least fill in ground + plane where you need it the most. + + - On solderless or soldered breadboard patterns, + cross connect the ground buses with jumper wires + between the ICs. + + - Termination, characteristic impedence, and + transmission line effects for needs to be + looked at for fast edge rate signals. + + - clock skew and signal skew needs to be looked at + for high speed logic, especially synchronous logic + (where data is updated on the active clock edge). + For bush league designs, update your data and + clock your data on opposite edges of the clock. + Much easier on the signal routing. But you + lose 50% speed. PCB software should be + able to measure, and match trace length. + + - Lazy techs and junior engineers think this stuff + doesn't matter. You see lots of failed + prototypes as a result. + + + +Maybe you should borrow some code from PCB. It does +a much better job at handling solid copper fill.
+0 + + +2581399 +dickelbeck +1196875262 +
Logged In: YES +user_id=1222857 +Originator: NO + +duplicate of 1834473
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=255012&aid= +255012 +junk1.brd + +97191 +application/octet-stream +1195504839 +whitis + + + + +5293948 +IP +Artifact Created: 67.76.175.5 +1195504839 +whitis + + +5293949 +File Added +255012: junk1.brd +1195504839 +whitis + + +5354170 +IP +Comment Added: 67.64.64.34 +1196875262 +dickelbeck + + +5354171 +status_id +1 +1196875262 +dickelbeck + + +5354172 +resolution_id +100 +1196875262 +dickelbeck + + +5354173 +close_date +0 +1196875262 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=1844278 +1844278 +2 +761682 +755198 +3 +nobody +nobody +dickelbeck +1196794205 +1196874218 +5 +ANSI C++ code broken +
cotation.cpp:133 -> unresolved ambiguity for auto casting at atan2(...) +graphpcb:694 ->unresolved ambiguity for auto casting at atan2(...) + +One must force the cast of at least one parameter for the C++ compiler beeing able to choose the right function: +atan2( (float)...) +
+0 + + +2581347 +dickelbeck +1196873881 +
Logged In: YES +user_id=1222857 +Originator: NO + +a duplicate of 1844285 +
+ + + + + + +5350127 +IP +Artifact Created: 217.226.108.197 +1196794205 +nobody + + +5353994 +IP +Comment Added: 67.64.64.34 +1196873881 +dickelbeck + + +5353995 +resolution_id +100 +1196873881 +dickelbeck + + +5353999 +resolution_id +105 +1196873947 +dickelbeck + + +5354039 +status_id +1 +1196874218 +dickelbeck + + +5354040 +close_date +0 +1196874218 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=1844285 +1844285 +2 +1015285 +755198 +3 +lainal +nobody +sf-robot +1196794647 +1198120809 +5 +ANSI C++ code broken +
*** libcmp.h:128-> suppress the trailing "," after the last member :PIN_DOWN, => PIN_DOWN +*** locate.cpp:880/843-> unresolved ambiguity for auto casting at sqrt(...) +*** symbdraw.cpp:584/768 ->unresolved ambiguity for auto casting at sqrt(...) +*** symbdraw.cpp:754/770/775 ->unresolved ambiguity for auto casting at atan2(...) +*** cleanup.cpp:259/260 ->unresolved ambiguity for auto casting at atan2(...) + +One must force the cast of at least one parameter for the C++ compiler beeing able to choose the right function: +atan2( (float)...) + +Prevent the target to compile on non-G++ compilers.
+0 + + +2581346 +nobody +1196873712 +
Logged In: NO + +The developers that I am aware of are all using g++. + +If you want to create a patch and add it as an attachment you are then a developer which uses a compiler other than g++, and as I said, we don't have any of those currently. + +So it is for you to fix, as the current crew is supporting g++ only. Only you can change that. +
+ + +2605272 +sf-robot +1198120809 +
Logged In: YES +user_id=1312539 +Originator: NO + +This Tracker item was closed automatically by the system. It was +previously set to a Pending status, and the original submitter +did not respond within 14 days (the time period specified by +the administrator of this Tracker).
+ + + + + + +5350189 +IP +Artifact Created: 217.226.108.197 +1196794647 +lainal + + +5353993 +IP +Comment Added: 67.64.64.34 +1196873712 +nobody + + +5354042 +status_id +1 +1196874271 +dickelbeck + + +5354043 +resolution_id +100 +1196874271 +dickelbeck + + +5354044 +close_date +0 +1196874271 +dickelbeck + + +5418052 +IP +Comment Added: +1198120809 +sf-robot + + +5418053 +status_id +4 +1198120809 +sf-robot + + +5418054 +close_date +1196874271 +1198120809 +sf-robot + + + + +http://sourceforge.net/support/tracker.php?aid=1844960 +1844960 +2 +761682 +755196 +1 +dickelbeck +charras +dickelbeck +1196875421 +1196986181 +3 +F1 after a FIND +
If you use the find dialog to find a part using reference number. Then immediately press F1 to zoom at that location (without moving the mouse in between), the cursor is jumping to someplace else. + +If you move the mouse just a little after the find but before the F1, then the cursor stays put. +
+0 + + +2581421 +dickelbeck +1196877128 +
Logged In: YES +user_id=1222857 +Originator: YES + +I tracked it down using D(printf();) in + +pcbnew/controle.cpp + +to this line: + + GetScreen()->m_Curseur = curpos; + +And curpos is coming from + + curpos = DrawPanel->CursorRealPosition( Mouse ); + +Please help.
+ + +2583117 +dickelbeck +1196986181 +
Logged In: YES +user_id=1222857 +Originator: YES + +Jean-Pierre fixed this today. Bug was also in eeschema, also fixed now.
+ + + + + + +5354182 +IP +Artifact Created: 67.64.64.34 +1196875422 +dickelbeck + + +5354293 +IP +Comment Added: 67.64.64.34 +1196877128 +dickelbeck + + +5359585 +IP +Comment Added: 67.64.64.34 +1196986181 +dickelbeck + + +5359586 +status_id +1 +1196986181 +dickelbeck + + +5359587 +resolution_id +100 +1196986181 +dickelbeck + + +5359588 +close_date +0 +1196986181 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=1845333 +1845333 +2 +761682 +100 +103 +nobody +charras +jerryjacobs +1196925468 +1267478894 +5 +one size via +
For a board I can make many different via. But when drill file was made only one size for all via set. + +When I use more the 8 different via, program lost last size.
+0 + + +3917392 +jerryjacobs +1267478894 +
Net classes to manage dimensions and settings added with last version.
+ + + + + + +5356106 +IP +Artifact Created: 217.150.32.243 +1196925468 +nobody + + +5359595 +resolution_id +100 +1196986276 +dickelbeck + + +5359596 +priority +5 +1196986276 +dickelbeck + + +5359597 +assigned_to +100 +1196986276 +dickelbeck + + +9227679 +IP +Comment Added: 84.25.204.235 +1267478894 +jerryjacobs + + +9227680 +status_id +1 +1267478894 +jerryjacobs + + +9227681 +resolution_id +102 +1267478894 +jerryjacobs + + +9227682 +allow_comments +1 +1267478894 +jerryjacobs + + +9227683 +close_date +0 +1267478894 +jerryjacobs + + +9227684 +priority +7 +1267478903 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=1867321 +1867321 +1 +1015285 +755196 +100 +wolverine222 +nobody +nobody +1199839703 +0 +5 +PADS netlist generator not working +
When generating a PADS netlist from a hierarquical schematic only the parts in the top schematic appear in the netlist. All the nets appear correctly, only the parts are missing. + +I've searched a bit and saw that a temporary file is generated from wich the PADS netlist is created. That file is missing the parts too (or already, according to the process). + +I attached an example of a netlist generated. you can see that there are nets that refer parts wich are not defined.
+0 + + +2635175 +ckgrier2 +1200507643 +
Logged In: YES +user_id=1921682 +Originator: NO + +Have you tried multiple versions of KiCad to see if this is isolated to newer releases? Are you using Win32?
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=261412&aid= +261412 +example.net +Just an example of the problem +5104 +application/octet-stream +1199839703 +wolverine222 + + + + +5486957 +IP +Artifact Created: 89.180.104.94 +1199839703 +wolverine222 + + +5486958 +File Added +261412: example.net +1199839704 +wolverine222 + + +5519721 +IP +Comment Added: 68.217.12.91 +1200507643 +ckgrier2 + + + + +http://sourceforge.net/support/tracker.php?aid=1873100 +1873100 +2 +1015287 +100 +100 +mungewell +nobody +dickelbeck +1200507258 +1228758121 +5 +Corrupted gerbv image - elements not shown properly +
Hi all, +I've been using Kicad for a while in a 'mucking around' sense, supporting the capture and layout done by contractors of ours. + +I have noticed that gerbv is failing to correctly represent gerbers that they have sent for inspection. The gerbers were created by Protel DXP. + +What appears to be happening is that a single gerber layer contains multiple elements which should be 'xor'ed drawn to create image, however gerbv is 'or'ing the elements together to produce a solid block of colour. + +I have attached a screen shot to my files showing the issue. + +The hidden elements of the gerber are visible as the gerbv layer is zoomed in/out, suggesting that they are drawn and then overdrawn/masked by other elements in the layer. + +On the left in the screenshot is another 'free' (beer) viewer which correctly renders the same layer. It has a mode setting 'colours merged' which will result in the same 'solid block' output as gerbv, normal setting is 'colours solid'. + +Cheers, +Mungewell.
+0 + + +2637081 +dickelbeck +1200585043 +
Logged In: YES +user_id=1222857 +Originator: NO + +I noticed you are using a 12-Jan-06 version of Kicad's Gerbview, correct? + +Please verify that the problem exists on the newest release. +
+ + +2653036 +mungewell +1201742381 +
Logged In: YES +user_id=39509 +Originator: YES + +The latest Windows version (2007-11-29) of Kicad/Gerbview also shows this problem. I am attempting to view gerbers generated by Protel DXP. I will attach a small example gerber. + +It looks like the flood fill is 'OR'ing areas rather than 'XOR'ing. Clicking the 'Show polygons in sketch mode' shows the individual elements of the design. +Mungewell.
+ + +2653037 +mungewell +1201742443 +
Logged In: YES +user_id=39509 +Originator: YES + +File Added: SCT_SC1302vc.GTL
+ + +3204277 +dickelbeck +1228758121 +
I am also seeing things like this and plan to fix it within the next 30 days or so. + +Dick +
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=262474&aid= +262474 +gerbv_failure.PNG +screeenshot showing issue +86260 +image/png +1200507258 +mungewell + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=264393&aid= +264393 +SCT_SC1302vc.GTL +Example gerber showing problem +11466 +application/octet-stream +1201742443 +mungewell + + + + +5519685 +IP +Artifact Created: 68.146.205.60 +1200507258 +mungewell + + +5519686 +File Added +262474: gerbv_failure.PNG +1200507260 +mungewell + + +5524196 +IP +Comment Added: 67.64.64.34 +1200585043 +dickelbeck + + +5574453 +IP +Comment Added: 68.146.205.60 +1201742381 +mungewell + + +5574454 +File Added +264393: SCT_SC1302vc.GTL +1201742443 +mungewell + + +5574455 +IP +Comment Added: 68.146.205.60 +1201742443 +mungewell + + +7157862 +IP +Comment Added: 67.64.64.34 +1228758121 +dickelbeck + + +7157863 +status_id +1 +1228758121 +dickelbeck + + +7157864 +close_date +0 +1228758121 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=1874663 +1874663 +2 +761682 +100 +100 +linuxcart +nobody +linuxcart +1200664792 +1200999964 +5 +Pad net assignation not working. +
Hello: + +I'm using kicad build from svn(20080110) and I have this problem: + +I place a footprint with 2 pads only used for mechanical stability. They should be solded but they don't need to belong to any net. + +I want to assign them to the ground net in the pcbnew editor. In order to do this I right click on the pad, and in the pad submenu I choose edit pad. + +I write GND(ground net name) in the net field and press ok in that dialog. + +If I open the pad edit dialog again the GND field is correct but if I try to route that pad is not realising that it's bound to the GND net. I've used the routing tool and the net highlight tool. + +A workaround is changing the pad net, exiting pcbnew and starting it again. + +Thanks.
+0 + + +2642323 +linuxcart +1200999963 +
Logged In: YES +user_id=1667631 +Originator: YES + +This bug is solved in development version dated 21st January, revision 662. + +Checkout here and seems to work. + +Thanks.
+ + + + + + +5528577 +IP +Artifact Created: 87.218.11.210 +1200664792 +linuxcart + + +5541395 +IP +Comment Added: 87.218.11.210 +1200999963 +linuxcart + + +5541396 +status_id +1 +1200999964 +linuxcart + + +5541397 +close_date +0 +1200999964 +linuxcart + + + + +http://sourceforge.net/support/tracker.php?aid=1875712 +1875712 +2 +761682 +100 +100 +nobody +nobody +jerryjacobs +1200826020 +1267475861 +5 +Lost pads on postscript plot +
With PCBNEW i have some invisible pads on the postscript plot. There is no such problem in printing or 3D mode. + +The pads are elliptic (size: 0.1x0.2). It is not systematic. Some other pads of this shape are visible (same module type, other part reference). + +A workaround for me was changing the pads shape from elliptic to round. + + +System: +PCBNEW (2007-07-09) installed under Fedora8 + + +Thanks for this nice piece of software. + +Br, +Oliver
+0 + + +2640436 +nobody +1200833671 +
Logged In: NO + +Little remark: + +Only in filled mode these pads are not visible. If you change the plot mode to outline plot the lost pads are visible again. + +Br, +Oliver
+ + +2727776 +pixostat +1207212768 +
Logged In: YES +user_id=2053322 +Originator: NO + +I found same problem (on PCBNEW 2008-02-20 Unicode and 2007-10-29 Unicode installed over Win XP Prof SP2). +The same workaround was for me good. +These pads are visible on normally print preview, on gerber files also but lost only in filled postscript plot. +There is no dependency on negativ/positiv plot. +I'm not sure but it looks that there are diferrence between cooper and component layers. +Same pads like on component layer are lost on both solder mask layers. +I found these lost pads only in multipin components (modules with 16 and 48 pin). +Lost pads was eliptic shape with baddly set diameter to 120milx120mil - when I corected it to round shape all goes OK. +When I change diameter of one of those critical pads to x=120mil and y=200mil - the pad is still lost, but in place of that pad are ploted two very thin vertical lines of summary lenght smaller than y size of pad (maby it was one line divided into two by drill in pad). +If I good remember, some time ago it has been similiar error with plot of square pads of SMD modules. +
+ + +3917337 +jerryjacobs +1267475823 +
Closing old bug
+ + + + + + +5533859 +IP +Artifact Created: 77.186.12.144 +1200826020 +nobody + + +5534096 +IP +Comment Added: 77.186.12.144 +1200833671 +nobody + + +5852681 +IP +Comment Added: 83.22.21.218 +1207212768 +pixostat + + +9227425 +IP +Comment Added: 84.25.204.235 +1267475823 +jerryjacobs + + +9227426 +status_id +1 +1267475861 +jerryjacobs + + +9227427 +allow_comments +1 +1267475861 +jerryjacobs + + +9227428 +close_date +0 +1267475861 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=1883241 +1883241 +2 +1015285 +100 +100 +nobody +nobody +dickelbeck +1201752639 +1201870380 +5 +Can`t create new library file. +
KiCad (2007-11-19) - Unicode version +Debian Etch/Lenny + +When I open symbol editor for make new symbol. I can`t save created symbol into new library via button named as "Create a new library an save current component into". Program not do anythink. A can save new symbol only into exist library. + +In old version it works well. +
+0 + + + + + + +5575194 +IP +Artifact Created: 81.9.81.5 +1201752639 +nobody + + +5580223 +status_id +1 +1201870379 +dickelbeck + + +5580224 +close_date +0 +1201870380 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=1889107 +1889107 +2 +1015285 +100 +103 +sb-sf +nobody +stambaughw +1202421356 +1268752334 +5 +Libedit: mouse pointer jumps +
Windows version 2007-11-29. Clicking on "show as de Morgan normal part" or "show as deMorgan converted part" icon causes mouse pointer to jump to another icon - "auto zoom", "zoom -" or another.
+0 + + +2661823 +sb-sf +1202421939 +
Logged In: YES +user_id=1653090 +Originator: YES + +actally mouse pointer jumps to cursor ("cross") position, which can be below icons when 50 mils grid selected.
+ + +3931576 +stambaughw +1268752334 +
Problem doesn't exist in release 2010-03-14 (svn-R2456)
+ + + + + + +5604877 +IP +Artifact Created: 194.19.225.133 +1202421356 +sb-sf + + +5604912 +IP +Comment Added: 194.19.225.133 +1202421940 +sb-sf + + +9290213 +IP +Comment Added: 162.83.115.135 +1268752334 +stambaughw + + +9290214 +status_id +1 +1268752334 +stambaughw + + +9290215 +resolution_id +100 +1268752334 +stambaughw + + +9290216 +allow_comments +1 +1268752334 +stambaughw + + +9290217 +close_date +0 +1268752334 +stambaughw + + + + +http://sourceforge.net/support/tracker.php?aid=1896790 +1896790 +2 +1015285 +516020 +1 +klui_ +stambaughw +stambaughw +1203414023 +1235595423 +5 +Ctrl-Z affects background eeSchema instead of library editor +
Also after mouse pressed "undo" button mouse cursor jumps into working area in library editor.
+0 + + +2731753 +diemer +1207504422 +
Logged In: YES +user_id=154672 +Originator: NO + +Confirmed for svn r970: Ctrl-Z in libedit affects the eeschema, not the library.
+ + +3551124 +stambaughw +1235595423 +
This bug has been fixed
+ + +3551125 +stambaughw +1235595423 +
Fixed in SVN 1619.
+ + + + + + +5656286 +IP +Artifact Created: 217.26.177.9 +1203414023 +klui_ + + +5867374 +IP +Comment Added: 82.83.218.100 +1207504422 +diemer + + +7793808 +IP +Comment Added: 162.83.115.135 +1235595423 +stambaughw + + +7793809 +IP +Comment Added: 162.83.115.135 +1235595423 +stambaughw + + +7793810 +status_id +1 +1235595423 +stambaughw + + +7793811 +assigned_to +100 +1235595423 +stambaughw + + +7793812 +allow_comments +1 +1235595423 +stambaughw + + +7793813 +close_date +0 +1235595423 +stambaughw + + +7793816 +resolution_id +100 +1235595466 +stambaughw + + + + +http://sourceforge.net/support/tracker.php?aid=1909165 +1909165 +2 +761682 +100 +1 +nobody +nobody +jerryjacobs +1204847492 +1267476220 +5 +Spurious lines in postscript output +
When I plot my circuit I get a spurious line in the output. Looking at the postscript there are actually about 10 lines very close together near the top of the output starting at about 8050,7700.
+0 + + +2699096 +nobody +1204847546 +
Logged In: NO + +Sorry, forgot to mention I'm using PCBNEW (2007-05-25) - Unicode version
+ + +3917342 +jerryjacobs +1267476220 +
This bug has been fixed
+ + +3917343 +jerryjacobs +1267476220 +
Closing old bug works for newer version.
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=269389&aid= +269389 +Piezo Preamp.zip +File that creates the offending output +9111 +application/zip +1204847492 +nobody + + + + +5728806 +IP +Artifact Created: 84.92.181.41 +1204847492 +nobody + + +5728808 +File Added +269389: Piezo Preamp.zip +1204847492 +nobody + + +5728810 +IP +Comment Added: 84.92.181.41 +1204847546 +nobody + + +9227450 +IP +Comment Added: 84.25.204.235 +1267476220 +jerryjacobs + + +9227451 +IP +Comment Added: 84.25.204.235 +1267476220 +jerryjacobs + + +9227452 +status_id +1 +1267476220 +jerryjacobs + + +9227453 +resolution_id +100 +1267476220 +jerryjacobs + + +9227454 +allow_comments +1 +1267476220 +jerryjacobs + + +9227455 +close_date +0 +1267476220 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=1910828 +1910828 +2 +1015285 +755198 +1 +nobody +nobody +diemer +1205126316 +1207503771 +5 +Missing pin on FPGA XC3S400PQ208 +
Pin 46 (IO_L19P_6) is missing in the kicad/library/xilinx.lib file. +Attached is a corrected version. + +Just hoping to spare anyone else from a mishap.. +
+0 + + +2731749 +diemer +1207503771 +
Logged In: YES +user_id=154672 +Originator: NO + +This bug has been fixed
+ + +2731750 +diemer +1207503771 +
Logged In: YES +user_id=154672 +Originator: NO + +Fixed in svn r926
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=269742&aid= +269742 +XC3S400-PQ208.lib +Corrected XC3S400-PQ208 +10093 +application/octet-stream +1205126316 +nobody + + + + +5739363 +IP +Artifact Created: 81.227.98.60 +1205126316 +nobody + + +5739364 +File Added +269742: XC3S400-PQ208.lib +1205126316 +nobody + + +5867344 +IP +Comment Added: 82.83.218.100 +1207503771 +diemer + + +5867345 +IP +Comment Added: 82.83.218.100 +1207503771 +diemer + + +5867346 +status_id +1 +1207503771 +diemer + + +5867347 +resolution_id +100 +1207503771 +diemer + + +5867348 +artifact_group_id +100 +1207503771 +diemer + + +5867349 +close_date +0 +1207503771 +diemer + + + + +http://sourceforge.net/support/tracker.php?aid=1914445 +1914445 +2 +1015285 +755198 +3 +fhsplitt +lifekidyeaa +diemer +1205515332 +1207501101 +5 +Old EESCHEMA cannot handle 20080312-r884 schematic +
Hi, + +under Windows XP, EESCHEMA ver. 2007-11-29-c aborts with an error message ("Component & position error at line 100, aborted") when attempting to open a schematic modified with EESCHEMA ver. 20080312-r884. + +Regards, + +Fred
+0 + + +2728513 +diemer +1207250167 +
Logged In: YES +user_id=154672 +Originator: NO + +It looks like the EESCHEMA file format has changed around SVN r750 (February 2008), due to changes regarding GLabels and Hierarchich Scheets. Seems like we have lost backwards-compatibility there. + +I don't know if it is possible to regain backwards compatibility though. We should at least improve handling of newer file formats, printing out a proper warning.
+ + +2731707 +diemer +1207501101 +
Logged In: YES +user_id=154672 +Originator: NO + +This bug has been fixed
+ + +2731708 +diemer +1207501101 +
Logged In: YES +user_id=154672 +Originator: NO + +EESchema now warns on a file format version mismatch. There probably won't be an export to an older file format, as people can simply upgrade their KiCAD.
+ + + + + + +5759050 +IP +Artifact Created: 84.188.119.251 +1205515332 +fhsplitt + + +5855932 +IP +Comment Added: 82.83.225.88 +1207250167 +diemer + + +5855933 +category_id +100 +1207250167 +diemer + + +5855934 +assigned_to +100 +1207250167 +diemer + + +5867199 +IP +Comment Added: 82.83.218.100 +1207501101 +diemer + + +5867200 +IP +Comment Added: 82.83.218.100 +1207501101 +diemer + + +5867201 +status_id +1 +1207501101 +diemer + + +5867202 +resolution_id +100 +1207501101 +diemer + + +5867203 +artifact_group_id +100 +1207501101 +diemer + + +5867204 +close_date +0 +1207501101 +diemer + + + + +http://sourceforge.net/support/tracker.php?aid=1915932 +1915932 +1 +761682 +100 +100 +a-lunev +nobody +nobody +1205709579 +0 +5 +problem with fractional numbers editing +
Fractional numbers are displayed in the following format: integer part point fractional part. For instance 1.05 is displayed. +If I try to edit 1.05 to e.g. 1.06 the result is incorrect. The only way to change it to 1.06 is to enter 1,06. I.e. a comma instead of point.
+0 + + +2708667 +a-lunev +1205709778 +
Logged In: YES +user_id=1930733 +Originator: YES + +It appears in PCBNEW.
+ + +2729555 +nobody +1207323646 +
Logged In: NO + +PLEASE CORRECT THIS BUG!!! pherhaps is only a compiling problem! It's very annoying! I still use the older versions for this bug, and so, I can't try new versions. + +
+ + + + + + +5766036 +IP +Artifact Created: 89.19.165.61 +1205709580 +a-lunev + + +5766041 +IP +Comment Added: 89.19.165.61 +1205709779 +a-lunev + + +5859718 +IP +Comment Added: 151.57.45.144 +1207323647 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1918746 +1918746 +2 +1015285 +755198 +1 +raburton +nobody +raburton +1205873804 +1206900315 +5 +eeschema: extremely slow redraw when grid is turned on +
Forwarded from: http://bugs.debian.org/469516 + +Information from original submitter: + +- Start eeschema. +- Switch on the grid (button to top left of viewport). +- Move another window in front and force eeschema to redraw. + +Redrawing pegs both CPUs on my dual-processor system at 100% for several +seconds at a time. +A little investigation using 'xtrace' shows that eeschema performs +one SetClipRectangles and one PolyPoint request for EVERY SINGLE +grid point. + +
+0 + + +2723164 +diemer +1206895886 +
Logged In: YES +user_id=154672 +Originator: NO + +Hi, + +I just tried the latest SVN revision 948, and it seems way faster than an +older version I tried (2007-05-25). It still takes some noticeable fractions +of a second to redraw, but it's much better. + +Bug Fixed? + +Best regards +Jonas
+ + +2723217 +raburton +1206900314 +
Logged In: YES +user_id=1213654 +Originator: YES + +This bug has been fixed
+ + +2723218 +raburton +1206900315 +
Logged In: YES +user_id=1213654 +Originator: YES + +Does appear to be much improved. Thanks Dick!
+ + + + + + +5778090 +IP +Artifact Created: 81.86.139.246 +1205873804 +raburton + + +5833865 +IP +Comment Added: 82.83.232.41 +1206895886 +diemer + + +5833866 +status_id +1 +1206895886 +diemer + + +5833867 +resolution_id +100 +1206895886 +diemer + + +5833868 +close_date +0 +1206895886 +diemer + + +5834059 +IP +Comment Added: 81.86.139.246 +1206900315 +raburton + + +5834060 +IP +Comment Added: 81.86.139.246 +1206900315 +raburton + + +5834061 +status_id +4 +1206900315 +raburton + + +5834062 +close_date +1206895886 +1206900315 +raburton + + + + +http://sourceforge.net/support/tracker.php?aid=1924526 +1924526 +2 +1015285 +755196 +1 +nobody +nobody +diemer +1206382642 +1206891172 +5 +window crashes when right clicking +
Kicad 20080320-r918 binary for Linux. running on SuSE10.0 + +When selecting component values to move or rotate, for example resistor values, normally depicted R in centre of the component, by right clicking on the schematic part the whole window crashes.
+0 + + +2716468 +nobody +1206390557 +
Logged In: NO + +Solved in 20080321 version (jp Charras)
+ + +2723119 +diemer +1206891172 +
Logged In: YES +user_id=154672 +Originator: NO + +closing bug, jp fixed it.
+ + + + + + +5807111 +IP +Artifact Created: 213.41.157.207 +1206382642 +nobody + + +5807613 +IP +Comment Added: 86.219.151.178 +1206390558 +nobody + + +5833734 +IP +Comment Added: 82.83.232.41 +1206891172 +diemer + + +5833735 +status_id +1 +1206891172 +diemer + + +5833736 +resolution_id +100 +1206891172 +diemer + + +5833737 +close_date +0 +1206891172 +diemer + + + + +http://sourceforge.net/support/tracker.php?aid=1925399 +1925399 +2 +761682 +516020 +103 +strangeril +nobody +jerryjacobs +1206467671 +1267477100 +5 +Pad displacement after changing its' diameter in mm +
When I change grid to milimeters and want to change pad diameter operation results in pad displaced from its' original position and also disconnected from its' net. +Only Windows version, reported to me that error occurs since r880. Tested on r931, error reproduced. + +In inch grid the same operation results in error message "Incorrect value for pad offset" although offset was not changed.
+0 + + +3917360 +jerryjacobs +1267477100 +
Works with newer (version) revision.
+ + + + + + +5812339 +IP +Artifact Created: 213.211.40.159 +1206467671 +strangeril + + +9227547 +IP +Comment Added: 84.25.204.235 +1267477100 +jerryjacobs + + +9227548 +status_id +1 +1267477100 +jerryjacobs + + +9227549 +resolution_id +100 +1267477100 +jerryjacobs + + +9227550 +allow_comments +1 +1267477100 +jerryjacobs + + +9227551 +close_date +0 +1267477100 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=1929364 +1929364 +2 +1015285 +100 +1 +diemer +nobody +diemer +1206883167 +1207082901 +5 +Undo of "Delete PinSheet" does not work properly +
Hi, + +I can undo a "Delete PinSheet", however, when I try to delete another pin of that Sheet, I get a popup: + +"DeleteSheetLabel error: m_Parent != DRAW_SHEET_STRUCT_TYPE" + +The Dangling test also seems to fail. + +When I try that again, eeschema crashes. + +This was tested with SVN revision 944.
+0 + + +2725977 +diemer +1207082901 +
Logged In: YES +user_id=154672 +Originator: YES + +I just noticed that Jean-Pierre fixed it in svn r949, the crash is gone. In addition, I just fixed the incorrectly shown dangling ends in svn r962. That should do it.
+ + + + + + +5833369 +IP +Artifact Created: 82.83.232.41 +1206883167 +diemer + + +5845506 +IP +Comment Added: 82.83.196.111 +1207082901 +diemer + + +5845507 +status_id +1 +1207082901 +diemer + + +5845508 +resolution_id +100 +1207082901 +diemer + + +5845509 +close_date +0 +1207082901 +diemer + + + + +http://sourceforge.net/support/tracker.php?aid=1930983 +1930983 +2 +1015285 +100 +1 +fhsplitt +nobody +diemer +1207036755 +1207083025 +5 +20080313-r890: "place hierarchical sheet" issues +
KiCAD 20080313-r890 under Windows XP SP2: + +(1) When attempting to "place a hierarchical sheet", the sheet shows up with a default file name that cannot be changed consistently. Sometimes, when the *.sch is reopened, a new (default?) filename reappears next to the rectangle for the hierarchical sheet. +(2) EEschema crashes when a non-existing file name is specified for a hierarchical sheet. + +
+0 + + +2725981 +diemer +1207083025 +
Logged In: YES +user_id=154672 +Originator: NO + +This bug has been fixed
+ + +2725982 +diemer +1207083025 +
Logged In: YES +user_id=154672 +Originator: NO + +According to the changelog and a quick test, this was fixed by Jean-Pierre in svn r948.
+ + + + + + +5842669 +IP +Artifact Created: 84.188.107.169 +1207036755 +fhsplitt + + +5845540 +IP +Comment Added: 82.83.196.111 +1207083025 +diemer + + +5845541 +IP +Comment Added: 82.83.196.111 +1207083025 +diemer + + +5845542 +status_id +1 +1207083025 +diemer + + +5845543 +resolution_id +100 +1207083025 +diemer + + +5845544 +category_id +100 +1207083025 +diemer + + +5845545 +close_date +0 +1207083025 +diemer + + + + +http://sourceforge.net/support/tracker.php?aid=1933550 +1933550 +2 +761682 +516020 +103 +fhsplitt +nobody +jerryjacobs +1207241172 +1267476627 +5 +localization issue - decimal points +
I am running PCBNEW under Windows XP with German language settings with the exception of having specified decimal points instead of commas (the comma is the standard German language decimal separator). Everything works well with most recent 2007 PCBNEW version. The module editor of all 2008 PCBNEW versions shows decimal points when I attempt to edit pads, but will not accept any input unless I use commas as a decimal separator. +Suggestion: either stick to the OS settings or simply stay with decimal points. + + +
+0 + + +2749019 +wrth +1208891926 +
Logged In: YES +user_id=1044669 +Originator: NO + +The same to me. All properties in PCBNEW which have a input box containing values with decimal points displays it with '.' but you have to input them with ','. The main problem is, when you change only one value, ALL other values on particular property page are set WRONG. + +Example: +when editting pad, all properties are displayed with DOT (some of them: Pad Drill 0.8128mm, Pad Size X=1.5748, Pad Size Y=2.286). +When you change only 'Pad Drill'(for example = 0,9mm - with comma as decimal point) other values are set to the number before decimal point -> Pad Size X = 1.0008mm, Pad Size Y=1.9990mm. + +I have also noticed that when I change the language to 'English' it works fine, but I have to use '.' as decimal point. I used to work in Polish language. + +This bug is very irritating. I can work with English interface, no problem, but it was very comfortable to use the numeric keyboard when setting parameters. Now I have to use numeric keyboard to input numbers and press '.' with my left hand on standard keyboard. + +
+ + +2767215 +rohel01 +1210321780 +
Logged In: YES +user_id=2082876 +Originator: NO + +This bug is also registered as bug 1915932. I'll comment here since this one is better documented. As previously said, this bug affects both PCBNEW and the module editor. + +It is very annoying : EVERY change in one specific value requires us to modify all other value aswell (replacing the dot by a comma). Failing to do so results in the LOSS of these settings. + +I think this bug should be raised to a higher priority. Beside the significant time waste, "vanishing" text strings can prevent new users from enjoying the professionnal quality of KiCad. + +
+ + +2769079 +nobody +1210493154 +
Logged In: NO + +MA CAZZO! Lo mettete a posto o no sto cazzo di problema, CAZZO!!! CAZZO!!! +
+ + +2769141 +nobody +1210498977 +
Logged In: NO + +MA CAZZO! Lo mettete a posto o no sto cazzo di problema, CAZZO!!! CAZZO!!! +
+ + +3204294 +dickelbeck +1228758494 +
Is this still a problem, or has it been fixed in latest code? +
+ + +3208732 +fhsplitt +1229021211 +
The decimal separator issue seems to have been fixed with the 20080715 release. + +
+ + + + + + +5855300 +IP +Artifact Created: 84.188.81.203 +1207241172 +fhsplitt + + +5933964 +IP +Comment Added: 89.206.7.227 +1208891926 +wrth + + +5991330 +IP +Comment Added: 86.196.170.29 +1210321780 +rohel01 + + +5996888 +IP +Comment Added: 90.131.8.231 +1210493154 +nobody + + +5997028 +IP +Comment Added: 90.131.8.231 +1210498977 +nobody + + +7157914 +IP +Comment Added: 67.64.64.34 +1228758494 +dickelbeck + + +7157915 +status_id +1 +1228758494 +dickelbeck + + +7157916 +close_date +0 +1228758494 +dickelbeck + + +7178310 +IP +Comment Added: 84.188.65.75 +1229021211 +fhsplitt + + +7178311 +status_id +4 +1229021211 +fhsplitt + + +7178312 +close_date +1228758494 +1229021211 +fhsplitt + + +9227498 +status_id +1 +1267476627 +jerryjacobs + + +9227499 +resolution_id +100 +1267476627 +jerryjacobs + + +9227500 +allow_comments +1 +1267476627 +jerryjacobs + + +9227501 +close_date +0 +1267476627 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=1934104 +1934104 +1 +100 +100 +100 +fhsplitt +nobody +nobody +1207287314 +0 +5 +PCBNEW - moving/deleting selected components +
Moving or deleting a group of selected identical components (30 LEDs in this case) which are still on top of each other before being manually or automatically positioned is impossible. + +Version: 2000313-r890 under Windows XP Home SP + +
+0 + + +2728971 +nobody +1207288106 +
Logged In: NO + +Hi, + +I figured out why the components could not be moved or deleted: In the module definition, the component was offset from the center of the coordinate system. + +Regards, + +Fred +
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=273154&aid= +273154 +marked_LED_group.jpeg + +52607 +image/pjpeg +1207287314 +fhsplitt + + + + +5857622 +IP +Artifact Created: 84.188.105.6 +1207287314 +fhsplitt + + +5857623 +File Added +273154: marked_LED_group.jpeg +1207287315 +fhsplitt + + +5857641 +IP +Comment Added: 84.188.105.6 +1207288106 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1945676 +1945676 +3 +1015285 +755196 +100 +jerryjacobs +nobody +jerryjacobs +1208523570 +1208948004 +5 +Libedit - exit and not save bug +
If i want to exit the libedit and changed a component it asks if i would save changes, when i say no it jumps back to libedit and doesn't exit libedit. When is say save changes it saves and exit... + +Jerry +20080416-r982 svn build used (made myself)
+0 + + +2749697 +jerryjacobs +1208948004 +
Logged In: YES +user_id=2066563 +Originator: YES + +.......Rewrite, +I did not read the dialog well it was no bug i was it myself.. + +Close this... + +Jerry
+ + + + + + +5915530 +IP +Artifact Created: 84.25.181.171 +1208523570 +jerryjacobs + + +5936199 +IP +Comment Added: 84.25.41.149 +1208948004 +jerryjacobs + + +5936200 +status_id +1 +1208948004 +jerryjacobs + + +5936201 +close_date +0 +1208948004 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=1947613 +1947613 +1 +761682 +755198 +100 +diemer +nobody +nobody +1208762619 +0 +5 +Track/segment delete shortcuts don't work +
From MK in users-ML: "how do I delete a trace? Backspace should do it but it does not. Any trick to doing it? Right click and selecting from the dialog works but too many steps." + +I checked with SVN r890 under Linux: I cannot delete tracks or segments using Backspace or Delete.
+0 + + +3221287 +f3nix +1229891282 +
For these shortcuts to work the "Add tracks and vias" tool must be turned on. I do not know if this is a bug or feature though... + +HTH, +Mateusz +
+ + +3221302 +f3nix +1229892094 +
The same applies to the delete module shortcut. You have to select "Add modules" tool to delete modules with these shortcuts...
+ + + + + + +5927289 +IP +Artifact Created: 134.169.117.46 +1208762620 +diemer + + +7252504 +IP +Comment Added: 83.12.84.19 +1229891282 +f3nix + + +7252505 +artifact_group_id +100 +1229891282 +f3nix + + +7252558 +IP +Comment Added: 83.12.84.19 +1229892094 +f3nix + + + + +http://sourceforge.net/support/tracker.php?aid=1947987 +1947987 +2 +761682 +100 +6 +diemer +nobody +diemer +1208789631 +1230461737 +5 +Track operations crashes +
Some PCBnew Track operations may crash the program... + +From Users-ML: + +> > - Board cleanup function (from menu) crashes program. A bug? +> +> Can't seem to find that function, can you be a bit more specific? + +It is called from (PCBnew): +Menu/Miscellaneous/Track operations +It seems that turning on 'Delete unconnected tracks' causes a crash for me. + +or maybe 'Connect to pads" but after the board is cleaned it does not crash anymore. +I think the cleaning algorithm crashes sometimes when it finds something. +You need things to cleanup to make it crash.
+0 + + +2748323 +diemer +1208847446 +
Logged In: YES +user_id=154672 +Originator: YES + +Attached a board that causes the crash. Select all four options of "Track operations" to provoke the crash. +File Added: crash.brd
+ + +3221295 +f3nix +1229891534 +
Hello Jonas, +could You please confirm that the crash still occurs with latest svn? It works for me... + +Thanks, +Mateusz +
+ + +3251156 +diemer +1230461737 +
Yep, I cannot reproduce this bug in the latest SVN 1488. It must have been fixed in the meantime.
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=275446&aid= +275446 +crash.brd +Board that causes the crash +210857 +application/octet-stream +1208847446 +diemer + + + + +5928814 +IP +Artifact Created: 134.169.117.46 +1208789631 +diemer + + +5931524 +File Added +275446: crash.brd +1208847446 +diemer + + +5931525 +IP +Comment Added: 134.169.117.46 +1208847446 +diemer + + +7252531 +IP +Comment Added: 83.12.84.19 +1229891534 +f3nix + + +7252532 +resolution_id +100 +1229891534 +f3nix + + +7309321 +IP +Comment Added: 82.83.228.128 +1230461737 +diemer + + +7309322 +status_id +1 +1230461737 +diemer + + +7309323 +close_date +0 +1230461737 +diemer + + + + +http://sourceforge.net/support/tracker.php?aid=1954396 +1954396 +1 +761682 +755198 +100 +kajtek1 +nobody +nobody +1209495807 +0 +5 +Moving tracks with zero length wrong +
By doing multiple track movements and merges you end up with some track having zero length. Especially on track corners. +Then, moving this corner moves all tracks correctly except the one with zero length which moves twice as far as the others ending up separated from the corner.
+0 + + +2757284 +kajtek1 +1209521433 +
Logged In: YES +user_id=1935577 +Originator: YES + +The same thing happens to via if you move a corner of a track that contains a via. Via moves twice as far. +If you drag a via instead of moving a track, it works correctly.
+ + + + + + +5960069 +IP +Artifact Created: 68.5.128.151 +1209495808 +kajtek1 + + +5961057 +IP +Comment Added: 68.5.128.151 +1209521434 +kajtek1 + + + + +http://sourceforge.net/support/tracker.php?aid=1955681 +1955681 +2 +100 +516020 +100 +f3nix +nobody +f3nix +1209674066 +1214154252 +7 +Translated strings are not picked up on Windows version +
Hi, +the current CMake policy is to install the "internat" folder into a "share" folder (eg. "c:\kicad\share\internat"). + +The problem is that when this folder is there, KiCad does not pick up the translated strings. + +When I move the "internat" folder to "c:\kicad" everything works as expected. + +Cheers, +Mateusz +
+0 + + +2813841 +f3nix +1214154195 +
Logged In: YES +user_id=1459455 +Originator: YES + +This bug has been fixed
+ + +2813842 +f3nix +1214154195 +
Logged In: YES +user_id=1459455 +Originator: YES + +Fixed in svn revision 1132.
+ + + + + + +5966627 +IP +Artifact Created: 83.12.84.19 +1209674066 +f3nix + + +6161467 +IP +Comment Added: 156.17.237.127 +1214154195 +f3nix + + +6161468 +IP +Comment Added: 156.17.237.127 +1214154195 +f3nix + + +6161469 +status_id +1 +1214154252 +f3nix + + +6161470 +close_date +0 +1214154252 +f3nix + + + + +http://sourceforge.net/support/tracker.php?aid=1956732 +1956732 +2 +1015285 +755196 +100 +durgadas +nobody +dickelbeck +1209823924 +1214839186 +5 +Filled rectangles and circles are not plotted as filled +
Ran into a problem generating (plotting) postscript schematics. Any rectangles or circles that I had selected as filled were not getting filled in the postscript file. Here's the patch I'm using, although it may not be the best solution: + +
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=276716&aid= +276716 +kicad.patch +Patch I am currently using +5217 +text/x-patch +1209823925 +durgadas + + + + +5972135 +IP +Artifact Created: 209.180.51.97 +1209823925 +durgadas + + +5972136 +File Added +276716: kicad.patch +1209823926 +durgadas + + +6188368 +status_id +1 +1214839186 +dickelbeck + + +6188369 +close_date +0 +1214839186 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=1956740 +1956740 +2 +1015285 +755196 +1 +durgadas +nobody +jerryjacobs +1209825061 +1267479170 +5 +eeschema core dumps when right click on ref field +
Sometimes I crash eeschema by right-clicking on the reference (or maybe value?) field of a component. Seems like the more I zoom in the less likely it is to happen. I've attached a stack trace, seems like somewhere between the right-click event and actually trying to choose a menu to pop-up it gets an invalid object pointer? or chooses the wrong context? + +Certain components do seem to do it more often, but it is possible to make it work even on troublesome components.
+0 + + +2776006 +mrblister +1210959788 +
Logged In: YES +user_id=98708 +Originator: NO + +I can reproduce this every time on 20080320-r918/Linux. Crash only occurs when right clicking on value field. Right click on reference field or anywhere else within component brings up the edit menu.
+ + +2807094 +nobody +1213422465 +
Logged In: NO + +Confirmed. eeschema will crash when right click on any field placed inside the component's area.
+ + +2872201 +nobody +1218437629 +
Logged In: NO + +Yes. Also confirm this on -r918 linux. + +This should get looked into since it renders the whole thing nearly useless since the context menus are essential for basic functionality. + +Test case: + +place an R component and rotate 90, menu is fine. Place a second , right-click to rotate and bam, no more eeschema. Pretty ugly. + +It seems to have something to do with multiple instance of a cmpt. + +gentoo linux, 2.6.20 , wxGTK-2.8.8.1 , gcc-4.2.3 + +Thx + +
+ + +2872211 +nobody +1218438149 +
Logged In: NO + +In my resistor example I have found that I do not get the crash if I select R each time. I do get the crash if I select R from the history list.
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=276719&aid= +276719 +kicad.crash +gdb stack traceback +2163 +application/octet-stream +1209825061 +durgadas + + + + +5972179 +IP +Artifact Created: 209.180.51.97 +1209825061 +durgadas + + +5972180 +File Added +276719: kicad.crash +1209825062 +durgadas + + +6018628 +IP +Comment Added: 81.174.132.135 +1210959788 +mrblister + + +6134105 +IP +Comment Added: 202.12.97.118 +1213422465 +nobody + + +6347801 +IP +Comment Added: 79.94.116.247 +1218437630 +nobody + + +6347826 +IP +Comment Added: 79.94.116.247 +1218438149 +nobody + + +9227703 +status_id +1 +1267479170 +jerryjacobs + + +9227704 +resolution_id +100 +1267479170 +jerryjacobs + + +9227705 +allow_comments +1 +1267479170 +jerryjacobs + + +9227706 +close_date +0 +1267479170 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=1959867 +1959867 +1 +100 +100 +100 +kajtek1 +nobody +nobody +1210202731 +0 +5 +Module Editor deletes multiple lines +
I modified a module in Module Editor (PCBnew -r982) by drawing a new outline (graphic line) next to existing one and then tried to delete the old lines one by one. +Deleting seemed to work fine but when I repainted the screen all of the new lines except one were also deleted. +The lines did not share the same end points so I do not know why whould it do that. +The new lines were close to the old ones but not overlaying.
+0 + + + + + + +5986610 +IP +Artifact Created: 206.135.71.2 +1210202731 +kajtek1 + + + + +http://sourceforge.net/support/tracker.php?aid=1961821 +1961821 +2 +1015285 +100 +103 +nobody +nobody +jerryjacobs +1210497072 +1267477859 +5 +Not printing the hierachical sheet when printing the main +
If you place a hierarchical sheet in your main sheet and you select "print-> Print all sheets", the first sheet is printed twice.
+0 + + +2790718 +cfdev +1212070089 +
Logged In: YES +user_id=1876469 +Originator: NO + +I confirme this ! for Print all sheets in version : 20080429-r1010 win32 +the first sheet is printed twice and in smaller format ! + +visibly the format of the scheme has changed because I try to re open the scheme with the stable version, but it is not possible... :( + +thank you to fixe it.
+ + +3917377 +jerryjacobs +1267477858 +
Printing is reworked, should work now.
+ + + + + + +5996981 +IP +Artifact Created: 217.250.48.116 +1210497072 +nobody + + +6069668 +IP +Comment Added: 90.52.144.92 +1212070089 +cfdev + + +9227587 +IP +Comment Added: 84.25.204.235 +1267477858 +jerryjacobs + + +9227588 +status_id +1 +1267477859 +jerryjacobs + + +9227589 +resolution_id +100 +1267477859 +jerryjacobs + + +9227590 +allow_comments +1 +1267477859 +jerryjacobs + + +9227591 +close_date +0 +1267477859 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=1963635 +1963635 +1 +1015285 +100 +100 +diemer +nobody +nobody +1210751073 +0 +7 +Multipart/multisheet entries in cvpcb (netlist) +
From Rok via devel-ML: + +Hi + +If there is an multipart element shared accross multiple sheets, there +are as many entries in cvpcb as there are sheets. So if you have 4 part element +U14 which is used on 3 sheets, there is 3 entries for U14 in CVPCB. + +SVN build 1065. + +Rok
+0 + + + + + + +6008095 +IP +Artifact Created: 134.169.117.46 +1210751074 +diemer + + + + +http://sourceforge.net/support/tracker.php?aid=1963636 +1963636 +1 +1015285 +100 +100 +diemer +nobody +nobody +1210751119 +0 +7 +Ploting multi instance of the same sheet +
From Rok via devel-ML: + +If you try to plot multisheet schematic with multi instance same name +schematic (same filename, different sheetname) only the last one is visible - +I guess it is overwriten. + +I would need all sheets because there are different designators on +different instances of the sheets. + +Rok
+0 + + +2821565 +lomarcan +1214821325 +
Logged In: YES +user_id=115128 +Originator: NO + +Uhm at a first glance it seems also that the plotting routine iterates on screens, not sheets (unlike the BOM builder). That may be the problem too. +
+ + + + + + +6008096 +IP +Artifact Created: 134.169.117.46 +1210751121 +diemer + + +6187419 +IP +Comment Added: 88.149.185.186 +1214821325 +lomarcan + + + + +http://sourceforge.net/support/tracker.php?aid=1963864 +1963864 +2 +1015285 +755198 +1 +rokmarko +nobody +rokmarko +1210776738 +1213115185 +7 +Part number of multipart element is not saved +
Part number of multipart element is not saved. In multipart element you can select which part you are using. This inforamation is never stored, even when you leave a child sheet and reopens edited one. + +Rok
+0 + + +2803429 +rokmarko +1213115185 +
Logged In: YES +user_id=1126317 +Originator: YES + +This bug has been fixed
+ + +2803430 +rokmarko +1213115185 +
Logged In: YES +user_id=1126317 +Originator: YES + +by jean-pierre
+ + + + + + +6010015 +IP +Artifact Created: 193.77.104.223 +1210776738 +rokmarko + + +6010017 +summary +Part number of multipart is not saved +1210776774 +rokmarko + + +6010023 +priority +5 +1210776814 +rokmarko + + +6118914 +IP +Comment Added: 193.77.104.223 +1213115185 +rokmarko + + +6118915 +IP +Comment Added: 193.77.104.223 +1213115185 +rokmarko + + +6118916 +status_id +1 +1213115185 +rokmarko + + +6118917 +resolution_id +100 +1213115185 +rokmarko + + +6118918 +close_date +0 +1213115185 +rokmarko + + + + +http://sourceforge.net/support/tracker.php?aid=1974672 +1974672 +2 +1015285 +516020 +1 +ddeeds +charras +f3nix +1211887135 +1229886384 +5 +White text/graphic on black background does not print +
I work with a black background for schematics and normally use white for the pin name and pin number. But when I print a schematic using the Black Color Print mode, any text or graphic that is white does not print even though it is not the same color as the background. +
+0 + + +3221209 +f3nix +1229886384 +
This bug has been fixed
+ + +3221210 +f3nix +1229886384 +
Fixed in SVN r1167. +Thanks!
+ + + + + + +6057386 +IP +Artifact Created: 96.226.65.105 +1211887135 +ddeeds + + +7252153 +IP +Comment Added: 83.12.84.19 +1229886384 +f3nix + + +7252154 +IP +Comment Added: 83.12.84.19 +1229886384 +f3nix + + +7252155 +status_id +1 +1229886384 +f3nix + + +7252156 +resolution_id +100 +1229886384 +f3nix + + +7252157 +assigned_to +100 +1229886384 +f3nix + + +7252158 +close_date +0 +1229886384 +f3nix + + + + +http://sourceforge.net/support/tracker.php?aid=1975710 +1975710 +2 +1015285 +516020 +103 +oecherexpat +nobody +jerryjacobs +1211933961 +1267477708 +5 +BOM creation incorrect when using extra fields +
BOM creation has issues when using component's extra fields: A column for sheet number and sheet name is created but not filled in on single-sheet schematics. The contents of all other columns is shifted (see attached file)
+0 + + +3917373 +jerryjacobs +1267477708 +
BOM creation is reworked, it has been tested and works.
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=279267&aid= +279267 +BOM-Test.lst +BOM *.lst with 4 components file created using extra fields +214 +application/octet-stream +1211933961 +oecherexpat + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=324710&aid= +324710 +IsCheckedStack + +1523 +application/octet-stream +1240890652 +bennett78 + + + + +6060902 +IP +Artifact Created: 222.153.213.254 +1211933961 +oecherexpat + + +6060903 +File Added +279267: BOM-Test.lst +1211933961 +oecherexpat + + +8220614 +File Added +324710: IsCheckedStack +1240890652 +bennett78 + + +9227569 +IP +Comment Added: 84.25.204.235 +1267477708 +jerryjacobs + + +9227570 +status_id +1 +1267477708 +jerryjacobs + + +9227571 +resolution_id +100 +1267477708 +jerryjacobs + + +9227572 +allow_comments +1 +1267477708 +jerryjacobs + + +9227573 +close_date +0 +1267477708 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=1977700 +1977700 +2 +761682 +100 +6 +nobody +nobody +f3nix +1212061969 +1229893485 +5 +Crash on Add Graphic Line or Polygon in Module editor +
Reproducible crash : +- Open Module Editor +- Create new module +- Draw line or polygon +- End it (double click, escape ...) +- Crash + +Add graphic arc, or add graphic circle are unaffected. + +Versions affected : +- 20080521 SVN-R1081 +- 20080320-r918-linux + +System : Ubuntu 8.04 + +
+0 + + +3221318 +f3nix +1229893485 +
Hi. I've tested the r918, r1081 and r1461. This crash is unreproducible. +I'm closing it for now. +Feel free to reopen it if the bug is still hitting You. +Thanks.
+ + + + + + +6068976 +IP +Artifact Created: 196.200.83.190 +1212061969 +nobody + + +7252625 +IP +Comment Added: 83.12.84.19 +1229893485 +f3nix + + +7252626 +status_id +1 +1229893485 +f3nix + + +7252627 +resolution_id +100 +1229893485 +f3nix + + +7252628 +close_date +0 +1229893485 +f3nix + + + + +http://sourceforge.net/support/tracker.php?aid=1980555 +1980555 +1 +1015285 +100 +100 +nobody +nobody +nobody +1212236732 +0 +5 +Numerical inputs dot/semicolon mixup +
Hi, + +while its still fine in 'Release 20070709', I'm having troubles with numerical input fields in '20080522-r1100-win32' running on an english Windows Vista in with German currency/math settings. + +Every time I'm asked for a numerical input, like size of a label, preexisting inputs get converted to use a dot instead of a semicolon ( 0.04 instead of 0,04). Now when I dont replace the dot with a semicolon again the input will be taken as '0.0' no matter what I enter. + +Workaround: Replace . with , every time you open the dialog + +This Bug seems to apply to all kicad programs.
+0 + + +2797960 +nobody +1212604728 +
Logged In: NO + +I have the same problem. German windows with german localization.
+ + +2805563 +nobody +1213285361 +
Logged In: NO + +I have the same problem. + +Windows XP
+ + +2859474 +nobody +1217591717 +
Logged In: NO + +If you use the englisch language setting ist works with the ".". It seems to be a problem with the locale or language setting. When parsing the entered values the decimal separator from current language is used but at the time of filling the dialog the current language is ignored. You can only notice the bug if the decimal seperator from the selced language has another character as the ".".
+ + + + + + +6079077 +IP +Artifact Created: 87.152.79.22 +1212236732 +nobody + + +6096470 +IP +Comment Added: 138.246.7.133 +1212604728 +nobody + + +6127687 +IP +Comment Added: 91.96.10.165 +1213285361 +nobody + + +6309618 +IP +Comment Added: 195.179.9.148 +1217591718 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1994698 +1994698 +2 +1015285 +516020 +103 +landyacht79 +nobody +jerryjacobs +1213581680 +1267476677 +5 +Wires don't connect +
I am running Kicad 2007-11-29-c on a Windows Vista Ultimate 64 bit laptop. When I am entering a schematic and adding wires, many times the wires do not connect to the component pins. How do I resolve this?
+0 + + +3127115 +nobody +1225402272 +
I realize a similar behavier using Windows XP, 32 bits. Vcc and GND power pins do not connect to other pins!
+ + +3917352 +jerryjacobs +1267476677 +
Should work with newer version.
+ + + + + + +6138956 +IP +Artifact Created: 68.81.85.143 +1213581680 +landyacht79 + + +6843557 +IP +Comment Added: 200.232.90.170 +1225402273 +nobody + + +9227505 +IP +Comment Added: 84.25.204.235 +1267476677 +jerryjacobs + + +9227506 +status_id +1 +1267476677 +jerryjacobs + + +9227507 +resolution_id +100 +1267476677 +jerryjacobs + + +9227508 +allow_comments +1 +1267476677 +jerryjacobs + + +9227509 +close_date +0 +1267476677 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=1995664 +1995664 +3 +761682 +100 +100 +nobody +nobody +jerryjacobs +1213668348 +1267477757 +5 +Net placed inside eeschema not correctly connected in pbcnew +
Nets created in eeschema will sometimes not properly connect in pcbnew. DRC does not return an error, but pcbnew will think all of those nets are all interconnected. pcbnew shows me all pins highlighted + +this happens with and without using bus entries. + +(reference picture) +the bus entries on the left of the tlc chips will all connect to each other in pcbnew. +also on the right side of the tlc, the connections 5-8 for the pin header used to be net names too to not make it too complicated. I placed a wire with 10 units length on the tlc and another wire on the pin header and named both nets the same (RED_5 to RED_8 for example) + +using version 20080522-r1100-win32 + +I cant verify if this happens in an older release as it the project wont load in an older version. + +Sometimes I was able to correct it by placing the wire and net again on both sides, but sometimes I cant get it fixed at all without drawing the wires from a to b. +(thats why I replaced the net labels on the connections) + +I redrew the whole schematic because i had the same problem the first time, its only got worse the second time, even thought it was layed out exaclty the same. only difference i used more underscores in the names of the components. + + + +add.: pulled the old layout from a backup, didnt restore the full project, thats why the tlc is not showing up, but this way you should get an idea how it used to be layed out. pcbnew then would think they are all connected. same procedures works on another sheet
+1 + + +2809937 +nobody +1213723828 +
Logged In: NO + +might have found the cause, might be a space in the name of the hierarchical sheet. the file name was "current-sink.sch" and the entered name was "current sink" +ever since i changed that it seems to connect the wires correctly.
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=281630&aid= +281630 +referencepics.zip +screenshot of connections +62966 +application/x-download +1213668348 +nobody + + + + +6143220 +IP +Artifact Created: 87.152.88.152 +1213668348 +nobody + + +6143221 +File Added +281630: referencepics.zip +1213668349 +nobody + + +6146151 +IP +Comment Added: 87.152.87.89 +1213723828 +nobody + + +9227577 +status_id +1 +1267477757 +jerryjacobs + + +9227578 +is_private +0 +1267477757 +jerryjacobs + + +9227579 +close_date +0 +1267477757 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=1995665 +1995665 +1 +1015288 +100 +100 +nobody +nobody +nobody +1213668650 +0 +5 +sm1206 and sm805 size mixup? +
when laying out my board, I noticed sm805 has the exact with and length (when viewed with the component viewer) as sm1206 and sm1206 is oversized.
+0 + + +2818745 +nobody +1214551914 +
Logged In: NO + +It's not a mixup, it's simply that there is an ambiguity with smd sizes... +IIRC the size can be either imperial (numbers in mils) or metric (tenth of mm). +So actually the 0805 imperial is exactly the same as the 1206 metric (or it's the other way? just make the calc) + +To add injury to damage, in some metric country (like here in Italy) we use imperial sizes! So if you ask a 1206 package (thinking in metric) you get a 'big' component, since suppliers give you a 1206 imperial! + +I think that's you problem, it's just industry's fault.
+ + + + + + +6143236 +IP +Artifact Created: 87.152.88.152 +1213668650 +nobody + + +6178504 +IP +Comment Added: 80.207.56.82 +1214551914 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2003834 +2003834 +2 +1015285 +755198 +100 +nobody +nobody +dickelbeck +1214553263 +1214839186 +5 +Postscript plot generates wrong fill code +
Using r918, a filled polygon plot generates the following: + +newpath 7075 3992 moveto +7225 3992 lineto +7225 3967 lineto +7075 3967 lineto +closepath fill stroke +newpath 7225 3992 moveto +7225 3992 lineto +stroke + +(I know, it's a rectangle, but filled rectangles don't work, as in another bug) + +There are two issues here: +1) the second path is spurious (it's just a dot in a corner on the previous path), simply it isn't needed +2) the fill operator flushes the path (executes an implicit newpath), so the following stroke is a no-op; as a result the polygon is filled but not outlined! + +The correct postscript idiom is (iirc it's stated in the red book): + +closepath gsave fill grestore stroke + +(I'm fixing this using a sed script) +
+0 + + +2818766 +lomarcan +1214553366 +
Logged In: YES +user_id=115128 +Originator: NO + +Actually I submitted this, I wasn't logged in :D
+ + + + + + +6178570 +IP +Artifact Created: 88.149.185.186 +1214553263 +nobody + + +6178575 +IP +Comment Added: 88.149.185.186 +1214553366 +lomarcan + + +6188366 +status_id +1 +1214839186 +dickelbeck + + +6188367 +close_date +0 +1214839186 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=2010222 +2010222 +2 +761682 +516020 +103 +oecherexpat +nobody +jerryjacobs +1215137001 +1267476831 +5 +Length of value field gets trunk'd when design is saved +
The length of the value filed gets trunk'd to 16 characters when the design is saved as PCB and re-opened. It is at full length when reading in the netlist.
+0 + + +3917357 +jerryjacobs +1267476831 +
All dialog are redone, this should now work.
+ + + + + + +6202081 +IP +Artifact Created: 222.153.213.254 +1215137001 +oecherexpat + + +9227524 +IP +Comment Added: 84.25.204.235 +1267476831 +jerryjacobs + + +9227525 +status_id +1 +1267476831 +jerryjacobs + + +9227526 +resolution_id +100 +1267476831 +jerryjacobs + + +9227527 +allow_comments +1 +1267476831 +jerryjacobs + + +9227528 +close_date +0 +1267476831 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2018936 +2018936 +2 +1015285 +755196 +105 +alpheb +nobody +jerryjacobs +1216154966 +1267479022 +5 +eeschema redraw errors under compiz +
Here is a bug report filled in Launchpad. + +eeschema redraw errors under compiz +Filed here by: Alexander Rice +When: 2008-03-04 + +Binary package hint: kicad + +Eeschema works fine with kwin, but tends to leave 'shadows' of components and the cursor when using compiz. + +Using: + +Eeschema Build Version: +EESchema (2007-05-25) - Unicode version + +Compiz 1:0.6.2 + + + +Yoann CONGAL wrote 24 minutes ago: + + * eeschema-with-compiz.png (32.3 KiB, image/png) +http://launchpadlibrarian.net/16047058/eeschema-with-compiz.png + +Thanks for your report. + +Here is a screenshot of what I see under compiz' + +To reproduce it : +Move the cursor fast over the window. Some seconds later, cursor "ghost" will appear. + Yoann CONGAL wrote 18 minutes ago: (permalink) + +Same bug here (Hardy and EESchema Build Version:EESchema (2007-11-29-a) - Unicode version) +
+0 + + +2838087 +alpheb +1216156609 +
Logged In: YES +user_id=1890423 +Originator: YES + +I forgot to give the launchpad bug link : + +https://bugs.launchpad.net/ubuntu/+source/kicad/+bug/198353 + +Regards, + +Yoann CONGAL
+ + +3917394 +jerryjacobs +1267479022 +
Compiz gives this kind of errors also with different programs, disable compiz.
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=284833&aid= +284833 +eeschema-with-compiz.png +screenshot +33042 +image/png +1216154966 +alpheb + + + + +6242717 +IP +Artifact Created: 81.64.68.143 +1216154966 +alpheb + + +6242723 +File Added +284833: eeschema-with-compiz.png +1216154966 +alpheb + + +6242826 +IP +Comment Added: 81.64.68.143 +1216156609 +alpheb + + +9227694 +IP +Comment Added: 84.25.204.235 +1267479022 +jerryjacobs + + +9227695 +status_id +1 +1267479022 +jerryjacobs + + +9227696 +resolution_id +100 +1267479022 +jerryjacobs + + +9227697 +allow_comments +1 +1267479022 +jerryjacobs + + +9227698 +close_date +0 +1267479022 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2020699 +2020699 +2 +1015285 +516020 +103 +nobody +nobody +jerryjacobs +1216307329 +1267476585 +5 +Library causes application to crash +
Submitted By: Kristen Wegner - branta.canadensis@gmail.com + +Context: While application "eeschema.exe" is loading part libraries ("Loading ..." is displayed in status bar.) Cannot see which library is the culprit. + +Assumption: Corrupt or incompatible library (?) causes application to crash. + +Error: Unhandled exception at 0x7c911639 in eeschema.exe: 0xC0000005: Access violation reading location 0x05512385. + +Threads: + +> 28012 Win32 Thread 7c911639 Normal + 21188 Win32 Thread 7c90eb94 Normal + 27008 Win32 Thread 7c90eb94 Normal + 28296 Win32 Thread 7c90eb94 Normal + 26748 Win32 Thread 7c90eb94 Above Normal + 27732 Win32 Thread 7c961be3 Normal + +Call Stack: + +> ntdll.dll!7c911639() + ntdll.dll!7c910732() + ntdll.dll!7c911538() + ntdll.dll!7c911596() + ntdll.dll!7c9106eb() + kernel32.dll!7c81095f() + eeschema.exe!007211d0() + eeschema.exe!005c93ce() + ntdll.dll!7c9106eb() + msvcrt.dll!77c2c3c9() + msvcrt.dll!77c2c3ce() + eeschema.exe!005c93ce() + msvcrt.dll!77c2c3c9() + eeschema.exe!005af6ad() + msvcrt.dll!77c2c3e7() + msvcrt.dll!77c2c42e() + eeschema.exe!005add71() + eeschema.exe!005ae46c() + eeschema.exe!005ae5d7() + eeschema.exe!006667a5() + eeschema.exe!0056f953() + eeschema.exe!007214d8() + msvcrt.dll!77c2c2de() + eeschema.exe!006669a2() + eeschema.exe!007ea9c8() + eeschema.exe!006670c7() + msvcrt.dll!77c2c3ce() + msvcrt.dll!77c2c3e7() + eeschema.exe!005add71() + eeschema.exe!005ae46c() + eeschema.exe!005bfea8() + msvcrt.dll!77c2c2de() + eeschema.exe!005ae4a7() + eeschema.exe!00502e61() + eeschema.exe!007ea701() + ntdll.dll!7c91056d() + msvcrt.dll!77c2c2de() + msvcrt.dll!77c2c2e3() + ntdll.dll!7c91094e() + kernel32.dll!7c80f30b() + eeschema.exe!00401ead() + msvcrt.dll!77c2c42e() + eeschema.exe!007f84c1() + eeschema.exe!006dc08b() + msvcrt.dll!77c2c2e3() + msvcrt.dll!77c2c3ce() + eeschema.exe!005be2cf() + eeschema.exe!007d7e21() + ntdll.dll!7c91094e() + eeschema.exe!00401466() + eeschema.exe!007ea278() + msvcrt.dll!77c39d60() + msvcrt.dll!77c34e2f() + eeschema.exe!0040124b() + eeschema.exe!004012b8() + kernel32.dll!7c816fd7() +
+0 + + +3917350 +jerryjacobs +1267476584 +
Should work with newer version.
+ + + + + + +6250308 +IP +Artifact Created: 75.69.128.102 +1216307329 +nobody + + +9227489 +IP +Comment Added: 84.25.204.235 +1267476584 +jerryjacobs + + +9227490 +status_id +1 +1267476585 +jerryjacobs + + +9227491 +resolution_id +100 +1267476585 +jerryjacobs + + +9227492 +allow_comments +1 +1267476585 +jerryjacobs + + +9227493 +close_date +0 +1267476585 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2025712 +2025712 +2 +761682 +755198 +1 +jerryjacobs +nobody +jerryjacobs +1216816979 +1217638357 +5 +[SVN-REV-1170] 3D Viewer Crashes X11 +
Dear Developers, +I checked out the latest SVN version ( do this mostly one time a week for testing ). + +If i now run PCBnew and select the 3D Viewer my complete X11 crashes. I tried to find it using GDB and logging it: + +Reading symbols from /usr/local/bin/pcbnew...done. +Starting program: /usr/local/bin/pcbnew +[Thread debugging using libthread_db enabled] +[New Thread 0xb5fb3a30 (LWP 5581)] + +Program received signal SIGHUP, Hangup. +[Switching to Thread 0xb5fb3a30 (LWP 5581)] +0xb76764a7 in __close_nocancel () from /lib/libpthread.so.0 + + +I hope we can fix this before "new release" + + +Jerry
+0 + + +2860348 +jerryjacobs +1217638322 +
Logged In: YES +user_id=2066563 +Originator: YES + +Fixed with version 1167
+ + + + + + +6272735 +IP +Artifact Created: 84.25.41.149 +1216816979 +jerryjacobs + + +6311914 +IP +Comment Added: 84.25.41.149 +1217638322 +jerryjacobs + + +6311915 +resolution_id +100 +1217638322 +jerryjacobs + + +6311918 +status_id +1 +1217638357 +jerryjacobs + + +6311919 +artifact_group_id +100 +1217638357 +jerryjacobs + + +6311920 +close_date +0 +1217638357 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2043168 +2043168 +1 +761682 +755198 +100 +nobody +nobody +nobody +1218207622 +0 +5 +ps plot broken with layer alignment in 2008-7-15 +
Hi, + +I added some layer alignment elements to my board. This broke the postscript plot in pcbnew. The offending code is: + +57500 60270 1250 cir150 +27200 41470 1250 cir150 + +cir150 is not defined. Reason seems to be that in plot_rtn.cpp:PlotCircle the fill and the width argument are interchanged in the call of PlotCirclePS. + +This bug is fixed in trunk. + +Is there a chance of a bugfix release anytime soon?
+0 + + + + + + +6338559 +IP +Artifact Created: 81.17.210.28 +1218207623 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2055599 +2055599 +2 +100 +755198 +1 +queueram +nobody +jerryjacobs +1218955519 +1267476154 +1 +kicad-doc 1.1 tarball extracts to "kicad" directory +
The kicad-doc 1.0 tarball extracted a directory named "kicad-doc". The kicad-doc 1.1 extracts to a directory named "kicad" which conflicts with the name of the directory that the kicad 20080715 extracts to. Workarounds are to rename the directory between extractions, or to check out the files from SVN. It would be preferable to avoid doing either of these though, especially for package generation. This might just be something to take care of at the next release.
+0 + + +2945330 +werner2101 +1223119775 +
It would even be nice if the tarballs extracts to a directory which contains the version number. + +kicad-20080825.tar.bz2 should extract to kicad-20080825 +kicad-doc-1.1.tar.bz2 should extract to kicad-doc-1.1 + +This is the used by almost all other projects. + +Regards +Werner +
+ + +3917340 +jerryjacobs +1267476154 +
This bug has been fixed
+ + +3917341 +jerryjacobs +1267476154 +
Closing old bug works for newer versions.
+ + + + + + +6376058 +IP +Artifact Created: 12.210.191.117 +1218955519 +queueram + + +6376059 +priority +5 +1218955540 +queueram + + +6608635 +IP +Comment Added: 87.179.55.254 +1223119775 +werner2101 + + +9227442 +IP +Comment Added: 84.25.204.235 +1267476154 +jerryjacobs + + +9227443 +IP +Comment Added: 84.25.204.235 +1267476154 +jerryjacobs + + +9227444 +status_id +1 +1267476154 +jerryjacobs + + +9227445 +resolution_id +100 +1267476154 +jerryjacobs + + +9227446 +allow_comments +1 +1267476154 +jerryjacobs + + +9227447 +close_date +0 +1267476154 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2069722 +2069722 +2 +761682 +755198 +100 +manneveru +a-lunev +a-lunev +1219499897 +1219626635 +8 +PCB edge always printed when PCB edge layer not selected +
I have created my own PCB design and I want to laser print copper layers for thermal transfer process. + +But when in print dialogue I select only Elements layer (I have SMD design), the edge of the board is printed, even when I do not want this! + +The Gerber plot dialogue has select box, which allow to disable PCB edge, and this works. Problem with Gerber is that I don't have alignment targets in Gerber files (I don't know whether it is a bug or not, probably this could be enabled for Gerber too), so I print from GerbView is usable, but problematic to place on laminate. + +For me this is a bug in software at level of printing architecture, not a feature request.
+0 + + +2892123 +a-lunev +1219626635 +
Logged In: YES +user_id=1930733 +Originator: NO + +It is resolved by adding 'Exclude Edges_Pcb layer' check box in 'Print' dialog.
+ + +2892377 +manneveru +1219647913 +
Logged In: YES +user_id=639576 +Originator: YES + +Am I understand correctly that this is on trunk? If yes I will try to rebuild code from svn.
+ + +2892581 +a-lunev +1219664037 +
Logged In: YES +user_id=1930733 +Originator: NO + +Yes, update your work copy from svn and rebuild newpcb.
+ + + + + + +6409778 +IP +Artifact Created: 213.134.171.113 +1219499897 +manneveru + + +6415467 +IP +Comment Added: 89.19.165.61 +1219626635 +a-lunev + + +6415468 +status_id +1 +1219626635 +a-lunev + + +6415469 +assigned_to +100 +1219626635 +a-lunev + + +6415470 +close_date +0 +1219626635 +a-lunev + + +6416441 +IP +Comment Added: 217.147.104.41 +1219647913 +manneveru + + +6417259 +IP +Comment Added: 77.73.25.202 +1219664038 +a-lunev + + + + +http://sourceforge.net/support/tracker.php?aid=2069872 +2069872 +1 +1015285 +516020 +100 +nobody +nobody +nobody +1219508603 +0 +5 +Sheet pin text size reduced after changing to an output +
When editing a sheet pin on a hierarchical sheet from an input (the default) to an output, the text size is changed to something tginy and cannot be changed back.
+0 + + +2890639 +nobody +1219511261 +
Logged In: NO + +This also occurs when adding pins to a new schematic libary - pin names and number have a size of 0.000" are not shown.
+ + +2890641 +nobody +1219511332 +
Logged In: NO + +Issue is in Kicad 20080429-r1010.
+ + +2890656 +nobody +1219512578 +
Logged In: NO + +Correction: Issue is in Kicad 20080429-r1010 when overwritten with release 20080522-r1100-win32.
+ + + + + + +6410135 +IP +Artifact Created: 68.158.174.138 +1219508603 +nobody + + +6410234 +IP +Comment Added: 68.158.174.138 +1219511262 +nobody + + +6410243 +IP +Comment Added: 68.158.174.138 +1219511332 +nobody + + +6410285 +IP +Comment Added: 68.158.174.138 +1219512578 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2070228 +2070228 +2 +100 +516020 +100 +manneveru +nobody +dickelbeck +1219525585 +1220985253 +7 +bitmaps/CMakeLists.txt is broken for Win32 +
I am trying to build 2008-08-04 on my Windows machine. I even made new tutorial how to do that with CMake and Visual Studio 2005 Express (link on wiki). + +But bitmaps/CMakeLists.txt contains apostrophe character instead of quote marks. + +Currently is: +COMMAND cmake -E copy '${PATH}/${BASENAME}.xpm' '${CPP_BITMAP}' + +Should be: + +COMMAND cmake -E copy \"${PATH}/${BASENAME}.xpm\" \"${CPP_BITMAP}\" + +With changed line it is working. I am not making any change in repository, because I do not know rules yet.
+0 + + +2892378 +manneveru +1219647976 +
Logged In: YES +user_id=639576 +Originator: YES + +I submitted a patch for VC++ 2005 on kicad-devel group file area.
+ + + + + + +6410811 +IP +Artifact Created: 213.134.171.113 +1219525585 +manneveru + + +6416444 +IP +Comment Added: 217.147.104.41 +1219647976 +manneveru + + +6494387 +status_id +1 +1220985253 +dickelbeck + + +6494388 +close_date +0 +1220985253 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=2072876 +2072876 +2 +1015285 +516020 +1 +gembler +charras +f3nix +1219637635 +1229886606 +5 +Libedit Places Edited Pin Instead of Creating New Pin +
To reproduce: + +1) Create new part and add pins +2) End Add Pins mode and edit any newly created pin +3) Switch back to Add Pins mode +4) Add a new pin -- the new pin placed is actually the pin just edited + +EESchema 20080715 - unicode version for Win XP +
+0 + + +3221214 +f3nix +1229886605 +
Fixed in SVN r1217. +Thanks.
+ + + + + + +6416060 +IP +Artifact Created: 198.144.208.125 +1219637635 +gembler + + +7252179 +IP +Comment Added: 83.12.84.19 +1229886605 +f3nix + + +7252180 +status_id +1 +1229886606 +f3nix + + +7252181 +resolution_id +100 +1229886606 +f3nix + + +7252182 +assigned_to +100 +1229886606 +f3nix + + +7252183 +close_date +0 +1229886606 +f3nix + + + + +http://sourceforge.net/support/tracker.php?aid=2074534 +2074534 +2 +1015285 +100 +100 +gembler +nobody +stambaughw +1219705179 +1270579506 +5 +Libedit Cannot Delete Rectangle +
To reproduce: + +1) In Libedit, select component FILTER in device.lib +2) Delete the rectangle +3) The rectangle reappears + +EESchema 20080715 - unicode version on Win XP +
+0 + + +3221322 +f3nix +1229893773 +
Hello, +could You please confirm that the bug exists in the latest version? +I've tested the latest svn snapshot and I can't reproduce it. +Thanks.
+ + +3954363 +stambaughw +1270579505 +
Fixed in release version 20100314.
+ + + + + + +6420363 +IP +Artifact Created: 198.144.208.125 +1219705179 +gembler + + +7252638 +IP +Comment Added: 83.12.84.19 +1229893773 +f3nix + + +9371345 +IP +Comment Added: 162.83.115.135 +1270579506 +stambaughw + + +9371346 +status_id +1 +1270579506 +stambaughw + + +9371347 +allow_comments +1 +1270579506 +stambaughw + + +9371348 +close_date +0 +1270579506 +stambaughw + + + + +http://sourceforge.net/support/tracker.php?aid=2081148 +2081148 +2 +1015285 +100 +101 +nobody +f3nix +f3nix +1219957952 +1229885270 +5 +Libedit Cannot Delete Rectangle +
To reproduce: + +1) In Libedit, select component FILTER in device.lib +2) Delete the rectangle +3) The rectangle reappears + +EESchema 20080715 - unicode version on Win XP +
+0 + + +3221198 +f3nix +1229885270 +
Duplicate of bug #2074534
+ + +3221231 +f3nix +1229887969 +
This artifact has been marked as a duplicate of artifact 2074534 with reason: +No explanation provided.
+ + + + + + +6438357 +IP +Artifact Created: 65.57.245.11 +1219957952 +nobody + + +7252087 +IP +Comment Added: 83.12.84.19 +1229885270 +f3nix + + +7252088 +status_id +1 +1229885270 +f3nix + + +7252089 +resolution_id +100 +1229885270 +f3nix + + +7252090 +close_date +0 +1229885270 +f3nix + + +7252092 +assigned_to +100 +1229885304 +f3nix + + +7252266 +IP +Comment Added: 83.12.84.19 +1229887969 +f3nix + + +7252267 +status_id +3 +1229887970 +f3nix + + + + +http://sourceforge.net/support/tracker.php?aid=2086372 +2086372 +2 +1015287 +755198 +100 +ok1rrmartin +nobody +ok1rrmartin +1220256170 +1220746067 +5 +Gerbview internal error +
Gerbview -> Preferences -> Show Current Hotkey List results in WinEDA_GerberFrame::Process_Config internal error
+0 + + + + + + +6451619 +IP +Artifact Created: 80.250.30.141 +1220256171 +ok1rrmartin + + +6480996 +status_id +1 +1220746067 +ok1rrmartin + + +6480997 +close_date +0 +1220746067 +ok1rrmartin + + + + +http://sourceforge.net/support/tracker.php?aid=2086382 +2086382 +2 +100 +100 +2 +ok1rrmartin +nobody +jerryjacobs +1220256550 +1267478687 +5 +Strings that can't be translated +
Both EESchema and Pcbnew contain strings that can't be translated in Preferences -> Show Current Hotkey List. They seems to be 'hardwired' into code.
+0 + + + + + + +6451636 +IP +Artifact Created: 80.250.30.141 +1220256550 +ok1rrmartin + + +9227662 +status_id +1 +1267478687 +jerryjacobs + + +9227663 +resolution_id +100 +1267478687 +jerryjacobs + + +9227664 +allow_comments +1 +1267478687 +jerryjacobs + + +9227665 +close_date +0 +1267478687 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2098306 +2098306 +2 +1015286 +100 +103 +nobody +nobody +jerryjacobs +1220778351 +1267478339 +5 +[Crash] On project save +
Kicad Project manager hangs up if i want to write a new project or save the nameless project. Also if in the settings the last project doesn't exist anymore kicad does not check if the project is existing .... + +[20080906 SVN 1239 BUILD]
+0 + + + + + + +6482318 +IP +Artifact Created: 84.25.41.149 +1220778351 +nobody + + +9227641 +status_id +1 +1267478339 +jerryjacobs + + +9227642 +resolution_id +100 +1267478339 +jerryjacobs + + +9227643 +allow_comments +1 +1267478339 +jerryjacobs + + +9227644 +close_date +0 +1267478339 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2136527 +2136527 +2 +1015285 +100 +1 +nobody +nobody +f3nix +1222712335 +1229889196 +5 +EESCHEMA freez... +
EESCHEMA freez while editing board in PCBNEW. ("Dual mode", first part location good, but at second eeschema freez out.. =( ). + +Debian Kernel: 2.6.18-6-686 +KiCad: 0.0.20071129a-1 + +contact: marcziselektronika@gmail.com + +Please let me know if I can help. + +KiCad is amazing ! +GOGOGO !
+0 + + +2942669 +nobody +1222896656 +
Okay, +I feel really dummy... I just realized, in Debi testing I have a very old kicad.... +I just finished installing the brand new kicad... and the problem of course gone... + +THANK YOU VERY MUCH KICAD ! + +
+ + + + + + +6583629 +IP +Artifact Created: 89.133.34.50 +1222712335 +nobody + + +6594860 +IP +Comment Added: 89.133.34.50 +1222896656 +nobody + + +7252362 +status_id +1 +1229889196 +f3nix + + +7252363 +resolution_id +100 +1229889196 +f3nix + + +7252364 +close_date +0 +1229889196 +f3nix + + + + +http://sourceforge.net/support/tracker.php?aid=2146251 +2146251 +2 +100 +100 +100 +werner2101 +nobody +dickelbeck +1223120207 +1228757391 +5 +wxwidgets 2.8 required +
I've tried to build kicad for openSUSE 10.2. It provides wxwidgets version 2.6.3.3. + +Refering the install.txt file this should be ok. + +The build fails with the following message: +-------- +Scanning dependencies of target 3d-viewer +[ 0%] Building CXX object 3d-viewer/CMakeFiles/3d-viewer.dir/3d_aux.cpp.o +In file included from /usr/src/packages/BUILD/kicad/3d-viewer/3d_aux.cpp:18: +/usr/src/packages/BUILD/kicad/include/common.h:9:25: error: wx/aboutdlg.h: No such file or directory +/usr/src/packages/BUILD/kicad/include/common.h:11:34: error: wx/generic/aboutdlgg.h: No such file or directory +/usr/src/packages/BUILD/kicad/include/common.h:611: error: variable or field 'InitKiCadAbout' declared void +/usr/src/packages/BUILD/kicad/include/common.h:611: error: 'wxAboutDialogInfo' was not declared in this scope +/usr/src/packages/BUILD/kicad/include/common.h:611: error: 'info' was not declared in this scope +make[2]: *** [3d-viewer/CMakeFiles/3d-viewer.dir/3d_aux.cpp.o] Error 1 +make[1]: *** [3d-viewer/CMakeFiles/3d-viewer.dir/all] Error 2 +make: *** [all] Error 2 +-------- + +The about dialog class has been added with wxwidgets version 2.8 + +Regards +Werner
+0 + + +3204252 +dickelbeck +1228757391 +
The latest tree now requires 2.8 of wxWidgets. You may need to build wxWidgets from source if your distro does not have a recent version. This is not a bug, we are allowed to move the project forward with the latest technology coming from wxWidgets. + +
+ + + + + + +6608652 +IP +Artifact Created: 87.179.55.254 +1223120207 +werner2101 + + +7157787 +IP +Comment Added: 67.64.64.34 +1228757391 +dickelbeck + + +7157788 +status_id +1 +1228757391 +dickelbeck + + +7157789 +close_date +0 +1228757391 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=2149301 +2149301 +2 +761682 +755196 +100 +galzsolt +nobody +galzsolt +1223291776 +1252529061 +5 +Printing doesn't work well +
I'am using Debian Etch 4.0. In PCBnew when I try to print boards, lines aren't continusly in the printed document and on the paper also incorrect. Lines looks like they are crashed and pads are squared instead of rouded or oval. I tryed it in Ubuntu 8.04 and the result is the same. I had never this problem in windows XP, but I want to use linux because of its licence.
+0 + + +3035482 +nobody +1224662589 +
I have the same problem with Ubunutu 8.04 on two different PC.
+ + +3095951 +nobody +1225138465 +
Same thing for me on debian sid and ubuntu. +I talked about that on kicad-users mailing list (see message #3753 for some pictures) + +vko
+ + +3158041 +nobody +1225992336 +
Me too. But in the meantime, you can use the plot function wich will pake a .ps file.
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=296268&aid= +296268 +Printing_400001_VNH-brd.pdf +It shows my problem. +54699 +application/pdf +1223291776 +galzsolt + + + + +6615784 +IP +Artifact Created: 82.141.181.16 +1223291776 +galzsolt + + +6615785 +File Added +296268: Printing_400001_VNH-brd.pdf +1223291776 +galzsolt + + +6776288 +IP +Comment Added: 193.194.132.79 +1224662589 +nobody + + +6825049 +IP +Comment Added: 213.41.32.234 +1225138465 +nobody + + +6882232 +IP +Comment Added: 91.150.229.252 +1225992336 +nobody + + +8653076 +status_id +1 +1252529061 +galzsolt + + +8653077 +allow_comments +1 +1252529061 +galzsolt + + +8653078 +close_date +0 +1252529061 +galzsolt + + + + +http://sourceforge.net/support/tracker.php?aid=2167848 +2167848 +2 +761682 +100 +1 +nobody +charras +f3nix +1224060288 +1229886890 +5 +crash on module editor - module properties +
Reproducible crash on Kicad 20080825 on windows XP. Bug does not afflict previous version and Linux version. + +- Open module editor +- Load module from library +- Open module +- Open module properties +- Click OK +Crash of PCBnew +
+0 + + +2988636 +nobody +1224060622 +
Federico Dami + +federico.dami@alice.it
+ + +3215834 +nobody +1229523603 +
I confirm +
+ + +3215836 +nobody +1229523664 +
I confirm +
+ + +3221218 +f3nix +1229886890 +
Fixed in SVN r1279. +Thanks!
+ + +3221219 +f3nix +1229886965 +
Fixed in SVN r1282. +Thanks!
+ + + + + + +6695236 +IP +Artifact Created: 81.80.37.124 +1224060289 +nobody + + +6695286 +IP +Comment Added: 81.80.37.124 +1224060622 +nobody + + +7216581 +IP +Comment Added: 90.49.22.52 +1229523603 +nobody + + +7216588 +IP +Comment Added: 90.49.22.52 +1229523664 +nobody + + +7252202 +IP +Comment Added: 83.12.84.19 +1229886890 +f3nix + + +7252203 +status_id +1 +1229886890 +f3nix + + +7252204 +resolution_id +100 +1229886890 +f3nix + + +7252205 +assigned_to +100 +1229886890 +f3nix + + +7252206 +close_date +0 +1229886890 +f3nix + + +7252209 +IP +Comment Added: 83.12.84.19 +1229886965 +f3nix + + + + +http://sourceforge.net/support/tracker.php?aid=2171561 +2171561 +1 +1015285 +100 +100 +josh_eeg +nobody +nobody +1224161383 +0 +5 +I am drawing the component MYCONN3 per tutorial instructions +
I am drawing the component MYCONN3 per tutorial instructions... but the box tool is not drawing a box it is acting like a rectangular selection and moveing my pins... +I am using the newest stable window$ build.
+0 + + +3221242 +f3nix +1229888664 +
Hi. You should not drag with pressed mouse button. You should only click on the start and end point of the rectangle. + +HTH +Mateusz
+ + + + + + +6712426 +IP +Artifact Created: 65.200.157.178 +1224161383 +josh_eeg + + +7252324 +IP +Comment Added: 83.12.84.19 +1229888664 +f3nix + + + + +http://sourceforge.net/support/tracker.php?aid=2179610 +2179610 +2 +100 +516020 +103 +nobody +nobody +jerryjacobs +1224419959 +1267478642 +5 +Grid does not show correct +
The grid does not show correct on Windows Vista Premium 32 bit. Didn't have any problems in Windows XP Pro. +Using a Dell Vostro laptop with ATI express 1150 video card. +Any questions: allembedded(at)gmail.com
+0 + + +3917389 +jerryjacobs +1267478641 +
No problems with new version 2010-02-28-RC5.
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=297942&aid= +297942 +kicad_grid_problem.jpg +Screen dump +211860 +image/pjpeg +1224419959 +nobody + + + + +6747106 +IP +Artifact Created: 78.27.53.49 +1224419959 +nobody + + +6747107 +File Added +297942: kicad_grid_problem.jpg +1224419960 +nobody + + +9227657 +IP +Comment Added: 84.25.204.235 +1267478641 +jerryjacobs + + +9227658 +status_id +1 +1267478641 +jerryjacobs + + +9227659 +resolution_id +100 +1267478641 +jerryjacobs + + +9227660 +allow_comments +1 +1267478641 +jerryjacobs + + +9227661 +close_date +0 +1267478642 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2311317 +2311317 +2 +1015285 +100 +100 +nobody +nobody +dickelbeck +1227041284 +1234193061 +5 +Saving Netlist defaults to ".net*" +
Build v1409 recently downloaded (Mac OS X 10.5). When I generate a netlist from inside EESCHEMA it wants to save it as a .net* file. Then, of course, PCBNEW will not read it until I manually rename the file to .net +
+0 + + +3514910 +dickelbeck +1234193462 +
This seems to be a bug in the wxWidgets library or the Mac OS X's file globbing handler. There should be no reason the mask cannot have two '*'s in it. + +The wildcard part of the mask component should be discarded when the user picks an actual file. For now, we work around this bug by removing the 2nd mask. +
+ + + + + + +6997474 +IP +Artifact Created: 76.235.68.246 +1227041285 +nobody + + +7660948 +status_id +1 +1234193061 +dickelbeck + + +7660950 +allow_comments +1 +1234193061 +dickelbeck + + +7660951 +close_date +0 +1234193061 +dickelbeck + + +7661511 +IP +Comment Added: 67.64.64.34 +1234193463 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=2320616 +2320616 +2 +1015288 +755196 +2 +josh_eeg +nobody +jerryjacobs +1227271923 +1267478301 +5 +button in eeschema for cvpcb causes error +
button in eeschema for cvpcb causes error... but the button in the main kicad window for it works fine. +this was proably just some kind of link and forgoten from the old version...
+0 + + +3221247 +f3nix +1229888951 +
Please provide more information. Which version of Kicad are You using?
+ + + + + + +7015213 +IP +Artifact Created: 65.200.157.178 +1227271923 +josh_eeg + + +7252343 +IP +Comment Added: 83.12.84.19 +1229888951 +f3nix + + +9227632 +status_id +1 +1267478301 +jerryjacobs + + +9227633 +resolution_id +100 +1267478301 +jerryjacobs + + +9227634 +allow_comments +1 +1267478301 +jerryjacobs + + +9227635 +close_date +0 +1267478301 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2322351 +2322351 +2 +1015285 +755198 +1 +lomarcan +dickelbeck +diemer +1227295164 +1227524789 +5 +Fields moving on anchor repositioning +
When moving the anchor point in the module editor only the reference and the value stay 'fixed' (have their coordinate moved in relation with the new anchor). So, for example, the footprint field moves away (since it keeps the same coordinate but using the new reference!!)
+0 + + +3184370 +diemer +1227524789 +
Seems to have been fixed by Lorenzo in svn 1414 (checked in by dick).
+ + + + + + +7018194 +IP +Artifact Created: 87.6.39.198 +1227295164 +lomarcan + + +7043474 +IP +Comment Added: 134.169.117.46 +1227524789 +diemer + + +7043475 +status_id +1 +1227524789 +diemer + + +7043476 +resolution_id +100 +1227524789 +diemer + + +7043477 +assigned_to +100 +1227524789 +diemer + + +7043478 +close_date +0 +1227524789 +diemer + + + + +http://sourceforge.net/support/tracker.php?aid=2354212 +2354212 +1 +1015285 +516020 +100 +nobody +nobody +nobody +1227819286 +0 +5 +Numerical inputs dot/semicolon mixup +
Hi, +I'm having troubles with +numerical input fields in '20080906-r1238-win32' running on an english +Windows Vista in with German currency/math settings. + +Every time I'm asked for a numerical input, like size of a label, +preexisting inputs get converted to use a dot instead of a semicolon ( 0.04 +instead of 0,04). Now when I dont replace the dot with a semicolon again +the input will be taken as '0.0' no matter what I enter. + +Workaround: Replace . with , every time you open the dialog + +This Bug seems to apply to all kicad programs.
+0 + + +3198363 +nobody +1228293625 +
For me, this bug does not occur on the "release" versions (like 20080715). So maybe it's a compiler setting. You could change your input settings in the Vista system configuration, but that's no real solution.
+ + + + + + +7074056 +IP +Artifact Created: 91.96.8.52 +1227819286 +nobody + + +7114944 +IP +Comment Added: 217.250.51.45 +1228293625 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2359892 +2359892 +2 +761682 +100 +1 +jdoire +charras +f3nix +1227993952 +1229884827 +5 +description of icons is shifted down +
on page 3-10 of the pcbnew manual, the description of icons is shift down by one, for example the "Draw arcs on technical layers" is beside the text icon.
+0 + + +3221190 +f3nix +1229884827 +
This bug has been fixed
+ + +3221191 +f3nix +1229884827 +
Fixed in SVN r1437. +Thanks!
+ + + + + + +7084347 +IP +Artifact Created: 66.11.173.63 +1227993952 +jdoire + + +7084349 +summary +description of icons is shift down +1227994038 +jdoire + + +7252052 +IP +Comment Added: 83.12.84.19 +1229884827 +f3nix + + +7252053 +IP +Comment Added: 83.12.84.19 +1229884827 +f3nix + + +7252054 +status_id +1 +1229884827 +f3nix + + +7252055 +resolution_id +100 +1229884827 +f3nix + + +7252056 +assigned_to +100 +1229884827 +f3nix + + +7252057 +close_date +0 +1229884827 +f3nix + + + + +http://sourceforge.net/support/tracker.php?aid=2359898 +2359898 +2 +761682 +100 +101 +jdoire +f3nix +f3nix +1227994157 +1229885352 +5 +description of icons is shift down +
on page 3-10 of the pcbnew manual, the description of icons is shift down by one, for example the "Draw arcs on technical layers" is beside the text icon.
+0 + + +3221195 +f3nix +1229884991 +
Duplicate of 2359892
+ + +3221228 +f3nix +1229887893 +
This artifact has been marked as a duplicate of artifact 2359892 with reason: +No explanation provided.
+ + + + + + +7084357 +IP +Artifact Created: 66.11.173.63 +1227994157 +jdoire + + +7252068 +IP +Comment Added: 83.12.84.19 +1229884991 +f3nix + + +7252069 +status_id +1 +1229884991 +f3nix + + +7252070 +resolution_id +100 +1229884991 +f3nix + + +7252071 +close_date +0 +1229884991 +f3nix + + +7252094 +status_id +2 +1229885352 +f3nix + + +7252095 +assigned_to +100 +1229885352 +f3nix + + +7252096 +close_date +1229884991 +1229885352 +f3nix + + +7252254 +IP +Comment Added: 83.12.84.19 +1229887893 +f3nix + + +7252255 +status_id +3 +1229887893 +f3nix + + + + +http://sourceforge.net/support/tracker.php?aid=2388871 +2388871 +2 +761682 +516020 +100 +cfdev +nobody +dickelbeck +1228401171 +1228757110 +5 +Pcbnew to FreeRouter +
Version : 20080825c +OS : windowsXP, other don't tested +program : Pcbnew + + +hello, + +I try to use the export specctra fonction with FreeRouter, but the border egde in component are not detected by FreeRouter or when the exporting file ?! + +see the pictures attached for more details! + +thanks +Cfdev.
+0 + + +3204243 +dickelbeck +1228757108 +
The edges layer is for board edges and that boundary must be contiguous with itself. Your circles are not contiguous, and they indicate you want holes in the board. If you want holes, use a hole, not a board edge. + +Dick +
+ + +3206768 +cfdev +1228927884 +
ok, +should I use an pad to do what I want ? to do an hole ? + +thanks for you reply
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=304000&aid= +304000 +pcbnewToFreeRouter.zip +pictures +61190 +application/zip +1228401171 +cfdev + + + + +7128309 +IP +Artifact Created: 90.52.207.22 +1228401171 +cfdev + + +7128310 +File Added +304000: pcbnewToFreeRouter.zip +1228401172 +cfdev + + +7157759 +IP +Comment Added: 67.64.64.34 +1228757109 +dickelbeck + + +7157760 +status_id +1 +1228757110 +dickelbeck + + +7157761 +close_date +0 +1228757110 +dickelbeck + + +7170899 +IP +Comment Added: 90.52.207.22 +1228927884 +cfdev + + + + +http://sourceforge.net/support/tracker.php?aid=2397258 +2397258 +2 +761682 +100 +100 +nobody +nobody +sf-robot +1228589321 +1231208426 +5 +Error Type 4, Track near Pad +
Error Type 4, Track near Pad, so how can i connect a pad with some kind of copper to another one then?? :) + +W2K SP4, placing an SMD and trying to 'hand-wire' a little board. Each time i like to connect a pad with a wire i get this weird error-message. (yes and the connection IS thinner than the pad...) + +Tried to browse the man and FAQ's - nothing found btw, there is a help-contact missing!! ;) and within the docs a list of known errors! + +Another one, how to correct the lqfp44 permanently in the parallax-library(P8X32-Q) ? + +
+0 + + +3204299 +dickelbeck +1228758721 +
Can you provide an example board, with a JPG showing where the problem is? The track and the pad will need to be part of the same net, this usually means starting the track from the pad. The error may be from a neighboring pad, not from the one you think. Study the error message carefully in the marker please to verify. +
+ + +3285868 +sf-robot +1231208426 +
This Tracker item was closed automatically by the system. It was +previously set to a Pending status, and the original submitter +did not respond within 14 days (the time period specified by +the administrator of this Tracker).
+ + + + + + +7142986 +IP +Artifact Created: 87.234.37.11 +1228589322 +nobody + + +7157929 +IP +Comment Added: 67.64.64.34 +1228758721 +dickelbeck + + +7157930 +status_id +1 +1228758721 +dickelbeck + + +7157931 +close_date +0 +1228758721 +dickelbeck + + +7368965 +IP +Comment Added: +1231208426 +sf-robot + + +7368966 +status_id +4 +1231208426 +sf-robot + + +7368967 +close_date +1228758721 +1231208426 +sf-robot + + + + +http://sourceforge.net/support/tracker.php?aid=2441116 +2441116 +1 +100 +100 +100 +bachkhois +nobody +nobody +1229533045 +0 +5 +Segmentation fault since upgraded to Ubuntu 8.10 +
The KiCad's 3D-Viewer on my PC encounters Segmentation Fault since I upgraded to Ubuntu 8.10. The error didn't happen on Ubuntu 8.04 +
+0 + + + + + + +7217728 +IP +Artifact Created: 118.69.163.146 +1229533045 +bachkhois + + + + +http://sourceforge.net/support/tracker.php?aid=2489509 +2489509 +2 +100 +755196 +101 +nobody +f3nix +f3nix +1231220004 +1232608624 +5 +Build from download (but not svn) dies +
Build from download (not svn) dies on FindSubversion.cmake but works OK when I build from +a svn get. It seems that the Cmake process expects +to be built in a 'svn' working copy. I get the process +to work by commenting the following lines from +CMakeLists.txt + +#if(UNIX) +# include(CreateSVNVersionHeader) +# create_svn_version_header() +#endif(UNIX) + +--------------------------------------- +> svn --version +svn, version 1.5.0 (dev build) + compiled Jun 7 2008, 01:10:17 +-------------------------------------------- + + +If I download the tar.bz2 and build as prescribed: + + mkdir -p build/release + cd build/releasecmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=/home/ken/kicad ../../ + +I get the following message: + +CMake Error at /usr/share/cmake/Modules/FindSubversion.cmake:81 (MESSAGE): +Command "/usr/bin/svn info /home/ken/tools/kicad/kicad" failed with output: + + svn: '/home/ken/tools/kicad/kicad' is not a working copy + +Call Stack (most recent call first): + CMakeModules/CreateSVNVersionHeader.cmake:5 (Subversion_WC_INFO) + CMakeLists.txt:118 (create_svn_version_header) +
+0 + + + + + + +7369746 +IP +Artifact Created: 66.159.224.125 +1231220004 +nobody + + +7505153 +status_id +1 +1232608623 +f3nix + + +7505154 +resolution_id +100 +1232608624 +f3nix + + +7505155 +assigned_to +100 +1232608624 +f3nix + + +7505156 +allow_comments +1 +1232608624 +f3nix + + +7505157 +close_date +0 +1232608624 +f3nix + + + + +http://sourceforge.net/support/tracker.php?aid=2492717 +2492717 +2 +100 +755196 +2 +nobody +nobody +jerryjacobs +1231361803 +1267478242 +5 +Build from download (but not svn) dies +
Build from download (not svn) dies on FindSubversion.cmake but works OK when I build from +a svn get. It seems that the Cmake process expects +to be built in a 'svn' working copy. I get the process +to work by commenting the following lines from +CMakeLists.txt + +#if(UNIX) +# include(CreateSVNVersionHeader) +# create_svn_version_header() +#endif(UNIX) + +--------------------------------------- +> svn --version +svn, version 1.5.0 (dev build) + compiled Jun 7 2008, 01:10:17 +-------------------------------------------- + + +If I download the tar.bz2 and build as prescribed: + + mkdir -p build/release + cd build/releasecmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=/home/ken/kicad ../../ + +I get the following message: + +CMake Error at /usr/share/cmake/Modules/FindSubversion.cmake:81 (MESSAGE): +Command "/usr/bin/svn info /home/ken/tools/kicad/kicad" failed with output: + + svn: '/home/ken/tools/kicad/kicad' is not a working copy + +Call Stack (most recent call first): + CMakeModules/CreateSVNVersionHeader.cmake:5 (Subversion_WC_INFO) + CMakeLists.txt:118 (create_svn_version_header) +
+0 + + + + + + +7382057 +IP +Artifact Created: 66.159.224.125 +1231361803 +nobody + + +9227626 +status_id +1 +1267478242 +jerryjacobs + + +9227627 +resolution_id +100 +1267478242 +jerryjacobs + + +9227628 +allow_comments +1 +1267478242 +jerryjacobs + + +9227629 +close_date +0 +1267478242 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2493551 +2493551 +2 +761682 +516020 +100 +cfdev +nobody +cfdev +1231410333 +1244792053 +5 +NetList and Pcbnew +
Version : 20080825c +OS : windowsXP, other don't tested +program : Pcbnew + + +hello, + +when the General net connection is show, there is an difference with the routing mode ? (see Attach File) + +the connection on routing mode is correct but not the other! + + +can you fixed it + +Thanks
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=308253&aid= +308253 +PB_interco.PNG + +44909 +image/png +1231410333 +cfdev + + + + +7388038 +IP +Artifact Created: 90.27.240.57 +1231410333 +cfdev + + +7388039 +File Added +308253: PB_interco.PNG +1231410333 +cfdev + + +8367971 +status_id +1 +1244792053 +cfdev + + +8367972 +allow_comments +1 +1244792053 +cfdev + + +8367973 +close_date +0 +1244792053 +cfdev + + + + +http://sourceforge.net/support/tracker.php?aid=2602865 +2602865 +1 +761682 +516020 +100 +dandumit +nobody +nobody +1234712274 +0 +5 +Change Same Modules make PCBNEW Crash +
Hi, + +A very handy function makes PCBNEW crash. +Over one module : right click mouse : +footprint>edit>change module>change same modules +On that text box it seems to update all modules from board but after that application crashes. + +REgards, +Daniel
+0 + + + + + + +7714397 +IP +Artifact Created: 89.34.224.194 +1234712274 +dandumit + + + + +http://sourceforge.net/support/tracker.php?aid=2610468 +2610468 +1 +761682 +516020 +100 +reniemarquet +nobody +nobody +1234909731 +0 +5 +Copy block in Modedit broken (20090216-RC1) +
In 20090216-RC1, + +Copying a block with pads, the modedit frezen and broken PcbNew. + +Note: tested in Win XP (SP2) and Win 2000
+0 + + + + + + +7733151 +IP +Artifact Created: 200.157.229.6 +1234909731 +reniemarquet + + + + +http://sourceforge.net/support/tracker.php?aid=2614648 +2614648 +1 +761682 +516020 +100 +reniemarquet +nobody +nobody +1235006901 +0 +5 +Button Cancel in Add Field don't work (20090216-RC1 +
In 20090216-RC1 (tested in Win XP), + +In PcbNew, right click a module, go to dialog Module Properties, click Add Field, the button Cancel +don't work, the new field is created with text = text.
+0 + + + + + + +7742210 +IP +Artifact Created: 189.25.221.16 +1235006901 +reniemarquet + + + + +http://sourceforge.net/support/tracker.php?aid=2625090 +2625090 +1 +1015288 +755198 +100 +arius-marius +nobody +nobody +1235245689 +0 +5 +CVpcb - language selection +
Hi, + +I have used KiCAD under WinXP in revision 1604. + +It is not possible to change the language for the CVpcb frame on the fly as it is possible for all the other frames like KiCad, Eeschema, ... + +/********************************************************/ +void WinEDA_CvpcbFrame::SetLanguage( wxCommandEvent& event ) +/********************************************************/ +{ + int id = event.GetId(); + + wxGetApp().SetLanguageIdentifier( id ); + wxGetApp().SetLanguage(); +} + +... could be possibly changed to ... + +/********************************************************/ +void WinEDA_CvpcbFrame::SetLanguage( wxCommandEvent& event ) +/********************************************************/ +{ + wxGetApp().SetLanguageIdentifier( event.GetId() ); + if ( wxGetApp().SetLanguage() ) + { + wxLogDebug( wxT( "Recreating menu bar due to language change." ) ); + ReCreateMenuBar(); + Refresh(); + } +} + +-arius-
+0 + + +3546155 +arius-marius +1235247615 +
The proposed solution works fine and allowes switching between the languages. + +-arius-
+ + +3546675 +arius-marius +1235304619 +
File Added: cvpcb_language-selection.patch
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=314638&aid= +314638 +cvpcb_language-selection.patch +Patch +618 +application/octet-stream +1235304619 +arius-marius + + + + +7764533 +IP +Artifact Created: 78.55.181.244 +1235245689 +arius-marius + + +7764686 +IP +Comment Added: 78.55.181.244 +1235247616 +arius-marius + + +7768469 +File Added +314638: cvpcb_language-selection.patch +1235304619 +arius-marius + + +7768470 +IP +Comment Added: 92.227.128.196 +1235304619 +arius-marius + + + + +http://sourceforge.net/support/tracker.php?aid=2625434 +2625434 +2 +761682 +516020 +1 +arius-marius +nobody +jerryjacobs +1235253500 +1267476991 +5 +Crash after trying to edit a line/drawing +
PCBnew in revision 1604 on WinXP + +1) Start PCBnew +2) Select layer: Edges_Pcb +3) Select tool for drawing a graphical line or polygon +4) Click into the drawing area to set the beginning of the line but do not stop the drawing tool +5) Right click to get the popup menu shown and select "Edit Drawing" -> PCBnew crashes at this point + +-arius-
+0 + + +3917358 +jerryjacobs +1267476991 +
Tested with new version.
+ + + + + + +7765097 +IP +Artifact Created: 78.55.181.244 +1235253500 +arius-marius + + +9227539 +IP +Comment Added: 84.25.204.235 +1267476991 +jerryjacobs + + +9227540 +status_id +1 +1267476991 +jerryjacobs + + +9227541 +resolution_id +100 +1267476991 +jerryjacobs + + +9227542 +allow_comments +1 +1267476991 +jerryjacobs + + +9227543 +close_date +0 +1267476991 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2628615 +2628615 +1 +761682 +100 +100 +arius-marius +nobody +nobody +1235333230 +0 +5 +Error message after right click into zone +
A right click into a zone to start filling leads to different error messages: +a) "WinEDA_PcbFrame::OnRightClick() Error: unknown DrawType 20907816" +b) "WinEDA_PcbFrame::OnRightClick() Error: illegal DrawType 0" + +1) I have two resistors on the board both together connected with wires. +2) I have drawn a zone outline around the components. +3) Right clicked into the zone area and selected from context menu "Fill or Refill All Zones". +4) Selected from context menu "Remove Filled Areas in All Zones" +5) Right click into the zone area leads sometimes to the mentioned error messages with different numbers for the draw type. + +Repeat step 3) to 5) until the error shows if not already occured. + +-arius-
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=314677&aid= +314677 +project.zip + +3714 +application/zip +1235333230 +arius-marius + + + + +7770529 +IP +Artifact Created: 92.227.128.196 +1235333230 +arius-marius + + +7770530 +File Added +314677: project.zip +1235333230 +arius-marius + + + + +http://sourceforge.net/support/tracker.php?aid=2630243 +2630243 +1 +100 +100 +100 +nobody +nobody +nobody +1235398324 +0 +5 +Unconnected pads issue +
After connecting pads with tracks, some of the connections are not recognized anymore. The connecting track is highlighted when clicking on it, but ratsnest and DRC still show the two pads as unconnected. This is not a "magnetic pads" issue, it occurs also when the tracks start exactly at the right coordinates. Google for "kicad unconnected pads", and you will find some interesting threads about it. Occurs in all versions so far.
+0 + + + + + + +7774964 +IP +Artifact Created: 89.217.201.158 +1235398324 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2653411 +2653411 +2 +1015285 +100 +2 +nobody +nobody +jerryjacobs +1235962821 +1267477927 +5 +No fields in component editor (RC4)! +
Just testing RC4 and found a great field list for schematic components. +But there is (hopefully) a bug here: The "fields" tab in the properties is completely gone! I don't think this is a feature as most users would use this to put things like stock IDs and manufacturers partnumbers in here which need to be edited at part creation time. + +
+0 + + +3568308 +oecherexpat +1236726657 +
Thanks for the help, it is NO bug.
+ + +3570255 +cfdev +1236855442 +
hi, + +it's not a bug! +the fields tab has changed for an list. I use too the fields to put the manufacturers number ...Now to enter this you can click on "Add field" and specifie what you want and it will be added to the list. + +++
+ + + + + + +7824590 +IP +Artifact Created: 222.153.213.254 +1235962821 +nobody + + +7887467 +IP +Comment Added: 222.153.213.254 +1236726657 +oecherexpat + + +7897539 +IP +Comment Added: 90.52.151.208 +1236855442 +cfdev + + +9227593 +status_id +1 +1267477927 +jerryjacobs + + +9227594 +resolution_id +100 +1267477927 +jerryjacobs + + +9227595 +allow_comments +1 +1267477927 +jerryjacobs + + +9227596 +close_date +0 +1267477927 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2656502 +2656502 +1 +1015285 +100 +100 +imrehg +nobody +nobody +1236060552 +0 +5 +wrong reference "transistors" library +
In the template/kicad.pro the "transistors" library is referenced as "transistor", thus resulting in error message when starting eeschema.
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=315928&aid= +315928 +template.patch +patch +289 +application/octet-stream +1236060552 +imrehg + + + + +7832744 +IP +Artifact Created: 140.109.113.62 +1236060552 +imrehg + + +7832745 +File Added +315928: template.patch +1236060552 +imrehg + + + + +http://sourceforge.net/support/tracker.php?aid=2660689 +2660689 +2 +761682 +100 +103 +rom4ik +nobody +jerryjacobs +1236156431 +1267476762 +5 +Unconnected pads in RC4 +
Symptoms are the same as for ID: 2630243. Repeatable only when using RC4 + +Problem: To route one track it is necessary to route it two times. + +Steps: +1. After the first routing http://img240.imageshack.us/img240/1061/step1.png +2. After the second routing http://img8.imageshack.us/img8/2830/step2q.png +3. Context menu for the track(s) http://img14.imageshack.us/img14/1943/step3j.png + +If the PCB is saved after the step 1 and loaded again - all OK. +
+0 + + +3559481 +rom4ik +1236156570 +
File Added: step2.PNG
+ + +3559483 +rom4ik +1236156599 +
File Added: step3.PNG
+ + +3917353 +jerryjacobs +1267476762 +
Don't have this problem.
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=316114&aid= +316114 +step1.PNG + +8772 +image/png +1236156431 +rom4ik + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=316116&aid= +316116 +step2.PNG + +9073 +image/png +1236156570 +rom4ik + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=316117&aid= +316117 +step3.PNG + +10277 +image/png +1236156599 +rom4ik + + + + +7842333 +IP +Artifact Created: 81.26.156.254 +1236156431 +rom4ik + + +7842334 +File Added +316114: step1.PNG +1236156431 +rom4ik + + +7842346 +File Added +316116: step2.PNG +1236156570 +rom4ik + + +7842347 +IP +Comment Added: 81.26.156.254 +1236156570 +rom4ik + + +7842355 +File Added +316117: step3.PNG +1236156599 +rom4ik + + +7842356 +IP +Comment Added: 81.26.156.254 +1236156599 +rom4ik + + +9227512 +IP +Comment Added: 84.25.204.235 +1267476762 +jerryjacobs + + +9227513 +status_id +1 +1267476762 +jerryjacobs + + +9227514 +resolution_id +100 +1267476762 +jerryjacobs + + +9227515 +allow_comments +1 +1267476762 +jerryjacobs + + +9227516 +close_date +0 +1267476762 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2661362 +2661362 +1 +1015288 +516020 +100 +jacobeluz +nobody +nobody +1236168613 +0 +5 +CVpcb open problem +
in CVpcb when klicking the open netlist it do nothing
+0 + + + + + + +7843625 +IP +Artifact Created: 212.179.61.36 +1236168613 +jacobeluz + + + + +http://sourceforge.net/support/tracker.php?aid=2680621 +2680621 +2 +761682 +516020 +1 +oecherexpat +nobody +jerryjacobs +1236726994 +1267476309 +5 +Print issue under RC4 +
When printing (not plotting) PCB documentation with more than 1 layer, the background is printed black. +For instance: Silkscreen and primary copper enabled -> background turns black on preview. Doesn't need to be a copper layer, same appears with silkscreen and solder mask enabled. + +Tested under WinXP-SP3 and 20090216-RC4
+0 + + +3917346 +jerryjacobs +1267476309 +
Closing old bug works for newer version.
+ + + + + + +7887489 +IP +Artifact Created: 222.153.213.254 +1236726994 +oecherexpat + + +9227464 +IP +Comment Added: 84.25.204.235 +1267476309 +jerryjacobs + + +9227465 +status_id +1 +1267476309 +jerryjacobs + + +9227466 +resolution_id +100 +1267476309 +jerryjacobs + + +9227467 +close_date +0 +1267476309 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2680640 +2680640 +1 +1015285 +100 +100 +oecherexpat +nobody +nobody +1236727590 +0 +5 +Number of fields is fixed to 9 in BOM +
An unlimited number of fields can be created for schematic symbols. When it comes to generating the BOM, only "footprint" and the first 8 fields can be selected to be printed. + +Field names are nowhere mentioned in the generated BOM, it's left to the user to make them common. This is very flexible but might lead to mistakes. A suggestion would be to have editable but global field names which could replace the "field x" labels.
+0 + + + + + + +7887535 +IP +Artifact Created: 222.153.213.254 +1236727590 +oecherexpat + + + + +http://sourceforge.net/support/tracker.php?aid=2689603 +2689603 +1 +1015285 +100 +100 +yneko +nobody +nobody +1237267149 +0 +5 +mis-connecting of VCCs of two different voltage +
Please see this message; +http://tech.groups.yahoo.com/group/kicad-users/message/4878 + +Place one 74HC00, name it U1, click "Show hidden pins", and connect its Vcc to "+3.3V" power port and GND to "GND". +Place one 74HC04, name it U2, connect its Vcc to "+5V" power port and GND to "GND". +14pin of U1 and 14pin of U2 are connected on netlist, but they should be separated normally.
+0 + + + + + + +7930780 +IP +Artifact Created: 203.141.143.22 +1237267149 +yneko + + + + +http://sourceforge.net/support/tracker.php?aid=2692073 +2692073 +1 +1015285 +100 +100 +wolverine222 +nobody +nobody +1237391885 +0 +5 +"reset to library defaults" fails in RC6 +
The "reset to library defaults" in component properties does not change the value of the fields, only its position.
+0 + + + + + + +7947011 +IP +Artifact Created: 213.63.0.163 +1237391885 +wolverine222 + + + + +http://sourceforge.net/support/tracker.php?aid=2724843 +2724843 +1 +761682 +100 +100 +lomarcan +nobody +nobody +1238581664 +0 +5 +Offset thermaled pads don't register as 'connected' +
An oval pad (maybe rectangular too) with offset hole, when thermaled, do not always register as connected (see screen shot)
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=320638&aid= +320638 +bad_thermal.png +Screenshot of anomaly +54135 +image/png +1238581664 +lomarcan + + + + +8064289 +IP +Artifact Created: 88.149.185.186 +1238581664 +lomarcan + + +8064290 +File Added +320638: bad_thermal.png +1238581665 +lomarcan + + + + +http://sourceforge.net/support/tracker.php?aid=2738052 +2738052 +1 +761682 +755196 +100 +nobody +nobody +nobody +1239037729 +0 +5 +"Remove: StructType 19 Inattendu" on deleting zone +
Attempting to delete a zone outline in 20090216-final release causes the error "Remove: StructType 19 Inattendu". The zone is not deleted. + +Steps to reproduce: + +Open a new board, create zone outline, attempt to delete zone outline.
+0 + + + + + + +8098147 +IP +Artifact Created: 82.71.75.78 +1239037729 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2773272 +2773272 +1 +1015285 +755198 +100 +nobody +nobody +nobody +1240095334 +0 +5 +Annotation disregards U?A +
When Assigning power to only U?A but not U?B and the other units of a device and then connecting special power to that, eeschema ignores this upon annotation. Meaning it then often places the A-unit somewhere else which cuts the power connection. + +Also, as Brian Sidebotham suggested in the Newsgroup eeschema should also ideally not touch the A, B, C, D ... assignments at all during annotate. In the analog world this can cause problems because we purposely assign units per thermal tracking within chips, for crosstalk mitigation, and other reasons. + +Regards, + +Joerg Schulze-Clewing +joergsch@analogconsultants.com
+0 + + + + + + +8176350 +IP +Artifact Created: 75.26.197.12 +1240095334 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2775460 +2775460 +1 +100 +755196 +100 +bennett78 +bennett78 +nobody +1240198444 +0 +4 +minor make install bug +
# svn info +Path: . +URL: https://kicad.svn.sourceforge.net/svnroot/kicad/trunk/kicad +Repository Root: https://kicad.svn.sourceforge.net/svnroot/kicad +Repository UUID: 16bec504-3128-0410-b3e8-8e38c2123bca +Revision: 1734 +Node Kind: directory +Schedule: normal +Last Changed Author: charras +Last Changed Rev: 1734 +Last Changed Date: 2009-04-19 10:03:48 -0600 (Sun, 19 Apr 2009) +# pwd +/s/opt/svn/kicad/trunk/kicad +# make -f makefile.gtk install +make[1]: Entering directory `/s/opt/svn/kicad/trunk/kicad/internat' +cp -R cs /usr/local/kicad/share/internat +cp -R de /usr/local/kicad/share/internat +cp -R es /usr/local/kicad/share/internat +cp -R fr /usr/local/kicad/share/internat +cp -R hu /usr/local/kicad/share/internat +cp -R it /usr/local/kicad/share/internat +cp -R ko /usr/local/kicad/share/internat +cp -R pl /usr/local/kicad/share/internat +cp -R pt /usr/local/kicad/share/internat +cp -R ru /usr/local/kicad/share/internat +cp -R sl /usr/local/kicad/share/internat +make[1]: Leaving directory `/s/opt/svn/kicad/trunk/kicad/internat' +make: *** modules: No such file or directory. Stop. +make[1]: Entering directory `/s/opt/svn/kicad/trunk/kicad/template' +cp -R kicad.pro /usr/local/kicad/share/template +make[1]: Leaving directory `/s/opt/svn/kicad/trunk/kicad/template' +make: *** library: No such file or directory. Stop. +make: *** [install-res] Error 2 +# ls internat/ +total 68 +4 ca/ 4 cs/ 4 es/ 4 hu/ 4 ko/ 4 nl/ 4 pt/ 4 sl/ 4 zh_CN/ +4 CMakeLists.txt 4 de/ 4 fr/ 4 it/ 4 makefile 4 pl/ 4 ru/ 4 sv/ +# ls template/ +total 16 +4 CMakeLists.txt 8 kicad.pro 4 makefile +
+0 + + +3635295 +bennett78 +1240755923 +
This bug has been fixed
+ + +3635296 +bennett78 +1240755923 +
works ok using cmake
+ + + + + + +8182864 +IP +Artifact Created: 76.76.79.173 +1240198444 +bennett78 + + +8214866 +IP +Comment Added: 76.76.79.173 +1240755923 +bennett78 + + +8214867 +IP +Comment Added: 76.76.79.173 +1240755923 +bennett78 + + +8214868 +assigned_to +100 +1240755923 +bennett78 + + + + +http://sourceforge.net/support/tracker.php?aid=2779049 +2779049 +1 +1015285 +755197 +100 +nobody +nobody +nobody +1240442409 +0 +5 +Osx addpart hangs +
In Osx 10.5.6, +Kicad r-1736 Eeschema hangs, when creating new part-> Add pins. + +About dialog does not work. + +
+0 + + +3635203 +hyarion +1240749162 +
(using r-17361) +it seems to only be a problem when adding the first pin... +a quick workaround: +1) save your component without adding any pins +2) close eeschema (this way we know that the library will be reloaded) +2) open up the library in a texteditor and a pin to the component and save it +3) open up eeschema and add new pins + +The about dialog in the help menu works but not the one in the program menu
+ + + + + + +8197557 +IP +Artifact Created: 195.148.50.152 +1240442410 +nobody + + +8214499 +IP +Comment Added: 85.24.222.45 +1240749164 +hyarion + + + + +http://sourceforge.net/support/tracker.php?aid=2783715 +2783715 +2 +100 +100 +1 +imrehg +nobody +imrehg +1241018427 +1241597747 +5 +make install error: missing file footprints_doc +
make install fails because of missing file in current revision (1743) and for some time now (I tried 1741 earlier and that fails as well). Here's the log cut to the relevant part: + +[......] +-- Installing: /tmp/kicad-svn/pkg/usr/share/doc/kicad/help/file_formats +-- Installing: /tmp/kicad-svn/pkg/usr/share/doc/kicad/help/file_formats/file_formats.pdf +CMake Error at doc/help/cmake_install.cmake:48 (FILE): + file INSTALL cannot find file + "/tmp/kicad-svn/src/kicad-doc/doc/help/footprints_doc" + to install. +Call Stack (most recent call first): + cmake_install.cmake:38 (INCLUDE) +
+0 + + +3639270 +imrehg +1241020580 +
checking out the svn tree, in rev1734 the directory was moved but the CMake files weren't changed. attached proposed fix. +(git format-patch format, sorry! :)
+ + +3648338 +imrehg +1241597747 +
This bug has been fixed
+ + +3648339 +imrehg +1241597747 +
rev1745 fixed this
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=324972&aid= +324972 +fix-2783715.patch +proposed fix +1592 +application/octet-stream +1241020404 +imrehg + + + + +8226988 +IP +Artifact Created: 118.168.179.18 +1241018427 +imrehg + + +8227109 +File Added +324972: fix-2783715.patch +1241020404 +imrehg + + +8227118 +IP +Comment Added: 118.168.179.18 +1241020580 +imrehg + + +8251861 +IP +Comment Added: 140.109.112.215 +1241597747 +imrehg + + +8251862 +IP +Comment Added: 140.109.112.215 +1241597747 +imrehg + + +8251863 +status_id +1 +1241597747 +imrehg + + +8251864 +resolution_id +100 +1241597747 +imrehg + + +8251865 +allow_comments +1 +1241597747 +imrehg + + +8251866 +close_date +0 +1241597747 +imrehg + + + + +http://sourceforge.net/support/tracker.php?aid=2788629 +2788629 +2 +1015285 +755198 +1 +henryvt +nobody +jerryjacobs +1241729593 +1267478792 +5 +Clock pins incorrect in 74LS393 +
The clock pins are currently common to both halves of the 74LS393. The attached patch fixes this. (svn diff to 1754)
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=326162&aid= +326162 +74393.patch +svn diff aginst svn rev 1754 +996 +text/x-diff +1241729594 +henryvt + + + + +8257099 +IP +Artifact Created: 75.8.123.171 +1241729594 +henryvt + + +8257100 +File Added +326162: 74393.patch +1241729595 +henryvt + + +9227669 +status_id +1 +1267478792 +jerryjacobs + + +9227670 +resolution_id +100 +1267478792 +jerryjacobs + + +9227671 +allow_comments +1 +1267478792 +jerryjacobs + + +9227672 +close_date +0 +1267478792 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2790760 +2790760 +2 +761682 +755196 +6 +nobody +nobody +jerryjacobs +1242145667 +1267479205 +5 +very slow PCBNEW +
moving, rotating, placing modules is very slow when version 2.16 of package libgtk2.0-0 (debian package) is used +package description: http://packages.debian.org/search?suite=all&section=all&arch=any&searchon=names&keywords=libgtk2.0-0 +with version 2.12 and 2.14 PCBNEW is OK, with 2.16 PCBNEW is slow, other GTK+ applications are OK
+0 + + +3658430 +jerryjacobs +1242851376 +
I have no problems here: +Debian 64Bits (Testing/Unstable), GTK2+ 2.16.1, KiCad SVN 1771
+ + +3791082 +nobody +1256658858 +
Problem disappears. It was caused probably by inconsistency in libraries versions.
+ + + + + + +8274835 +IP +Artifact Created: 147.229.200.42 +1242145667 +nobody + + +8300617 +IP +Comment Added: 84.25.219.10 +1242851376 +jerryjacobs + + +8821252 +IP +Comment Added: 147.229.220.96 +1256658858 +nobody + + +9227707 +status_id +1 +1267479205 +jerryjacobs + + +9227708 +resolution_id +100 +1267479205 +jerryjacobs + + +9227709 +allow_comments +1 +1267479205 +jerryjacobs + + +9227710 +close_date +0 +1267479205 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2797109 +2797109 +2 +761682 +755198 +100 +bennett78 +nobody +bennett78 +1243378709 +1244414173 +7 +ratsnest on connected nets +
The attached 4 layer design example has 2 pins connected to a GND plane zone on an internal +layer using 2 through hole vias. The ratsnest still shows an non-connection between the two pins. +Freeroute doesn't show the extra ratsnests. But I wonder if the via type is correct! + +Using a two sided board seems to work ok.
+0 + + +3669588 +bennett78 +1244139351 +
All nets (connections) to Zones show as disconnects until zone fills are enabled +and then agree with DRC. However the rat's nest is hard to see with zones filled. + +Filled zones show keepout areas but should not be necessary to detect connectivity. +I suggest that vias to named zones be considered good enough to establish a +connection and not showup in the rats nest.
+ + +3671567 +bennett78 +1244414173 +
Workaround - select from left toolbar "don't show filled area in zones" then run DRC + +Note: turning general rats nest on/off via left toolbar misses a Redraw event for off! +Requiring a redraw button push.
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=328554&aid= +328554 +rats.zip +eeschema, netl and brd file +3436 +application/zip +1243378709 +bennett78 + + + + +8316899 +IP +Artifact Created: 76.76.79.173 +1243378709 +bennett78 + + +8316900 +File Added +328554: rats.zip +1243378710 +bennett78 + + +8344692 +IP +Comment Added: 76.76.79.173 +1244139351 +bennett78 + + +8352444 +IP +Comment Added: 76.76.79.173 +1244414173 +bennett78 + + +8352445 +status_id +1 +1244414173 +bennett78 + + +8352446 +allow_comments +1 +1244414173 +bennett78 + + +8352447 +close_date +0 +1244414173 +bennett78 + + + + +http://sourceforge.net/support/tracker.php?aid=2797788 +2797788 +2 +761682 +755198 +1 +nobody +diemer +jerryjacobs +1243502912 +1267478119 +5 +Module Editor: Display Grid Button not working +
In r1783 the "Display Grid" Button in the footprint editor (module editor) isn't working as expected: When pressed, the grid disappears as desired. However, there is no way to re-enable the grid by pressing the button again.
+0 + + +3663728 +paxer +1243505015 +
Here is a patch: + + +Index: pcbnew/tool_modedit.cpp +=================================================================== +--- pcbnew/tool_modedit.cpp (revision 1783) ++++ pcbnew/tool_modedit.cpp (working copy) +@@ -203,8 +203,10 @@ + + m_OptionsToolBar->AddTool( ID_TB_OPTIONS_SHOW_GRID, wxEmptyString, + wxBitmap( grid_xpm ), +- _( "Display Grid OFF" ) ); ++ _( "Display Grid OFF" ), wxITEM_CHECK ); + ++ m_OptionsToolBar->ToggleTool( ID_TB_OPTIONS_SHOW_GRID, m_Draw_Grid ); ++ + m_OptionsToolBar->AddTool( ID_TB_OPTIONS_SHOW_POLAR_COORD, wxEmptyString, + wxBitmap( polar_coord_xpm ), + _( "Display Polar Coord ON" ), wxITEM_CHECK ); +
+ + +3663803 +diemer +1243510744 +
Applied patch in r1785
+ + + + + + +8321166 +IP +Artifact Created: 134.169.117.87 +1243502912 +nobody + + +8321316 +IP +Comment Added: 134.169.117.87 +1243505015 +paxer + + +8321498 +artifact_group_id +100 +1243509895 +diemer + + +8321499 +assigned_to +100 +1243509895 +diemer + + +8321576 +IP +Comment Added: 134.169.117.46 +1243510744 +diemer + + +8321577 +resolution_id +100 +1243510744 +diemer + + +9227613 +status_id +1 +1267478119 +jerryjacobs + + +9227614 +allow_comments +1 +1267478119 +jerryjacobs + + +9227615 +close_date +0 +1267478119 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2801809 +2801809 +2 +1015285 +755198 +1 +cfdev +nobody +cfdev +1244217274 +1270653409 +5 +Translation bug +
Hi, +see the attach file ;) +EESCHEMA stable 20090216-Final + +++
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=329867&aid= +329867 +Translation_bug.png + +14071 +image/png +1244217274 +cfdev + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=331195&aid= +331195 +rename_file.png + +12283 +image/png +1245165180 +cfdev + + + + +8347302 +IP +Artifact Created: 90.52.202.205 +1244217274 +cfdev + + +8347303 +File Added +329867: Translation_bug.png +1244217274 +cfdev + + +8380400 +File Added +331195: rename_file.png +1245165180 +cfdev + + +9374967 +status_id +1 +1270653409 +cfdev + + +9374968 +resolution_id +100 +1270653409 +cfdev + + +9374969 +close_date +0 +1270653409 +cfdev + + + + +http://sourceforge.net/support/tracker.php?aid=2802877 +2802877 +2 +1015285 +755198 +1 +cfdev +nobody +cfdev +1244462389 +1244791484 +5 +Properties of libEdit +
hi + +In the properties of libEdit, the tab "DOC" and the field "Doc" are visibly an not good nomination. (see the attach file) +"Description" are better ?
+0 + + +3672100 +nobody +1244467832 +
Bug closed on svn trunk 1810
+ + +3672102 +nobody +1244467848 +
Bug closed on svn trunk 1810
+ + +3675325 +cfdev +1244791484 +
This bug has been fixed
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=330161&aid= +330161 +Properties_LibEdit.png + +9736 +image/png +1244462390 +cfdev + + + + +8354126 +IP +Artifact Created: 90.52.202.205 +1244462390 +cfdev + + +8354127 +File Added +330161: Properties_LibEdit.png +1244462390 +cfdev + + +8354925 +IP +Comment Added: 84.25.137.47 +1244467832 +nobody + + +8354930 +IP +Comment Added: 84.25.137.47 +1244467848 +nobody + + +8367952 +IP +Comment Added: 90.52.202.205 +1244791484 +cfdev + + +8367953 +status_id +1 +1244791484 +cfdev + + +8367954 +resolution_id +100 +1244791484 +cfdev + + +8367955 +allow_comments +1 +1244791484 +cfdev + + +8367956 +close_date +0 +1244791484 +cfdev + + + + +http://sourceforge.net/support/tracker.php?aid=2803506 +2803506 +2 +1015285 +755198 +1 +cfdev +nobody +cfdev +1244554724 +1244789299 +5 +Mirror of an bloc of bus connection +
hi, + +I saw an bug when I mirrored an bloc of bus... see the attach file + +thx
+0 + + +3674999 +jerryjacobs +1244748173 +
Bug fixed SVN-1812 + +2009-june-11 UPDATE Jean-Pierre Charras <jean-pierre.charras@gipsa-lab.inpg.fr> +================================================================================ +++Eeschema: + Added text justification for graphic texts in libedit + Minor bug 2803506 fixed (error when mirroring bus entries) + Some code cleaning. + Better locating algo for arcs in libedit
+ + +3675316 +cfdev +1244789210 +
well done
+ + +3675317 +cfdev +1244789299 +
This bug has been fixed
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=330328&aid= +330328 +bus_mirrors.png + +8713 +image/png +1244554725 +cfdev + + + + +8358315 +IP +Artifact Created: 90.52.202.205 +1244554725 +cfdev + + +8358316 +File Added +330328: bus_mirrors.png +1244554725 +cfdev + + +8366664 +IP +Comment Added: 84.25.137.47 +1244748173 +jerryjacobs + + +8367900 +IP +Comment Added: 90.52.202.205 +1244789210 +cfdev + + +8367901 +IP +Comment Added: 90.52.202.205 +1244789299 +cfdev + + +8367902 +status_id +1 +1244789299 +cfdev + + +8367903 +resolution_id +100 +1244789299 +cfdev + + +8367904 +allow_comments +1 +1244789299 +cfdev + + +8367905 +close_date +0 +1244789299 +cfdev + + + + +http://sourceforge.net/support/tracker.php?aid=2807228 +2807228 +1 +1015285 +100 +100 +briansidebotham +nobody +nobody +1245166312 +0 +5 +Adding a library with a relative library path +
If when editing the Preferences->Library dialog, a relative path is used +for the Default library file path, KiCad successfully navigates to the +correct directory when the Add button is used to add a library. However, +instead of adding the selected library name, it adds the complete file path +instead. + +If the .pro preferences file is edited by hand the relative library path +works fine.
+0 + + + + + + +8380481 +IP +Artifact Created: 87.74.132.43 +1245166312 +briansidebotham + + + + +http://sourceforge.net/support/tracker.php?aid=2807295 +2807295 +1 +1015285 +100 +100 +nobody +nobody +nobody +1245174876 +0 +5 +Error in cursor position +
I just dled the latest build for the osx (nice that there is a mac build, thanks). However when moving parts and adding wires, I have to offset the cursor in order for it to be at the proper place. basically I have to go about 45 degrees NE of where it should be. This makes doing anything quite a chore. + +Also shouldn't it create automatically the noname.pro, the first time kikad is run?
+0 + + + + + + +8380891 +IP +Artifact Created: 189.137.59.158 +1245174876 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2810360 +2810360 +2 +761682 +516020 +1 +lodentoni +nobody +jerryjacobs +1245686902 +1267478558 +5 +negative plot is complete black +
Hi, +there is a problem with generating negative plots in postscript format. If I try to plot layers which contain text items the generated *.ps file shows a complete black board. +I discussed it on mikrocontroller.net. We found out that in the .ps file are wrong lines ("0.000 0.000 0.000 setrgbcolor"), if they were deleted, the negative plot did work. + +I use FreePDFXP to generate PDFs from the .ps file.
+0 + + +3917388 +jerryjacobs +1267478558 +
Board plots correct with 2010-02-28-RC5
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=331946&aid= +331946 +Filmtest.brd +example file +205076 +application/octet-stream +1245686903 +lodentoni + + + + +8397600 +IP +Artifact Created: 193.174.73.86 +1245686903 +lodentoni + + +8397601 +File Added +331946: Filmtest.brd +1245686904 +lodentoni + + +9227652 +IP +Comment Added: 84.25.204.235 +1267478558 +jerryjacobs + + +9227653 +status_id +1 +1267478558 +jerryjacobs + + +9227654 +resolution_id +100 +1267478558 +jerryjacobs + + +9227655 +allow_comments +1 +1267478558 +jerryjacobs + + +9227656 +close_date +0 +1267478558 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2813170 +2813170 +1 +1015285 +755196 +100 +sergeiste +nobody +nobody +1246094130 +0 +5 +senselsess/unhelpful error message +
I have a multi-level block/schematics (3 levels of hierarchy). + +If I'm running "Schematic Annotation" on the whole schematics, I'm getting the a popup window with the following error message: + +Multiple item C1 (unit 1) +. + +The version is: Build: (20090216-final) (SUSE-10.3). + +Since 'eeschema' is capable of detecting multiple "C1" items, it knows in which subblocks/files th eitem is present, so to make this message sensible/helpful it should tell the use where to look for the mistake he/she has made - it doesn't at the moment. + +If necessary, I'll upload the schematics, but as far as I can tell from the message the bug is not specific WRT my schematics, i.e. it will manifest itself in any similar case.
+0 + + + + + + +8412887 +IP +Artifact Created: 87.69.49.127 +1246094130 +sergeiste + + + + +http://sourceforge.net/support/tracker.php?aid=2813187 +2813187 +2 +1015285 +755196 +1 +sergeiste +nobody +jerryjacobs +1246097678 +1267478210 +5 +'eeschema' segfaults when requested to create BOM +
This is apparently a regression - it happens in kicad-2009-02-16-final and it doesn't happen in kicad-full-version-2008-08-25c-final. + +BOM == Bill of materials. + +The details. + +If I start 'eeschema' afresh, with no editor to browse BOM set, in kicad-full-version-2008-08-25c-final 'eeschema' first asks about the editor location, I then enter full path to the editor, them it creates BOM. + +In case of kicad-2009-02-16-final 'eeschema' does not ask about editor location and just crashes with segmentation fault.
+0 + + +3917382 +jerryjacobs +1267478210 +
BOM creation reworked, should work now.
+ + + + + + +8412998 +IP +Artifact Created: 87.69.49.127 +1246097678 +sergeiste + + +8412999 +priority +5 +1246097774 +sergeiste + + +9227619 +IP +Comment Added: 84.25.204.235 +1267478210 +jerryjacobs + + +9227620 +status_id +1 +1267478210 +jerryjacobs + + +9227621 +resolution_id +100 +1267478210 +jerryjacobs + + +9227622 +priority +8 +1267478210 +jerryjacobs + + +9227623 +allow_comments +1 +1267478210 +jerryjacobs + + +9227624 +close_date +0 +1267478210 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2813190 +2813190 +1 +1015285 +755196 +100 +sergeiste +nobody +nobody +1246098758 +0 +5 +wrong BOM generation for hierarchical block +
As a simple case I have two blocks, let's call the 'father', 'son', and 'son' is instantiated four times into 'father'. + +If I choose to generate BOM (Bill of materials) for 'father', I'm getting it only for the 'father', but not for the sons. This is senseless - I need BOM for the whole thing in order to correctly create the list of components I need to order. + +And such hierarchical BOM generation should be the default.
+0 + + + + + + +8413014 +IP +Artifact Created: 87.69.49.127 +1246098758 +sergeiste + + + + +http://sourceforge.net/support/tracker.php?aid=2813197 +2813197 +1 +1015285 +755196 +100 +sergeiste +nobody +nobody +1246099870 +0 +5 +wrong BOM generation for hierarchical block +
As a simple case I have two blocks, let's call the 'father', 'son', and 'son' is instantiated four times into 'father'. + +If I choose to generate BOM (Bill of materials) for 'father', I'm getting it only for the 'father', but not for the sons. This is senseless - I need BOM for the whole thing in order to correctly create the list of components I need to order. + +And such hierarchical BOM generation should be the default.
+0 + + + + + + +8413045 +IP +Artifact Created: 87.69.49.127 +1246099870 +sergeiste + + + + +http://sourceforge.net/support/tracker.php?aid=2813200 +2813200 +1 +1015285 +755196 +100 +sergeiste +nobody +nobody +1246100364 +0 +5 +'eeschema' allows instances with the same name +
When I add sons to top level block using "Place the hierarchical sheet", a form with two fields pops up - the fields are file name and sheet name. + +While the file name can be any, and can be repetitive (several instances of the same subblock), sheet name, which is instance name, should be unique in a given sheet. + +In a hierarchical design items are identifies as + +top_level.instance_name_1.instance_name_2...instance_name_N.item_name + +where item_name is node, component, etc. + +I.e. at each hierarchical level instance names should be unique - otherwise it's impossible to differentiate between the instances. It's the same as if in a family twins are born, they are given different names - twins in this case are like different instances of the same subblock.
+0 + + + + + + +8413057 +IP +Artifact Created: 87.69.49.127 +1246100364 +sergeiste + + + + +http://sourceforge.net/support/tracker.php?aid=2813959 +2813959 +2 +1015287 +516020 +102 +cfdev +nobody +cfdev +1246280321 +1270653742 +6 +Gerber import incorrect +
Hi, +To replace the missing import dxf or svg..., I tried to import the gerber generate by ORCAD in GerbView in first, and export to pcbnew in second... + +I was 2 bugs : +-when I load the gbr file in GerbView this is an different with the GC-prevue (gerber tool free).the circle is normally not complet, but GerbView draw an entire circle !!?? + +-Wen I export this gbr file to pcbnew with GerbView, Pcbnew draws an polygone ?! + +see the attach file +++ +
+0 + + +3955347 +cfdev +1270653742 +
Only -> Gerbview to pcbnew It's Ok
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=332785&aid= +332785 +Gerber_import.png +gerber import +30100 +image/png +1246280321 +cfdev + + + + +8417218 +IP +Artifact Created: 90.52.63.25 +1246280321 +cfdev + + +8417219 +File Added +332785: Gerber_import.png +1246280321 +cfdev + + +8417222 +priority +5 +1246280371 +cfdev + + +9227667 +summary +Import Gerber wasn't correct ?! +1267478761 +jerryjacobs + + +9374996 +IP +Comment Added: 92.153.22.228 +1270653742 +cfdev + + +9374997 +status_id +1 +1270653742 +cfdev + + +9374998 +resolution_id +100 +1270653742 +cfdev + + +9374999 +close_date +0 +1270653742 +cfdev + + + + +http://sourceforge.net/support/tracker.php?aid=2819678 +2819678 +2 +100 +100 +1 +mnurolcay +nobody +jerryjacobs +1247238686 +1267478824 +5 +start up error +
Im using the latest svn revision of Kicad, im getting an error for all start ups what says "the project file not found bla bla". Just attached screenshot
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=334524&aid= +334524 +kicad.png +Kicad start up error +37077 +image/png +1247238687 +mnurolcay + + + + +8455879 +IP +Artifact Created: 78.161.89.148 +1247238687 +mnurolcay + + +8455880 +File Added +334524: kicad.png +1247238687 +mnurolcay + + +9227674 +status_id +1 +1267478824 +jerryjacobs + + +9227675 +resolution_id +100 +1267478824 +jerryjacobs + + +9227676 +allow_comments +1 +1267478824 +jerryjacobs + + +9227677 +close_date +0 +1267478824 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2825880 +2825880 +2 +761682 +516020 +100 +cfdev +nobody +cfdev +1248340641 +1270653964 +4 +[PCBNEW]Preview of print +
PCBNEW stable version 20090216 final + +I have 4 layers, In preview of print, the interne layers 2 and 3 are inverse ! +to show this I have annotate all layers. it's an small bug ok. + +++
+0 + + + + + + +8499477 +IP +Artifact Created: 90.52.57.77 +1248340641 +cfdev + + +8499478 +priority +5 +1248340658 +cfdev + + +9375018 +status_id +1 +1270653964 +cfdev + + +9375019 +allow_comments +1 +1270653964 +cfdev + + +9375020 +close_date +0 +1270653964 +cfdev + + + + +http://sourceforge.net/support/tracker.php?aid=2828243 +2828243 +1 +1015285 +100 +100 +brummig +nobody +nobody +1248765255 +0 +5 +Component Footprint Dialog Faulty +
Selecting Edit Component...Footprint from the context menu displays in a simple dialog the current text of the component footprint (eg SM0603). If one clicks OK the footprint is retained, but if one clicks Cancel the entire text is deleted from the footprint field (rather than any edits being ignored). + +EESCHEMA 20090216-final running on WinXP/SP3, but probably also affects the previous EESCHEMA release as that was when I first noticed that I appeared to be randomly losing footprint assignments.
+0 + + + + + + +8513812 +IP +Artifact Created: 83.216.148.11 +1248765255 +brummig + + + + +http://sourceforge.net/support/tracker.php?aid=2831506 +2831506 +1 +100 +755196 +100 +frohro +nobody +nobody +1249308323 +0 +5 +Path Names with spaces don't work for Component Docs +
If you want to like a PDF datasheet to a library component, there is a nice way to do this in the library editor, however it seems not to work if your path contains spaces in it. For example this path fails: + +/home/frohro/Araya Classes/Prop & Rad/DG8SAQ VNA/AD9859.pdf + +Rob
+0 + + + + + + +8534214 +IP +Artifact Created: 66.62.174.7 +1249308323 +frohro + + + + +http://sourceforge.net/support/tracker.php?aid=2836106 +2836106 +1 +761682 +516020 +100 +brummig +nobody +nobody +1250069065 +0 +5 +CombineAreas() Error +
After moving a node on a copper layer zone PCBNew displayed a message box: + +Error +! BOARD::CombineAreas() error: unexpected outside contour descriptor +[OK] + +Clicking OK caused the message box to be redisplayed, seemingly ad-infinitum. PCBNew had to be shut down forcibly with the task manager. + +Windows XP/SP3/PCBNew 20090216-final/WxWidgets 2.8.10 Unicode +
+0 + + + + + + +8561142 +IP +Artifact Created: 83.216.148.11 +1250069065 +brummig + + + + +http://sourceforge.net/support/tracker.php?aid=2836748 +2836748 +1 +761682 +755196 +100 +bioname +charras +nobody +1250147319 +0 +5 +dialog_edit_module_for_modedit_base.cpp +
CMake Error in pcbnew/CMakeLists.txt: + Cannot find source file "dialog_edit_module_for_modedit_base.cpp". Tried + extensions .c .C .c++ .cc .cpp .cxx .m .M .mm .h .hh .h++ .hm .hpp .hxx .in + .txx +At revision 1921. (1920) +found: +pcbnew/dialog_edit_module_for_Modedit_base.cpp
+1 + + +3724387 +bioname +1250147737 +
also +dialog_edit_module_for_Modedit.cpp +pls update pcbnew/CMakeLists.txt
+ + +3724427 +bioname +1250151142 +
pls update files: +CMakeLists.txt ++ dialog_edit_module_for_Modedit_base.cpp +- dialog_edit_module_for_modedit_base.cpp ++ dialog_edit_module_for_Modedit.cpp +- dialog_edit_module_for_modedit.cpp + +dialog_edit_module_for_Modedit.cpp +-#include "dialog_edit_module_for_modedit.h" ++#include "dialog_edit_module_for_Modedit.h" + +dialog_edit_module_for_Modedit.h +-#include "dialog_edit_module_for_modedit_base.h" ++#include "dialog_edit_module_for_Modedit_base.h" + +modedit.cpp +-#include "dialog_edit_module_for_modedit.h" ++#include "dialog_edit_module_for_Modedit.h" +
+ + + + + + +8564217 +IP +Artifact Created: 194.110.126.3 +1250147319 +bioname + + +8564237 +IP +Comment Added: 194.110.126.3 +1250147737 +bioname + + +8564327 +IP +Comment Added: 194.110.126.3 +1250151142 +bioname + + +8564328 +artifact_group_id +100 +1250151142 +bioname + + +8564329 +assigned_to +100 +1250151142 +bioname + + +8564330 +is_private +0 +1250151142 +bioname + + + + +http://sourceforge.net/support/tracker.php?aid=2839630 +2839630 +1 +761682 +516020 +100 +nobody +nobody +nobody +1250604186 +0 +5 +connecting net to GND zone - +
after refilling a GND zone in layer Inner_L1 on a 4 layer PCB, net "Sheet4A1" is connected to ground plane !! + +
+0 + + +3740337 +zougloub +1252015312 +
Hi, + +I can also reproduce the problem. +Procedure : + - load the model supplied by "nobody" + - click "add zones" + - perform a refill of zones + - diplay the L1 layer + +Then you can see on the bottom left part that the signal Sheet4A1 is connected to the ground plane. + +When using a 32-segment/360° arcs approximation in the fill zone, the bug does not appear when filling the zone. +
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=339609&aid= +339609 +Inner_L1-refilling-PB.brd +board +188296 +application/octet-stream +1250604186 +nobody + + + + +8582448 +IP +Artifact Created: 207.134.5.122 +1250604186 +nobody + + +8582449 +File Added +339609: Inner_L1-refilling-PB.brd +1250604187 +nobody + + +8634128 +IP +Comment Added: 207.134.5.122 +1252015312 +zougloub + + + + +http://sourceforge.net/support/tracker.php?aid=2840150 +2840150 +2 +1015288 +755198 +100 +jerryjacobs +nobody +jerryjacobs +1250673352 +1250785911 +5 +Close component view closes cvpcb bug +
Hi Jerry, + +I have one more problem with Kicad (rev. 1931). If you close the component-preview window of cvpcb, cvpcb also closes itself. Can you please fix this? + +Thanks +Michael
+0 + + +3730097 +nobody +1250778881 +
fix by charras. Thanks!
+ + +3730181 +jerryjacobs +1250785910 +
Closed by Jean-Pierre Charras
+ + + + + + +8585931 +IP +Artifact Created: 84.25.137.47 +1250673352 +jerryjacobs + + +8590274 +IP +Comment Added: 87.163.116.176 +1250778881 +nobody + + +8590548 +IP +Comment Added: 84.25.137.47 +1250785911 +jerryjacobs + + +8590549 +status_id +1 +1250785911 +jerryjacobs + + +8590550 +close_date +0 +1250785911 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2840153 +2840153 +2 +761682 +100 +100 +jerryjacobs +nobody +jerryjacobs +1250673511 +1250785966 +5 +PCBnew svn 1931 text size edit error and then closes +
Hi, + +also in PCBnew rev. 1931 is a bug: When you edit a module, and set the text size, and make it more little a message box occures: "Text size will be claimed". Then pcbnew closes itself. Hope you can also help me with this issue. + +Thanks a lot + +Michael
+0 + + +3730098 +nobody +1250778910 +
fixed by charras. Thanks!
+ + +3730183 +jerryjacobs +1250785966 +
Closed by Jean-Pierre Charras
+ + + + + + +8585937 +IP +Artifact Created: 84.25.137.47 +1250673511 +jerryjacobs + + +8590276 +IP +Comment Added: 87.163.116.176 +1250778910 +nobody + + +8590552 +IP +Comment Added: 84.25.137.47 +1250785966 +jerryjacobs + + +8590553 +status_id +1 +1250785966 +jerryjacobs + + +8590554 +allow_comments +1 +1250785966 +jerryjacobs + + +8590555 +close_date +0 +1250785966 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2840154 +2840154 +2 +761682 +100 +100 +jerryjacobs +nobody +jerryjacobs +1250673612 +1250786005 +5 +PCBnew netlist bad module to delete closes pcbnew +
Hi Jerry, + +sorry for sending you so much bugs. But I have one more problem: If you read the netlist for the pcb and set bad modules to delete, you are ask if it's okay. If you press okay, pcbnew just closes. + +Sorry for sending you so much bugs, but you are my kicad-contact-person number one. + +Michael
+0 + + +3730100 +nobody +1250778956 +
Fixed by Charras. Thanks. Michael
+ + +3730184 +jerryjacobs +1250786005 +
Closed by Jean-Pierre Charras
+ + + + + + +8585938 +IP +Artifact Created: 84.25.137.47 +1250673612 +jerryjacobs + + +8590278 +IP +Comment Added: 87.163.116.176 +1250778956 +nobody + + +8590556 +IP +Comment Added: 84.25.137.47 +1250786005 +jerryjacobs + + +8590557 +status_id +1 +1250786005 +jerryjacobs + + +8590558 +allow_comments +1 +1250786005 +jerryjacobs + + +8590559 +close_date +0 +1250786005 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2849000 +2849000 +1 +100 +100 +100 +nobody +nobody +nobody +1251888110 +0 +5 +Bottommask Soldering stop: Viapads not print +
I just want to order a pcb, and my manufaturare tells me that the bottom pads are not okay. Eg. Via Pads are not printed. TOP is all right! Could you please fix this very very fast? + +Thank you a lot! + +Michael + +Please look at the attachment +
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=341463&aid= +341463 +crisdriver1rc2v2-loetstopp.zip + +3054 +application/zip +1251888111 +nobody + + + + +8628341 +IP +Artifact Created: 217.233.178.203 +1251888110 +nobody + + +8628342 +File Added +341463: crisdriver1rc2v2-loetstopp.zip +1251888111 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2870835 +2870835 +1 +1015285 +755198 +100 +nobody +nobody +nobody +1254326956 +0 +5 +Direction wrong in global/hierarchical label properties +
I do not know whether the radio buttons "right up left down" are supposed to refer to the text or to the connection point. Either way, they are wrong 50% of the time. The text actually goes "left up right down" while the connection point goes "right down left up". + +My preference would be to refer to the connection point, and simply relabel the radio buttons in the order "right down left up". + +-- Pat Maupin
+0 + + + + + + +8723638 +IP +Artifact Created: 209.217.155.166 +1254326956 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2874346 +2874346 +1 +1015285 +100 +100 +sb-sf +nobody +nobody +1254950934 +0 +5 +Annotation exchanges parts and breaks circuit +
If component parts contains different component elements (such as relay coil in one part and contacts in other) annotation can change part numbers and replace coil part with contacts part. Annotation should not change parts in heterogeneous components, other words if part created with "Edit pins part per part" turned on.
+0 + + +3775275 +nobody +1255285282 +
False. +This is option "Parts are locked" that must be checked
+ + + + + + +8747123 +IP +Artifact Created: 91.135.22.160 +1254950934 +sb-sf + + +8760464 +IP +Comment Added: 90.9.167.135 +1255285282 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2883987 +2883987 +1 +761682 +100 +100 +nobody +nobody +nobody +1256223796 +0 +5 +Can't import *ses +
I tried to use the online Freerouter and it worked out fine. My problem is that whenever I try to import the generated *.ses file I get the following error-message: +Expecting 'number' in file C:\...\project.ses on line 62 at offset 21 +BOARD may be corrupted, do not save it. +Fix problem and try again. +What's the problem?
+0 + + + + + + +8805288 +IP +Artifact Created: 129.187.5.225 +1256223796 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2885162 +2885162 +2 +100 +100 +1 +nobody +nobody +jerryjacobs +1256346001 +1267476032 +5 +Documentation Needs Updating.... +
Hi, + +The help files say Shift Left Mouse Button mirrors, but that seems out of date. Similar problems with other button mouse combinations. The pages for these updates are 8 and 9. + +Rob
+0 + + +3917339 +jerryjacobs +1267476032 +
Done some time ago by jean-pierre
+ + + + + + +8810426 +IP +Artifact Created: 66.62.174.2 +1256346001 +nobody + + +9227434 +IP +Comment Added: 84.25.204.235 +1267476032 +jerryjacobs + + +9227435 +status_id +1 +1267476032 +jerryjacobs + + +9227436 +resolution_id +100 +1267476032 +jerryjacobs + + +9227437 +allow_comments +1 +1267476032 +jerryjacobs + + +9227438 +close_date +0 +1267476032 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2885164 +2885164 +2 +1015285 +755196 +100 +frohro +nobody +frohro +1256346382 +1256676494 +5 +ERC Arrows don't change color when Options Change +
Hi, +I was successful changing the arrow color in EESchema only once. Now it is stuck with the red color I chose, no matter what I select in the preferences. I'll upload the schematic file. + +Rob
+0 + + +3791314 +frohro +1256676492 +
This appears to be fixed as of r2056 at least in svn.
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=347967&aid= +347967 +VNA.sch +Schematic that the color won't change in. +71449 +application/octet-stream +1256346382 +frohro + + + + +8810440 +IP +Artifact Created: 66.62.174.2 +1256346382 +frohro + + +8810441 +File Added +347967: VNA.sch +1256346382 +frohro + + +8822232 +IP +Comment Added: 66.62.165.3 +1256676492 +frohro + + +8822233 +status_id +1 +1256676494 +frohro + + +8822234 +allow_comments +1 +1256676494 +frohro + + +8822235 +close_date +0 +1256676494 +frohro + + + + +http://sourceforge.net/support/tracker.php?aid=2886059 +2886059 +2 +761682 +100 +100 +frohro +nobody +frohro +1256497453 +1256676045 +5 +3D Viewer doesn't show text mirrored correctly. +
The text on the 3D viewer copper layer isn't shown reading correctly when mirrored. (You should be able to rotate the board around and see it correctly, but it doesn't show that way. It is still backwards.) + +Rob
+0 + + +3791308 +frohro +1256676043 +
This appears to be fixed at least in r2056.
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=348134&aid= +348134 +$savepcb-drc.rpt +Here is an example file. +170 +application/octet-stream +1256497454 +frohro + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=348171&aid= +348171 +M0DFI.lib +library file needed +18101 +application/octet-stream +1256523211 +frohro + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=348172&aid= +348172 +attiny.lib +another library file needed for the example +15083 +application/octet-stream +1256523249 +frohro + + + + +8815683 +IP +Artifact Created: 66.62.174.2 +1256497453 +frohro + + +8815684 +File Added +348134: $savepcb-drc.rpt +1256497454 +frohro + + +8816447 +File Added +348171: M0DFI.lib +1256523212 +frohro + + +8816448 +File Added +348172: attiny.lib +1256523249 +frohro + + +8822203 +IP +Comment Added: 66.62.165.3 +1256676043 +frohro + + +8822204 +status_id +1 +1256676045 +frohro + + +8822205 +allow_comments +1 +1256676045 +frohro + + +8822206 +close_date +0 +1256676045 +frohro + + + + +http://sourceforge.net/support/tracker.php?aid=2886431 +2886431 +1 +1015285 +755196 +100 +frohro +nobody +nobody +1256557413 +0 +5 +Powers with different names, & same pin names are connected. +
I have four regulators for different analog and digital power supplies on my circuit supplying the same voltage. So I made them up by copying one and changing the names of the powers, however, I did not change the pin names because they all are the same voltage. EESchema makes them all connected at least according to ERC. I think this is unexpected behavior that could cause circuit errors. + +You can find the circuit in my last bug report, number 2886059. The problems are with AVDD_RF AVDD_LO and +1.8VD_LO and +1.8VD_RF being connected. + +Rob
+0 + + +3790971 +charras +1256648597 +
I do not see any schematic file and library cache file uploaded. +Any *must* give the version of kicad you are using.
+ + +3791323 +frohro +1256676964 +
This is still there as of r2056.
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=348442&aid= +348442 +VNA.sch +This is the correct file, not the one in the previous bug, but the libraries are still needed. +75102 +application/octet-stream +1256677093 +frohro + + + + +8817272 +IP +Artifact Created: 66.62.174.2 +1256557414 +frohro + + +8820768 +IP +Comment Added: 81.255.31.5 +1256648597 +charras + + +8822271 +IP +Comment Added: 66.62.165.3 +1256676964 +frohro + + +8822274 +File Added +348442: VNA.sch +1256677093 +frohro + + + + +http://sourceforge.net/support/tracker.php?aid=2888951 +2888951 +2 +100 +100 +1 +frohro +nobody +stambaughw +1256839106 +1268752763 +5 +Zoom scroll jumps around now.... +
Since the last development release I note that when you use the scroll wheel to zoom, the center point that you are zooming in seems to move about 25% of the time now. This used to work fine, but something changed between february 2009 release and r2056.
+0 + + +3931587 +stambaughw +1268752763 +
Fixed in R2312
+ + + + + + +8829748 +IP +Artifact Created: 66.62.165.3 +1256839106 +frohro + + +9290247 +IP +Comment Added: 162.83.115.135 +1268752763 +stambaughw + + +9290248 +status_id +1 +1268752763 +stambaughw + + +9290249 +resolution_id +100 +1268752763 +stambaughw + + +9290250 +allow_comments +1 +1268752763 +stambaughw + + +9290251 +close_date +0 +1268752763 +stambaughw + + + + +http://sourceforge.net/support/tracker.php?aid=2897050 +2897050 +2 +761682 +100 +2 +nobody +nobody +jerryjacobs +1258095928 +1267478063 +5 +Layer Setup dialog controls are sticked together +
all Layer setup dialog controls appears in the left-top corner of its area - all in the same position
+0 + + + + + + +8874192 +IP +Artifact Created: 195.122.227.150 +1258095928 +nobody + + +9110321 +resolution_id +100 +1264531786 +charras + + +9227602 +status_id +1 +1267478063 +jerryjacobs + + +9227603 +allow_comments +1 +1267478063 +jerryjacobs + + +9227604 +close_date +0 +1267478063 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2897763 +2897763 +3 +1015288 +516020 +100 +nobody +nobody +jerryjacobs +1258221864 +1267476064 +5 +path with spaces does not allow saving of .net +
On a windows install, if the directory path has a period in it, saving the .net file fails. CVPCB screen disappears but the executable remains in the task manager. Adding module libraries to CVPCB and footprint associations cannot be done if the project has a period in the directory path.
+1 + + + + + + +8878348 +IP +Artifact Created: 24.108.210.16 +1258221864 +nobody + + +9227439 +status_id +1 +1267476064 +jerryjacobs + + +9227440 +is_private +0 +1267476064 +jerryjacobs + + +9227441 +close_date +0 +1267476064 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2897772 +2897772 +1 +1015288 +516020 +100 +nobody +nobody +nobody +1258223571 +0 +5 +path with spaces does not allow saving of .net +
On a windows install, if the directory path has a period in it, saving the .net file fails. CVPCB screen disappears but the executable remains in the task manager. Adding module libraries to CVPCB and footprint associations cannot be done if the project has a period in the directory path.
+0 + + + + + + +8878407 +IP +Artifact Created: 24.108.210.16 +1258223571 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2903063 +2903063 +2 +761682 +755196 +6 +crasic +nobody +jerryjacobs +1259063690 +1259173359 +5 +Zoom-in with an arc Causes Xorg to crash +
Relevant information: + +Radeon mobile x300 video card +Kernel 2.6.31 +Xorg 1.7.1.902 (confirmed with other 1.7.1.x xorgs as well) +Kicad 20090216-final (also confirmed with latest svn build) + +Description: +In PCBNEW, upon zooming in to zoom 50 or higher. Xorg crashes reporting a segmentation fault. (PCBnew goes with it as well, obviously) + +This only happens when there is an graphical Arc on the drawing layer OR edges layer of the pcboard. Otherwise everything works as usual. + +This only started happening on update from Xorg 1.6.9 + +I'm tempted to think its an xorg issue since it only started after an update. But considering how many bugs are reported on xorg, I wanted to report it here in order to get some insight on the issue and to have a more specific issue to report to the xorg devels (like segfault on this or that system call) rather than just "crashes on kicad zoom in". + +Potentially something changed in the xorg api from 1.6 to 1.7 so it might be some kicad library misbehaving. But I know next to nothing about X so I cant confirm. + +I'm on running arch, and most of these packages havent trickled down to more stable distro's so I havent confirmed if it happens on other distro's/hardware. +
+0 + + +3815988 +jerryjacobs +1259079594 +
In Fedora 12 virtual machine with Xorg 1.7.1 and svn 2117 no problems. +On my slackware 12.2 with Nvidia driver and Xorg 1.4.2 no problems. +On ubuntu 9.10 with nvidia driver (dont know X version) no problems. + +I think there is somethings wrong maybe with the packages/libraries that are incompatible, or a driver issue. Or just a bad Xorg build ...
+ + +3816329 +crasic +1259102641 +
It seems the issue is the radeon driver, I just tried with a generic vesa driver and there is no issue. + +Its strange that the issue is so specific... Its only happened in PCBnew and under these conditions specific conditions. Any idea as to what exactly crashes the driver would help in reporting the bug to radeon developers. + +
+ + +3817302 +jerryjacobs +1259173359 +
This bug is closed because there is no real bug inside pcbnew with other setups and VESA driver, seems a bug inside driver of ATI Radeon.
+ + + + + + +8911102 +IP +Artifact Created: 67.180.26.5 +1259063690 +crasic + + +8911825 +IP +Comment Added: 84.25.204.235 +1259079594 +jerryjacobs + + +8912901 +IP +Comment Added: 67.180.26.5 +1259102641 +crasic + + +8915494 +IP +Comment Added: 84.25.204.235 +1259173359 +jerryjacobs + + +8915495 +status_id +1 +1259173359 +jerryjacobs + + +8915496 +resolution_id +100 +1259173359 +jerryjacobs + + +8915497 +assigned_to +100 +1259173359 +jerryjacobs + + +8915498 +allow_comments +1 +1259173359 +jerryjacobs + + +8915499 +close_date +0 +1259173359 +jerryjacobs + + +9332816 +assigned_to +2066563 +1269776551 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2904058 +2904058 +2 +1015285 +100 +100 +sb-sf +nobody +charras +1259184904 +1264441962 +5 +Selecting pointer icon doesn't deselct active tool +
Selecting upper right icon with arrow doesn't deselect current selected tool. Tool icon remains selected, while pointer icon selects too. The only way to "drop" active tool is "End tool" item in right-click drop-down menu.
+0 + + +3817491 +sb-sf +1259184992 +
P.S. tested on svn revision 2117
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=352566&aid= +352566 +screenshot.jpg + +4517 +image/jpeg +1259184905 +sb-sf + + + + +8916003 +IP +Artifact Created: 91.135.22.160 +1259184904 +sb-sf + + +8916007 +File Added +352566: screenshot.jpg +1259184905 +sb-sf + + +8916010 +IP +Comment Added: 91.135.22.160 +1259184992 +sb-sf + + +9106723 +status_id +1 +1264441962 +charras + + +9106724 +allow_comments +1 +1264441962 +charras + + +9106725 +close_date +0 +1264441962 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2906754 +2906754 +2 +761682 +516020 +1 +sb-sf +nobody +jerryjacobs +1259672887 +1259783630 +5 +Board ratsnest unconditionally displayed after block command +
After block command (move/copy) ratsnest displayed independently of "Show board ratsnest" icon pressed/released state. Ratsnest disappears only after single component move or checking-unchecking "Show board ratsnest" icon + +svn rev. 2117
+0 + + +3824708 +sb-sf +1259750526 +
seems like bug introduced into ratsnest.cpp in rev. 1901: http://kicad.svn.sourceforge.net/viewvc/kicad/trunk/kicad/pcbnew/ratsnest.cpp?r1=1860&r2=1901 +calling function with DC == 0 causes VISIBLE flag to remain set. Removing back DC from condition seems bug to be solved.
+ + +3825121 +jerryjacobs +1259783630 +
This bug has been fixed
+ + +3825122 +jerryjacobs +1259783630 +
Seems to be fixed revision 2125
+ + + + + + +8932547 +IP +Artifact Created: 91.135.22.160 +1259672891 +sb-sf + + +8936331 +IP +Comment Added: 91.135.22.160 +1259750526 +sb-sf + + +8937922 +IP +Comment Added: 84.25.204.235 +1259783630 +jerryjacobs + + +8937923 +IP +Comment Added: 84.25.204.235 +1259783630 +jerryjacobs + + +8937924 +status_id +1 +1259783630 +jerryjacobs + + +8937925 +resolution_id +100 +1259783630 +jerryjacobs + + +8937926 +allow_comments +1 +1259783630 +jerryjacobs + + +8937927 +close_date +0 +1259783630 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2906799 +2906799 +2 +761682 +516020 +105 +sb-sf +nobody +jerryjacobs +1259675337 +1267478082 +5 +Hotkeys doesn't work in some cases +
Delete track/Delete segment hotkeys doesn't work in Cancel tool mode (right toolbar Icon with arrow selected) while they are still available throw right click pop-up menu. In Placement of tracks and vias mode hotkeys work as desired. + +svn rev 2117.
+0 + + + + + + +8932664 +IP +Artifact Created: 91.135.22.160 +1259675337 +sb-sf + + +9110320 +resolution_id +100 +1264531704 +charras + + +9227607 +status_id +1 +1267478082 +jerryjacobs + + +9227608 +allow_comments +1 +1267478082 +jerryjacobs + + +9227609 +close_date +0 +1267478082 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2907870 +2907870 +1 +1015285 +516020 +100 +tregare +nobody +nobody +1259805175 +0 +5 +ERC Randomly reports connections as missing. +
While working on a schematic, I ran ERC and it informed me I had missing connections(errors). I corrected those and saved, made sure the markers were cleared and re-ran ERC, different pins/connections were showing as missing. corrected those , cleared markers and saved. Re-Ran the ERC, the connections I had just fixed were showing as errors. + +this is rather frustrating.
+0 + + +3825365 +tregare +1259805213 +
the version is 20090216-final
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=353672&aid= +353672 +74xx_tester.erc + +324 +application/octet-stream +1259805175 +tregare + + + + +8938868 +IP +Artifact Created: 12.153.241.168 +1259805175 +tregare + + +8938869 +File Added +353672: 74xx_tester.erc +1259805176 +tregare + + +8938870 +IP +Comment Added: 12.153.241.168 +1259805213 +tregare + + + + +http://sourceforge.net/support/tracker.php?aid=2909237 +2909237 +1 +100 +755196 +100 +werner2101 +nobody +nobody +1260007258 +0 +5 +sourceforge file download outdated +
The files on SF are outdated: +https://sourceforge.net/projects/kicad/files/ + +It's hard to find the current version of kicad. +This led to an rpm packaging error on openSUSE: +http://bugzilla.novell.com/show_bug.cgi?id=549936 + +The kicad-library does not work with the current kicad +package. +kicad-library 1.0 is incompatible with the latest kicad package which is located at http://iut-tice.ujf-grenoble.fr/cao/kicad-sources-2009-02-16.tar.gz + +Please consider to publish updated and compatible packages on SF. + +Regards +Werner Hoch + + +
+0 + + + + + + +8947082 +IP +Artifact Created: 87.179.12.225 +1260007258 +werner2101 + + + + +http://sourceforge.net/support/tracker.php?aid=2909498 +2909498 +2 +1015285 +755196 +103 +nobody +nobody +jerryjacobs +1260076874 +1267476506 +5 +Plotting PostScript omits unhidden field text +
I have a schematic containing single-pin connectors (component CONN_1). By default the 'Value' field is not shown (the Show Text check box is clear). I edited the 'Value' field and checked the Show Text checkbox. In EESchema the Value field becomes visible. When I plot the schematic as PostScript the Value field is not shown. When I plot the schematic as SVG the Value field is shown. + +I am using Build Version: KiCad (2007-11-29-a) - Unicode version. This is the packaged version shipped with my distro. I have not looked for this bug (or a bug fix) in a later version. + +This is not a big problem for me, but since I noticed it I thought it might be useful to report it. Great piece of software!! Thanks.
+0 + + +3828259 +jerryjacobs +1260093266 +
Please have a look at a newer release, or try to compile yourself to do more bug hunting to make next release more bugfree. Thanks for you comment, i will have a look at this with latest source.
+ + +3917349 +jerryjacobs +1267476506 +
Working with newer version.
+ + + + + + +8948540 +IP +Artifact Created: 119.199.147.51 +1260076874 +nobody + + +8948697 +IP +Comment Added: 84.25.204.235 +1260093266 +jerryjacobs + + +9227478 +IP +Comment Added: 84.25.204.235 +1267476506 +jerryjacobs + + +9227479 +status_id +1 +1267476506 +jerryjacobs + + +9227480 +resolution_id +100 +1267476506 +jerryjacobs + + +9227481 +allow_comments +1 +1267476506 +jerryjacobs + + +9227482 +close_date +0 +1267476506 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2909776 +2909776 +1 +1015285 +516020 +100 +hyperflexed +nobody +nobody +1260140067 +0 +5 +Rendering glitch with wire to bus connections +
Windows Version. + +Steps to reproduce: +1. Create a bus +2. Add wire to bus entries to bus +3. Holding down CTRL + SHIFT, group select the bus and wire to bus connections (drag a rectangle) to delete +4. Note that the wire to bus connectors still remain visible +5. Zoom in and out and note that the wire to bus connectors disappear
+0 + + + + + + +8950304 +IP +Artifact Created: 74.14.150.113 +1260140067 +hyperflexed + + + + +http://sourceforge.net/support/tracker.php?aid=2910563 +2910563 +1 +761682 +100 +100 +nobody +nobody +nobody +1260265541 +0 +5 +Highlighted pads don't follow component when moving +
When you move a component with highlit pads, +these don't move with the component + +Ubuntu 9.04 +PCBNew Build: (20080825c-final) + +Marc BERLIOUX
+0 + + + + + + +8954348 +IP +Artifact Created: 81.56.216.19 +1260265542 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2912231 +2912231 +1 +761682 +516020 +100 +sb-sf +nobody +nobody +1260476427 +0 +5 +use netlist for module selection fails +
All my library elements has Footprint field filled with appropriate module name. So I don't need .cmp file - all necessary information already exist in netlist. Last svn builds issues warning "File <name.cmp> not found, use netlist for lib module selection, but after that issue error Compnent [C1]: footprint <> not found. I can insert modules into board manually, so library setup is correct. Reported against svn rev. 2146 + +Official release issue the same warning about .cmp file absence but loads modules correctly.
+0 + + + + + + +8962855 +IP +Artifact Created: 91.135.22.160 +1260476427 +sb-sf + + + + +http://sourceforge.net/support/tracker.php?aid=2914663 +2914663 +2 +1015285 +100 +100 +nobody +nobody +charras +1260868639 +1264531598 +5 +Mirror image in GUI +
I am using last version of kicad-16022009 and the whole GUI is mirrored including the menus and components and layout. I can mirror each component separately but it means that I will get mirror image of what I see in the PCB... +I installed it on windows XP and I am attaching a screenshot.
+0 + + +3834806 +vovanium +1260872122 +
Looks like someone's joke. +This is probably not a problem with KiCad, but with Windows or at least with wxWidgets. Better scan your computer for malware.
+ + +3834882 +st7 +1260882620 +
No joke. Only after I change language from default to English the problem is solved. I guess that's because I have an Hebrew enabled XP (we are writing from left to right).
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=355271&aid= +355271 +mirrored-kicad.JPG +screenshot +172148 +image/jpeg +1260868639 +nobody + + + + +8974976 +IP +Artifact Created: 91.207.90.10 +1260868639 +nobody + + +8974977 +File Added +355271: mirrored-kicad.JPG +1260868639 +nobody + + +8975127 +IP +Comment Added: 195.208.204.245 +1260872122 +vovanium + + +8975429 +IP +Comment Added: 87.70.136.223 +1260882620 +st7 + + +9110304 +status_id +1 +1264531598 +charras + + +9110305 +allow_comments +1 +1264531598 +charras + + +9110306 +close_date +0 +1264531598 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2916161 +2916161 +2 +100 +100 +100 +werner2101 +nobody +charras +1261046648 +1264531597 +5 +Broken examples: supports.mod library not found +
Hi there, + +when using kicad-2009-02-16 with the current kicad-library, then the examples from kicad cannot be viewed. +Kicad tells that the library /usr/share/kicad/modules/supports.mod is missing. + +This library was renamed to sockets.mod on 2008-11-22 in the SVN commit +Rev1415 "Some cleanup and library update" + +see also: +https://bugzilla.novell.com/show_bug.cgi?id=549936 + +I'm using kicad library from SVN. Downloaded on 2009-12-05. + +workaround: +create symbolic links from supports.mod and supports.mdc to sockets.mod an sockets.mdc + +Regards +Werner Hoch
+0 + + + + + + +8981142 +IP +Artifact Created: 87.179.3.175 +1261046648 +werner2101 + + +9110301 +status_id +1 +1264531597 +charras + + +9110302 +allow_comments +1 +1264531597 +charras + + +9110303 +close_date +0 +1264531597 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2917077 +2917077 +2 +761682 +100 +105 +brummig +nobody +charras +1261149206 +1265461604 +5 +Arcs in 3D Viewer +
Arcs of greater than 90 degrees display as 90 degree arcs in the 3D viewer. To recreate this, try creating a board edge using two 180 degree arcs and then displaying in the 3D viewer. Note that arcs greater than 90 degrees are created by creating an arc of 90 degrees and then editing the arc. + +PCBNew 20090216-final/Windows XP SP3.
+0 + + + + + + +8984532 +IP +Artifact Created: 83.216.148.11 +1261149206 +brummig + + +9149239 +status_id +1 +1265461604 +charras + + +9149240 +resolution_id +100 +1265461604 +charras + + +9149241 +allow_comments +1 +1265461604 +charras + + +9149242 +close_date +0 +1265461604 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2919213 +2919213 +1 +100 +100 +100 +nobody +nobody +nobody +1261471796 +0 +5 +'Move block' includes locked components +
'Move block' should exclude components that have been locked.
+0 + + + + + + +8994282 +IP +Artifact Created: 213.64.86.172 +1261471796 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2919215 +2919215 +1 +100 +100 +100 +nobody +nobody +nobody +1261471934 +0 +5 +F10 dual function +
Pressing F10 activates the File menu (WindowsXP) even if this key has been configured for other use. That means F10 has to be pressed twice (to decativate then menu and activate the other command).
+0 + + + + + + +8994286 +IP +Artifact Created: 213.64.86.172 +1261471934 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2919219 +2919219 +2 +761682 +516020 +100 +nobody +nobody +charras +1261472432 +1264531597 +5 +'Drag via' rendering +
While draging a via, new positions are drawn, but none are erased.
+0 + + + + + + +8994309 +IP +Artifact Created: 213.64.86.172 +1261472433 +nobody + + +9110298 +status_id +1 +1264531597 +charras + + +9110299 +allow_comments +1 +1264531597 +charras + + +9110300 +close_date +0 +1264531597 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2919697 +2919697 +2 +761682 +516020 +100 +nobody +nobody +charras +1261525561 +1264531597 +5 +Fillzone crash +
When trying to fill a zone in windows under Windows Vista with 20090216 or kicad-20091222-r2174 windows binary, pcbnew probably loops through an array 'beyond the array' + +This causes pcbnew to crash due to memory violation
+0 + + + + + + +8996536 +IP +Artifact Created: 85.225.172.198 +1261525561 +nobody + + +9110295 +status_id +1 +1264531597 +charras + + +9110296 +allow_comments +1 +1264531597 +charras + + +9110297 +close_date +0 +1264531597 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2929252 +2929252 +2 +761682 +755196 +100 +nobody +nobody +charras +1263125460 +1264441828 +5 +error in the creation of trails Build: (20100108 SVN-R2200)- +
when I try to create a derivation of a path of 1.6 mm to 0.4 mm an example it returns me an error in the track width, in previous versions it did not and it helps me a lot in the manual routing
+0 + + + + + + +9055736 +IP +Artifact Created: 201.78.215.139 +1263125460 +nobody + + +9106720 +status_id +1 +1264441828 +charras + + +9106721 +allow_comments +1 +1264441828 +charras + + +9106722 +close_date +0 +1264441828 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2929256 +2929256 +3 +761682 +755196 +100 +nobody +nobody +charras +1263125891 +1264531934 +5 +error creating tracks Build: (20100108 SVN-R2200) +
creating trails rastness lines keep coming, and need a redraw to make it disappear, one idea would be to create a procedure after the creation of the trail it to automatically redraw the
+0 + + + + + + +9055755 +IP +Artifact Created: 201.78.215.139 +1263125892 +nobody + + +9106717 +status_id +1 +1264441828 +charras + + +9106718 +allow_comments +1 +1264441828 +charras + + +9106719 +close_date +0 +1264441828 +charras + + +9110329 +status_id +2 +1264531934 +charras + + +9110330 +close_date +1264441828 +1264531934 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2929257 +2929257 +3 +761682 +755196 +100 +nobody +nobody +charras +1263125927 +1264531934 +5 +error tracks rastness Build: (20100108 SVN-R2200) +
creating trails rastness lines keep coming, and need a redraw to make it disappear, one idea would be to create a procedure after the creation of the trail it to automatically redraw the
+0 + + + + + + +9055756 +IP +Artifact Created: 201.78.215.139 +1263125928 +nobody + + +9106714 +status_id +1 +1264441828 +charras + + +9106715 +allow_comments +1 +1264441828 +charras + + +9106716 +close_date +0 +1264441828 +charras + + +9110327 +status_id +2 +1264531934 +charras + + +9110328 +close_date +1264441828 +1264531934 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2929277 +2929277 +2 +761682 +755196 +100 +nobody +nobody +charras +1263129201 +1264441828 +5 +error tracks rastness Build: (20100108 SVN-R2200) +
creating trails rastness lines keep coming, and need a redraw to make it disappear, one idea would be to create a procedure after the creation of the trail it to automatically redraw the
+0 + + + + + + +9055857 +IP +Artifact Created: 201.78.236.149 +1263129202 +nobody + + +9106711 +status_id +1 +1264441828 +charras + + +9106712 +allow_comments +1 +1264441828 +charras + + +9106713 +close_date +0 +1264441828 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2929278 +2929278 +2 +761682 +755196 +100 +nobody +nobody +charras +1263129648 +1264441828 +5 +Errtype(27) +
I'm trying to use manual routing and when I try to leave a trail of 0.047 inch to 0.023 of one he accuses Errtype (27), but not this wrong my tracks because it is only a low current output and not have the space to use the tracks wide while in the main circuit of the tracks need wide. thanks
+0 + + + + + + +9055875 +IP +Artifact Created: 201.78.236.149 +1263129648 +nobody + + +9106708 +status_id +1 +1264441828 +charras + + +9106709 +allow_comments +1 +1264441828 +charras + + +9106710 +close_date +0 +1264441828 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2929862 +2929862 +2 +761682 +755196 +105 +nobody +nobody +charras +1263223272 +1264441827 +5 +maximum number of undo +
currently the maximum number of undo is not enough, that about 10 ideal for a media card would be in the range of 99, because it is often necessary. thanks
+0 + + + + + + +9059082 +IP +Artifact Created: 201.78.138.205 +1263223272 +nobody + + +9106705 +status_id +1 +1264441827 +charras + + +9106706 +allow_comments +1 +1264441827 +charras + + +9106707 +close_date +0 +1264441827 +charras + + +9110326 +resolution_id +100 +1264531852 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2933074 +2933074 +1 +761682 +516020 +100 +elw_2 +nobody +nobody +1263586966 +0 +6 +Gray export Picture in the 3D +
Will I export the 3D Modell into a png or a jpg the Picture is gray (bad English, but my German is better ;)) +Wenn ich die 3D Darstellung in eine png oder jpg Datei umwandeln möchte, bekomme ich nicht das Bild zusehen, sondern immer nur ein graues Bild (siehe Anhang) + +OS: Windows 7 x64 Professionell and Windows Vista x64 Ultimate
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=359101&aid= +359101 +Zusatzplatine_Labornetzteil_01.jpg + +18546 +image/jpeg +1263586966 +elw_2 + + + + +9075520 +IP +Artifact Created: 88.208.165.253 +1263586966 +elw_2 + + +9075521 +File Added +359101: Zusatzplatine_Labornetzteil_01.jpg +1263586966 +elw_2 + + +9075522 +priority +5 +1263586998 +elw_2 + + + + +http://sourceforge.net/support/tracker.php?aid=2934980 +2934980 +2 +1015285 +100 +1 +briansidebotham +nobody +charras +1263909957 +1266067012 +5 +Eeschema crashes when alias already exists +
eeschema (library editor) crashes when a library part is saved when there is an alias specified that already exists in the library. This happens often when you start a new component from an old component, make a few changes and forget to delete the aliases. Upon saving eeschema crashes irrecoverably.
+0 + + +3863226 +jerryjacobs +1263914319 +
Hello Brian. + +Which: +Application version, or Subversion revision. +Can you reproduce the problem?
+ + +3863320 +briansidebotham +1263918673 +
Hi Jerry, + +Latest SVN version (R2243) and previous SVN versions all exhibit the same. R2243 needs HK_UNDO and HK_REDO added to the hotkey enum to compile. + +To reproduce, start eeschema and load a library entry which has an alias set. Modify the value field of the component to generate a new library entry and click save, eeschema crashes. + +Do the same again, having deleted the alias or changed the alias name and eeschema doesn't crash.
+ + + + + + +9085187 +IP +Artifact Created: 87.74.132.43 +1263909957 +briansidebotham + + +9085365 +IP +Comment Added: 84.25.204.235 +1263914319 +jerryjacobs + + +9085778 +IP +Comment Added: 87.74.132.43 +1263918673 +briansidebotham + + +9174774 +status_id +1 +1266067012 +charras + + +9174775 +resolution_id +100 +1266067012 +charras + + +9174776 +allow_comments +1 +1266067012 +charras + + +9174777 +close_date +0 +1266067012 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2936252 +2936252 +2 +100 +100 +100 +nobody +nobody +charras +1264075778 +1264441827 +5 +pcbnew zoom +
após as alterações realizadas no pcbnew depois da (20100115 SVN-R2224) quando se da um zoom na placa e rola a tela para baixo ela quadricula tudo deformando a imagem , até nessa versao nao havia esse problema
+0 + + + + + + +9106702 +status_id +1 +1264441827 +charras + + +9106703 +allow_comments +1 +1264441827 +charras + + +9106704 +close_date +0 +1264441827 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2936255 +2936255 +2 +761682 +755196 +100 +nobody +nobody +charras +1264075865 +1264441827 +5 +zoom pcbnew ubuntu 9,04 +
after the changes made after the Pcbnew (20100115 SVN-R2224) when the zoom on the board and roll the screen down it all raster image warping, even in this version there was no such problem
+0 + + + + + + +9106699 +status_id +1 +1264441827 +charras + + +9106700 +allow_comments +1 +1264441827 +charras + + +9106701 +close_date +0 +1264441827 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2940466 +2940466 +2 +761682 +755196 +2 +nobody +nobody +charras +1264539394 +1266067083 +5 +error in the library after the release kicad-20100115-r2224- +
in ubuntu 9.04 erro +pcbnew: relocation error: pcbnew: symbol _ZTI12wxAuiToolBar, version WXU_2.8 not defined in file libwx_gtk2u_aui-2.8.so.0 with link time reference + +until this version worked well kicad-20100115-r2224-linux
+0 + + +3868964 +jerryjacobs +1264542632 +
Did you tried with a clean checkout, or after invoking cmake . to gegenerate new makefiles so that it doesn't tries to link against aui because this is in wxwidgets base? + +Good luck.
+ + + + + + +9110758 +IP +Comment Added: 84.25.204.235 +1264542632 +jerryjacobs + + +9174782 +status_id +1 +1266067083 +charras + + +9174783 +resolution_id +100 +1266067083 +charras + + +9174784 +allow_comments +1 +1266067083 +charras + + +9174785 +close_date +0 +1266067083 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2942887 +2942887 +2 +1015285 +100 +1 +nobody +nobody +charras +1264878664 +1265095172 +5 +Duplicate Pin 23 in CONN_25X2 in conn.lib +
Duplicate pin 23 "P23" at location (-0,400, -0,100) conflicts with pin 23 "P23" at location (-0,400, -0,100). + +Pin 25 is without name P25
+0 + + + + + + +9133380 +status_id +1 +1265095172 +charras + + +9133381 +resolution_id +100 +1265095172 +charras + + +9133382 +allow_comments +1 +1265095172 +charras + + +9133383 +close_date +0 +1265095172 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2943571 +2943571 +2 +100 +516020 +6 +nobody +nobody +jerryjacobs +1265012437 +1265029032 +5 +Missing dll +
I overwrote my existing/working latest prod version with r2270 but then I get the missing dll error below. Any ideas +wxbase28u_gcc.custom.dll
+0 + + +3874731 +jerryjacobs +1265029031 +
This bug has been fixed
+ + +3874732 +jerryjacobs +1265029032 +
This is not much information. +Did you compiled yourself or did you downloaded from the http://kicad.1301.cz snapshot builds? +You should download also the dll package then ! +http://kicad.1301.cz/dlls/kicad-wx28-dlls.zip + +Bug closed, not a real bug ;-)
+ + + + + + +9129496 +IP +Comment Added: 84.25.204.235 +1265029031 +jerryjacobs + + +9129497 +IP +Comment Added: 84.25.204.235 +1265029032 +jerryjacobs + + +9129498 +status_id +1 +1265029032 +jerryjacobs + + +9129499 +resolution_id +100 +1265029032 +jerryjacobs + + +9129500 +allow_comments +1 +1265029032 +jerryjacobs + + +9129501 +close_date +0 +1265029032 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2945885 +2945885 +2 +761682 +100 +1 +brummig +nobody +charras +1265283119 +1265461667 +5 +Oval Pads Fail DRC Incorrectly +
One end of an oval pad needs to be *twice* the clearance set in the DRC dialog from the nearest copper in order to pass the DRC. The other end passes the DRC as expected. + +PCBNew 20090216 running on XP Pro/SP3
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=361600&aid= +361600 +DRCFail.pdf +Shows how one end of an oval pad incorrectly fails the DRC +135507 +application/pdf +1265283119 +brummig + + + + +9140960 +IP +Artifact Created: 83.216.148.11 +1265283119 +brummig + + +9140961 +File Added +361600: DRCFail.pdf +1265283119 +brummig + + +9149243 +status_id +1 +1265461667 +charras + + +9149244 +resolution_id +100 +1265461667 +charras + + +9149245 +allow_comments +1 +1265461667 +charras + + +9149246 +close_date +0 +1265461667 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2947745 +2947745 +1 +100 +755196 +100 +nobody +nobody +nobody +1265623700 +0 +5 +folder kicad +
a suggestion for the sake of organization is to put configuration files in $ HOME / .kicad / files at least it is all together now is all in $ HOME / files that makes up the settings
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2952213 +2952213 +2 +761682 +100 +1 +mrluzeiro +nobody +charras +1266255566 +1267187204 +5 +Design Rules Editor GUI layout +
In Design Rules Editor, NetClassEditor, the layout of gui (Add,Remove,Move up keys) are hide by the framegrid of "net classes" +Can you make the frame "membership" a little more short? + +I'm using xubuntu64 and last SVN release. + +Also: +in Global Design Rules, the custom via and track options the grid passes the frame size.. + +my monitor resolution is 1366x768 +
+0 + + + + + + +9180818 +IP +Artifact Created: 85.241.153.82 +1266255566 +mrluzeiro + + +9216781 +status_id +1 +1267187204 +charras + + +9216782 +resolution_id +100 +1267187204 +charras + + +9216783 +allow_comments +1 +1267187204 +charras + + +9216784 +close_date +0 +1267187204 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2953214 +2953214 +1 +761682 +516020 +100 +oecherexpat +nobody +nobody +1266368034 +0 +5 +Font on new layer manager toolbar is too small +
As the topic says: Font on new layer manager toolbar is too small (see attached screenshot) +WinXP-SP3, en. Kicad (20100209 RC2)-RC2
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=363224&aid= +363224 +ScreenShot004.png +Font on new layer manager toolbar is too small +21363 +image/png +1266368035 +oecherexpat + + + + +9185418 +IP +Artifact Created: 222.153.213.254 +1266368035 +oecherexpat + + +9185419 +File Added +363224: ScreenShot004.png +1266368035 +oecherexpat + + + + +http://sourceforge.net/support/tracker.php?aid=2955025 +2955025 +2 +1015285 +100 +1 +brummig +nobody +charras +1266595523 +1267187204 +5 +DATE Field Has Odd Update Behaviour +
The DATE field only seems to update when annotating circuits, but of course a circuit can change in other ways too. Should it not update when any change is made? One slight problem is how to deal with non-changes (eg clicking OK to a dialog but not changing any fields) and changes that get reversed. That could perhaps be solved by calculating the file CRC and comparing it between what is was when the file was opened and what it is on saving. + +The current behaviour is not explained in the help (which just says "The date is automatically updated"), and has resulted in posts on the users group.
+0 + + + + + + +9194324 +IP +Artifact Created: 83.216.148.11 +1266595523 +brummig + + +9216777 +status_id +1 +1267187204 +charras + + +9216778 +resolution_id +100 +1267187204 +charras + + +9216779 +allow_comments +1 +1267187204 +charras + + +9216780 +close_date +0 +1267187204 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2959609 +2959609 +2 +761682 +516020 +105 +alidoig +nobody +charras +1267187557 +1267431383 +5 +Invisible text still showing +
When either the reference or value text field are defined as invisible within the module properties dialogue, they are only greyed-out in PCBNEW (as happens in the module editor) rather than being made invisible. The only way to make them invisible is to turn the whole referene or value layer off, which defeats the purpose of being able to define them on a mode-by-module basis. + +I am running RC4.
+0 + + +3916382 +charras +1267431523 +
Pcbnew dispkay invisible texts on screen only (you must have to edit or change status of these texts) +Select the BLACK color to really hide them. +
+ + + + + + +9216789 +IP +Artifact Created: 92.24.45.200 +1267187557 +alidoig + + +9224868 +status_id +1 +1267431383 +charras + + +9224869 +resolution_id +100 +1267431383 +charras + + +9224870 +allow_comments +1 +1267431383 +charras + + +9224871 +close_date +0 +1267431383 +charras + + +9224886 +IP +Comment Added: 152.77.63.2 +1267431523 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2959625 +2959625 +2 +1015285 +516020 +1 +alidoig +nobody +charras +1267189425 +1267473049 +5 +Mirror Block does not work in Component Editor +
If you try to mirror a block in the Component Library Editor, the block is instead moved twice the distance from the anchor point in both X and Y, with no mirroring at all. +Mirroring in eeschema itself is fine. I am using Windows RC4. + +
+0 + + + + + + +9216835 +IP +Artifact Created: 92.24.45.200 +1267189425 +alidoig + + +9227212 +status_id +1 +1267473049 +charras + + +9227213 +resolution_id +100 +1267473049 +charras + + +9227214 +allow_comments +1 +1267473049 +charras + + +9227215 +close_date +0 +1267473049 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2959926 +2959926 +2 +100 +100 +1 +nobody +nobody +charras +1267234136 +1267473304 +5 +PCBnew text "Hide Layers Manager" shown wrong. +
PCBnew 20100221 RC4 +(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) + +"Hide Layers Manager" shown wrong. +1. Start PCBnew +2. Click Preferences, click Hide Layers Manager +3. Click File, click Quit +4. Start PCBnew +5. Click Preferences +6. "Hide Layers Manager" should read "Show Layers Manager"
+0 + + + + + + +9227234 +status_id +1 +1267473304 +charras + + +9227235 +resolution_id +100 +1267473304 +charras + + +9227236 +allow_comments +1 +1267473304 +charras + + +9227237 +close_date +0 +1267473304 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2959928 +2959928 +1 +100 +100 +100 +nobody +nobody +nobody +1267234307 +0 +5 +PCBnew Locked modules are not locked. +
PCBnew 20100221 RC4 +(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) + +If a module is locked, it should be locked until it is unlocked. +1. Activate "Manual and automatic move or place of modules" +2. Click right mouse button on a module +3. Click Lock module +4. Click right mouse button on the module +5. Select Footprint ... > Move +6. The footprint can be moved +7. Move/Drag/Rotate+/Rotate-/Flip/Edit/Delete Module should not work if LOCKED
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2959930 +2959930 +2 +100 +100 +1 +nobody +nobody +charras +1267234423 +1268128371 +5 +PCBnew inconsistent Layer names sequence. +
PCBnew 20100221 RC4 +(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) + +The sequence of Layer names is inconsistent. +In Layers Manager the top down sequence of Layer names, should be the same sequence as in Design Rules > Layers Setup.
+0 + + + + + + +9253091 +status_id +1 +1268128371 +charras + + +9253092 +resolution_id +100 +1268128371 +charras + + +9253093 +allow_comments +1 +1268128371 +charras + + +9253094 +close_date +0 +1268128371 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2959932 +2959932 +1 +100 +100 +100 +nobody +nobody +nobody +1267234492 +0 +5 +Inconsistent menu text Zoom. +
EESchema 20100221 RC4 +(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) + +Click View > "Zoom In" should read "Zoom in F1" +Click View > "Zoom Out" should read "Zoom out F2" +Click View > "Fit on Screen Home" should read "Zoom fit Home" +Click Right mouse button > "Zoom auto Home" should read "Zoom fit Home" +Button Tooltip > "Zoom auto <Home>" should read "Zoom fit <Home>" + + +PCBnew 20100221 RC4 +(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) + +Click View > "Zoom in" should read "Zoom in F1" +Click View > "Zoom out" should read "Zoom out F2" +Click View > "Fit on Screen Home" should read "Zoom fit Home" +Click Right mouse button > "Zoom auto Home" should read "Zoom fit Home" +Button Tooltip > "Zoom auto <Home>" should read "Zoom fit <Home>"
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2960099 +2960099 +2 +100 +100 +1 +nobody +nobody +charras +1267267929 +1267430848 +5 +PCBnew Window "Display settings" has no Name. +
PCBnew 20100221 RC4 +(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) + +Please refer to attached screen capture. + +1. Start PCBnew +2. Click Preferences +3. Click Display +4. The window Name is missing, should read "Display settings".
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=364663&aid= +364663 +KiCad Window -Display settings- has no Name.PNG +Window Name is missing. +21306 +image/x-png +1267267929 +nobody + + + + +9224842 +status_id +1 +1267430848 +charras + + +9224843 +resolution_id +100 +1267430848 +charras + + +9224844 +allow_comments +1 +1267430848 +charras + + +9224845 +close_date +0 +1267430848 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2960100 +2960100 +2 +100 +100 +105 +nobody +nobody +charras +1267268277 +1267430338 +5 +PCBnew Drop-Down-Box Zoom inconsistent. +
PCBnew 20100221 RC4 +(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) + +Please refer to attached screen capture. + +01. Start PCBnew +02. Drop-Down-Box Zoom is empty +03. Click down-arrow to the right side of the Drop-Down-Box Zoom +04. Zoom list is shown +05. Text "Auto" should read "Fit" + +06. Select "Auto", press left mouse button +07. Drop-Down-Box Zoom is empty, should read "Fit" + +08. Select "Zoom 7", press left mouse button +09. Drop-Down-Box Zoom shows "Zoom 7" +10. Press Home-key, do NOT move the mouse +11. Drop-Down-Box Zoom shows "Zoom 7", should read "Fit" + +12. Move the mouse +13. Drop-Down-Box Zoom is empty, should read "Fit" + +14. Select "Zoom 7", press left mouse button +15. Drop-Down-Box Zoom shows "Zoom 7" +16. Click "Zoom auto <Home>", do NOT move the mouse +17. Drop-Down-Box Zoom shows "Zoom 7", should read "Fit" + +18. Move the mouse +19. Drop-Down-Box Zoom is empty, should read "Fit"
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=364665&aid= +364665 +KiCad Drop-Down-Box Zoom.PNG +Drop-Down-Box Zoom update is inconsistent. +21756 +image/x-png +1267268277 +nobody + + + + +9224832 +status_id +1 +1267430338 +charras + + +9224833 +resolution_id +100 +1267430338 +charras + + +9224834 +allow_comments +1 +1267430338 +charras + + +9224835 +close_date +0 +1267430338 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2960364 +2960364 +2 +761682 +100 +1 +nobody +nobody +charras +1267301366 +1267530698 +5 +PCBnew Design Rules Editor inconsistent Column Names. +
PCBnew 20100221 RC4 +(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) + +Please refer to attached screen capture. + +In Membership: area, the Column Names "Net" and "Class" are displayed inconsistently. +This happens during dragging the column line when resizing the column width.
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=364726&aid= +364726 +KiCad Net Classes Editor screen capture.PNG +Column Names mostly missing. +25899 +image/x-png +1267301366 +nobody + + + + +9229249 +status_id +1 +1267530698 +charras + + +9229250 +resolution_id +100 +1267530698 +charras + + +9229251 +allow_comments +1 +1267530698 +charras + + +9229252 +close_date +0 +1267530698 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2960432 +2960432 +2 +761682 +516020 +105 +nobody +nobody +charras +1267312828 +1267430338 +5 +Addition to ID: 2960100 +
Please note that the behaviour as described in ID: 2960100 was observed when ecc83-pp_v2.brd was opened in PCBnew. + +When interf_u.brd is opened in PCBnew, the described behaviour is similar when the window is NOT maximized to full screen. If the window IS maximised the behavior is different than described in ID: 2960100.
+0 + + + + + + +9224828 +status_id +1 +1267430338 +charras + + +9224829 +resolution_id +100 +1267430338 +charras + + +9224830 +allow_comments +1 +1267430338 +charras + + +9224831 +close_date +0 +1267430338 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2960554 +2960554 +2 +761682 +516020 +1 +nobody +nobody +charras +1267349419 +1267443620 +5 +PCBnew Ratsnest color is wrong (Layers Manager). +
PCBnew 20100221 RC4 +(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) + +Ratsnest color is WHITE but Layers Manager show RED. +Please refer to attached screen capture.
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=364784&aid= +364784 +KiCad ratsnest color wrong.PNG + +49823 +image/x-png +1267349419 +nobody + + + + +9225359 +status_id +1 +1267443620 +charras + + +9225360 +resolution_id +100 +1267443620 +charras + + +9225361 +allow_comments +1 +1267443620 +charras + + +9225362 +close_date +0 +1267443620 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2960683 +2960683 +2 +1015285 +755196 +1 +jerryjacobs +bennett78 +charras +1267370546 +1267523818 +9 +Bill of materials single parts per line crashes +
After revision 2397 when i select Output format: Single Part per line and click ok and select file in the browser it crashes. +Gnu Debugger gives me the line of code at frame 3. I can reproduce this problem with my schematics and the one from the demos. When I select List or Text for speadsheat it works. See below. + +(gdb) frame 3 +#3 0x00000000004b38d6 in DIALOG_BUILD_BOM::PrintComponentsListByPart (this=0x1898910, f=0x19d85a0, + aList=std::vector of length 34, capacity 64 = {...}) at /home/jerry/builds/kicad/kicad-trunk/eeschema/build_BOM.cpp:872 +872 printf("%c%-20s", s_ExportSeparatorSymbol, CONV_TO_UTF8( cmpFields[FIELD1]) ); + +(gdb) where +#0 0x0000003a9f8af180 in wxMBConvUTF8::WC2MB(char*, wchar_t const*, unsigned long) const () from /usr/lib64/libwx_baseu-2.8.so.0 +#1 0x0000003a9f8b0abd in wxMBConv::cWC2MB(wchar_t const*) const () from /usr/lib64/libwx_baseu-2.8.so.0 +#2 0x00000000004a6cd6 in wxMBConv::cWX2MB (this=0x3a9fb67550, psz=0x5200000057 <Address 0x5200000057 out of bounds>) + at /usr/include/wx-2.8/wx/strconv.h:111 +#3 0x00000000004b38d6 in DIALOG_BUILD_BOM::PrintComponentsListByPart (this=0x1898910, f=0x19d85a0, + aList=std::vector of length 34, capacity 64 = {...}) at /home/jerry/builds/kicad/kicad-trunk/eeschema/build_BOM.cpp:872 +#4 0x00000000004b119f in DIALOG_BUILD_BOM::CreatePartsList (this=0x1898910, aFullFileName=..., aIncludeSubComponents=false) + at /home/jerry/builds/kicad/kicad-trunk/eeschema/build_BOM.cpp:172 +#5 0x00000000004b0ef1 in DIALOG_BUILD_BOM::Create_BOM_Lists (this=0x1898910, aTypeFile=2, aIncludeSubComponents=false, + aExportSeparatorSymbol=44 ',', aRunBrowser=false) at /home/jerry/builds/kicad/kicad-trunk/eeschema/build_BOM.cpp:126 +#6 0x00000000004fdebb in DIALOG_BUILD_BOM::OnOkClick (this=0x1898910, event=...) + at /home/jerry/builds/kicad/kicad-trunk/eeschema/dialog_build_BOM.cpp:182 +#7 0x0000003a9f8f2070 in wxEvtHandler::ProcessEventIfMatches(wxEventTableEntryBase const&, wxEvtHandler*, wxEvent&) () + from /usr/lib64/libwx_baseu-2.8.so.0
+0 + + + + + + +9222800 +IP +Artifact Created: 84.25.204.235 +1267370546 +jerryjacobs + + +9227042 +status_id +1 +1267469305 +charras + + +9227043 +close_date +0 +1267469305 +charras + + +9229000 +status_id +4 +1267523818 +charras + + +9229001 +resolution_id +100 +1267523818 +charras + + +9229002 +allow_comments +1 +1267523818 +charras + + +9229003 +close_date +1267469305 +1267523818 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2960706 +2960706 +2 +761682 +100 +1 +nobody +nobody +charras +1267373095 +1267465935 +5 +PCBnew Pad Properties show wrong Layer Names. +
PCBnew 20100221 RC4 +(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) + +Layer Names in Pad Properties are different (old?) Layer Names. +Please refer to attached screen capture.
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=364843&aid= +364843 +KiCad Pad Properties wrong Layer Names.PNG + +59990 +image/x-png +1267373096 +nobody + + + + +9226877 +status_id +1 +1267465935 +charras + + +9226878 +resolution_id +100 +1267465935 +charras + + +9226879 +allow_comments +1 +1267465935 +charras + + +9226880 +close_date +0 +1267465935 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2960893 +2960893 +2 +761682 +100 +1 +mrluzeiro +nobody +charras +1267396316 +1267523694 +5 +Plot to postscrip and pcb page layout +
@SVN R2400 + +I've selected a custom page layout size (frame) and I ploted it to Postscript (non A4) +and the generated file doesn't show the PCB... (probable a canvas problem? or coordinates? maybe plot expects only A4 frames?) +
+0 + + + + + + +9223916 +IP +Artifact Created: 85.241.171.1 +1267396316 +mrluzeiro + + +9228991 +status_id +1 +1267523694 +charras + + +9228992 +resolution_id +100 +1267523694 +charras + + +9228993 +allow_comments +1 +1267523694 +charras + + +9228994 +close_date +0 +1267523694 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2960923 +2960923 +2 +761682 +100 +105 +nobody +nobody +charras +1267401523 +1267430196 +5 +PCBnew Mask_Front not shown (Layers Manager). +
PCBnew 20100221 RC4 +(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) + +Solder stop mask pads "Mask_Front (Solder mask Cmp)" are not shown. +Please refer to attached screen capture. + +1. In Pad Properties, Layers: "Solder mask Cmp" is checked (on). + +2. In Pad Properties, Clearances: are all zeros. + +3. In Module properties > Properties, Mask clearances local values: are all zeros. + +4. In Preferences > Dimensions > Pads Mask Clearance, Solder mask clearance is 0,0100. + +5. In Design Rule Editor > Net Classes Editor, Default Clearance is 0,0100. + +6. In Layers Manager > Render, Pads Front is unchecked (off). Therefore pads are not visable and clearance outlines are not visable. + +7. In Layers Manager > Layer, Mask_Front is checked (on). Color is Magenta. Refer to attached screen capture. + +8. Solder stop mask pads are not shown, which I believe is wrong. + +Solder stop mask pads "Mask_Front (Solder mask Cmp)" should be visable in Magenta colour!!??
+0 + + +3916354 +charras +1267430139 +
Layer manager>render is set to NO SHOW pads front, so they are not displayed. +Therefore you do not see pads on mask front. +No bug here.
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=364897&aid= +364897 +KiCad Mask_Front should be visable.PNG + +45553 +image/x-png +1267401523 +nobody + + + + +9224816 +IP +Comment Added: 152.77.63.2 +1267430140 +charras + + +9224819 +status_id +1 +1267430196 +charras + + +9224820 +resolution_id +100 +1267430196 +charras + + +9224821 +allow_comments +1 +1267430196 +charras + + +9224822 +close_date +0 +1267430196 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2961071 +2961071 +2 +761682 +516020 +1 +nobody +nobody +charras +1267435954 +1267442510 +5 +3D viewer does not operate +
KiCad-2010-02-28-RC5-WinXP pcbnew: When we press a button "Browse Shapes" ("Open module editor" > "Module Properties" > "3D settings" > "Browse Shapes") and select an object for viewing 3D viewer does not operate.
+0 + + + + + + +9225314 +status_id +1 +1267442510 +charras + + +9225315 +resolution_id +100 +1267442510 +charras + + +9225316 +allow_comments +1 +1267442510 +charras + + +9225317 +close_date +0 +1267442510 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2961086 +2961086 +2 +1015285 +516020 +1 +nobody +nobody +charras +1267437095 +1267442510 +5 +Delete Bus Entry +
KiCad-2010-02-28-RC5-WinXP eeschema: When we Delete Bus Entry, his image does not disappear and should be done "Redraw view" order disappeared it.
+0 + + + + + + +9225310 +status_id +1 +1267442510 +charras + + +9225311 +resolution_id +100 +1267442510 +charras + + +9225312 +allow_comments +1 +1267442510 +charras + + +9225313 +close_date +0 +1267442510 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2961122 +2961122 +1 +100 +516020 +100 +nobody +nobody +nobody +1267441138 +0 +5 +Maximize size of window +
KiCad-2010-02-28-RC5-WinXP: When we start any program (cvpcb, eeschema, gerbview, kicad or pcbnew) they always open in Restore Down size of window, but never in Maximize size of window, even if ones were closed before this in Maximize size of window.
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2961163 +2961163 +2 +1015285 +516020 +105 +nobody +nobody +charras +1267446007 +1267465840 +5 +module after "clear annotation" error +
KiCad-2010-02-28-RC5-WinXP eeschema and cvpcb: If we have already completed the scheme, and want for example, add a new resistor which location after the resistors R1 and R2, then after the "Reset existing annotation", "Clear annotation", "Annotation" and "Netlist generation" we see in cvpcb the new resistor R3 without the module and we appointed a new module for him. That is correct. +If we add a new resistor, located between R1 and R2 (R1 => R1, the new resistor => R2, R2 => R3), then after the "Reset existing annotation", "Clear annotation", "Annotation" and "Netlist generation " we see in cvpcb, that the module, which previously belonged to the R2 now illegal belongs to the new resistor (which is now R2), and the old resistor R2 (which is now R3) was left without module. This is wrong. +For me, it is important to "Reset existing annotation", "Clear annotation", so the board described in http://tech.groups.yahoo.com/group/kicad-users/message/5624 for me is not suitable.
+0 + + + + + + +9226861 +status_id +1 +1267465840 +charras + + +9226862 +resolution_id +100 +1267465840 +charras + + +9226863 +allow_comments +1 +1267465840 +charras + + +9226864 +close_date +0 +1267465840 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2961186 +2961186 +2 +1015285 +516020 +6 +alidoig +nobody +charras +1267448954 +1267466507 +5 +Edit Pins per part Setting gets changed +
I have noticed that compenents created with the previous release of Kicad that have more than 1 unit (as convert) that required "edit Pins per part" enabled, appear to ignore the "edit pins per part" setting in RC5. I hadn't checked this in previous release candiadates, sorry. + +When modifying component to have "edit pins per part" enabled using RC5, and after correcting one of the a pin names of UnitB (lets call this pin 4), trying to edit any other pin on the part always brought up the dialogue as if I was trying to edit pin4 again. The only way I could rename all the pins correctly was to save the component after each change. + +One more oddity... If you edit a component that does not have "edit pins per part" enabled and then edit a part that did have it enabled, the "edit pins per part" setting reverts back to being disabled too. + +My appologies if this is a bit confusing.
+0 + + +3917203 +charras +1267466399 +
Works fine in RC5 for me
+ + + + + + +9225543 +IP +Artifact Created: 81.149.216.219 +1267448955 +alidoig + + +9226897 +IP +Comment Added: 90.41.62.219 +1267466399 +charras + + +9226898 +status_id +1 +1267466507 +charras + + +9226899 +resolution_id +100 +1267466507 +charras + + +9226900 +allow_comments +1 +1267466507 +charras + + +9226901 +close_date +0 +1267466507 +charras + + +9227041 +resolution_id +5 +1267469261 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2961194 +2961194 +3 +1015285 +516020 +101 +alidoig +nobody +alidoig +1267450187 +1267450301 +5 +Edit Pins per part Setting gets changed +
I have noticed that compenents created with the previous release of Kicad that have more than 1 unit (as convert) that required "edit Pins per part" enabled, appear to ignore the "edit pins per part" setting in RC5. I hadn't checked this in previous release candiadates, sorry. + +When modifying component to have "edit pins per part" enabled using RC5, and after correcting one of the a pin names of UnitB (lets call this pin 4), trying to edit any other pin on the part always brought up the dialogue as if I was trying to edit pin4 again. The only way I could rename all the pins correctly was to save the component after each change. + +One more oddity... If you edit a component that does not have "edit pins per part" enabled and then edit a part that did have it enabled, the "edit pins per part" setting reverts back to being disabled too. + +My appologies if this is a bit confusing.
+0 + + +3916761 +alidoig +1267450301 +
Sorry, I must have somehow clicked update twice.
+ + + + + + +9225585 +IP +Artifact Created: 81.149.216.219 +1267450187 +alidoig + + +9225590 +IP +Comment Added: 81.149.216.219 +1267450301 +alidoig + + +9225591 +status_id +1 +1267450301 +alidoig + + +9225592 +resolution_id +100 +1267450301 +alidoig + + +9225593 +allow_comments +1 +1267450301 +alidoig + + +9225594 +close_date +0 +1267450301 +alidoig + + + + +http://sourceforge.net/support/tracker.php?aid=2961343 +2961343 +2 +1015285 +516020 +105 +nobody +nobody +charras +1267459730 +1267465817 +5 +horizontal and vertical wires and buses only +
KiCad-2010-02-28-RC5-WinXP eeschema: If we set on "Draw horizontal and vertical wires and buses only" and after that try make "Drag Component", connecting wires stretched over component like rubber threads, but not as "horizontal and vertical wires and buses only".
+0 + + + + + + +9226854 +status_id +1 +1267465817 +charras + + +9226855 +resolution_id +100 +1267465817 +charras + + +9226856 +allow_comments +1 +1267465817 +charras + + +9226857 +close_date +0 +1267465817 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2961374 +2961374 +1 +1015285 +516020 +100 +nobody +nobody +nobody +1267462410 +0 +5 +Set Bus Entry +
KiCad-2010-02-28-RC5-WinXP eeschema: It would be better to replace "Set Bus Entry" to "Turn Bus Entry" for more comprehensible.
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2961845 +2961845 +1 +1015285 +755196 +6 +nobody +nobody +charras +1267526986 +1267682840 +5 +eeschema does not restore library settings correctly +
A current version of Kicad (r2413), Ubuntu Karmic build does restore library setting correctly. + +After a program restart the settings have disappeared and the locally specified (in the .pro file) is not loaded. Also the "User Defined Search Path" is not restored. + +pcbnew does not expose the problem.
+0 + + +3923867 +jtaprogge +1268131008 +
As it seems the problem only occurs when the local library is not in the same directory as the project. + +Steps to reproduce: + 1. Create new project. + 2. Create new library in parent directory. + 3. Add library to project. + 4. Restart eeschema. + +At this point the library is now longer part of the project.
+ + + + + + +9236281 +status_id +1 +1267682840 +charras + + +9236282 +resolution_id +100 +1267682840 +charras + + +9236283 +close_date +0 +1267682840 +charras + + +9253337 +status_id +4 +1268131008 +jtaprogge + + +9253338 +IP +Comment Added: 138.131.217.79 +1268131008 +jtaprogge + + + + +http://sourceforge.net/support/tracker.php?aid=2962142 +2962142 +2 +1015285 +755196 +1 +bennett78 +nobody +charras +1267560208 +1267630846 +7 +Crash SaveEEFile on demo +
Crash saving whole schematic project Revision: 2416 +[Debug] 12:56:24: LoadLibraries () requested component library sort order: +[Debug] 12:56:24: Real component library sort order: +[Debug] 12:56:24: end LoadLibraries () +[Debug] 12:56:24: LoadOneEEProject() load schematic cache library file </s/opt/svn/kicad/trunk/kicad/demos/kit-dev-coldfire-xilinx_5213/kit-dev-coldfire-xilinx_5213.cache.lib> +SaveEEFile, /s/opt/svn/kicad/trunk/kicad/demos/kit-dev-coldfire-xilinx_5213/kit-dev-coldfire-xilinx_5213.sch +SaveEEFile, in_out_conn.sch +SaveEEFile, xilinx.sch +[Debug] 12:56:26: Alias <+3,3V> not found in component <GND> alias list in library <> +[Debug] 12:56:26: Alias <+3,3V> not found in component <DIODE> alias list in library <> +[Debug] 12:56:26: Alias <+3,3V> not found in component <C> alias list in library <> +[Debug] 12:56:26: Alias <+3,3V> not found in component <CONN_1> alias list in library <> +[Debug] 12:56:26: Alias <+3,3V> not found in component <LT1129_QPACK> alias list in library <> +[Debug] 12:56:26: Alias <+3,3V> not found in component <CONN_1> alias list in library <> +[Debug] 12:56:26: Alias <CAPAPOL> not found in component <+3.3V> alias list in library <> +[Debug] 12:56:26: Alias <+3,3V> not found in component <CP> alias list in library <> +[Debug] 12:56:26: Alias <+3,3V> not found in component <CONN_4X2> alias list in library <> +[Debug] 12:56:26: Alias <MAX202> not found in component <CONN_4X2> alias list in library <> +Segmentation fault +
+0 + + + + + + +9230611 +IP +Artifact Created: 76.76.79.173 +1267560209 +bennett78 + + +9233723 +status_id +1 +1267630846 +charras + + +9233724 +resolution_id +100 +1267630846 +charras + + +9233725 +allow_comments +1 +1267630846 +charras + + +9233726 +close_date +0 +1267630846 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2963369 +2963369 +2 +761682 +755198 +1 +brummig +nobody +charras +1267707950 +1267968551 +5 +Copperless Pads (Drill Holes) Do Not Obey Design Rules +
If you create a pad with no copper layers (for example as a drill hole for a mounting bolt), PCBNew will not apply the track spacing rule. Consequently a copper fill (zone) will go right up to the edge of the drill hole. If the board has plated-through holes, then when the board is manufactured by default *all* holes will be plated, including the copper-less pad holes. If there is a copper fill around the copper-less pad on another layer, the two layers will be connected by the plating and the board will be scrap. However, as far kicad is concerned the two layers will not be connected, so it will not even issue a warning in the DRC check.
+0 + + +3919620 +brummig +1267711045 +
I forgot to mention that this problem has tripped up others in the user group.
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=365393&aid= +365393 +LethalHole.png +This board passes the DRC, but it will be manufactured with a plated through hole in the centre of the silk-screen donut that will short 5V to ground. +8036 +image/png +1267707950 +brummig + + + + +9237417 +IP +Artifact Created: 83.216.148.11 +1267707950 +brummig + + +9237418 +File Added +365393: LethalHole.png +1267707950 +brummig + + +9237523 +IP +Comment Added: 83.216.148.11 +1267711045 +brummig + + +9246437 +status_id +1 +1267968551 +charras + + +9246438 +resolution_id +100 +1267968551 +charras + + +9246439 +allow_comments +1 +1267968551 +charras + + +9246440 +close_date +0 +1267968551 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2964094 +2964094 +1 +1015288 +755196 +100 +mrluzeiro +nobody +nobody +1267782356 +0 +5 +cvPCB freezes 100%cpu when loading my file +
When I load the file in attachment in cvPCB the program freezes (100% CPU) and never recover back. +I suspect could be because my installed libs? +I'm using last SVN version (but I think this problems comes from very long time.. ) + +In any way i consider it a bug because the program cannot crashs in that way. if there is something wrong should display a error log =) +
+0 + + +3922328 +mrluzeiro +1267980214 +
I've cheked and it seams that are related to the libs huge list that have to open.
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=365493&aid= +365493 +R2K10_Arduino_Expansion.net +File that makes my cvPCB crashes +7943 +application/octet-stream +1267782357 +mrluzeiro + + + + +9240463 +IP +Artifact Created: 82.154.249.123 +1267782357 +mrluzeiro + + +9240464 +File Added +365493: R2K10_Arduino_Expansion.net +1267782357 +mrluzeiro + + +9246935 +IP +Comment Added: 85.241.175.179 +1267980214 +mrluzeiro + + + + +http://sourceforge.net/support/tracker.php?aid=2965646 +2965646 +2 +761682 +516020 +1 +alidoig +nobody +charras +1268079849 +1268128370 +5 +Cancelling text operation hides text +
I have just noticed that if I move some text, but press excape to abort the operation, the text does not return to its original location. Furthermore, redrawing the screen hides the text altogether and the only way I have found to gett it back is to save the board and reload it again. + +Drawing objects are fine and component text are both fine, it is just graphical text on any layer I have had problems with. I have been through the bugs list to see if this has been reported already, so my appologies if it has. + +I am still running RC5 on windows.
+0 + + + + + + +9250806 +IP +Artifact Created: 92.24.45.200 +1268079849 +alidoig + + +9253084 +status_id +1 +1268128370 +charras + + +9253085 +resolution_id +100 +1268128370 +charras + + +9253086 +allow_comments +1 +1268128370 +charras + + +9253087 +close_date +0 +1268128370 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2966482 +2966482 +2 +1015285 +100 +103 +nobody +nobody +charras +1268143915 +1268161419 +5 +Editing a component changes its orientation +
If you change the orientation of a component using the context menu, and then later edit the component using Edit Component...Edit, the component will change its orientation even if the orientation was not changed in the dialog. Lethal if you don't spot it! + +EESchema 20090216-final / XP SP3
+0 + + +3924071 +brummig +1268144159 +
Report filed by brummig (I thought I was logged in when I filed it).
+ + + + + + +9254157 +IP +Comment Added: 83.216.148.11 +1268144160 +brummig + + +9255367 +status_id +1 +1268161419 +charras + + +9255368 +resolution_id +100 +1268161419 +charras + + +9255369 +allow_comments +1 +1268161419 +charras + + +9255370 +close_date +0 +1268161419 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2969055 +2969055 +1 +100 +100 +100 +nobody +nobody +nobody +1268355419 +0 +5 +3d viewer does not work on win 7 +
3d viewer does not work on win 7 +a white screen is come up gives the note " error in GL command
+0 + + +3928432 +charras +1268466504 +
Works for me (with W7 32 bits version) +Are you using a W7 64 bits version?
+ + + + + + +9278614 +IP +Comment Added: 90.41.187.165 +1268466504 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2969856 +2969856 +1 +100 +100 +100 +nobody +nobody +nobody +1268482568 +0 +5 +locking and graphics heavy +
Hello I'm using the svn version and eesquema and Pcbnew are with the graphics too slow (video 128mb) and stop responding and must constantly be forced to leave tested on 2 computers (ubuntu 9.04) + +This happens in grand schemes in my case the page was completely filled using labels to plug in
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2970719 +2970719 +1 +100 +755196 +100 +nobody +nobody +nobody +1268669413 +0 +5 +Design checl rules menu - segmentation failed ! +
After making some design in PCBNEW, I wanted to go in the design check rules menu and the software crashed ! I start a new design and make the same operations ! When i wanted to change de classes of the differents net ! Both seems to be segmentation failure ! it is the last version uploaded the 3-14 !
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2970757 +2970757 +2 +1015285 +516020 +1 +alidoig +nobody +charras +1268674533 +1268741218 +5 +Component text does not rotate with component +
Bah, trust me to have the first bug report of the final release. + +If you create a new component with drawing text, then try to rotate the finished component in EESCHEMA, the text does not rotate with the component. +My workaround is to add text as a field, in which case it does rotate fine. + +Sorry. + +KiCad-2010-03-14-SVN2456-final
+0 + + + + + + +9285978 +IP +Artifact Created: 89.240.57.123 +1268674533 +alidoig + + +9289626 +status_id +1 +1268741218 +charras + + +9289627 +resolution_id +100 +1268741218 +charras + + +9289628 +allow_comments +1 +1268741218 +charras + + +9289629 +close_date +0 +1268741218 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2970765 +2970765 +1 +761682 +755196 +100 +yageek +nobody +nobody +1268675018 +0 +9 +Segmentation failed - final 20100314 +
Segmentation failed with the design rules menu ! The application crashes when I try to load the menu after I have done some design with the pcb !
+0 + + +3932340 +yageek +1268815163 +
More precisly, the bug happens when I want to change a signal from one class to another ! pcbnew crashes and i have a segmentation failed ! The version is kicad-2010-03-14-final (SVN 2456) + +
+ + +3933888 + +1268947847 +
Same trouble here, tested with 3 versions : Ubuntu (wx statically linked), WinXP, from sources (wx dynamic). +Problem occured after afftecting a netclass in a given pcbnew project. Since then, design rule menu issues a segfault each time it should be displayed. +I can provide my faulty design file (.brd) if needed.
+ + +3937115 +paulgittings +1269250993 +
Having the same issue. I've been working on a board for awhile and now when I attempt to access the "Design Rules"->"Design Rules" menu PCBNew just disappears. +I've tried up-grading to the current SVN version (20100322 SVN-R2470) to see if it would resolve the issue but the problem still remains. +I using 64-bit Ubunut 9.04.
+ + +3937122 +paulgittings +1269251489 +
Don't know if this helps but this is the log message when pcbnew seg faults: + +Mar 22 20:25:05 studypc kernel: [ 7352.589879] pcbnew[10112]: segfault at 119 ip 00007ffea362fa90 sp 00007fff88c7c778 error 4 in libwx_baseu-2.8.so.0.6.0[7ffea3580000+144000] +
+ + +3953594 + +1270498521 +
For me, release svn-2505 seems to have fixed this bug.
+ + +3954025 +paulgittings +1270547618 +
Works for me as well in svn-2506. + +Thanks to all involved in fixing it! + +Cheers, +Paul +
+ + + + + + +9286003 +IP +Artifact Created: 80.13.200.215 +1268675018 +yageek + + +9293255 +IP +Comment Added: 80.13.200.215 +1268815163 +yageek + + +9293256 +priority +5 +1268815163 +yageek + + +9294475 +priority +6 +1268839551 +yageek + + +9298870 +IP +Comment Added: 86.67.51.130 +1268947847 + + + +9309722 +IP +Comment Added: 211.30.110.233 +1269250993 +paulgittings + + +9309751 +IP +Comment Added: 211.30.110.233 +1269251489 +paulgittings + + +9367791 +IP +Comment Added: 86.67.51.130 +1270498521 + + + +9369975 +IP +Comment Added: 211.30.110.233 +1270547618 +paulgittings + + + + +http://sourceforge.net/support/tracker.php?aid=2970825 +2970825 +2 +1015285 +516020 +1 +alidoig +nobody +charras +1268683004 +1268741218 +5 +Block move/copy does not include graphic text +
Not much I can add to the summary - doing a block move in EESCHEMA does not include graphic text. +When you select a block,only components and graphic lines are highlighted. + +I rolled back to the previous release candidate, and it did the same. Soryr for not spotting this before the release.
+0 + + +3930583 +alidoig +1268683884 +
It turns out that new text is being included in the block command and it is only older text created with a previous release candidate that isn't, + +I can't remember exactly which release candidate was used to create the text, but it might have been around RC2. + +Tomorrow, I should be able to roll back to 2009-02-16 then forward to make sure it is only an incompatibility with one of the recent release candidates, in which case this should be a non-issue. Fingers crossed.
+ + +3930595 +alidoig +1268685017 +
Right, hopefully last one on this tonight. + +Unfortunately it is nothing to do with old text - it is rotated graphic text that isn't getting included in the block commands. + +Of course, when I tried to block move new text I didn't think to rotate it first! + +KiCad-2010-03-14-SVN2456-final.
+ + + + + + +9286373 +IP +Artifact Created: 89.240.57.123 +1268683004 +alidoig + + +9286416 +IP +Comment Added: 89.240.57.123 +1268683884 +alidoig + + +9286473 +IP +Comment Added: 89.240.57.123 +1268685017 +alidoig + + +9289622 +status_id +1 +1268741218 +charras + + +9289623 +resolution_id +100 +1268741218 +charras + + +9289624 +allow_comments +1 +1268741218 +charras + + +9289625 +close_date +0 +1268741218 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2971633 +2971633 +1 +761682 +755196 +100 +nobody +nobody +nobody +1268781424 +0 +5 +erro on save file +
today I had a problem with Pcbnew, worked on a plate for 4 hours and closed for my lunch the project was saved every 10 to 15 minutes and when I reopen it it was the same as before I started working on it in these 4 hours that the stranger is the auto save saved the plate in the middle of service i gave you a little advance I'm using ubuntu 9.04 version ppa.
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2973475 +2973475 +1 +761682 +755198 +100 +pisulski +nobody +nobody +1269033485 +0 +4 +Proposal to introduce so-called reference pointpoint +
I think it will be a goog idea introduce reference point. It is point used tu draw line with knew coordinates. +Where i will use it? for example for drawing PCB dimennsions. + +Sorry for my grammar
+0 + + + + + + +9303043 +IP +Artifact Created: 77.255.38.194 +1269033486 +pisulski + + +9303044 +priority +5 +1269033561 +pisulski + + + + +http://sourceforge.net/support/tracker.php?aid=2974272 +2974272 +1 +761682 +755196 +100 +nobody +nobody +nobody +1269210917 +0 +5 +error in dimensions +
do any one scheme, have exported to svg or even print, note that the dimensions will leave dferentes both svg as the printer + + +Note: once again after having saved the file I open it again and he had not saved and autosave (10 minutes) saved the changes
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2974273 +2974273 +1 +1015285 +755196 +100 +nobody +nobody +nobody +1269211031 +0 +5 +stop responding and locks everything +
schematic editor stopped responding and hangs it on ubuntu 9.04
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2974276 +2974276 +1 +761682 +755196 +100 +nobody +nobody +nobody +1269211211 +0 +5 +Pcbnew when you start trails +
command when you start hiking, I click the mouse and pull it almost always starts trails somewhere different and empty
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2974983 +2974983 +1 +761682 +755196 +100 +nobody +nobody +nobody +1269308934 +0 +5 +error layer edge when printing svg +
when I order prints in svg layers appear to put the edge inskape not recognize you need to choose property in the completion and color of the pen in any place and then solid and then he prints that layer
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2975062 +2975062 +1 +1015285 +755198 +100 +lomarcan +nobody +nobody +1269328968 +0 +5 +Bounding box for hierarchical sheet is wrong +
A hier. sheet is treated as is if it were wider than it really is i.e. right clicking somewhat on the right of a sheet shows the context menu for the sheet (even if there is NOTHING under the cursor)
+0 + + + + + + +9313221 +IP +Artifact Created: 80.207.56.82 +1269328968 +lomarcan + + + + +http://sourceforge.net/support/tracker.php?aid=2975063 +2975063 +2 +1015285 +755198 +1 +lomarcan +nobody +charras +1269329044 +1269791589 +5 +Move for a pinsheet can't be canceled +
When moving a pinsheet inside a hier. sheet symbol, pressing ESC confirms the move instead of canceling it
+0 + + + + + + +9313222 +IP +Artifact Created: 80.207.56.82 +1269329044 +lomarcan + + +9313234 +category_id +100 +1269329229 +lomarcan + + +9313235 +artifact_group_id +100 +1269329229 +lomarcan + + +9333281 +status_id +1 +1269791589 +charras + + +9333282 +resolution_id +100 +1269791589 +charras + + +9333283 +allow_comments +1 +1269791589 +charras + + +9333284 +close_date +0 +1269791589 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2975065 +2975065 +2 +1015285 +755198 +1 +lomarcan +nobody +charras +1269329087 +1269791589 +5 +Dragging a hierarchical sheet is broken +
It just move the sheet without dragging the wires.
+0 + + + + + + +9313227 +IP +Artifact Created: 80.207.56.82 +1269329087 +lomarcan + + +9313232 +category_id +100 +1269329195 +lomarcan + + +9313233 +artifact_group_id +100 +1269329195 +lomarcan + + +9333277 +status_id +1 +1269791589 +charras + + +9333278 +resolution_id +100 +1269791589 +charras + + +9333279 +allow_comments +1 +1269791589 +charras + + +9333280 +close_date +0 +1269791589 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2975066 +2975066 +2 +1015285 +755198 +1 +lomarcan +nobody +charras +1269329171 +1269791589 +5 +Hierarchical sheet operations cannot be undone +
They simply don't go in the undo stack. Pressing undo reverts other operations before.
+0 + + + + + + +9313231 +IP +Artifact Created: 80.207.56.82 +1269329171 +lomarcan + + +9333273 +status_id +1 +1269791589 +charras + + +9333274 +resolution_id +100 +1269791589 +charras + + +9333275 +allow_comments +1 +1269791589 +charras + + +9333276 +close_date +0 +1269791589 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2975068 +2975068 +1 +1015285 +755198 +100 +lomarcan +nobody +nobody +1269329437 +0 +1 +Hierarchical sheet resize +
An option to resize the sheet from the top could be useful. Otherwise you need to move all the pinsheet down to make space for the new ones.
+0 + + + + + + +9313238 +IP +Artifact Created: 80.207.56.82 +1269329437 +lomarcan + + +9313240 +priority +5 +1269329454 +lomarcan + + + + +http://sourceforge.net/support/tracker.php?aid=2975069 +2975069 +1 +1015285 +755198 +100 +lomarcan +nobody +nobody +1269329548 +0 +5 +Track cleanup after insertion of wire with INS +
Found because hier. sheet drag didn't work :P you have an array of wires like this: + +--- |> +--- |> Sheet +--- |> + +I used the W tool to add the missing part of wire in the first, the repeated +with INS. The first wire was 'fused' as one, the other ones remained with +dangling ends.
+0 + + + + + + +9313241 +IP +Artifact Created: 80.207.56.82 +1269329548 +lomarcan + + + + +http://sourceforge.net/support/tracker.php?aid=2975070 +2975070 +1 +1015285 +755198 +100 +lomarcan +nobody +nobody +1269329620 +0 +1 +Delete wire/delete node not intuitive +
The whole delete wire/delete node operation isn't really clear. The most +useful thing to do for a DEL keypress is to delete till the end or a junction +not the WHOLE wire (and not even always the whole, it depends on how it was +drawn to begin with). Example: + +A 1 B 2 C 3 D +---*---*---*--- (wire with junction) + +Pressing DEL on the A segment should delete only A, not the whole ABCD, or ABC, +or AB. Also the junction cleanup could be improved, often some 'corner' junction +remain or even some 'floating' ones. +
+0 + + + + + + +9313244 +IP +Artifact Created: 80.207.56.82 +1269329620 +lomarcan + + +9313245 +priority +5 +1269329646 +lomarcan + + + + +http://sourceforge.net/support/tracker.php?aid=2975071 +2975071 +1 +1015285 +755198 +100 +lomarcan +nobody +nobody +1269329698 +0 +1 +Power symbol drag +
Sometime G for a drag on a power symbol doesn't move the symbol itself but +only the wire. Something similar happen when ctrl dragging to the edge of a +part, they may be related issues.
+0 + + + + + + +9313246 +IP +Artifact Created: 80.207.56.82 +1269329698 +lomarcan + + +9313247 +priority +5 +1269329715 +lomarcan + + + + +http://sourceforge.net/support/tracker.php?aid=2975072 +2975072 +1 +1015285 +755198 +100 +lomarcan +nobody +nobody +1269329833 +0 +1 +Cut in eeschema? +
How do you cut in eeschema? Moving the cursor while moving scroll the view and warps the mouse (so the toolbar isn't accessible) and the accelerator key (S-DEL or C-X or whatever) isn't bound.
+0 + + + + + + +9313249 +IP +Artifact Created: 80.207.56.82 +1269329833 +lomarcan + + +9313251 +priority +5 +1269329848 +lomarcan + + + + +http://sourceforge.net/support/tracker.php?aid=2976225 +2976225 +1 +761682 +755196 +100 +nobody +nobody +nobody +1269476599 +0 +5 +breaking trails (rastnet) when trying to move or drag node s +
breaking trails (rastnet) when trying to move or drag node segment
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2976887 +2976887 +2 +761682 +755198 +105 +nobody +nobody +charras +1269592044 +1269887463 +5 +show on/off mask layer doesn't work ! +
hi all, + +sorry but show on/off mask layer doesn't work ! +see the file attach + +best regards
+0 + + +3946801 +charras +1269887463 +
Pads (on front and/ or back side) have their specific show/hide control. + this is not the show/hide layers options because pads are usually on more than one layer.
+ + +3946860 +jerryjacobs +1269891110 +
I agree with Jean-Pierre, this is also with Highly proffesional EDA packages like Altium. It also has capability to have multi-layer pads. This is normal behaivour.
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=368271&aid= +368271 +show_layers.png + +20288 +image/png +1269592045 +nobody + + + + +9338776 +IP +Comment Added: 90.41.69.61 +1269887463 +charras + + +9338777 +status_id +1 +1269887463 +charras + + +9338778 +resolution_id +100 +1269887463 +charras + + +9338779 +allow_comments +1 +1269887463 +charras + + +9338780 +close_date +0 +1269887463 +charras + + +9338979 +IP +Comment Added: 84.25.204.235 +1269891110 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2976893 +2976893 +2 +761682 +755198 +1 +cfdev +charras +charras +1269593105 +1269887747 +7 +svg export doesn't work with the mask layer +
hi, + +I have created an pad rect with only the mak layer, and when I export it to svg from pcbnew, +and I open the svg with Inkscape there is only the outline of a rectangle?? + +see attach file + +best regards, + +Cyril
+0 + + +3941127 +cfdev +1269597266 +
In fact, it's the rectangle that don't display correctly + +kicad code svg : + <g + style="fill:black; stroke:black; stroke-width:1" + id="g8" /> + <g + style="fill:#a000a0;fill-opacity:1;stroke:#a000a0;stroke-linecap:round;stroke-linejoin:round;stroke-opacity:1;stroke-width:1" + transform="translate(0 0) scale(1 1)" + id="g350"> + <path + d="M42616 25116 L44584 25116" + id="path352" + style="fill:#a000a0;fill-opacity:1;stroke:#a000a0;stroke-opacity:1" /> + <path + d="M44584 25116 L44584 27084" + id="path354" + style="fill:#a000a0;fill-opacity:1;stroke:#a000a0;stroke-opacity:1" /> + <path + d="M44584 27084 L42616 27084" + id="path356" + style="fill:#a000a0;fill-opacity:1;stroke:#a000a0;stroke-opacity:1" /> + <path + d="M42616 25116 L42616 27084" + id="path358" + style="fill:#a000a0;fill-opacity:1;stroke:#a000a0;stroke-opacity:1" /> + </g> + + + +Inkscape code : + + <rect + style="opacity:0.87999998;fill:#a000a0;fill-opacity:1;fill-rule:nonzero;stroke:#a000a0;stroke-width:0.89313447;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" + id="rect4152" + width="1968.0778" + height="1968.0377" + x="42616.004" + y="25115.973" /> +
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=368273&aid= +368273 +TestSerigraphie-Mask_Front.svg + +14876 +image/svg+xml +1269593105 +cfdev + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=368274&aid= +368274 +mask_svg.png + +95359 +image/png +1269593133 +cfdev + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=368275&aid= +368275 +TestSerigraphie.brd + +37315 +application/octet-stream +1269593215 +cfdev + + + + +9325483 +IP +Artifact Created: 92.153.128.34 +1269593105 +cfdev + + +9325484 +File Added +368273: TestSerigraphie-Mask_Front.svg +1269593105 +cfdev + + +9325485 +File Added +368274: mask_svg.png +1269593133 +cfdev + + +9325488 +File Added +368275: TestSerigraphie.brd +1269593215 +cfdev + + +9325492 +priority +5 +1269593243 +cfdev + + +9325493 +assigned_to +100 +1269593243 +cfdev + + +9325595 +IP +Comment Added: 92.153.128.34 +1269597267 +cfdev + + +9338800 +status_id +1 +1269887747 +charras + + +9338801 +resolution_id +100 +1269887747 +charras + + +9338802 +allow_comments +1 +1269887747 +charras + + +9338803 +close_date +0 +1269887747 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2977619 +2977619 +1 +100 +755196 +100 +nobody +nobody +nobody +1269696992 +0 +5 +Layers manager toolbar is not resized +
In GerbView and PCBnew, the layers manager toolbar is not resized with the window, it keeps its initial size and masks the task bar. + +screen resolution : 1440*900 +version : 2010-03-14 on Ubuntu 9.10
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=368413&aid= +368413 +Gerbview-20100314-reduced.png +Layers manager tolbar in Gerbview +91477 +image/png +1269696993 +nobody + + + + + + +http://sourceforge.net/support/tracker.php?aid=2977970 +2977970 +2 +1015285 +755198 +1 +jerryjacobs +charras +charras +1269776502 +1269791588 +5 +Print/Plot dialog for SVG sheet or symbol file browser +
Exporting a symbol in eeschema libedit for png is able to select a path and filename with a file browser dialog. This is not possible in SVG plot/print and if I open eeschema without a new project and try to plot a SVG from the kicad-newlib then I'm not able to find where it writes the SVG file to the harddisk. + +For me this is more a "bug" than a future request. +Correct me if i'm wrong. + +Regards, +Jerry
+0 + + + + + + +9332813 +IP +Artifact Created: 84.25.204.235 +1269776502 +jerryjacobs + + +9333269 +status_id +1 +1269791588 +charras + + +9333270 +resolution_id +100 +1269791588 +charras + + +9333271 +allow_comments +1 +1269791588 +charras + + +9333272 +close_date +0 +1269791588 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2978373 +2978373 +2 +761682 +100 +6 +cfdev +nobody +charras +1269849435 +1269887708 +5 +Delete bloc with zones doesn't work +
hi everybody, + +When I want to remove an bloc with all options checked, the zones always exist ?
+0 + + + + + + +9336252 +IP +Artifact Created: 92.153.128.34 +1269849435 +cfdev + + +9338796 +status_id +1 +1269887708 +charras + + +9338797 +resolution_id +100 +1269887708 +charras + + +9338798 +allow_comments +1 +1269887708 +charras + + +9338799 +close_date +0 +1269887708 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2979337 +2979337 +2 +1015285 +755198 +1 +lomarcan +nobody +charras +1269952647 +1270132369 +5 +Find part doesn't work for subparts +
You can't specify the subpart qualifier when searching i.e. U9 finds all the subparts in U9, but U9A doesn't find anything.
+0 + + + + + + +9341989 +IP +Artifact Created: 80.207.56.82 +1269952647 +lomarcan + + +9353468 +status_id +1 +1270132369 +charras + + +9353469 +resolution_id +100 +1270132369 +charras + + +9353470 +allow_comments +1 +1270132369 +charras + + +9353471 +close_date +0 +1270132369 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2979953 +2979953 +2 +761682 +1083307 +1 +khame +nobody +charras +1270036341 +1270058393 +5 +Can't generate Gerber file in normal user mode +
Under Windows Vista (sp2) with Kicad build 20100314SVN-R2460-final: + + - If you try to plot Gerber files in User mode you can only have empty files (No error displayed). PostScript plotting is good. + + - If you try to plot Gerber files after launching Kicad in Administrator mode the Gerber plotting is good. + +Maybe for the gerber plotting there is an access on a configuration file with higher permissions requirements.
+0 + + + + + + +9348319 +IP +Artifact Created: 88.160.11.132 +1270036342 +khame + + +9349426 +status_id +1 +1270058393 +charras + + +9349427 +resolution_id +100 +1270058393 +charras + + +9349428 +allow_comments +1 +1270058393 +charras + + +9349429 +close_date +0 +1270058393 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2980243 +2980243 +2 +761682 +516020 +2 +herg +nobody +herg +1270069556 +1270127105 +5 +Module attributes incorrectly populated +
I have a module with attributes: +T0 83 2736 600 600 0 120 N I 21 N"TSSOP16" +T1 126 1866 600 600 0 120 N V 21 N"VAL**" + +I then use CVpcb to link this module to: + ( /4BB25547 $noname U6 ADG888 {Lib=ADG888} + +I then read the netlist into PCBnew, and in the .brd: +T0 83 2736 600 600 0 120 N I 21 N"U6" +T1 126 1866 600 600 0 120 N V 21 N"ADG888" + +As you can see, I intended to make the reference designator visible, and the value invisible. The result is the opposite. +
+0 + + +3950041 +herg +1270127104 +
Upon further review, it looks like I misinterpreted the documentation: + +Module fields + + * The field that has the module name becomes the reference designator (R1 for a resistor). The field that contains: + + VAL** + +reflects the Part name that pointed to the module.
+ + + + + + +9350444 +IP +Artifact Created: 98.191.170.34 +1270069556 +herg + + +9353243 +IP +Comment Added: 98.191.170.34 +1270127105 +herg + + +9353244 +status_id +1 +1270127105 +herg + + +9353245 +resolution_id +100 +1270127105 +herg + + +9353246 +close_date +0 +1270127105 +herg + + + + +http://sourceforge.net/support/tracker.php?aid=2980726 +2980726 +2 +761682 +516020 +105 +pisulski +nobody +charras +1270153957 +1270217732 +5 +Visibility/unvisibility in editor library is not available +
first problem.Visibility option in Library editor is not available in case when i Want to unvisibility pin name. +Second problem: Enter key forces to go to the next field. He should confirm the change. +Third problem. In new version Kicad don`t work funktionality: WHen i take some module in new pcb, kicad show me the element in eeschema window.
+0 + + + + + + +9355121 +IP +Artifact Created: 77.253.92.138 +1270153957 +pisulski + + +9358632 +status_id +1 +1270217732 +charras + + +9358633 +resolution_id +100 +1270217732 +charras + + +9358634 +allow_comments +1 +1270217732 +charras + + +9358635 +close_date +0 +1270217732 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2980729 +2980729 +2 +1015285 +100 +105 +pisulski +nobody +charras +1270154331 +1270217732 +5 +Group rotate not work +
When I select few element's in eeschema and when i klik "R" key - it is no action.
+0 + + + + + + +9355128 +IP +Artifact Created: 77.253.92.138 +1270154331 +pisulski + + +9358628 +status_id +1 +1270217732 +charras + + +9358629 +resolution_id +100 +1270217732 +charras + + +9358630 +allow_comments +1 +1270217732 +charras + + +9358631 +close_date +0 +1270217732 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2980736 +2980736 +2 +1015285 +100 +6 +pisulski +nobody +charras +1270154599 +1270217641 +5 +Filed Don1't change their position. +
When i edit some component and i change position "reference" filed and "component name" filed, I aktualize my component in eeschema windoot this 2 filed dont change position.
+0 + + +3950601 +vovanium +1270157168 +
This is a feature -- ref and value position in library is only actual when you newly place a symbol on the scheme, then you may freely move ref and value on the scheme and their positions will be saved with the schematics.
+ + + + + + +9355146 +IP +Artifact Created: 77.253.92.138 +1270154599 +pisulski + + +9355362 +IP +Comment Added: 91.76.122.230 +1270157169 +vovanium + + +9358623 +status_id +1 +1270217641 +charras + + +9358624 +resolution_id +100 +1270217641 +charras + + +9358625 +allow_comments +1 +1270217641 +charras + + +9358626 +close_date +0 +1270217641 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2981754 +2981754 +2 +761682 +755196 +1 +dionysos-sf +nobody +charras +1270372677 +1270496092 +9 +PCBnew crash when trying to add a net in a netclass +
I created a new netclass (50_ohms) where I tried to add some nets. +I selected my netclass in the right list with the selector, then selected a net name in the left list and then clicked on the button ">>>". +Pcbnew crashes. + +Here is the backtrace of gdb: + +Program received signal SIGSEGV, Segmentation fault. +wxStringBase::compare (this=0x1294bc8, str=...) at src/common/string.cpp:948 +948 return ::wxDoCmp(data(), length(), str.data(), str.length()); +(gdb) bt +#0 wxStringBase::compare (this=0x1294bc8, str=...) at src/common/string.cpp:948 +#1 0x000000000047dbf1 in ?? () +#2 0x000000000047e3e6 in DIALOG_DESIGN_RULES::makePointers(std::vector<NETCUP*, std::allocator<NETCUP*> >*, wxString const&) () +#3 0x000000000047e841 in DIALOG_DESIGN_RULES::FillListBoxWithNetNames(wxListCtrl*, wxString const&) () +#4 0x0000000000482f4c in DIALOG_DESIGN_RULES::OnRightToLeftCopyButton(wxCommandEvent&) () +#5 0x0000003a730f2070 in wxEvtHandler::ProcessEventIfMatches (entry=<value optimized out>, handler=<value optimized out>, event=...) + at src/common/event.cpp:1231 +#6 0x0000003a730f21df in wxEvtHandler::SearchDynamicEventTable (this=0x122bde0, event=...) at src/common/event.cpp:1413 +#7 0x0000003a730f30e2 in wxEvtHandler::ProcessEvent (this=0x122bde0, event=...) at src/common/event.cpp:1289 +#8 0x000000346162f3c9 in gtk_button_clicked_callback (button=0x122bde0) at src/gtk/button.cpp:53 +#9 0x0000003faa80ba8e in IA__g_closure_invoke (closure=0x122bbc0, return_value=0x0, n_param_values=1, param_values=0x12d7e80, invocation_hint= + 0x7fffffffbe40) at gclosure.c:767 +#10 0x0000003faa8214b0 in signal_emit_unlocked_R (node=<value optimized out>, detail=<value optimized out>, instance=<value optimized out>, + emission_return=<value optimized out>, instance_and_params=<value optimized out>) at gsignal.c:3317 +#11 0x0000003faa82225f in IA__g_signal_emit_valist (instance=<value optimized out>, signal_id=<value optimized out>, detail=<value optimized out>, + var_args=0x7fffffffc030) at gsignal.c:2980 +#12 0x0000003faa8227a3 in IA__g_signal_emit (instance=<value optimized out>, signal_id=<value optimized out>, detail=<value optimized out>) + at gsignal.c:3037 +#13 0x000000346008d6f5 in gtk_real_button_released (button=0x11c1190 [GtkButton]) at gtkbutton.c:1707 +#14 0x0000003faa80ba8e in IA__g_closure_invoke (closure=0xb40b90, return_value=0x0, n_param_values=1, param_values=0x12d3940, invocation_hint= + 0x7fffffffc250) at gclosure.c:767 +#15 0x0000003faa8207dc in signal_emit_unlocked_R (node=<value optimized out>, detail=<value optimized out>, instance=<value optimized out>, + emission_return=<value optimized out>, instance_and_params=<value optimized out>) at gsignal.c:3177 +#16 0x0000003faa82225f in IA__g_signal_emit_valist (instance=<value optimized out>, signal_id=<value optimized out>, detail=<value optimized out>, + var_args=0x7fffffffc440) at gsignal.c:2980 +#17 0x0000003faa8227a3 in IA__g_signal_emit (instance=<value optimized out>, signal_id=<value optimized out>, detail=<value optimized out>) + at gsignal.c:3037 +#18 0x000000346008bf57 in gtk_button_button_release (widget=<value optimized out>, event=<value optimized out>) at gtkbutton.c:1599 +#19 0x0000003460153ae3 in _gtk_marshal_BOOLEAN__BOXED (closure=0xba75d0, return_value=0x7fffffffc6f0, n_param_values=<value optimized out>, + param_values=0x12c7400, invocation_hint=<value optimized out>, marshal_data=<value optimized out>) at gtkmarshalers.c:84 +#20 0x0000003faa80b9d9 in IA__g_closure_invoke (closure=0xba75d0, return_value=0x7fffffffc6f0, n_param_values=2, param_values=0x12c7400, + invocation_hint=0x7fffffffc6b0) at gclosure.c:767 +#21 0x0000003faa820b8d in signal_emit_unlocked_R (node=<value optimized out>, detail=<value optimized out>, instance=<value optimized out>, + emission_return=<value optimized out>, instance_and_params=<value optimized out>) at gsignal.c:3285 +#22 0x0000003faa8220fa in IA__g_signal_emit_valist (instance=<value optimized out>, signal_id=<value optimized out>, detail=<value optimized out>, + var_args=0x7fffffffc8a0) at gsignal.c:2990 +#23 0x0000003faa8227a3 in IA__g_signal_emit (instance=<value optimized out>, signal_id=<value optimized out>, detail=<value optimized out>) + at gsignal.c:3037 +#24 0x000000346027633f in gtk_widget_event_internal (widget=0x11c1190 [GtkButton], event=0x10a45f0) at gtkwidget.c:4775 +#25 0x000000346014a844 in IA__gtk_propagate_event (widget=0x11c1190 [GtkButton], event=0x10a45f0) at gtkmain.c:2417 +#26 0x000000346014b983 in IA__gtk_main_do_event (event=0x10a45f0) at gtkmain.c:1622 +#27 0x000000345fc5feac in gdk_event_dispatch (source=<value optimized out>, callback=<value optimized out>, user_data=<value optimized out>) + at gdkevents-x11.c:2372 +#28 0x0000003faa43923e in g_main_dispatch (context=0xb2c210) at gmain.c:1960 +#29 IA__g_main_context_dispatch (context=0xb2c210) at gmain.c:2513 +#30 0x0000003faa43cc28 in g_main_context_iterate (context=0xb2c210, block=<value optimized out>, dispatch=<value optimized out>, + self=<value optimized out>) at gmain.c:2591 +#31 0x0000003faa43d075 in IA__g_main_loop_run (loop=0x128cd90) at gmain.c:2799 +#32 0x000000346014beb7 in IA__gtk_main () at gtkmain.c:1218 +#33 0x00000034615e5c58 in wxEventLoop::Run (this=0x7fffffffcc70) at src/gtk/evtloop.cpp:76 +#34 0x000000346163ad51 in wxDialog::ShowModal (this=0x7fffffffccb0) at src/gtk/dialog.cpp:146 +#35 0x000000000045ccb3 in WinEDA_PcbFrame::ShowDesignRulesEditor(wxCommandEvent&) () +#36 0x0000003a730f2070 in wxEvtHandler::ProcessEventIfMatches (entry=<value optimized out>, handler=<value optimized out>, event=...) + at src/common/event.cpp:1231 +#37 0x0000003a730f3034 in wxEventHashTable::HandleEvent (this=<value optimized out>, event=..., self=0xb9efc0) at src/common/event.cpp:906 +#38 0x0000003a730f3117 in wxEvtHandler::ProcessEvent (this=0xb9efc0, event=...) at src/common/event.cpp:1293 +#39 0x0000003a730f30a0 in wxEvtHandler::ProcessEvent (this=0xb9f2f8, event=...) at src/common/event.cpp:1300 +#40 0x00000034616552e6 in gtk_menu_clicked_callback (widget=<value optimized out>, menu=0x11cc720) at src/gtk/menu.cpp:653 +#41 0x0000003faa80ba8e in IA__g_closure_invoke (closure=0x11ccd20, return_value=0x0, n_param_values=1, param_values=0x10ac8c0, invocation_hint= + 0x7fffffffd3b0) at gclosure.c:767 +#42 0x0000003faa820ec3 in signal_emit_unlocked_R (node=<value optimized out>, detail=<value optimized out>, instance=<value optimized out>, + emission_return=<value optimized out>, instance_and_params=<value optimized out>) at gsignal.c:3247 +#43 0x0000003faa82225f in IA__g_signal_emit_valist (instance=<value optimized out>, signal_id=<value optimized out>, detail=<value optimized out>, + var_args=0x7fffffffd5a0) at gsignal.c:2980 +#44 0x0000003faa8227a3 in IA__g_signal_emit (instance=<value optimized out>, signal_id=<value optimized out>, detail=<value optimized out>) + at gsignal.c:3037 +#45 0x000000346027d4ee in IA__gtk_widget_activate (widget=0x11c79e0 [GtkImageMenuItem]) at gtkwidget.c:4806 +#46 0x00000034601647bd in IA__gtk_menu_shell_activate_item (menu_shell=0x11c5340 [GtkMenu], menu_item=0x11c79e0 [GtkImageMenuItem], + force_deactivate=<value optimized out>) at gtkmenushell.c:1139 +#47 0x000000346016646a in gtk_menu_shell_button_release (widget=0x11c5340 [GtkMenu], event=<value optimized out>) at gtkmenushell.c:678 +#48 0x0000003460153ae3 in _gtk_marshal_BOOLEAN__BOXED (closure=0xba75d0, return_value=0x7fffffffd8f0, n_param_values=<value optimized out>, + param_values=0xf15cd0, invocation_hint=<value optimized out>, marshal_data=<value optimized out>) at gtkmarshalers.c:84 +#49 0x0000003faa80ba8e in IA__g_closure_invoke (closure=0xba75d0, return_value=0x7fffffffd8f0, n_param_values=2, param_values=0xf15cd0, + invocation_hint=0x7fffffffd8b0) at gclosure.c:767 +#50 0x0000003faa820b8d in signal_emit_unlocked_R (node=<value optimized out>, detail=<value optimized out>, instance=<value optimized out>, + emission_return=<value optimized out>, instance_and_params=<value optimized out>) at gsignal.c:3285 +#51 0x0000003faa8220fa in IA__g_signal_emit_valist (instance=<value optimized out>, signal_id=<value optimized out>, detail=<value optimized out>, + var_args=0x7fffffffdaa0) at gsignal.c:2990 +#52 0x0000003faa8227a3 in IA__g_signal_emit (instance=<value optimized out>, signal_id=<value optimized out>, detail=<value optimized out>) + at gsignal.c:3037 +#53 0x000000346027633f in gtk_widget_event_internal (widget=0x11c5340 [GtkMenu], event=0xd11b30) at gtkwidget.c:4775 +#54 0x000000346014a844 in IA__gtk_propagate_event (widget=0x11c5340 [GtkMenu], event=0xd11b30) at gtkmain.c:2417 +#55 0x000000346014b983 in IA__gtk_main_do_event (event=0xd11b30) at gtkmain.c:1622 +#56 0x000000345fc5feac in gdk_event_dispatch (source=<value optimized out>, callback=<value optimized out>, user_data=<value optimized out>) + at gdkevents-x11.c:2372 +#57 0x0000003faa43923e in g_main_dispatch (context=0xb2c210) at gmain.c:1960 +#58 IA__g_main_context_dispatch (context=0xb2c210) at gmain.c:2513 +#59 0x0000003faa43cc28 in g_main_context_iterate (context=0xb2c210, block=<value optimized out>, dispatch=<value optimized out>, + self=<value optimized out>) at gmain.c:2591 +#60 0x0000003faa43d075 in IA__g_main_loop_run (loop=0x1036e80) at gmain.c:2799 +#61 0x000000346014beb7 in IA__gtk_main () at gtkmain.c:1218 +#62 0x00000034615e5c58 in wxEventLoop::Run (this=0xd0f5a0) at src/gtk/evtloop.cpp:76 +#63 0x000000346166e9eb in wxAppBase::MainLoop (this=0xb2bee0) at src/common/appcmn.cpp:312 +#64 0x0000003a73097abc in wxEntry (argc=<value optimized out>, argv=<value optimized out>) at src/common/init.cpp:460 +#65 0x000000000055c2d2 in main () + +
+0 + + +3952688 + +1270387353 +
This bug is probably linked to bug #2970765.
+ + +3952835 +dionysos-sf +1270406725 +
Probably, and 2970719 too.
+ + + + + + +9363579 +IP +Artifact Created: 82.224.136.31 +1270372677 +dionysos-sf + + +9363840 +priority +5 +1270375382 +dionysos-sf + + +9364059 +IP +Comment Added: 86.67.51.130 +1270387353 + + + +9364658 +IP +Comment Added: 82.224.136.31 +1270406725 +dionysos-sf + + +9367678 +status_id +1 +1270496092 +charras + + +9367679 +resolution_id +100 +1270496092 +charras + + +9367680 +allow_comments +1 +1270496092 +charras + + +9367681 +close_date +0 +1270496092 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2981759 +2981759 +2 +761682 +755196 +1 +dionysos-sf +nobody +charras +1270373635 +1270496091 +5 +PCBnew crash when trying to add a net name to a pad in ModEd +
PCBnew crash when trying to add a net name to a pad in ModEdit. +Perhaps this is something we are not allowed to do. +I wanted to add a net name (GND) to some pads of a module in ModEdit. +When I clicked OK, a popup opened saying "Unknown netname, no change". +I clicked OK on this popup, then PCBnew crashes. + +Here is the baktrace from gdb: +Program received signal SIGSEGV, Segmentation fault. +0x0000003461758128 in typeinfo name for wxWindowBase () from /usr/lib64/libwx_gtk2u_core-2.8.so.0 +(gdb) bt +#0 0x0000003461758128 in typeinfo name for wxWindowBase () from /usr/lib64/libwx_gtk2u_core-2.8.so.0 +#1 0x00000034615faeec in gtk_window_realized_callback (m_widget=0x7fffffffc850, win=0x11c4b60) at src/gtk/window.cpp:2150 +#2 0x00000034616ee365 in wxGetTopLevelParent (win=0x7fffffffc850) at src/common/wincmn.cpp:2808 +#3 0x00000034616f254c in wxWindowBase::~wxWindowBase (this=0x11c4b60, __in_chrg=<value optimized out>) at src/common/wincmn.cpp:324 +#4 0x00000032a4e9676a in ~WinEDA_MessageDialog (this=0x11c4b60, __in_chrg=<value optimized out>) + at /usr/src/debug/kicad-2010.03.14/common/confirm.cpp:35 +#5 WinEDA_MessageDialog::~WinEDA_MessageDialog (this=0x11c4b60, __in_chrg=<value optimized out>) + at /usr/src/debug/kicad-2010.03.14/common/confirm.cpp:35 +#6 0x000000346166eb22 in wxAppBase::DeletePendingObjects (this=<value optimized out>) at src/common/appcmn.cpp:423 +#7 0x000000346166ebeb in wxAppBase::ProcessIdle (this=0xb1a770) at src/common/appcmn.cpp:454 +#8 0x00000034615ce900 in wxapp_idle_callback () at src/gtk/app.cpp:213 +#9 0x0000003faa43923e in g_main_dispatch (context=0xb1aa00) at gmain.c:1960 +#10 IA__g_main_context_dispatch (context=0xb1aa00) at gmain.c:2513 +#11 0x0000003faa43cc28 in g_main_context_iterate (context=0xb1aa00, block=<value optimized out>, dispatch=<value optimized out>, + self=<value optimized out>) at gmain.c:2591 +#12 0x0000003faa43d075 in IA__g_main_loop_run (loop=0xeb7fb0) at gmain.c:2799 +#13 0x000000346014beb7 in IA__gtk_main () at gtkmain.c:1218 +#14 0x00000034615e5c58 in wxEventLoop::Run (this=0xeb76f0) at src/gtk/evtloop.cpp:76 +#15 0x000000346166e9eb in wxAppBase::MainLoop (this=0xb1a770) at src/common/appcmn.cpp:312 +#16 0x0000003a73097abc in wxEntry (argc=<value optimized out>, argv=<value optimized out>) at src/common/init.cpp:460 +#17 0x000000000055c2d2 in main () + +
+0 + + + + + + +9363681 +IP +Artifact Created: 82.224.136.31 +1270373635 +dionysos-sf + + +9367674 +status_id +1 +1270496091 +charras + + +9367675 +resolution_id +100 +1270496091 +charras + + +9367676 +allow_comments +1 +1270496091 +charras + + +9367677 +close_date +0 +1270496091 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2981769 +2981769 +2 +761682 +755196 +105 +dionysos-sf +nobody +charras +1270375278 +1270489033 +5 +Pad colors aren't the same than the tracks +
I changed the default layer color in PCBnew by switching colors between solder layer and component layer +Now, solder layer tracks are red and component layer tracks are green. +Unfortunately, pad colors are not changed: solder layer pads are still green and component layer pads are still red, which isn't easy to work with.
+0 + + + + + + +9363839 +IP +Artifact Created: 82.224.136.31 +1270375278 +dionysos-sf + + +9367382 +status_id +1 +1270489033 +charras + + +9367383 +resolution_id +100 +1270489033 +charras + + +9367384 +allow_comments +1 +1270489033 +charras + + +9367385 +close_date +0 +1270489033 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2982119 +2982119 +2 +1015285 +100 +105 +thewarpi +nobody +charras +1270480629 +1270489033 +5 +Underscores added when creating new part +
Hi! + +When creating a new part in "Component Library Editor" writing the name under "Component name", it automaticly adds underscores instead of space. It also makes the letters uppercase. I know this is a bug because, you can change the name afterwards in the "Field properties" afterwards, and then it works to use partnames with spaces and lowercase.
+0 + + +3953398 +thewarpi +1270483764 +
This goes for aliases aswell.. Why,,,, WHYY??? :)
+ + +3953439 +thewarpi +1270485805 +
Ok, maybe it is not a bug since, it didnt work using partnames with spaces. Some error shows up when trying to load the schematic at a later time. + +Can we move this to a feature request?
+ + + + + + +9366835 +IP +Artifact Created: 90.237.202.7 +1270480629 +thewarpi + + +9366971 +IP +Comment Added: 90.237.202.7 +1270483764 +thewarpi + + +9367165 +IP +Comment Added: 90.237.202.7 +1270485805 +thewarpi + + +9367378 +status_id +1 +1270489033 +charras + + +9367379 +resolution_id +100 +1270489033 +charras + + +9367380 +allow_comments +1 +1270489033 +charras + + +9367381 +close_date +0 +1270489033 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2982146 +2982146 +2 +1015285 +100 +105 +thewarpi +nobody +charras +1270484084 +1270489032 +5 +Changing Value field of component creates a new one +
I dont know if this is suppose to be this way, when renaming a components value in the "Fields properties" it automaticly creates a new component with that name. Its a very nice way to copy components but it not a very logic one for people who dosent know about it.
+0 + + + + + + +9366987 +IP +Artifact Created: 90.237.202.7 +1270484084 +thewarpi + + +9366989 +category_id +100 +1270484114 +thewarpi + + +9367374 +status_id +1 +1270489032 +charras + + +9367375 +resolution_id +100 +1270489032 +charras + + +9367376 +allow_comments +1 +1270489032 +charras + + +9367377 +close_date +0 +1270489032 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2982182 +2982182 +2 +761682 +755196 +1 +nobody +nobody +charras +1270489450 +1270545636 +5 +PCBNew File - Revert function don't work. +
Sorry my english is not so good :-) I think the Revert-Funktion don't work. If I use the File -> Revert function from the Menu I get the error message: + +Recovery file /home/myuser/project/myproject.000 not found. + +PCBNew create not a backupfile. If I create the file (e.g. with touch command under Linux) then PCBNew update the backupfile correct. +
+0 + + + + + + +9369894 +status_id +1 +1270545636 +charras + + +9369895 +resolution_id +100 +1270545636 +charras + + +9369896 +allow_comments +1 +1270545636 +charras + + +9369897 +close_date +0 +1270545636 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2982617 +2982617 +1 +100 +100 +100 +nobody +nobody +nobody +1270557838 +0 +5 +List unconnected: center on component +
Rightclicking and selecting a pad in the list no longer centers on the chosen pad/component, as it used to in the previous version.
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2982636 +2982636 +1 +100 +100 +100 +nobody +nobody +nobody +1270560526 +0 +5 +List hotkeys +
The function List Hotkeys doesn't show a correct list. (I have assigned F5-F10 to different layers, which works). E g the F9 key is assigned "Switch to Inner layer 5" in file, but is listed both as "key F9: Switch to Inner layer 1" and "key F9: Switch to Inner layer 5".
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2982787 +2982787 +1 +761682 +755196 +100 +daveplatt +nobody +nobody +1270580048 +0 +5 +XORG crash when zooming +
This bug is actually a duplicate of 293063 - I couldn't figure out how to add a comment/artifact to that bug since it has already been closed. + +I also have run into the "Xorg server crash when zooming" using pcbnew, and as with the above bug it started occurring after my Xorg install was upgraded to version 1.7 (I run Debian's "testing" distribution). + +I dug around for a while on the net, and have confirmed that this is a real problem in the new version of Xorg. It certainly affects the Radeon driver, and may affect others as well. + +The problem seems to be centered in the EXA acceleration code in the X server (which the Radeon driver will use on request). There appears to be a situation in which the acceleration code can try to use an internal resource (an offscreen pixmap if I recall correctly) without activating it properly prior to use... smash, bang, segfault. Apparently, pcbnew's drawing of arcs seems to tickle this bug, which is otherwise somewhat difficult to trigger. + +The Xorg people seem to be looking into the cause, but the fix isn't straightforward, so it may take a while to correct the problem. + +Fortunately, there is an effective workaround. Go into your /etc/X11/xorg.conf file, find your Device section, and add (or change) the AccelMethod parameter. Set it to + + AccelMethod "xaa" + +This disables the new EXA accelerator, and switches back to the older XAA acceleration. + +There may be some reduction in screen rendering performance on some systems... this appears to be very dependent on the specific X card you use, and your graphics settings and what programs you're running. + +I didn't notice any degradation on my laptop's Radeon setup last night, when I confirmed that this workaround does actually correct the problem.
+0 + + + + + + +9371406 +IP +Artifact Created: 204.176.49.46 +1270580048 +daveplatt + + + + +http://sourceforge.net/support/tracker.php?aid=2982989 +2982989 +1 +761682 +755196 +100 +nobody +nobody +nobody +1270611363 +0 +5 +error adding board +
If I have the card "A" command and add to plate "B" when I send save it saves as a board "B" append the path of plate "B" being the right thing is to save card as "A" simply because I sent save and at worst should save as a board "A" to append the file is not the primary and secondary
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2983282 +2983282 +1 +1015287 +100 +100 +cfdev +nobody +nobody +1270652596 +0 +1 +Gerbview show/hide all layers +
show/hide all layers works only on 16 first layers (1 to 16)
+0 + + + + + + +9374927 +IP +Artifact Created: 92.153.22.228 +1270652597 +cfdev + + +9374928 +priority +5 +1270652628 +cfdev + + + + +http://sourceforge.net/support/tracker.php?aid=2983287 +2983287 +1 +1015287 +100 +100 +cfdev +nobody +nobody +1270653156 +0 +5 +Gerbview to pcbnew Layer problem +
when I import 2 layers, top and bottom in gerbview, it's ok, +I export to pcnew with select the layer ( *.brd ) + +When I open the *.brd in pcbnew, the board is correct, But I don't work with 2 layers, +so, I go to "design rules" -> impossible to check the layer uncheched, select an different number of layer and reselect 2 layers, +and It"s Ok I can check the layer. + +ps: sorry if I explained poorly
+0 + + + + + + +9374955 +IP +Artifact Created: 92.153.22.228 +1270653156 +cfdev + + + + +http://sourceforge.net/support/tracker.php?aid=2983318 +2983318 +1 +761682 +516020 +100 +nobody +nobody +nobody +1270656622 +0 +5 +Oval Pads Fail DRC Incorrectly +
Although DRC for oval pads works better with the new final release (20100314), it seems that pads placed at corners are treated like rectangular pads, which (depending on rotation) generates an incorrect error. Rotation 0 and 90 generates an error, rotation 0 and -90 does not. + +This issue was mentioned in 2945885 and is supposed to have been corrected, which is not the case (for the final release, at least).
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2983903 +2983903 +1 +761682 +100 +100 +nobody +nobody +nobody +1270734959 +0 +5 +Pad in Zone error +
I have a problem with "Add zones" function. Problem is: When i add zone GND all track and vias on the tracks have a good antipad size and thermal relife. But i have zones GND on the top and on the bottom side and i want to compensate potentianl on the bord. I do it throught vias. I trace the GND track to the vias ( see include file) I dont have thrmal relief. Exclude pads in this case also don`t work. +I highlight the GND net. and display Zones option. Mayby i have bad/incorect settings
+0 + + +3956972 +sebc26 +1270736823 +
Hi ... + +I have a problem that looks like the same : + +http://sourceforge.net/tracker/?func=detail&aid=2980541&group_id=145591&atid=762477 + +I hope this will be solved soon.
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=369871&aid= +369871 +Fill Zones Option and little bord.JPG + +139819 +image/jpeg +1270734959 +nobody + + + + +9381580 +IP +Comment Added: 82.244.110.178 +1270736823 +sebc26 + + + + +http://sourceforge.net/support/tracker.php?aid=2983906 +2983906 +1 +100 +100 +100 +pisulski +nobody +nobody +1270735441 +0 +5 +Show action layer selection -error +
Show action layer selection button don`t change colour when i change layer.
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=369872&aid= +369872 +Show action layer.JPG + +19071 +image/jpeg +1270735441 +pisulski + + + + +9381512 +IP +Artifact Created: 178.36.47.210 +1270735441 +pisulski + + +9381513 +File Added +369872: Show action layer.JPG +1270735441 +pisulski + + + + +http://sourceforge.net/support/tracker.php?aid=2984216 +2984216 +1 +761682 +755196 +100 +nobody +nobody +nobody +1270772601 +0 +5 +erro move zones in blocks +
failed to move the block that contains areas(zones) ,moves after they stay in place that were, only the fill.
+0 + + + + + + + + + + +http://sourceforge.net/?group_id=145591&atid=762477 +762477 +Support Requests +Tech Support Tracking System +All site users +Yes +No +1296000 + + +1209600 +0 +0 +0 + + + + +516021 +v1.0 (example) + + + + +761683 +Install Problem (example) +nobody + + + + + + +1 +Open + + +2 +Closed + + +3 +Deleted + + +4 +Pending + + + + +http://sourceforge.net/support/tracker.php?aid=1528910 +1528910 +3 +100 +100 +plyatov +nobody +dickelbeck +1153911779 +1187885389 +9 +site admin can\'t change file ownersheep +
I'm cannot make command +"chown manneveru +/home/groupsk/ki/kicad/htdocs/pl/index.shtml" + at shell.sourceforge.net . +Error is "Operation not permitted". +"manneveru" is member of my project. +Please help!
+0 + + + + + + +4958170 +status_id +1 +1187885389 +dickelbeck + + +4958171 +summary +site admin can't change file ownersheep +1187885389 +dickelbeck + + +4958172 +close_date +0 +1187885389 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=1943039 +1943039 +1 +100 +100 +nobody +nobody +nobody +1208268198 +0 +5 +KiCAD on PenDrive? +
Is it possible to create KiCAD's directory structure on PenDrive to have "mobile" version of KiCAD?
+0 + + +2897061 +manneveru +1219910997 +
Logged In: YES +user_id=639576 +Originator: NO + +Probably yes. KiCad can be built static with most libraries included. But I don't think anyone tried this before. If you have success, please publish it on wiki.
+ + +3580022 +nobody +1237303746 +
It works fine under windows. Make the install on the pendrive and run kicad's exe.
+ + + + + + +5902178 +IP +Artifact Created: 134.134.136.33 +1208268198 +nobody + + +6434266 +IP +Comment Added: 217.147.104.41 +1219910997 +manneveru + + +7933342 +IP +Comment Added: 212.99.4.114 +1237303746 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1956745 +1956745 +3 +761683 +516021 +durgadas +nobody +jerryjacobs +1209825873 +1257534813 +5 +looks for libraries and directories that don't exist +
When I start a new schematic I get a long long trail of dialog boxes complaining about libraries that don't exist. I can find no code or config file that names these libraries so can't tell where it gets the idea these should exist. I can edit the schematic file and eliminate the complaints, but every new schematic has them. Seems like either something is missing from the distro or someones private list of libraries has crept into the code (but I can't find them in any code!). + +Also, I get a complaint when kicad opens a browse dialog box about some applinks directory in kde3 not having search permissions. I also cannot find any code that is trying to use that directory. + +Does anyone know where these paths/filenames might be coming from?
+0 + + +3799528 +jerryjacobs +1257534813 +
There should be no problems with new releases.
+ + + + + + +5972200 +IP +Artifact Created: 209.180.51.97 +1209825874 +durgadas + + +8855069 +IP +Comment Added: 84.25.204.235 +1257534813 +jerryjacobs + + +8855070 +status_id +1 +1257534813 +jerryjacobs + + +8855071 +close_date +0 +1257534813 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2075168 +2075168 +1 +100 +100 +and10 +nobody +nobody +1219732824 +0 +5 +Schematic print multiple pages +
I have tried to print my A3 sized schematic on an A4 printer HP1200 (and on PDF printer as well) spanning multiple pages, but the "Layout\spread 1 page on 2 pages" doesn't do the trick. +I also wondered if it is correct that all print options resets when I press "preview", which means that it is not possible to preview with specific settings and then immediately print with the same settings. +Running ubuntu linux. + +
+0 + + + + + + +6421914 +IP +Artifact Created: 85.82.142.172 +1219732825 +and10 + + + + +http://sourceforge.net/support/tracker.php?aid=2980541 +2980541 +1 +100 +100 +sebc26 +nobody +nobody +1270127146 +0 +5 +Vias / Zone filling problem +
Hi world, + +From some times, there is a problem I cannot solve ... + +The goal is to set heat sink for SOT_23_5. += vias under SOT23 will act as heat pipe and GND plane will be the heat sink. + +Please take a look at the picture, there are 4 STEPs on it : + +STEP 1 = I've put 3 vias under my SOT23, and connect them to the GND pin (net 8 on picture). + +STEP 2 = I use the equipotential tool to ensure that there are really connected to GND (net 8). + +STEP 3 = I fill the zone, and them, the zone "take" the vias at center, but avoid the upper and lowers ones ?! + +STEP 4 = What I want ( drawn in paint.net ) + +So ... Do I something wrong ? ... Is there a trick I haven't found ??? + +Maybe some of you have found the same problem ... and maybe some of them have solve it ??!! + +Thanks for reading. + +Sébastien (FR)
+0 + + +3950047 +sebc26 +1270127456 +
Note : to add vias, I need to disable DRC check, looks like it doesn't like this kind of "useless" tracks ... + +Sebastien. +
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762477&file_id=369090&aid= +369090 +Problem_Kicad.png +Pictures +121858 +image/png +1270127147 +sebc26 + + + + +9353250 +IP +Artifact Created: 82.244.110.178 +1270127147 +sebc26 + + +9353251 +File Added +369090: Problem_Kicad.png +1270127147 +sebc26 + + +9353278 +IP +Comment Added: 82.244.110.178 +1270127456 +sebc26 + + + + + + +http://sourceforge.net/?group_id=145591&atid=762478 +762478 +Patches +Patch Tracking System +All site users +Yes +No +1296000 + + +1209600 +0 +0 +0 + + + + +516022 +Unstable (example) + + + + +761684 +Widget (example) +nobody + + +1084471 +eeschema +nobody + + +1084472 +pcbnew +nobody + + + + +1 +Fixed + + +2 +Invalid + + +3 +Wont Fix + + +4 +Later + + +5 +Remind + + +6 +Works For Me + + +100 +None + + +101 +Duplicate + + +102 +Accepted + + +103 +Out of Date + + +104 +Postponed + + +105 +Rejected + + + + +1 +Open + + +2 +Closed + + +3 +Deleted + + +4 +Pending + + + + +http://sourceforge.net/support/tracker.php?aid=1781977 +1781977 +2 +100 +100 +102 +llamatronique +nobody +kintel +1188125222 +1213545924 +5 +Path & execution fixes for Mac OS +
This patch fixes a number of issues regarding the the MacOS handling of execution, arguments and search paths, and is a bit closer to having the kicad applications behave like a typical mac app. + +The convention is for Application Bundles to be executable from the root of an application folder with all support paths relative to the bundle path. + +- Changed SetBinDir() to return application directory rather than executable location. +- Changed executable paths to be relative to application directory. +- Split file dialog paths to path & filename (workaround for file dialogs which substitute path delimiter with "-") +- Added a (temporary) fix to assume that the help/data paths will be the application directory. + +Build changes : + +- Added __UNIX__ compiler flag. +- Added Debug targets. +- Changed path to wxWidgets source to a single variable. +- Better handling for bundle creation (links no longer required, & app bundlers included in clean and install targets)
+0 + + +2807912 +kintel +1213545924 +
Logged In: YES +user_id=145718 +Originator: NO + +Old patch, was accepted last year sometime.
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=242857&aid= +242857 +mac_fixes_20070826_201.patch +Path & execution fixes for Mac OS +16124 +application/octet-stream +1188125222 +llamatronique + + + + +4967277 +IP +Artifact Created: 121.44.11.126 +1188125222 +llamatronique + + +4967278 +File Added +242857: mac_fixes_20070826_201.patch +1188125223 +llamatronique + + +6137451 +IP +Comment Added: 85.127.109.16 +1213545924 +kintel + + +6137452 +status_id +1 +1213545924 +kintel + + +6137453 +resolution_id +100 +1213545924 +kintel + + +6137454 +close_date +0 +1213545924 +kintel + + + + +http://sourceforge.net/support/tracker.php?aid=1905661 +1905661 +2 +100 +100 +102 +diemer +diemer +plyatov +1204460769 +1204577685 +5 +3d-viewer rotation/panning fix +
Hi, + +the attached patch fixes panning in 3d-viewer. The problem was that after the view had been rotated (by left-mouse dragging), panning didn't work intitively anymore. + +The fix was to simply change the order of how rotation and translation get applied in Pcb3D_GLCanvas::Redraw(). + +Best reagards.
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=268807&aid= +268807 +fix_drawing.patch +Patch against latest svn +1265 +text/x-patch +1204460769 +diemer + + + + +5707161 +IP +Artifact Created: 82.83.204.160 +1204460769 +diemer + + +5707162 +File Added +268807: fix_drawing.patch +1204460770 +diemer + + +5713508 +status_id +1 +1204577684 +plyatov + + +5713509 +close_date +0 +1204577685 +plyatov + + +5778213 +resolution_id +100 +1205875552 +diemer + + +5778214 +assigned_to +100 +1205875552 +diemer + + + + +http://sourceforge.net/support/tracker.php?aid=1919368 +1919368 +2 +1084471 +100 +100 +diemer +diemer +jerryjacobs +1205916506 +1257524383 +5 +XOR Artifacts +
To be done: + + - Implement the remaining GetBoundingBox() functions (or use ifs to fall back to the old xor-Method for missing parts). + + - Replace call(s) to EDA_BaseStruct::GetBoundingBox() by returning a simple empty rect. + +
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=271001&aid= +271001 +eeschema_redraw-3.patch + +5992 +text/x-patch +1205916506 +diemer + + + + +5780267 +IP +Artifact Created: 134.169.117.46 +1205916506 +diemer + + +5780268 +File Added +271001: eeschema_redraw-3.patch +1205916506 +diemer + + +8854543 +status_id +1 +1257524383 +jerryjacobs + + +8854544 +close_date +0 +1257524383 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2526177 +2526177 +1 +100 +100 +100 +cfdev +nobody +nobody +1232543764 +0 +5 +WinEDA_PositionCtrl +
hi, +To filter the numeric char : + +In /kicad/common/wxwineda.cpp + ++ #include <wx/valtext.h> + +//in WinEDA_PositionCtrl::WinEDA_PositionCtrl(...) + + * m_FramePosX = new wxTextCtrl( parent, -1, wxEmptyString, wxDefaultPosition, wxDefaultSize, 0, wxTextValidator(wxFILTER_NUMERIC)); + + *m_FramePosY = new wxTextCtrl( parent, -1, wxEmptyString, wxDefaultPosition, wxDefaultSize, 0, wxTextValidator(wxFILTER_NUMERIC)); + + +For me the char '.' is not valide for the value, maybe make an custom list "wxTextValidator". + +++
+0 + + + + + + +7499128 +IP +Artifact Created: 90.52.22.12 +1232543764 +cfdev + + + + +http://sourceforge.net/support/tracker.php?aid=2805197 +2805197 +1 +100 +100 +100 +hauptmech +nobody +nobody +1244773398 +0 +5 +using wxMSW zlib src fails silently +
Altered CMake so that if it can't find the wxMSW /src/zlib/*.h it fails with a hint of what's wrong. CMakeCache.txt can be subsequently modified if necessary
+0 + + +3675855 +hauptmech +1244839701 +
One of the path changes I incorrectly made while trying to compile snuck into the original patch. Updated patch is correct
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=330787&aid= +330787 +improved_cmake.patch + +1562 +text/x-diff +1244841510 +hauptmech + + + + +8367691 +IP +Artifact Created: 118.90.106.51 +1244773398 +hauptmech + + +8367692 +File Added +330674: kicad_compile.patch +1244773399 +hauptmech + + +8369989 +File Deleted +330674: +1244839602 +hauptmech + + +8369991 +IP +Comment Added: 118.90.106.51 +1244839701 +hauptmech + + +8370048 +File Added +330787: improved_cmake.patch +1244841510 +hauptmech + + + + +http://sourceforge.net/support/tracker.php?aid=2805206 +2805206 +1 +1084472 +100 +100 +hauptmech +nobody +nobody +1244776444 +0 +5 +Configurable epoxy thickness for 3D view +
The config variable "LayerThickness" is used to set the distance between layers in the 3D view. The *.brd file must be edited directly, there is no user interface for this.
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=330676&aid= +330676 +brd_thk.diff +Adds LayerThickness variable for 3D viewer +3258 +application/octet-stream +1244776444 +hauptmech + + + + +8367731 +IP +Artifact Created: 118.90.106.51 +1244776444 +hauptmech + + +8367732 +File Added +330676: brd_thk.diff +1244776445 +hauptmech + + + + +http://sourceforge.net/support/tracker.php?aid=2805221 +2805221 +2 +100 +100 +100 +hauptmech +nobody +jerryjacobs +1244779322 +1257524112 +5 +default name for hotkey files incorrect +
Default name was: "prog..key" (such as "pcbnew..key")
+0 + + +3675410 +hauptmech +1244800521 +
Previous patch file did not cover all cases. Working on a new one.
+ + + + + + +8367776 +IP +Artifact Created: 118.90.106.51 +1244779322 +hauptmech + + +8367777 +File Added +330679: hotkey_file.diff +1244779322 +hauptmech + + +8368297 +File Deleted +330679: +1244800495 +hauptmech + + +8368299 +IP +Comment Added: 118.90.106.51 +1244800521 +hauptmech + + +8854532 +status_id +1 +1257524112 +jerryjacobs + + +8854533 +allow_comments +1 +1257524112 +jerryjacobs + + +8854534 +close_date +0 +1257524112 +jerryjacobs + + +8854535 +allow_comments +0 +1257524118 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2805860 +2805860 +2 +100 +516022 +100 +hauptmech +nobody +sf-robot +1244889019 +1258770019 +5 +Last tool used toggle +
Patch creating a command to toggle between the present tool and the last used tool in pcbnew. Adds hotkey hooks for pcbnew add_module and add_tracks.
+0 + + +3799394 +jerryjacobs +1257524052 +
Tried to get it in SVN trunk after hand editing it did not work, could you create a new patch?
+ + +3812838 +sf-robot +1258770019 +
This Tracker item was closed automatically by the system. It was +previously set to a Pending status, and the original submitter +did not respond within 14 days (the time period specified by +the administrator of this Tracker).
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=330835&aid= +330835 +ToggleCommand.patch + +17294 +text/x-diff +1244889019 +hauptmech + + + + +8371098 +IP +Artifact Created: 118.90.106.51 +1244889019 +hauptmech + + +8371099 +File Added +330835: ToggleCommand.patch +1244889019 +hauptmech + + +8854319 +status_id +1 +1257520699 +jerryjacobs + + +8854320 +close_date +0 +1257520699 +jerryjacobs + + +8854524 +IP +Comment Added: 84.25.204.235 +1257524052 +jerryjacobs + + +8901593 +IP +Comment Added: +1258770019 +sf-robot + + +8901594 +status_id +4 +1258770019 +sf-robot + + +8901595 +allow_comments +1 +1258770019 +sf-robot + + +8901596 +close_date +1257520699 +1258770019 +sf-robot + + + + +http://sourceforge.net/support/tracker.php?aid=2806042 +2806042 +1 +1084472 +100 +100 +hauptmech +nobody +nobody +1244938036 +0 +5 +Move/drag hotkey grabs nodes/tracks +
When the track tool is active, using the 'move footprint' hotkey will move the selected node; using the 'drag footprint' hotkey will move the selected track.
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=330898&aid= +330898 +move_track_hotkey.patch + +6984 +text/x-diff +1244938960 +hauptmech + + + + +8372250 +IP +Artifact Created: 118.90.106.51 +1244938036 +hauptmech + + +8372251 +File Added +330897: move_track_hotkey.patch +1244938036 +hauptmech + + +8372271 +File Deleted +330897: +1244938920 +hauptmech + + +8372272 +File Added +330898: move_track_hotkey.patch +1244938960 +hauptmech + + + + +http://sourceforge.net/support/tracker.php?aid=2806129 +2806129 +2 +1084472 +516022 +100 +hauptmech +nobody +jerryjacobs +1244972676 +1257520170 +5 +Track clearance dropdown menu +
Adds a history and drop down menu for clearance width next to track width. +Adds a toggle button to show/hide "invisible" text.
+0 + + +3676981 +hauptmech +1245020964 +
Last patch was generated by git because I've accumulated too many changes to sort the changes out by hand. You can either strip the git specific stuff or grab the full patch attached and sort through it by hand. + +The combined patch is against svn 1816. It compiles/runs but I don't know the codebase well enough to guarantee stability.
+ + +3799346 +jerryjacobs +1257520162 +
Added revision 1828
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=330921&aid= +330921 +clr_dropdown.diff + +25996 +application/octet-stream +1244972676 +hauptmech + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=330982&aid= +330982 +hauptmech.patch +Patch of all changes against svn 1816 +80439 +text/x-diff +1245020803 +hauptmech + + + + +8372724 +IP +Artifact Created: 118.90.106.51 +1244972676 +hauptmech + + +8372725 +File Added +330921: clr_dropdown.diff +1244972676 +hauptmech + + +8374015 +File Added +330982: hauptmech.patch +1245020803 +hauptmech + + +8374017 +IP +Comment Added: 118.90.106.51 +1245020964 +hauptmech + + +8374018 +category_id +100 +1245020964 +hauptmech + + +8374019 +artifact_group_id +100 +1245020964 +hauptmech + + +8854272 +IP +Comment Added: 84.25.204.235 +1257520162 +jerryjacobs + + +8854273 +status_id +1 +1257520170 +jerryjacobs + + +8854274 +allow_comments +1 +1257520170 +jerryjacobs + + +8854275 +close_date +0 +1257520170 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2807379 +2807379 +2 +1084472 +100 +100 +hauptmech +nobody +jerryjacobs +1245187092 +1257519776 +5 +Netnames on other layers not shown in high-contrast mode +
Netnames on other layers not shown in high-contrast mode. Only netnames from the current layer are shown. Helps readability in dense circuits.
+0 + + +3679192 +jerryjacobs +1245262176 +
Patch approved SVN 1820
+ + +3799343 +jerryjacobs +1257519768 +
Patched added
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=331227&aid= +331227 +contrast_netnames.patch +Patch against SVN1819 +1522 +text/x-diff +1245187092 +hauptmech + + + + +8381425 +IP +Artifact Created: 118.90.106.51 +1245187092 +hauptmech + + +8381426 +File Added +331227: contrast_netnames.patch +1245187092 +hauptmech + + +8384410 +IP +Comment Added: 84.25.137.47 +1245262176 +jerryjacobs + + +8854261 +IP +Comment Added: 84.25.204.235 +1257519768 +jerryjacobs + + +8854264 +status_id +1 +1257519776 +jerryjacobs + + +8854265 +allow_comments +1 +1257519776 +jerryjacobs + + +8854266 +close_date +0 +1257519776 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2809677 +2809677 +1 +1084472 +100 +100 +hauptmech +nobody +nobody +1245557608 +0 +5 +Hotkey to show/hide clearance +
Hotkey switches between showing all clearances, and the previous state (ie show with new track/via, etc)
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=331758&aid= +331758 +clearance_display.patch + +2142 +text/x-diff +1245557608 +hauptmech + + + + +8393997 +IP +Artifact Created: 118.90.106.51 +1245557608 +hauptmech + + +8393998 +File Added +331758: clearance_display.patch +1245557608 +hauptmech + + + + +http://sourceforge.net/support/tracker.php?aid=2809678 +2809678 +1 +1084472 +100 +100 +hauptmech +nobody +nobody +1245557721 +0 +5 +Read saved track clearances from config file +
A bit of code to read track clearance history that was saved in the config file. (should have been included in a previous patch)
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=331759&aid= +331759 +clearance_width_save.patch + +585 +text/x-diff +1245557721 +hauptmech + + + + +8394000 +IP +Artifact Created: 118.90.106.51 +1245557721 +hauptmech + + +8394001 +File Added +331759: clearance_width_save.patch +1245557721 +hauptmech + + + + +http://sourceforge.net/support/tracker.php?aid=2851908 +2851908 +1 +1084472 +100 +100 +bjerre +nobody +nobody +1252102580 +0 +5 +Copper zone option to inhibit combines with other zones +
Patch to let the user explicitly allow or disallow combining of the current zone with other zones, in the fill zone options menu. The need came from a ground plane requiring two different clearances, one for a microprocessor part and one for a rf frontend part. (Other users might like the same feature for hosting high and low voltage circuits on the same plane ?). In both cases it is akward that the zones gets combined. +Please notice that the attached patch is only a proof of concept, there is no guarantee that it doesn't bite. +
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=341816&aid= +341816 +ZoneMergeOption.patch +Made against svn rev 1949 +15666 +application/octet-stream +1252102580 +bjerre + + + + +8638205 +IP +Artifact Created: 62.107.125.243 +1252102580 +bjerre + + +8638206 +File Added +341816: ZoneMergeOption.patch +1252102581 +bjerre + + + + +http://sourceforge.net/support/tracker.php?aid=2976667 +2976667 +1 +1084471 +100 +100 +nobody +nobody +nobody +1269547292 +0 +5 +Patch to fix PostScript plotting of user-specified sheet siz +
This patch generates the correct %%DocumentMedia tag when generating PostScript plots of user specified sheet sizes. Works against SVN R2347.
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=368217&aid= +368217 +common_plotPS_functions.patch +This patch applies to common/common_plotPS_functions.cpp +707 +text/x-patch +1269547293 +nobody + + + + + + + + +http://sourceforge.net/?group_id=145591&atid=762479 +762479 +Feature Requests +Feature Request Tracking System +All site users +Yes +No +3888000 + + +1209600 +0 +0 +0 + + + + +516023 +Next Release (example) + + + + +761685 +Interface Improvements (example) +nobody + + +1026579 +PCBNEW +nobody + + +1026580 +EESCHEMA +nobody + + +1026581 +PROJECT MGR +nobody + + +1026582 +CVPCB +nobody + + +1026583 +GERBVIEW +nobody + + + + + + +1 +Open + + +2 +Closed + + +3 +Deleted + + +4 +Pending + + + + +http://sourceforge.net/support/tracker.php?aid=1782201 +1782201 +1 +761685 +516023 +tonymux +nobody +nobody +1188175260 +0 +5 +Components registered in database +
+Just wanted to suggest an implementation of a solution whereby each component (reference) would be uniquely associated to information stored on a database (link postgres) including: + - Geometry + - Tolerance + - Other generic info that could be edited (manufacturer, distributer, ref. price, etc) + - Possibility to embed data sheet information into the component info as well as note files + - Possibility to associate with each sheet a text information that could be processed by DoxyGen
+0 + + +2492058 +dickelbeck +1189608309 +
Logged In: YES +user_id=1222857 +Originator: NO + +This posting leaves me asking more questions than it answers. + +Which program, eescema or pcbnew? + +Why is the database desireable? This sounds like a solution without a problem. Please describe the problem first. Databases are not easily moved from one machine to another, so it comes with a bag of disadvantages too. + +Unless you want a globally accessible database, one that every kicad user shares over the internet. + + +
+ + + + + + +4968638 +IP +Artifact Created: 85.139.172.13 +1188175260 +tonymux + + +5035371 +IP +Comment Added: 67.64.64.34 +1189608309 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=1783527 +1783527 +1 +761685 +100 +nwimpney +nobody +nobody +1188320339 +0 +5 +Keeping dragged parts connected. +
When re-arranging parts on a crowded layout, it would be useful to have an option to have the connections remain. Even if it's not perfect, it would often be preferable to having to delete and re-connect all of the traces individually. The schematic and board editor could both benefit from this behaviour.
+0 + + +2490077 +nobody +1189452680 +
Logged In: NO + +Or (for now) add an option to automaticaly delete tracks (in PCBnew) and wires (in EEschema) that was connected to the dragged part.
+ + +2641671 +alanjshea +1200940917 +
Logged In: YES +user_id=803932 +Originator: NO + +Automatically deleting tracks for a moved part is a bad idea, as you have to recreate the connections and that could be more time-consuming than doing it yourself. At least if they are still hanging there you can more readily re-connect the tracks.
+ + +2641673 +alanjshea +1200941039 +
Logged In: YES +user_id=803932 +Originator: NO + +This feature is one of the most important for my application. I can't contribute code, but what else could I do to encourage this?
+ + + + + + +4976644 +IP +Artifact Created: 204.174.223.110 +1188320339 +nwimpney + + +5027345 +IP +Comment Added: 89.102.22.118 +1189452680 +nobody + + +5539068 +IP +Comment Added: 207.32.229.26 +1200940918 +alanjshea + + +5539074 +IP +Comment Added: 207.32.229.26 +1200941039 +alanjshea + + + + +http://sourceforge.net/support/tracker.php?aid=1785173 +1785173 +2 +100 +100 +theamigo +nobody +stambaughw +1188503787 +1270750482 +5 +Option to plot without border +
I'd like a checkbox in EESchema's Plot dialog (specifically SVG) that would prevent it from plotting the page border and block that has Title, Size, Rev, etc. + +I use KiCAD for drawing schematics for my electronics class. I plot to SVG and import into OpenOffice. But at the moment, I have to manually remove all of that every time I import a drawing. Adding this feature would help make real-time note taking easier.
+0 + + +3957168 +stambaughw +1270750482 +
Check box to disable plotting reference frame in SVG, PS, and DXF plot dialogs as of release 20100314.
+ + + + + + +4986395 +IP +Artifact Created: 129.188.69.145 +1188503787 +theamigo + + +9382243 +IP +Comment Added: 162.83.115.135 +1270750482 +stambaughw + + +9382244 +status_id +1 +1270750482 +stambaughw + + +9382245 +allow_comments +1 +1270750482 +stambaughw + + +9382246 +close_date +0 +1270750482 +stambaughw + + + + +http://sourceforge.net/support/tracker.php?aid=1789042 +1789042 +1 +761685 +516023 +nobody +nobody +nobody +1189035834 +0 +5 +Associate eeschema parts with pcbnew footprints +
Currently, to design a PCB, the user has to design the schematic, then run cv2pcb and tell which footprint to use for every single component, and then run pcbnew and use all the footprints. Changing the footprint of a device after starting on the PCB layout means going back to cv2pcb and editing that entry, then re-importing the cv2pcb output in pcbnew. + +Cv2pcb should simply be eliminated altogether, and eeschema and pcbnew should work more closely together. + +Each component in eeschema's library should have the ability to have one or more footprints, from pcbnew, associated with it. This way, if the user has a particular diode, he can just place it on his schematic, and when he exports to pcbnew, the DO-31 (for example) footprint will automatically show up; he should not have to choose that footprint, except for when he first creates the part in his library. Parts in the main library (included with Kicad) would already have default associations set up. + +It's also useful to allow more than one possible footprint. For instance, some components have thru-hole and SMT versions. Others have multiple orientations (horizontal vs. vertical). After importing a design from eeschema, the user, while laying out the PCB, should be able to right-click on a component, choose Properties or similar, and select any alternate footprint that might be available. The new footprint should immediately replace the old one on the screen. + +Professional CAD programs like PADS generally work like this. +
+0 + + +2485832 +plyatov +1189061775 +
Logged In: YES +user_id=1325376 +Originator: NO + +Possibility to change or select alternate footprint, must be implemented in schematic editor - not in PCB editor! +Because, when user create bill of materials, it is wery important to have the information about footprint in BOM. +In Altium "Protel", user can change the properties of component by double click on it in schematic editor.
+ + + + + + +5009935 +IP +Artifact Created: 192.88.158.212 +1189035834 +nobody + + +5010712 +IP +Comment Added: 81.176.8.172 +1189061775 +plyatov + + + + +http://sourceforge.net/support/tracker.php?aid=1789164 +1789164 +1 +100 +100 +plyatov +nobody +nobody +1189061309 +0 +5 +internal planes connection +
"pcbnew" has a problem connecting to internal planes. +I selected the proper layers for the via's and then selected the proper working layer and created/filled a zone. +It looks like there are connections, but it still shows a ratsnest to the ground and power connections and I have unconnected nets.
+0 + + +2492067 +dickelbeck +1189609010 +
Logged In: YES +user_id=1222857 +Originator: NO + +From all the discussion on the mailing lists, I believe now that zones are not "electrically aware" as far as DRC is concerned. What I understand is that you have to put tracks down for all connections, then fill over them as the last step using one or more zones. So maybe you want zones to be electrically aware? What are they doing in geda regarding zones? Maybe we can borrow some ideas and code from them.
+ + + + + + +5010698 +IP +Artifact Created: 81.176.8.172 +1189061309 +plyatov + + +5035392 +IP +Comment Added: 67.64.64.34 +1189609010 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=1790488 +1790488 +1 +761685 +516023 +nobody +nobody +nobody +1189210271 +0 +5 +Pins-swap and Gate-swap +
Please add pins-swap and gate-swap functions. For instance, on a 7400 quad NAND gate chip, there are 4 separate gates, all identical. It may ease routing to use gate C instead of gate A, but that's not how the schematic is drawn. pcbnew already has the concept of separate gates, but doesn't have a simple way of swapping them; you have to change the schematic and re-import it to pcbnew. This should be a one-click operation. +
+0 + + + + + + +5018640 +IP +Artifact Created: 192.88.158.212 +1189210271 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1794774 +1794774 +1 +761685 +100 +nobody +nobody +nobody +1189781352 +0 +5 +Netlist editor enhancement +
In addition to assigning the footprint, it +would be nice to edit the module name and +maybe even the ref designator.
+0 + + + + + + +5044158 +IP +Artifact Created: 199.3.246.231 +1189781352 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1794790 +1794790 +1 +761685 +100 +bennett78 +nobody +nobody +1189782392 +0 +5 +contrib: PCB123 to Kicad netlist translator +
Included is a utility I call pcb2kicad, a +PCB123 netlist to kicad translator. I +could not find a good home for this code +and perhaps this might inspire other +translators. + +I like the KiCad netlist format in that +for a ref designator includes: +footprint, ref, module name, value? and schematic symbol. + timestamp SM1208 C1 capacitor 10uf {Lib=C} + +KiCad is "si bon" to rival the >$5000US packages +out there.
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=245679&aid= +245679 +pcb2kicad.tgz +source - pcb123 2 kicad netlist converter +4694 +application/x-gzip +1189782392 +bennett78 + + + + +5044208 +IP +Artifact Created: 199.3.246.231 +1189782392 +bennett78 + + +5044209 +File Added +245679: pcb2kicad.tgz +1189782392 +bennett78 + + + + +http://sourceforge.net/support/tracker.php?aid=1798404 +1798404 +1 +761685 +100 +bennett78 +nobody +nobody +1190236031 +0 +5 +EDIF (Orcad) to KiCad Netlist +
edif.y - Revision x - Frank Bennett - Wed Sep 19 14:19:42 MDT 2 + Modified to output a KiCad Netlist + 1) find/store InstanceNameDef. ViewRef - i.e. CMP31.cap + 2) find/store Nets: NetNameDef, InstRef, PortRef + 3) sort Nets by InstRef + + Files: + makefile - Unix style makefile, runs Bison & runs gcc + edif.y - edif BNF Grammer, yylex, & main.c + PS10 - OrCad schematic in EDIF format + PS10.EDF - Original Ps10 + PS10.pdf - PS10 schematic + PS10.net - KiCad netlist output see below + batest.1 - edif test file + batest.2 - edif test file + hptest - edif test file + hptest.net - KiCad netlist output see below + bugin.net - KiCad bug, pin name truncated + bugout.net - KiCad bug, pin name truncated + + Tested under Linux and cygwin + + Install: + make + edif < PS10.EDF > PS10.net + or edif < hptest >hptest.net + + Edif Notes: + o hptest is more readable for parser debugging. This begs for + EdifBeautifier for the OrCad file + o EDIF schematic file contain + - symbol ports names, Direction, Designator + - symbol graphics, justification, orientation, origin + - sheet ports, instances, instance location, symbol reference + - sheet Netlist, wire paths + Doesn't seem to include footprint references + + TODO: + o find/output schematic drawing, symbol graphics +
+0 + + +2502331 +dickelbeck +1190517318 +
Logged In: YES +user_id=1222857 +Originator: NO + +Very promising so far.
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=246367&aid= +246367 +edif.zip +edif.y and examples +124408 +application/x-zip-compressed +1190236031 +bennett78 + + + + +5064005 +IP +Artifact Created: 199.3.246.231 +1190236031 +bennett78 + + +5064006 +File Added +246367: edif.zip +1190236033 +bennett78 + + +5077398 +IP +Comment Added: 67.64.64.34 +1190517318 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=1800554 +1800554 +1 +761685 +100 +nobody +nobody +nobody +1190546231 +0 +5 +Sugested Project Managment Enhancements +
Project window to have ability to edit the project definitions to modify directories and file names etc. This would be realy useful to allow the project launch window to be updated if the underlying files/directorires etc had been moved/modified/renamed. + +andy@kirbyand.co.uk
+0 + + + + + + +5078120 +IP +Artifact Created: 78.32.7.177 +1190546231 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1800556 +1800556 +1 +761685 +100 +nobody +nobody +nobody +1190546545 +0 +5 +Sugested Project Managment Enhancements 2 +
Project window to have the ability to delete a project either as a reference to the project directories and files or both ie delete the whole thing files as well or delete the project from the list. (pref from right clisk on project name in tree) + +andy@kirbyand.co.uk
+0 + + + + + + +5078130 +IP +Artifact Created: 78.32.7.177 +1190546545 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1800557 +1800557 +1 +761685 +100 +nobody +nobody +nobody +1190546615 +0 +5 +Sugested Project Managment Enhancements 3 +
Project window to have the ability to restore an archived project creating if not already exisiting the relevant files and directories. + +andy@kirbyand.co.uk +
+0 + + + + + + +5078133 +IP +Artifact Created: 78.32.7.177 +1190546615 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1800560 +1800560 +1 +761685 +100 +nobody +nobody +nobody +1190546850 +0 +5 +Schematic capture Symbol Managment. +
Wouldn't it be cool to have a set of capabilities/menus as part of the symbol management that linked to an online cvs/svn etc like repository to allow symbol retrieval, use, modification and submission. + +Libraries could optionally be downloaded then for standalone or the shared online library used to ensure it was always up to date and everybody's contributions to the symbols libraries would be available to all and version controlled. + +andy@kirbyand.co.uk
+0 + + +2507579 +bennett78 +1190927718 +
Logged In: YES +user_id=464167 +Originator: NO + +OR just add cvpcb footprint viewer/assignment per Ref designator and +to the symbol cache to eeSchema. Multiple instances seldon use a +different footprint per board design. + +How well does backannotate from PCBnew -> eeSchema work? for gate swap, +package part swap, netlist compare, etc. + +cvpcb would be only needed for either review or if a netlist exists +without a schematic. + +But then a standalone sym/footprint graphical Library manager would also be +useful. It's cool the KiCad design allows for symbol aliases and multiple +footprints for the same symbol. This improved design productivity.
+ + + + + + +5078142 +IP +Artifact Created: 78.32.7.177 +1190546850 +nobody + + +5097894 +IP +Comment Added: 199.3.246.231 +1190927718 +bennett78 + + + + +http://sourceforge.net/support/tracker.php?aid=1803862 +1803862 +1 +761685 +100 +bennett78 +nobody +nobody +1190928158 +0 +5 +PCBnew - Rats nest enhancement +
While manually routing traces, it would be nice +to include the new partial trace endpoint to the +rats nest display. This would help the user +visually to navigate toward the next target pad. + +This is a nice feature currently in PCB123. + +Thanks for the new, improved "selection" user interface.
+0 + + + + + + +5097924 +IP +Artifact Created: 199.3.246.231 +1190928158 +bennett78 + + + + +http://sourceforge.net/support/tracker.php?aid=1808261 +1808261 +1 +1026579 +100 +dickelbeck +nobody +nobody +1191609042 +0 +5 +Change layer of existing track +
Edit the layer that a track resides on, without having to re-create the track
+0 + + + + + + +5126180 +IP +Artifact Created: 67.64.64.34 +1191609042 +dickelbeck + + + + +http://sourceforge.net/support/tracker.php?aid=1815423 +1815423 +2 +1026580 +100 +nobody +nobody +bennett78 +1192662340 +1210343389 +5 +More efficient footprint entry +
We need a quicker way to go over a schematic and set the footprints. Right click -> Edit Component -> Edit -> Fields tab -> Footprint radiobutton is too much work. + +It would be a major step forward for EEscheema to remove this limitation. While footprints can be entered in the library editor and via cvpcb, the schematic editor is often the place where component decisions are made during the design process. + +We often use Eeschema for netlist generation without Kicad PCB and enter custom footprint names not available in Kicad libraries.
+0 + + +2541649 +ckgrier2 +1193848149 +
Logged In: YES +user_id=1921682 +Originator: NO + +This could be added to the existing hot-key list in hotkeys.cpp. Check out the forum message here: +http://tech.groups.yahoo.com/group/kicad-devel/message/480 + +Would that suffice for what you need? I usually pick a footprint for a part and then copy it wherever it is needed in the schematic. All the Fields get copied too. This makes sense if you change footprints depending on the board.
+ + +2757185 +bennett78 +1209510191 +
Logged In: YES +user_id=464167 +Originator: NO + +To close the design loop in EEschema add a BackAnnotate button: +that reads the cvpcb "stuff file" and updates the components by reference designator +with the footprint info. A placeholder(F2) already exists to hold the footprint in +the schematics file (database). + +The process for keeping the schematic up to date would be: +eeschema: +o enter starting schematic +o output initial netlist +cvpcb: +o read initial netlist +o add footprint info +o output modified netlist & stuff list (with footprint info) +pcbnew: +o the modified netlist could be used to start initial placement +o save working pcb +eeschema: +o backannotate footprint info from stuff list +o modify schematic if desired, maybe add a few footprints +o output updated netlist (containing footprints) +pcbnew: +o import updated netlist with new components, optionally removed unused parts no longer in netlist +o place new components +
+ + +2767442 +bennett78 +1210343389 +
Logged In: YES +user_id=464167 +Originator: NO + +Feature added to EEschema - svn version r1064
+ + + + + + +5171579 +IP +Artifact Created: 202.63.59.69 +1192662340 +nobody + + +5220996 +IP +Comment Added: 65.83.202.55 +1193848149 +ckgrier2 + + +5960743 +IP +Comment Added: 208.69.212.143 +1209510191 +bennett78 + + +5992192 +IP +Comment Added: 208.69.212.143 +1210343389 +bennett78 + + +5992193 +status_id +1 +1210343389 +bennett78 + + +5992194 +close_date +0 +1210343389 +bennett78 + + + + +http://sourceforge.net/support/tracker.php?aid=1818392 +1818392 +1 +761685 +100 +brummig +nobody +nobody +1193129157 +0 +5 +Metric Grid Options +
If one switches pcbnew or eeschema to metric, the grid size options are equivalent in size to user-friendly imperial options (such as 25 thousandths of an inch). The result is the list of grid sizes in metric is user-unfriendly (25 thousandths of an inch becomes 0.635mm, for example). This is particularly problematic in pcbnew, as this works with real engineering components. It should be possible to have user-friendly metric grid options, such as 1mm, 0.5mm, 0.1mm. Metric is the measurement system of choice for engineers in all but one advanced country, so kicad needs to make proper use of it. + +If one makes this step, clearly a simple imperial/metric switch is inadequate, as sometimes one might want to switch between user-friendly imperial, and user-friendly metric, and sometimes one will want to keep the grid size but just have pcbnew/eeschema display it in alternative units. There are many ways to solve that, but perhaps the simplest is to replace the current two buttons with four - one pair for switching units ('metric units/imperial units'), and one for switching grids ('metric grids/imperial grids'). Alternatively one of the two existing buttons could be 'metric units/imperial units', and the other could be 'metric grids/imperial grids'.
+0 + + +2610312 +nobody +1198406202 +
Logged In: NO + +There is more and more components with "metric" dimensions, like connectors with 2,5 mm pitch and some SMT IC. It's very useful to have a metric grid. +And in the schematic there is simply no reason to keep that stone-age units.
+ + + + + + +5189038 +IP +Artifact Created: 83.216.148.11 +1193129157 +brummig + + +5430242 +IP +Comment Added: 151.47.56.117 +1198406203 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1832573 +1832573 +1 +761685 +100 +nobody +nobody +nobody +1195143381 +0 +5 +Browsing through the files like Eagle +
It would be really good that kicad would change its main interface more like eagle, where you can browse though the projects and libraries and edit them at will. +And another feature that should be added and that is being compatible with eagle files especially to eagle's libary files, or at least being able to convert them.
+0 + + + + + + +5278511 +IP +Artifact Created: 84.151.52.48 +1195143381 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1841163 +1841163 +1 +1026579 +100 +demarchidaniele +nobody +nobody +1196361202 +0 +5 +Import/export of DXF drawings +
Import DXF: +It will be nice to import the DXF drawings of the chassis that will contain the PCB. + +Export DXF: +Some holes of PCB supports/potentiometers/etc may be exported to the mechanical CAD system.
+0 + + +3714238 +nobody +1249034432 +
Yes, I would be a great, great feature I never found in linux (and perhaps windows ?) EDA projects ... I often would use it if it would be implemented and make me save a lot of time ... + +Phil
+ + + + + + +5331238 +IP +Artifact Created: 87.2.23.137 +1196361202 +demarchidaniele + + +8526025 +IP +Comment Added: 82.251.254.159 +1249034432 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1845336 +1845336 +1 +1026580 +100 +nobody +nobody +nobody +1196925778 +0 +5 +switch to compounents +
Make possible swith to properties of other component from properties of current component. Combo list. For make easily edit properties a lot of components. Checkbox for change focus in viewly area to editing component.
+0 + + + + + + +5356110 +IP +Artifact Created: 217.150.32.243 +1196925778 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1845337 +1845337 +1 +1026580 +100 +nobody +nobody +nobody +1196925844 +0 +5 +Exec external programm/scripts +
Exec any external programm/script for other works with exported BOM list. + +This need for more simple make BOM list in HTML, XML, PDF format, for automatic calculation of budget, automatic make order in the online store and other.
+0 + + + + + + +5356113 +IP +Artifact Created: 217.150.32.243 +1196925844 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1857566 +1857566 +1 +100 +100 +scls19fr +nobody +nobody +1198508439 +0 +5 +Simulation in Kicad +
Hello, + +first thanks for Kicad. +I'm (or I was) a PSpice 9.2 user (rather old !!). +I like Kicad but unfortunately there is no easy graphical user interface for simulation. +I think you should support spice [ng-spice] or gnucap simulation with a user friendly interface (like PSpice/OrCad). + +Moreover, about simulation, one feature is very usefull for teaching digital electronic (gate, flip-flop, ...) ; this is pseudo-real time simulation... some software support this like Proteus. I really think that Kicad should also add this killer-feature. I know that it's a hard work to do... + +About simulation... maybe Kicad should also support "applications" like in DigSim +http://patrick.furon.free.fr/_elecnumerique/indexDigSim.html +so it could be possible so see both the electronic and the system that is connect to the electronic board +So it will be like the interaction between grafcet and the system with IRAI Automgen and IRIS 2D or IRIS 3D objects + + +Thanks again. + +Regards
+0 + + +2613264 +lab_tdp +1198785125 +
Logged In: YES +user_id=1965738 +Originator: NO + +Kicad is a great work but it would be complete with simulation. The best could be mixed-signal, analog AND digital in the same circuit.
+ + +2615277 +scls19fr +1198946251 +
Logged In: YES +user_id=996465 +Originator: YES + +I see on LinuxFR ( http://linuxfr.org/2007/12/24/23498.html see comments ) that Qucs will be integrated with Kicad (or Kicad will be integrated into Qucs). This is a very good idea. + +I would like to add that simulating microcontrollers (like in Proteus VSM or VMLAB for ATMEL AVR) will be very usefull. You can send the .hex file (that you get after compiling a C source code or an ASM code) to the simulated microcontroller and you start the real-time simulation. You can see blinking leds around your microcontroller, you can also use the RS232 terminal of your computer to send data to the uC, etc... + +see +about Proteus VSM http://www.labcenter.co.uk/products/vsm_overview.htm +about VMLAB http://www.amctools.com/vmlab.htm
+ + +2615282 +scls19fr +1198946781 +
Logged In: YES +user_id=996465 +Originator: YES + +See also about Qucs +http://sourceforge.net/tracker/index.php?func=detail&aid=1860457&group_id=90337&atid=593245 +
+ + +2879703 +licho1983 +1218837252 +
Logged In: YES +user_id=2063229 +Originator: NO + +Estamos con muchos deseos de ver integrado un simulador en kicad para agilizar la depuracion de circuitos. Desde ya, gracias por el excelente programa que nos brindan.
+ + + + + + +5433833 +IP +Artifact Created: 86.210.181.100 +1198508439 +scls19fr + + +5442404 +IP +Comment Added: 151.47.56.117 +1198785125 +lab_tdp + + +5450403 +IP +Comment Added: 90.50.27.237 +1198946251 +scls19fr + + +5450423 +IP +Comment Added: 90.50.27.237 +1198946782 +scls19fr + + +6371744 +IP +Comment Added: 200.16.16.13 +1218837252 +licho1983 + + + + +http://sourceforge.net/support/tracker.php?aid=1873088 +1873088 +1 +1026579 +100 +nobody +nobody +nobody +1200506218 +0 +5 +Metric coordinates inaccuracy. +
When using very little dimensions using metric units, there are inaccuracies in the value stored in pcbnew. + +For example, 0.5 mm is stored as 0.5004mm which is slightly wrong. I guess this problem comes from the fact that kicad stores the measurement values using 1/10000th of inch, but I think this measurement mechanism is obsolete and should be improved. + +Regards,
+0 + + +2635122 +linuxcart +1200506486 +
Logged In: YES +user_id=1667631 +Originator: NO + +Sorry, I'm the author of this, I think this is more a bug than a feature request. + +Would anyone be so kind to state so and point me as the author? + +Thanks.
+ + +2699123 +nobody +1204849497 +
Logged In: NO + +Who cares? It's out by 4um, which is about the wavelength of IR light. This is a non-issue and should be deleted.
+ + + + + + +5519596 +IP +Artifact Created: 87.218.11.210 +1200506218 +nobody + + +5519610 +IP +Comment Added: 87.218.11.210 +1200506486 +linuxcart + + +5728933 +IP +Comment Added: 84.92.181.41 +1204849497 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1873094 +1873094 +1 +1026579 +100 +linuxcart +nobody +nobody +1200506794 +0 +5 +ratsnets coloring/visibility. +
I would like to see some important ratsnest in a different colour or even being able to not showing them when you have ratsnest drawing enabled. + +I guess the Miscellaneous->nets list.. would be useful for it. You could add a new column that specify the visibility and/or colour and draw them in the pcb view accordingly. + +Thanks.
+0 + + +2645109 +nobody +1201193530 +
Logged In: NO + +Yes, for me it's a big enhancement, too!!! +
+ + + + + + +5519641 +IP +Artifact Created: 87.218.11.210 +1200506795 +linuxcart + + +5551435 +IP +Comment Added: 151.57.43.144 +1201193530 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1874673 +1874673 +1 +100 +100 +linuxcart +nobody +nobody +1200665157 +0 +5 +Automatic opening of gerber when invoking gerbview +
Once you open a project you can press the "schematic tool" or the "pcb editor" and the design you are working on is automatically opened. + +I would like gerber viewer worked same way. Currently if you press the gerbview button you will have no gerber shown. It would be great that rather than this, and if the gerbers are already generated, gerbview opened all of the upon invocation. + +Thanks.
+0 + + + + + + +5528606 +IP +Artifact Created: 87.218.11.210 +1200665157 +linuxcart + + + + +http://sourceforge.net/support/tracker.php?aid=1875717 +1875717 +1 +100 +100 +nobody +nobody +nobody +1200827238 +0 +5 +3D view export for case construction +
It would be nice to have an option to export the 3D view to dxf, 3ds, vrml or somthing different. This is for having a dataset for case construction. + +Br, +Oliver
+0 + + +2682051 +nobody +1203506407 +
Logged In: NO + +I second that notion. For desktop prototyping, having access to a 3D model cuts out the round-about conversions needed to get board data into a quickly millable format.
+ + +3608066 +nobody +1239281614 +
I also vote for this feature. A simple export would work for most tasks. An import of case-models for dimensional constraints would even be better :)
+ + + + + + +5533896 +IP +Artifact Created: 77.186.12.144 +1200827238 +nobody + + +5661347 +IP +Comment Added: 195.173.118.233 +1203506408 +nobody + + +8119210 +IP +Comment Added: 195.13.40.237 +1239281614 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1875718 +1875718 +1 +100 +100 +nobody +nobody +nobody +1200827508 +0 +5 +preview windows in part selection +
I am missing preview windows for symbol and module selection. + +Br, +Oliver
+0 + + + + + + +5533900 +IP +Artifact Created: 77.186.12.144 +1200827508 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1875722 +1875722 +1 +100 +100 +nobody +nobody +nobody +1200828039 +0 +5 +Instant global labels +
For large schematics with parts with many pins (controllers, etc.) it is not easy to work with global labels. Defining and connecting all of them on the root sheet results in a huge ratsnest on it. + +I think it was under PADS where i worked with a different type. There a global label was instantly global and usable on other sheets. + +Br, +Oliver
+0 + + + + + + +5533910 +IP +Artifact Created: 77.186.12.144 +1200828039 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1875723 +1875723 +1 +100 +100 +nobody +nobody +nobody +1200828208 +0 +5 +Block rotation +
I think block rotation under eeschema and pcbnew will be useful. + +Br, +Oliver
+0 + + + + + + +5533913 +IP +Artifact Created: 77.186.12.144 +1200828208 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1875724 +1875724 +1 +1026582 +100 +nobody +nobody +nobody +1200828458 +0 +5 +simple board wizard +
I think it is useful to have some help for simple boards like euro cards to have a fast setup. To create the outlines only by editing width and heights of the board. + +Br, +Oliver
+0 + + + + + + +5533915 +IP +Artifact Created: 77.186.12.144 +1200828458 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1877170 +1877170 +1 +1026579 +100 +nobody +nobody +nobody +1200999509 +0 +5 +Undo/Redo +
undo/redo method using save/load commands. Simple boards are 100Kb, complex are 2Mb*. Prerequisition is Ctrl-Z/Y hotkeys mapping to undoredo_save(), undoredoload() functions. (PLEASE add them!). + +Advantages: simplicity, infinite history, history AFTER save command** +Disadvantage: soiling hdd space* + +*50 Level undo buffer will be 10-100Mb w/o compression (compression results in 1:8-1:100 ratio for structured files like this, 1:100 for solid/tar) + +** = you could save and close a project (turn off a computer). Next week open a project and press Ctrl-Z to undo last week actions. +
+0 + + + + + + +5541390 +IP +Artifact Created: 217.26.177.9 +1200999509 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1877281 +1877281 +3 +1026579 +100 +nobody +nobody +plyatov +1201009549 +1201011059 +5 +Undo/Redo +
undo/redo method using save/load commands. Simple boards are 100Kb, complex are 2Mb*. Prerequisition is Ctrl-Z/Y hotkeys mapping to undoredo_save(), undoredoload() functions. (PLEASE add them!). + +Advantages: simplicity, infinite history, history AFTER save command** +Disadvantage: soiling hdd space* + +*50 Level undo buffer will be 10-100Mb w/o compression (compression results in 1:8-1:100 ratio for structured files like this, 1:100 for solid/tar) + +** = you could save and close a project (turn off a computer). Next week open a project and press Ctrl-Z to undo last week actions. +
+0 + + +2642465 +linuxcart +1201010718 +
Logged In: YES +user_id=1667631 +Originator: NO + +You already reported this, please report requests just once. + +Thanks.
+ + + + + + +5541847 +IP +Artifact Created: 217.26.177.9 +1201009549 +nobody + + +5541915 +IP +Comment Added: 87.218.11.210 +1201010718 +linuxcart + + +5541927 +status_id +1 +1201011059 +plyatov + + +5541928 +close_date +0 +1201011059 +plyatov + + + + +http://sourceforge.net/support/tracker.php?aid=1880640 +1880640 +1 +1026580 +100 +damunix +nobody +nobody +1201432791 +0 +5 +Text Editor +
Minor request : +I think it would be interesting to have the choise to change the text color in EEschema, and to have a style like a notepad (with a background color). I think that because I put lots of notes on my schematics, and I would like to put some "Warnings".
+0 + + + + + + +5559600 +IP +Artifact Created: 82.245.194.55 +1201432791 +damunix + + + + +http://sourceforge.net/support/tracker.php?aid=1880645 +1880645 +1 +1026579 +100 +damunix +nobody +nobody +1201433270 +0 +5 +Teardrop +
It could be interesting to have a Teardrop functionnality when connecting track to pads in pcbnew, because of the personnal soldering.
+0 + + +2912501 +m_beischer +1220810192 +
Logged In: YES +user_id=2207628 +Originator: NO + +Just adding a picture of what tear drops look like in another application. Look at the second picture at: +http://beischer.com/opencad/fillzone.htm
+ + + + + + +5559628 +IP +Artifact Created: 82.245.194.55 +1201433270 +damunix + + +6483947 +IP +Comment Added: 83.227.224.244 +1220810192 +m_beischer + + + + +http://sourceforge.net/support/tracker.php?aid=1884643 +1884643 +1 +100 +100 +terrybarnaby +nobody +nobody +1201883351 +0 +5 +Object selections +
Ability to select one or more items in a standard way +(CTRL + Button1 + mouse click and drag etc) and then +be able to perform general operations on the whole selection such as move and rotate. +Currently there is a special block move on an area +only.
+0 + + + + + + +5581568 +IP +Artifact Created: 82.152.34.172 +1201883352 +terrybarnaby + + + + +http://sourceforge.net/support/tracker.php?aid=1884644 +1884644 +1 +100 +100 +terrybarnaby +nobody +nobody +1201883399 +0 +5 +Zoom/Pan +
Zoom/Pan in smaller steps especially with mouse wheel in +eeschema and pcbnew.
+0 + + + + + + +5581578 +IP +Artifact Created: 82.152.34.172 +1201883400 +terrybarnaby + + + + +http://sourceforge.net/support/tracker.php?aid=1884649 +1884649 +1 +100 +100 +terrybarnaby +nobody +nobody +1201883584 +0 +5 +More organised placement of main function buttons +
It would be better to have a more organised placement of main function buttons in order of work +For example in eeschema group the following buttons in order "annotate, Check, Netlist, Cvpcb, Pcbnew". +This would make it more obvious for new users as to the stages required.
+0 + + + + + + +5581594 +IP +Artifact Created: 82.152.34.172 +1201883584 +terrybarnaby + + + + +http://sourceforge.net/support/tracker.php?aid=1884651 +1884651 +1 +1026580 +100 +terrybarnaby +nobody +nobody +1201883666 +0 +5 +Rubberband wires when components are moved. +
It would be good to rubber band or redraw the wires when a component or block of components is moved. Gschem does this.
+0 + + +2757798 +gouskov +1209579846 +
Logged In: YES +user_id=2076224 +Originator: NO + +I think that, more common, the integrity of conections must be preserved when a component or +block of components is moved. +
+ + +2934699 +ckgrier2 +1222224653 +
Already in EEschema and PCBnew. Use the Control key when dragging symbols or the G key to drag modules.
+ + + + + + +5581598 +IP +Artifact Created: 82.152.34.172 +1201883666 +terrybarnaby + + +5962741 +IP +Comment Added: 79.98.8.3 +1209579846 +gouskov + + +6557335 +IP +Comment Added: 68.158.4.54 +1222224653 +ckgrier2 + + + + +http://sourceforge.net/support/tracker.php?aid=1884654 +1884654 +1 +1026580 +100 +terrybarnaby +nobody +nobody +1201883738 +0 +5 +Auto shorten of wires. +
When modifying wires and joining to a wire that already exists but is to long, it would be good if the wire was automatically shortened.
+0 + + + + + + +5581605 +IP +Artifact Created: 82.152.34.172 +1201883739 +terrybarnaby + + + + +http://sourceforge.net/support/tracker.php?aid=1884658 +1884658 +1 +1026580 +100 +terrybarnaby +nobody +nobody +1201883802 +0 +5 +Better editing of wires in eeschema +
It would be good to have better editing of wires in eeschema, more like in pcbnew for tracks. For example: move/add/delete nodes and segments.
+0 + + + + + + +5581611 +IP +Artifact Created: 82.152.34.172 +1201883802 +terrybarnaby + + + + +http://sourceforge.net/support/tracker.php?aid=1884661 +1884661 +1 +100 +100 +terrybarnaby +nobody +nobody +1201883842 +0 +5 +Some more standerdised hot keys +
It would be good to have some more standerdised hot keys like CRTL-S for save in eeschema.
+0 + + +2934700 +ckgrier2 +1222224702 +
Done. They are fully customizable now.
+ + + + + + +5581614 +IP +Artifact Created: 82.152.34.172 +1201883842 +terrybarnaby + + +6557336 +IP +Comment Added: 68.158.4.54 +1222224702 +ckgrier2 + + + + +http://sourceforge.net/support/tracker.php?aid=1884663 +1884663 +1 +1026580 +100 +terrybarnaby +nobody +nobody +1201884029 +0 +5 +Better component browser +
The component browser in eeschema is poor especially when you have extensive libraries this could be improved perhaps with some hierarchy ability based on the libraries. Perhaps it would be good to have a component "type" field to group components by type (capacitors, logic, Microprocessors etc).
+0 + + + + + + +5581626 +IP +Artifact Created: 82.152.34.172 +1201884029 +terrybarnaby + + + + +http://sourceforge.net/support/tracker.php?aid=1884665 +1884665 +2 +1026579 +100 +terrybarnaby +nobody +jerryjacobs +1201884089 +1256496629 +5 +Ability to turn off layers +
It would be good to be able to select the layers viewable in pcbnew. Ideally with an on-screen list of toggle buttons that can be left on the screen.
+0 + + +2841696 +maxgaukler +1216406985 +
Logged In: YES +user_id=937039 +Originator: NO + +Please specify what exactly you want: Do you want to +- hide layers temporarily +or +- "delete" layers so that they aren't available for use (e.g. if you have a PCB with no layers inside, delete all inner layers that KiCad offers) + +Max Gaukler
+ + +3789005 + +1256402271 +
I think that Terry tell us the possibility of only view one layer at the same time, when you are working with multiple layer. Because sometimes is really difficult view your work clear with all layers available. +Thanks.
+ + +3789753 +jerryjacobs +1256496628 +
For next release Dr. Isaac wrote already patches for layer selection and since SVN 2029 added. +See http://kicad.svn.sourceforge.net/viewvc/kicad?view=rev&revision=2029 +Try latest SVN build (see main wiki) or compile yourself.
+ + + + + + +5581629 +IP +Artifact Created: 82.152.34.172 +1201884089 +terrybarnaby + + +6255219 +IP +Comment Added: 88.65.53.228 +1216406985 +maxgaukler + + +8812542 +IP +Comment Added: 84.126.155.8 +1256402271 + + + +8815661 +IP +Comment Added: 84.25.204.235 +1256496628 +jerryjacobs + + +8815662 +status_id +1 +1256496629 +jerryjacobs + + +8815663 +allow_comments +1 +1256496629 +jerryjacobs + + +8815664 +close_date +0 +1256496629 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=1884835 +1884835 +1 +1026579 +100 +terrybarnaby +nobody +nobody +1201898082 +0 +5 +Cooamnd line window +
Ability to use command line entry window to place components/tracks accurately. Ideally with some scripting language.
+0 + + + + + + +5582667 +IP +Artifact Created: 82.152.34.172 +1201898082 +terrybarnaby + + + + +http://sourceforge.net/support/tracker.php?aid=1884836 +1884836 +1 +1026579 +100 +terrybarnaby +nobody +nobody +1201898120 +0 +5 +More default track widths for first time users +
More default track widths for first time users. +Such as (8, 17, 50, 75, 100).
+0 + + +2934694 +ckgrier2 +1222224095 +
This will only clutter up the track width selection. I don't see any reason someone can't add their own width options. It takes two clicks.
+ + + + + + +5582724 +IP +Artifact Created: 82.152.34.172 +1201898120 +terrybarnaby + + +6557324 +IP +Comment Added: 68.158.4.54 +1222224095 +ckgrier2 + + + + +http://sourceforge.net/support/tracker.php?aid=1884838 +1884838 +1 +1026579 +100 +terrybarnaby +nobody +nobody +1201898177 +0 +5 +Ability to turn off "non visable" labels. +
Module labels that have been set to "no show" are still shown when viwing the PCB. This clutters the display.
+0 + + + + + + +5582794 +IP +Artifact Created: 82.152.34.172 +1201898177 +terrybarnaby + + + + +http://sourceforge.net/support/tracker.php?aid=1884839 +1884839 +1 +1026579 +100 +terrybarnaby +nobody +nobody +1201898340 +0 +5 +Better component browser +
The Module browser is very poor in pcbnew, worse than eeschema. It could be improved perhaps with a hierarchy of modules. There could be a type field in the modules to +allow selection of types such as Capacitors, Resistors, Logic, Microprocessors etc. +
+0 + + +3654895 +nobody +1242384236 +
Yes, KiCAD need better component browser i think, too !!! + +Yob. +
+ + + + + + +5582891 +IP +Artifact Created: 82.152.34.172 +1201898340 +terrybarnaby + + +8284802 +IP +Comment Added: 134.109.65.160 +1242384236 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1884841 +1884841 +1 +100 +100 +terrybarnaby +nobody +nobody +1201898401 +0 +5 +Different track joins at nodes (curved join etc) +
It would be good to have the ability to have different styles of track joins at nodes (curved join etc). +Useful when tracking differential pairs.
+0 + + + + + + +5582901 +IP +Artifact Created: 82.152.34.172 +1201898402 +terrybarnaby + + + + +http://sourceforge.net/support/tracker.php?aid=1884842 +1884842 +1 +1026579 +100 +terrybarnaby +nobody +nobody +1201898466 +0 +5 +Differential pair track layout tool. +
It would be good to have a differential pair tracking tool that would allow two tracks to be tracked simultaneously with a set gap and track width.
+0 + + +2671997 +nobody +1202843469 +
Logged In: NO + +Yes, please. +Even the upcoming v5 of Eagle will not support differential pairs :-///
+ + +2737418 +nobody +1207916797 +
Logged In: NO + +Differential pairs routing? + +Is this feature coming up?
+ + +2936400 +johnpuke +1222329211 +
Hello, + +are there any plans to support differential pairs? + +Thanks, John Puke
+ + + + + + +5582902 +IP +Artifact Created: 82.152.34.172 +1201898466 +terrybarnaby + + +5627183 +IP +Comment Added: 84.169.21.177 +1202843469 +nobody + + +5887304 +IP +Comment Added: 84.169.19.135 +1207916797 +nobody + + +6563508 +IP +Comment Added: 84.169.14.120 +1222329211 +johnpuke + + + + +http://sourceforge.net/support/tracker.php?aid=1892491 +1892491 +1 +100 +100 +nobody +nobody +nobody +1202890788 +0 +5 +Dot in library name fails! +
Library files with dots in filename (example "my.library.mod" or ".lib") is added to .pro file with right name "my.library". + +Problem: open_library() function fails because it uses a ".library" as extension. +Possible corrections: + a) write full name with "my.library.mod" to .pro file + or + b) remove "." check from open_library() function + +P.S. open_library() is a "pseudo-name".
+0 + + +2695350 +nobody +1204578742 +
Logged In: NO + +I think I have nailed it down to MakeFileName() in common/gestfich.cpp, which is being called by LoadLibraries() in eeschema/eelibs_read_libraryfiles.cpp (and probably elsewhere). + +It looks like MakeFileName() is designed to not add an extension (e.g. ".lib") if there is already an extension (i.e. any "." after the last "/"). + +I am not sure why it is like this and whether it is safe to remove it. In my first tests, it looks like all files (at least in eeschema) have no extensions, so it might be OK to remove that code.
+ + +2872350 +nobody +1218446730 +
Logged In: NO + +b) remove "." check from open_library() function + +I suggest correct parsing of file name . The file "extension" , whatever meaning that can have in cross-platform software , is that part after the last "." and not after the first. + +This is not even correct parsing in the limitted context of win32. + +This is a bug not a feature request. Please file as bug. + +
+ + + + + + +5629257 +IP +Artifact Created: 217.26.177.9 +1202890788 +nobody + + +5713555 +IP +Comment Added: 82.83.204.133 +1204578743 +nobody + + +6348225 +IP +Comment Added: 79.94.128.197 +1218446730 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1892493 +1892493 +1 +100 +100 +klui_ +nobody +nobody +1202891143 +0 +5 +Net highlight tool in eeSchema. +
Net highlight is very useful with buses and aliases in schema when wire is splitted into parts.
+0 + + + + + + +5629272 +IP +Artifact Created: 217.26.177.9 +1202891143 +klui_ + + + + +http://sourceforge.net/support/tracker.php?aid=1892773 +1892773 +2 +761685 +100 +klui_ +nobody +plyatov +1202913775 +1204570139 +5 +3D Display: Pan when mouse wheel pressed. +
It's very useful to ``pan'' scene in '3D Display' mode using pressed mouse wheel instead of separate panel arrows.
+0 + + +2693798 +diemer +1204460456 +
Logged In: YES +user_id=154672 +Originator: NO + +I have implemented that, see attached patch
+ + +2693799 +diemer +1204460477 +
Logged In: YES +user_id=154672 +Originator: NO + +Here goes the patch: + +Index: 3d-viewer/3d_canvas.cpp +=================================================================== +--- 3d-viewer/3d_canvas.cpp (Revision 821) ++++ 3d-viewer/3d_canvas.cpp (Arbeitskopie) +@@ -283,14 +283,22 @@ + + if( event.Dragging() ) + { +- /* drag in progress, simulate trackball */ +- trackball( spin_quat, ++ if (event.LeftIsDown()){ ++ /* drag in progress, simulate trackball */ ++ trackball( spin_quat, + (2.0 * g_Parm_3D_Visu.m_Beginx - size.x) / size.x, + (size.y - 2.0 * g_Parm_3D_Visu.m_Beginy) / size.y, + ( 2.0 * event.GetX() - size.x) / size.x, + ( size.y - 2.0 * event.GetY() ) / size.y ); + +- add_quats( spin_quat, g_Parm_3D_Visu.m_Quat, g_Parm_3D_Visu.m_Quat ); ++ add_quats( spin_quat, g_Parm_3D_Visu.m_Quat, g_Parm_3D_Visu.m_Quat ); ++ } else if (event.MiddleIsDown()){ ++ /* middle button drag -> pan */ ++ /* Current zoom and an additional factor are taken into account for the amount of panning. */ ++ const float PAN_FACTOR = 8.0 * g_Parm_3D_Visu.m_Zoom; ++ g_Draw3d_dx -= PAN_FACTOR * (g_Parm_3D_Visu.m_Beginx - event.GetX()) / size.x; ++ g_Draw3d_dy -= PAN_FACTOR * (event.GetY() - g_Parm_3D_Visu.m_Beginy) / size.y; ++ } + + /* orientation has changed, redraw mesh */ + DisplayStatus(); +
+ + + + + + +5630738 +IP +Artifact Created: 217.26.177.9 +1202913775 +klui_ + + +5707155 +IP +Comment Added: 82.83.204.160 +1204460457 +diemer + + +5707156 +IP +Comment Added: 82.83.204.160 +1204460477 +diemer + + +5712301 +status_id +1 +1204570138 +plyatov + + +5712302 +close_date +0 +1204570139 +plyatov + + + + +http://sourceforge.net/support/tracker.php?aid=1900617 +1900617 +1 +100 +100 +klui_ +nobody +nobody +1203808711 +0 +5 +Grids offsets. Metric VS English. +
Modern frames uses both metric dimensions (body+mounts) and inches (pins). Please add "grid offset" in "User Grid size" to greatly simplify footprint designing process.
+0 + + + + + + +5677233 +IP +Artifact Created: 89.178.163.70 +1203808712 +klui_ + + + + +http://sourceforge.net/support/tracker.php?aid=1900688 +1900688 +3 +100 +100 +klui_ +nobody +stambaughw +1203829219 +1270750121 +5 +Grids offsets. Metric VS English. +
Modern frames uses both metric dimensions (body+mounts) and inches (pins). Please add "grid offset" in "User Grid size" to greatly simplify footprint designing process.
+0 + + +3957160 +stambaughw +1270750023 +
Duplicates feature request 1900617.
+ + +3957162 +stambaughw +1270750120 +
Duplicate
+ + + + + + +5677869 +IP +Artifact Created: 89.178.163.70 +1203829220 +klui_ + + +9382217 +IP +Comment Added: 162.83.115.135 +1270750023 +stambaughw + + +9382218 +status_id +1 +1270750023 +stambaughw + + +9382219 +allow_comments +1 +1270750023 +stambaughw + + +9382220 +close_date +0 +1270750023 +stambaughw + + +9382227 +IP +Comment Added: 162.83.115.135 +1270750120 +stambaughw + + +9382228 +status_id +2 +1270750121 +stambaughw + + +9382229 +close_date +1270750023 +1270750121 +stambaughw + + + + +http://sourceforge.net/support/tracker.php?aid=1902057 +1902057 +1 +761685 +100 +klui_ +nobody +nobody +1204022721 +0 +5 +Block selection in eeSchema selects also in PCBnew. +
It's very useful when manually placing a logical group!
+0 + + + + + + +5687356 +IP +Artifact Created: 217.26.177.9 +1204022721 +klui_ + + + + +http://sourceforge.net/support/tracker.php?aid=1902854 +1902854 +1 +761685 +100 +klui_ +nobody +nobody +1204104233 +0 +5 +Block selection in eeSchema selects also in PCBnew. +
It's very useful when manually placing a logical group!
+0 + + +2783226 +cfdev +1211467994 +
Logged In: YES +user_id=1876469 +Originator: NO + +I agree with this. + +In PCBNEW, +It's will be good to show the content's block when we moving it ! + +Thanks ++
+ + + + + + +5691853 +IP +Artifact Created: 217.26.177.9 +1204104234 +klui_ + + +6039888 +IP +Comment Added: 90.52.51.69 +1211467994 +cfdev + + + + +http://sourceforge.net/support/tracker.php?aid=1905019 +1905019 +1 +1026581 +100 +elbuit +nobody +nobody +1204325440 +0 +5 +Store configuration files in .config directory under linux +
Store configuration files in .config directory under linux like the freedesktop standard: +http://standards.freedesktop.org/basedir-spec/basedir-spec-0.6.html
+0 + + + + + + +5703427 +IP +Artifact Created: 84.123.141.48 +1204325440 +elbuit + + + + +http://sourceforge.net/support/tracker.php?aid=1906962 +1906962 +1 +761685 +100 +klui_ +nobody +nobody +1204633868 +0 +5 +Selection improvement. +
Please add the following: +1. selection marquee from-left-to-right selects only 100%inside selection objects (as it now does) +2. from-right-to-left selects all overlapping objects inside selection marquee
+0 + + +2767096 +nobody +1210311009 +
Logged In: NO + +I would like to have a selection like in the Windows Explorer or Eagle, where you can add single items to the selection or remove it while holding down the the Ctrl-Key and clicking on it.
+ + + + + + +5715643 +IP +Artifact Created: 217.26.177.9 +1204633869 +klui_ + + +5990970 +IP +Comment Added: 138.246.7.133 +1210311009 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1909202 +1909202 +1 +100 +100 +nobody +nobody +nobody +1204851097 +0 +5 +Show contents of block selection while dragging +
What is says in the title really. It's a bit tricky having to guess where things are going to end up without being able to see them
+0 + + +2784055 +cfdev +1211528171 +
Logged In: YES +user_id=1876469 +Originator: NO + +I agree with this. + +In PCBNEW, +It's will be good to show the content's block when we moving it ! +
+ + + + + + +5729034 +IP +Artifact Created: 84.92.181.41 +1204851098 +nobody + + +6042084 +IP +Comment Added: 90.52.51.69 +1211528172 +cfdev + + + + +http://sourceforge.net/support/tracker.php?aid=1920376 +1920376 +1 +100 +100 +nobody +nobody +nobody +1205970758 +0 +5 +Command line utilities +
Add command line utilities for everything where it makes sense: + +Plotting, Printing, netlist generation, autorouting, conversion to pdf, ps, .... +
+0 + + +3580557 +nobody +1237330833 +
That would be really nice
+ + +3580558 +nobody +1237330916 +
That would be really nice
+ + +3580561 +nobody +1237331137 +
That would be really nice
+ + + + + + +5784957 +IP +Artifact Created: 85.178.27.18 +1205970758 +nobody + + +7935241 +IP +Comment Added: 91.150.229.252 +1237330833 +nobody + + +7935251 +IP +Comment Added: 91.150.229.252 +1237330916 +nobody + + +7935266 +IP +Comment Added: 91.150.229.252 +1237331137 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1925393 +1925393 +1 +100 +100 +nobody +nobody +nobody +1206467264 +0 +5 +hole matrix board-function in KiCad and another function. +
install a funtion that we can create a virtual hole matrix board. + +make the Programm easier for non-professionel +electronician! For example, when I would create a new electronic component it is too unclear for new user. +Please organize the function new, that new user find the function better. + +Create a function that people can simulate a board with all his function, in the PC. + +Please create a function that we can checking a complete board. + +create a function that we can simulate a IC on the board and we can programm it, too. + +Sincerely yours...
+0 + + + + + + +5812308 +IP +Artifact Created: 84.163.88.231 +1206467264 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1938219 +1938219 +1 +1026579 +100 +nobody +nobody +nobody +1207697939 +0 +5 +Export to G-Code +
Greetings, +In fact I'm very intusiast on this program, but there some issues that you need to re-think, one of them is usability, because there are some functionalities that could increase usability of this program, one is the zoom that we do with the wheel of the mouse, the steps are very big. The change should be smoother. +But what I believe it hould be a huge improvement was the export to G-code the board.
+0 + + +2821551 +lomarcan +1214820415 +
Logged In: YES +user_id=115128 +Originator: NO + +There are already some programs (even free) which generates G-code for milling PCB (and anyhow photomechanical processing is better :P) + +You can look, for example, to kcam or deskcam. + +The zoom issue is already on file :D +
+ + + + + + +5877353 +IP +Artifact Created: 87.196.203.110 +1207697939 +nobody + + +6187372 +IP +Comment Added: 88.149.185.186 +1214820415 +lomarcan + + + + +http://sourceforge.net/support/tracker.php?aid=1943010 +1943010 +1 +100 +100 +nobody +nobody +nobody +1208267315 +0 +5 +KiCAD as PortableApps application. +
Is it possible to made KiCAD "installation" compatible with PortableApps.com applications? +
+0 + + + + + + +5902096 +IP +Artifact Created: 143.183.121.4 +1208267316 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1947959 +1947959 +1 +1026579 +100 +diemer +nobody +nobody +1208788810 +0 +5 +Optical/Accoustic feedback on DRC violation +
Basically, there should be a beep/blink when a track cannot be created due to DRC violations. + + +From Users-ML: +"> > - when DRC is ON and something is not allowed it should at least sound +> > a beep or something to let user know about the problem. +> +> You mean a beep when trying to place a track that violates DRC rules (e.g. +> spacing) ? + +Exactly, for a beginner, I could not figure out why I could not lay a trace sometimes. +Later I noticed the status on a status line, but it is not obvious right away. +A beep or a highlighting of the error area would be nice (feature request)." +
+0 + + + + + + +5928737 +IP +Artifact Created: 134.169.117.46 +1208788810 +diemer + + + + +http://sourceforge.net/support/tracker.php?aid=1959203 +1959203 +1 +1026582 +100 +nobody +nobody +nobody +1210132197 +0 +5 +Pre-link between schematic symbol and footprint +
One of the wishe is "Support for including part #'s(Digikey, Mouser,etc) and price in BOM" +I agree with this approach, wouldn't put it into the package files but as a downloadable list to add to the libraries. +One condition for this is to have a default footprint for each component. KiCad does not go this way yet so I would like to suggest to have a pre-fixed footprint which is still changeable in CVPCB. + +[I am a HW and PCB designer myself and just looking for a capable but not too expensive CAD package as I just started with a small company. The work you guys did is incredible and I really hope the enthusiasm will continue + +heiko.lange@baycity-technologies.com]
+0 + + +2821547 +lomarcan +1214820146 +
Logged In: YES +user_id=115128 +Originator: NO + +I use one of the fields for saving the RS/Distrelec/whatever part number, and it comes out in the BOM if you ask for it. + +The default footprint can be done with equiv files in cvpcb or footprint filters in the library (never tried that, anyhow). + +Latest (developement only) version also support backannotating using a stuff file.
+ + + + + + +5982895 +IP +Artifact Created: 222.153.213.254 +1210132197 +nobody + + +6187354 +IP +Comment Added: 88.149.185.186 +1214820146 +lomarcan + + + + +http://sourceforge.net/support/tracker.php?aid=1962617 +1962617 +1 +1026579 +100 +blixhavn +nobody +nobody +1210623822 +0 +5 +Improved DRC +
The DRC should be able to detect annular ring width violations in vias and pads. +It would also be nice to have a check of overlapping drill holes. I have sometimes managed to place vias on pads.
+0 + + + + + + +6002382 +IP +Artifact Created: 88.90.95.148 +1210623822 +blixhavn + + + + +http://sourceforge.net/support/tracker.php?aid=1975439 +1975439 +1 +1026582 +100 +ddeeds +nobody +nobody +1211920276 +0 +5 +No-connect should color entire pad +
A no-connect pin currently indicates the no-connect with a slash (/) through the pin number. It would be preferable to color the entire pin with the no-connect color. It would also be preferable to allow the user to select the no-connect color.
+0 + + + + + + +6059820 +IP +Artifact Created: 96.226.65.105 +1211920277 +ddeeds + + + + +http://sourceforge.net/support/tracker.php?aid=1989008 +1989008 +1 +1026579 +100 +nobody +nobody +nobody +1213028271 +0 +5 +Add Assembly Drawing Layers +
When creating a new PCB footprint, there should be an assembly drawing layer available to put the actual part outline on. +Often (especially with SMT components) it is not practical to place the outline on the silk screen layer, and it would be helpful to have some component documentation to print for reference during PCB assembly.
+0 + + + + + + +6114540 +IP +Artifact Created: 63.241.173.64 +1213028272 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=1993312 +1993312 +1 +1026580 +100 +jerryjacobs +nobody +nobody +1213386742 +0 +5 +Copy multiple selected components +
It could be handy if we could select multiple components at ones and copy them. + +Greets +Jerry
+0 + + + + + + +6132790 +IP +Artifact Created: 84.25.41.149 +1213386742 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2003295 +2003295 +1 +761685 +516023 +josteinaj +nobody +nobody +1214500344 +0 +5 +Online library +
This one goes for libraries in general, whether it's a schematic, a footprint or a 3D model; + +An effective (and simple) way to build a big library of components would be to allow users to submit their creations to an online database, search the db for components, and download them. Why keep the library offline when you can have it online? (Well, of course you'll need an offline version as well, but still...)
+0 + + +2827160 +over2there +1215326570 +
Logged In: YES +user_id=1664921 +Originator: NO + +Grate idea!
+ + +3158034 +nobody +1225992054 +
Really neat :P
+ + +3953299 +thewarpi +1270473533 +
Very nice! Reduce all the double work everywhere. + +Working online is far more common and therefore I believe that the libraries should be there aswell. Maybe you could download an offline version just temporary if you need it.
+ + +3956598 +seaton +1270708114 +
I would like to see a central repository with the client build into kicad, that would allow the user to select what components they want, these would then get synced locally. + +By using existing technology, such as GIT or HG rather than SVN it would 1) allow revision management of the library, but also 2) allow different versions of existing components to be created and placed under revision control, i.e. same footprints but with pad or solder mask variations etc. + +I would also like to see integrated into the local client would be a comment or voting system so users could comment on how well the component worked, or why it didn't work for them. + +By using a centralised approach then any faulty footprints would be quickly rectified and distributed to all users.
+ + + + + + +6176642 +IP +Artifact Created: 193.71.117.211 +1214500344 +josteinaj + + +6207504 +IP +Comment Added: 217.233.235.34 +1215326570 +over2there + + +6882212 +IP +Comment Added: 91.150.229.252 +1225992054 +nobody + + +9366594 +IP +Comment Added: 90.237.202.7 +1270473534 +thewarpi + + +9380166 +IP +Comment Added: 58.6.1.177 +1270708114 +seaton + + + + +http://sourceforge.net/support/tracker.php?aid=2006617 +2006617 +1 +1026580 +100 +lomarcan +nobody +nobody +1214821629 +0 +5 +Grid reference in BOM +
It would be VERY useful in the BOM to add as a field the grid locator reference (like sheet 2, square B4). Otherwise the sheet cartouche isn't very useful as is...
+0 + + + + + + +6187439 +IP +Artifact Created: 88.149.185.186 +1214821629 +lomarcan + + + + +http://sourceforge.net/support/tracker.php?aid=2008118 +2008118 +1 +100 +100 +nobody +nobody +nobody +1214937648 +0 +5 +Need simple cluster-of-vias method +
For some surface mount power components, the manufacturer requires the designer to tie a single component pin (actually a very large pad) through a dozen or more vias to an inner layer or opposite side of the board for heat dissipation. PCBNEW 2007-11-29a makes this frustratingly difficult by deleting vias already tied in parallel to the same layers. + My interim solution for now is to define new module footprints for these power components with a multitude of pins tied to small pads, then wire each pad through a via in the pad to another layer, and finally to create zones on the component layer and inner layer that merge the pads into rectangular filled areas. This is a LOT of work, and my schematic looks weird with a huge number of pins on these components.
+0 + + + + + + +6193383 +IP +Artifact Created: 192.18.128.5 +1214937649 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2011581 +2011581 +1 +100 +100 +over2there +nobody +nobody +1215326524 +0 +5 +Funktion to add smd resistors as a bridge +
It would be great to have a function (e.g. you press b) and you are asked which type of smd resistor you want to use as a bridge. That would ease designing single layer smd layouts very much! Hope you can realize that!
+0 + + +3763939 +korp +1254234857 +
Please also consider implementing an extra option to exclude these resistor bridges from being removed on netlist re-import, when "Remove Extra Footprints" is selected.
+ + + + + + +6207503 +IP +Artifact Created: 217.233.235.34 +1215326525 +over2there + + +8718869 +IP +Comment Added: 194.71.159.2 +1254234858 +korp + + + + +http://sourceforge.net/support/tracker.php?aid=2013694 +2013694 +1 +1026579 +100 +nobody +nobody +nobody +1215539349 +0 +5 +wish list IPC-2581 compliance +
+I would like to see KiCAD conform to IPC-2581. It would be the first package to support this standard as far as I know. If picked up by the industry this standard would eliminate the need for us to enter pads. + +http://webstds.ipc.org/2581/documents/IPC-2581witham1pub.pdf
+0 + + + + + + +6217343 +IP +Artifact Created: 207.254.33.78 +1215539349 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2024791 +2024791 +1 +1026579 +516023 +nobody +nobody +nobody +1216740618 +0 +5 +3D images export, POVRay +
I think it would be nice to use POVRay instead of wings3d, just like matwei.de has done it with Eagle PCB. By the reading from the links, it seems fairly easy to do this. + +The reasons of doing this is mainly, because that an nice library already exist and that it looks very nice. Besides I think that it will make Kicad even more popular. + +Links: +http://www.matwei.de/doku.php?id=en:eagle3d:eagle3d +http://www.matwei.de/doku.php?id=en:eagle3d:documentation +http://www.matwei.de/doku.php?id=en:eagle3d:library +http://www.matwei.de/doku.php?id=en:eagle3d:gallery + +BTW: Kicad rocks!
+0 + + +2904025 +nobody +1220340200 +
Logged In: NO + +I think it could be integrated into kicad, there needs to be somebody with POVray knowledge and how to integrate it into KiCad
+ + +2904026 +nobody +1220340255 +
Logged In: NO + +I think it could be integrated into kicad, there needs to be somebody with POVray knowledge and how to integrate it into KiCad
+ + +2904027 +nobody +1220340293 +
Logged In: NO + +I think it could be integrated into kicad, there needs to be somebody with POVray knowledge and how to integrate it into KiCad
+ + +3160729 +nobody +1226137931 +
Yes, I believe so too, therefore this request. But unfortunately I am not the one for the job yet.
+ + +3508980 +nobody +1234131197 +
In addition, I think Blender would be an excellent source of models.
+ + +3508987 +nobody +1234131219 +
In addition, I think Blender would be an excellent source of models.
+ + +3508992 +nobody +1234131240 +
In addition, I think Blender would be an excellent source of models.
+ + +3509081 +nobody +1234131844 +
In addition, I think Blender would be an excellent source of models.
+ + +3509100 +nobody +1234132043 +
In addition, I think Blender would be an excellent source of models.
+ + +3509122 +nobody +1234132192 +
In addition, I think Blender would be an excellent source of models.
+ + + + + + +6268701 +IP +Artifact Created: 91.150.229.252 +1216740618 +nobody + + +6457363 +IP +Comment Added: 212.178.132.86 +1220340200 +nobody + + +6457366 +IP +Comment Added: 212.178.132.86 +1220340255 +nobody + + +6457367 +IP +Comment Added: 212.178.132.86 +1220340293 +nobody + + +6897603 +IP +Comment Added: 91.150.229.252 +1226137931 +nobody + + +7656210 +IP +Comment Added: 155.246.252.94 +1234131197 +nobody + + +7656214 +IP +Comment Added: 155.246.252.94 +1234131219 +nobody + + +7656222 +IP +Comment Added: 155.246.252.94 +1234131240 +nobody + + +7656257 +IP +Comment Added: 155.246.252.94 +1234131844 +nobody + + +7656292 +IP +Comment Added: 155.246.252.94 +1234132043 +nobody + + +7656321 +IP +Comment Added: 155.246.252.94 +1234132192 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2031726 +2031726 +1 +1026583 +516023 +nobody +nobody +nobody +1217355776 +0 +5 +CAM capabilities (PCB milling) +
The possibility to generate toolpaths for PCB milling machines (e.g. LPKF) or CNC routers (e.g. ISEL, Roland) would be desirable. + +At the moment, the only electronic CAD package that integrates this functionality is Cadsoft Eagle. Major PCB milling machine manufacturers have their own CAM packages, that take as input Gerber and Excellon files, and output the toolpaths. Eagle is limited to milling out track contours and drilling holes. Proprietary packages can also mill out (rub out) the unnecessary copper from selected areas. + +If a rubout function, as above, is provided, for usability it must be possible to select the areas where to apply it. This because rubouts are extremely demanding on machine time and tool wear, and should therefore be applied where strictly necessary only. + +The output format should be either HPGL or simple G-Code (lines only, with no arcs, and possibility to select metric or imperial G-Code, for highest compatibility) or, possibly, both, as PCB millers normally require HPGL and milling machines G-Code. + +Possibly the best tools for such integration would be Gerbview or EeSchema, with a preference for Gerbtool, as the generation of toolpath code effectively follows the generation of geometrical production data (Gerber, Excellon). + + +E-mail: giardini@btinternet.com
+0 + + + + + + +6297536 +IP +Artifact Created: 138.251.105.6 +1217355776 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2035487 +2035487 +1 +100 +100 +jerryjacobs +nobody +nobody +1217638501 +0 +5 +Auto-Refresh after draw +
Sometimes i hate it to refresh many times when drawing, maybe somewone could add a auto-refresh function ( with toggle button )
+0 + + +2899278 +nobody +1220026933 +
Logged In: NO + +Isen't that fixed in new version?
+ + + + + + +6311924 +IP +Artifact Created: 84.25.41.149 +1217638501 +jerryjacobs + + +6442722 +IP +Comment Added: 91.150.229.252 +1220026933 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2098301 +2098301 +1 +1026579 +516023 +nobody +nobody +nobody +1220777988 +0 +5 +[Enhancement] Fillzone Smoothness +
I found this on the internet: + +http://beischer.com/opencad/fillzone.htm
+0 + + +3185405 +nobody +1227563071 +
Currently implemented in svn (r1426) as polygon fill mode.
+ + + + + + +6482311 +IP +Artifact Created: 84.25.41.149 +1220777988 +nobody + + +7047337 +IP +Comment Added: 91.153.138.49 +1227563071 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2098313 +2098313 +1 +761685 +100 +nobody +nobody +nobody +1220778556 +0 +5 +Line and Cross grid +
It would be nice if there is a option to choose from different grids, dot, line, crosses. + +In PCBNEW and EESCHEMA
+0 + + + + + + +6482326 +IP +Artifact Created: 84.25.41.149 +1220778556 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2098983 +2098983 +1 +1026579 +100 +m_beischer +nobody +nobody +1220811131 +0 +5 +File driven post processing +
It would be very nice if there was a function that could read a file (unique to every board) that controls the generation of production files. + +The reason for having such function is: +- This is a very important step and it should not be done manually (more than once). +- When changing an old design it is desireble to be able to regenerate the manufacturing data with the same settings. + +The file could contain: +#Gerber settings, PCB manufacturing data +- Layers to generate +- Gerber format and other settings that can be done manually +- Settings for drill file + +#Printing and circuit board manufacturing data +- Layers to generate for printing +- Format and other stuff + +#Other settings +- Output directory +- Naming conventions etc. + +
+0 + + + + + + +6483986 +IP +Artifact Created: 83.227.224.244 +1220811131 +m_beischer + + + + +http://sourceforge.net/support/tracker.php?aid=2099036 +2099036 +1 +100 +100 +m_beischer +nobody +nobody +1220813476 +0 +5 +Unplated holes in separate drill file +
It would be very nice to have 2 drill files instead of one. The second file would contain the unplated holes. Today I don't think that KiCAD supports unplated holes at all... (please correct me if I'm wrong). Unplated holes are drilled in the last manufaturing process step, so a seperate file is desireble. + +The way around this for me is to just put unplated holes as circles in the board outline layer in the sympols that require unplated holes, but this method puts extra responsibility and manuall work on the PCB manufacturer. There is also no way to change the diameter of such a hole in the module editor (you have to create a new circle in the edge layer and delete the old one and place it on the exact same coorinate).
+0 + + + + + + +6484069 +IP +Artifact Created: 83.227.224.244 +1220813476 +m_beischer + + + + +http://sourceforge.net/support/tracker.php?aid=2130008 +2130008 +1 +1026580 +100 +brendansimon +nobody +nobody +1222428095 +0 +5 +[FEATURE-REQUEST] OS X build +
Could we please have OS X support for kicad. + +I'd like to be able to download OS X binaries, with timely releases inline with UNIX and MSW releases. + +Thanks, Brendan. +
+0 + + +3185012 +nobody +1227549009 +
2nd that.
+ + + + + + +6569353 +IP +Artifact Created: 124.168.26.242 +1222428095 +brendansimon + + +7045982 +IP +Comment Added: 76.235.68.246 +1227549009 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2211764 +2211764 +1 +1026579 +100 +lomarcan +nobody +nobody +1225457031 +0 +5 +Nonplated holes +
They could be implemented with and additional flag in the pad, together with the drill size... + +So in the excellon/drill report they would be assigned different tools and the NPTH label. + +Once declared a tool as non-plated it's trivial for the manufacturer to separate it in two. +
+0 + + + + + + +6846424 +IP +Artifact Created: 88.149.185.186 +1225457031 +lomarcan + + + + +http://sourceforge.net/support/tracker.php?aid=2211768 +2211768 +1 +1026579 +100 +lomarcan +nobody +nobody +1225457223 +0 +5 +Zone grid filling +
Sometimes a solid fill is not the right thing (tm) to do. It would be useful a cross hatched filling, specifying the hatch pitch/density. + +Something like seen in +http://www.labcenter.co.uk/products/zones.gif
+0 + + +3581559 +damunix +1237395762 +
Yeah I think that this should be in Kicad PCBNEW software. It gives a better look'n feel to the board. + +another example : http://www.adamthole.com/ee/wp-content/uploads/2007/02/tiltboard.jpg
+ + +3913172 + +1267154167 +
This feature is critical for a successful PCB layout program.
+ + + + + + +6846428 +IP +Artifact Created: 88.149.185.186 +1225457223 +lomarcan + + +7947327 +IP +Comment Added: 91.121.195.179 +1237395762 +damunix + + +9215661 +IP +Comment Added: 24.59.31.155 +1267154167 + + + + + +http://sourceforge.net/support/tracker.php?aid=2220944 +2220944 +2 +100 +100 +damunix +nobody +raburton +1225805671 +1226322713 +5 +kicad deb file +
Hi all, + +I made a deb file of the last kicad stable version for Ubuntu 64 bits desktop. + +You can download it at http://dtc.brainfault.net/kicad_20081104-1_amd64.deb + +Tell me if you have any problems with it (I think about dependencies that are not shure ) + + +damunix
+0 + + +3158031 +nobody +1225991968 +
:-) Why are you posting this under "Feature request"? Why don't you visit #kicad on freenode?
+ + +3162605 +xtronics +1226280630 +
?? the last stable release was 2008-08-25 ? + +Was there a release that missed the mailing list on yahoo?
+ + +3163049 +raburton +1226322034 +
There is no stable release 20081104. The last stable release is 20080825c. + +The latest stable release is availble from the official debian repository (inc. for amd64), which should work on Ubuntu as well. The Debian packages are pulled into Ubuntu's universe repository. + +If you want to build your own packages of svn builds I recommend you use the offical Debian build files from here: +https://svn.flexserv.de/kicad/trunk/debian/ +This has the additional benefit of finding problems in the official Debian packages in advance of a release, and in advance of them being pulled into Ubuntu. + +Richard.
+ + + + + + +6865622 +IP +Artifact Created: 195.221.233.56 +1225805671 +damunix + + +6882186 +IP +Comment Added: 91.150.229.252 +1225991968 +nobody + + +6912219 +IP +Comment Added: 63.245.153.165 +1226280630 +xtronics + + +6916328 +IP +Comment Added: 128.243.82.246 +1226322034 +raburton + + +6916396 +status_id +1 +1226322713 +raburton + + +6916397 +close_date +0 +1226322713 +raburton + + + + +http://sourceforge.net/support/tracker.php?aid=2339553 +2339553 +1 +1026579 +100 +nobody +nobody +nobody +1227549178 +0 +5 +Layer Viewing Isolation Mode +
(Searched, but unable to see if this is possible in current version). + +I would be outstanding to be able to isolate layers for viewing. This is a standard feature in Altium, and it makes routing certain areas of the board easier. + +Basically, an option to "View Selected Layer Only" in the right-click menu with a corollary "View All Layers" to return to the normal high contrast mode. + +I really wish I had this right now as I struggle with silkscreens and such. + +Thanks!!! +-Red
+0 + + +3198361 +nobody +1228293245 +
Yes, I'd even wish to have user definable layer sets, where the layouter can activate his layer sets for e.g. all layers associated with top side, or tracks & pads only, etc. + +Rob
+ + +3651058 +nobody +1241964156 +
I agree. The ability to turn off selected layers would be very nice. I started a board yesterday, and the first thing I did was create the outline. So now I have a drawing layer with dimensions that are always visible. I'd love to turn them off for a while.
+ + + + + + +7045999 +IP +Artifact Created: 76.235.68.246 +1227549178 +nobody + + +7114926 +IP +Comment Added: 83.189.111.196 +1228293245 +nobody + + +8268931 +IP +Comment Added: 72.74.211.34 +1241964156 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2394764 +2394764 +1 +100 +100 +djsbriscoe +nobody +nobody +1228556661 +0 +5 +Highlight selected nets in EEschema +
Please implement the highlighting of a selected net or multiple nets in EEschema. This will help a user to understand how a net is connected. It would be ideal if nets could be highlighted throughout the hierarchical structure of a design. +Thanks
+0 + + + + + + +7139688 +IP +Artifact Created: 213.160.109.227 +1228556662 +djsbriscoe + + + + +http://sourceforge.net/support/tracker.php?aid=2407747 +2407747 +1 +1026579 +100 +gembler +nobody +nobody +1228775412 +0 +5 +Autoscroll Zone Boundary Drawing +
Add autoscrolling to the drawing of zone boundary lines. +
+0 + + + + + + +7159465 +IP +Artifact Created: 216.239.45.4 +1228775412 +gembler + + + + +http://sourceforge.net/support/tracker.php?aid=2410898 +2410898 +1 +1026581 +100 +fransschreuder +nobody +nobody +1228818921 +0 +5 +Global library locations +
Could it be possible to have the option to have a global library location? I mean that when you add a library in schematic, that it is also there in the converter and in pcbnew? (it is all saved in the same project file, so it wouldn't be too much effort)
+0 + + + + + + +7164003 +IP +Artifact Created: 129.125.37.39 +1228818921 +fransschreuder + + + + +http://sourceforge.net/support/tracker.php?aid=2414195 +2414195 +2 +1026580 +100 +cfdev +nobody +stambaughw +1228927402 +1270749499 +5 +Improve the search fonction +
hi, + +is It possible to improve the search fonction in EESCHEMA, by peace of word, not by exact word ? + +sample: +I search in library 'PIC', result : don't found... :( +but PIC16F627 is in the library. + + +For example: + +the fonction search, will search with : +if ( m_lib->componentName.Find(wxT("PIC")) != wxNOT_FOUND ) +{ +...// OK +} +And the result of search fonction will writing in an listbox. + + + +thanks + +Cyril Frausti
+0 + + +3307198 +nobody +1231487304 +
This is already done +And you can use jokers (?, *) in names
+ + +3307273 +nobody +1231487912 +
Ok thanks, I don't know the jokers. +But the result of search is in wxMessagebox so, +if there are many components in result, the visibility is not very good.
+ + +3957150 +stambaughw +1270749499 +
New find dialog in SVN r2464 fixes this problem.
+ + + + + + +7170856 +IP +Artifact Created: 90.52.207.22 +1228927402 +cfdev + + +7399452 +IP +Comment Added: 86.219.149.61 +1231487304 +nobody + + +7399521 +IP +Comment Added: 90.52.146.141 +1231487912 +nobody + + +9382172 +IP +Comment Added: 162.83.115.135 +1270749499 +stambaughw + + +9382173 +status_id +1 +1270749499 +stambaughw + + +9382174 +allow_comments +1 +1270749499 +stambaughw + + +9382175 +close_date +0 +1270749499 +stambaughw + + + + +http://sourceforge.net/support/tracker.php?aid=2489807 +2489807 +1 +1026579 +516023 +fransschreuder +nobody +nobody +1231235842 +0 +5 +Add arcs / circles on copper layers +
Hi, + +Would it be possible to draw arcs on copper layers? + +Thanks for the nice software! + +Frans
+0 + + + + + + +7371637 +IP +Artifact Created: 129.125.37.39 +1231235842 +fransschreuder + + + + +http://sourceforge.net/support/tracker.php?aid=2493392 +2493392 +1 +1026579 +100 +dandumit +nobody +nobody +1231399444 +0 +5 +Push Aside and Springback on Routing +
a very handy and usefull functionality while routing would be "push aside" other tracks and (eventually) "spring back" . +The movie from link it's self explanatory : + +http://www.cadstarworld.com/avis/CMovie/routing.html seconds 0.59 and 03.05
+0 + + + + + + +7386765 +IP +Artifact Created: 81.12.134.7 +1231399444 +dandumit + + + + +http://sourceforge.net/support/tracker.php?aid=2494013 +2494013 +1 +1026579 +516023 +cfdev +nobody +nobody +1231427875 +0 +5 +Fill Zones Why ? +
Hello, + +why in the newest stable version of pcbnew, it's not possible to create an zone to an other Layer than copper and component ? + +Why there must attach an NET to the Zone ? + + +I use Kicad in professional midle, and I uses this very often this 2 fonctions what I said. + +It's possible to change this in the next release? + + + +Thanks +cfdev
+0 + + + + + + +7390859 +IP +Artifact Created: 90.27.240.57 +1231427875 +cfdev + + + + +http://sourceforge.net/support/tracker.php?aid=2495741 +2495741 +2 +1026580 +516023 +cfdev +bennett78 +bennett78 +1231508184 +1267319591 +5 +bill of material +
Hi, + +is it possible with an checkbox on the Bill of material windows, to choice if the value of component are on the same line with the number like orcad ? + +Example: +Quantity Reference Value FootPrint +4 C1,C2,C25,C29 100nF C0805 + +Actually: +C1 100nF C0805 +C2 100nF C0805 +C25 100nF C0805 +C29 100nF C0805 + + +it's quicker to equip pcb. + + +Thanks + +
+0 + + +3329763 +cfdev +1231746500 +
<< +Actually: +C1 100nF C0805 +C2 100nF C0805 +C25 100nF C0805 +C29 100nF C0805 +>> + +correction +<< +Currently: +C1 100nF C0805 +C2 100nF C0805 +C25 100nF C0805 +C29 100nF C0805 +>> + +Sorry
+ + +3634532 +drannou +1240681833 +
done ! +See in PCBnew in svn version
+ + +3674521 +cfdev +1244709006 +
PCBnew ? no no this fonctionality is in Eeschema, +but it is not implemented yet ?? isn't it
+ + +3915053 +bennett78 +1267319591 +
I just added an option to the BOM output format & updated the documentaion +(EEschema->Help->Contents) in SVN Revision: 2399....all parts with the same +Value are combined into a "Single Part per line" + +The only problem is figuring out what release will contain Rev 2399 if you can't +svn and build the latest code. +
+ + + + + + +7402021 +IP +Artifact Created: 90.52.146.141 +1231508184 +cfdev + + +7426314 +IP +Comment Added: 90.52.205.11 +1231746500 +cfdev + + +8212713 +IP +Comment Added: 92.135.120.54 +1240681833 +drannou + + +8364838 +IP +Comment Added: 90.52.202.205 +1244709006 +cfdev + + +9221503 +IP +Comment Added: 76.76.79.173 +1267319591 +bennett78 + + +9221504 +status_id +1 +1267319591 +bennett78 + + +9221505 +assigned_to +100 +1267319591 +bennett78 + + +9221506 +allow_comments +1 +1267319591 +bennett78 + + +9221507 +close_date +0 +1267319591 +bennett78 + + + + +http://sourceforge.net/support/tracker.php?aid=2503160 +2503160 +1 +100 +100 +nobody +nobody +nobody +1231808934 +0 +5 +Renove title block & frame +
It would be good if title block and frame could be removed, better yet fully customized (not just its lines). Often schematics are drawn to be included in a paper and then it gets in the way. Also, often custom title blocks are needed that look a bit more professional. + +Just a suggestion. + +Regards, +Joerg +joergsch@analogconsultants.com
+0 + + + + + + +7432197 +IP +Artifact Created: 75.26.171.247 +1231808934 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2505497 +2505497 +1 +1026579 +100 +spedgenius +nobody +nobody +1231884104 +0 +5 +per module layer isolation +
I would like to see the ability to isolate a layer for routing in each module. currently the only way to do that is to edit the footprint library, which means all modules with the same footprint get changed.
+0 + + + + + + +7440798 +IP +Artifact Created: 65.184.25.198 +1231884104 +spedgenius + + + + +http://sourceforge.net/support/tracker.php?aid=2508886 +2508886 +1 +1026581 +100 +randy_u +nobody +nobody +1231995547 +0 +5 +project cost +
I have recently been designing a couple of devices and using Kicad to design them; I have to say it’s been a quite enjoyable experience. This program is top quality especially considering its price. + +The most tedious part of the engineering process has been the importing of data on each part into a database or into Kicad to document the bill of materials and calculate units costs. I have probably spent more time doing that than actually designing circuits and pcbs. + +I had an idea that would make the process significantly easier and much faster but would require effort on both the developers of Kicad and parts suppliers. + +My idea is fairly simple. On each supplier part page have a link to a file, probably XML, that contains all of the data the supplier has (or wants to publish) on that part. This would require the creation of some documented, hopefully open source developed, XML structure that can be easily generated from manufacturer data or suppliers existing databases and can be imported into Kicad. The user would be able to select the part in EESchema or CVpcb (and back annotate into EESchema) to allow PCBnew to put the correct package footprint on the pcb when the netlist is read. This would allow the Bill of Materials to be more robust and the addition of a project cost sub-module in EESchema (based on user selection of quantity). + +Off the top of my head the XML structure would look something like this: + +<Manufacturer> +<Manufacturer Part Number> +<Part Group> +<Part Type> +<Part Subtype> +<Part Value> +<Mount Type> +<Package> ++<Suppliers> + <Supplier Name> + <Supplier Part Number> + +<Price> + <Qty_Start> + <Qty_End> + <Price> +<Datasheet Link> ++<Additional Specifications> + <Spec Name> + <Spec Value> + +I’m sure there’s plenty more to add to that structure and I’m pretty sure that there's plenty of people that have experience that would be beneficial to the creation of the standard structure. + +Even if the suppliers don't initially subscribe to this idea us users could create and share these XML files and hopefully this concept (open standard) would be adopted by not just Kicad but all major EDA software applications - then eventually the suppliers would come on board. +
+0 + + +3349932 +nobody +1232035877 +
To go one step further, integrate with one or more of the open source ERP/CRM systems such as Compiere.
+ + +3409728 +nobody +1232848173 +
What it is really needed is the company_part_number because this can be the index to the data base where all the other data are stored. +One of the field of the component properties should be Pno. and may be one fieeld can be Manufacturer P No. +No part should be used if does not have a company part number. For one time circuit you can use the project number followed by a sequential number. +Gianni +
+ + +3422425 +randy_u +1233074093 +
ADDITION: +I talked to Mouser and they said they would be interested in pursuing this concept.
+ + +3574845 +nobody +1237004477 +
SUre !!
+ + +3915078 +bennett78 +1267321183 +
Check out octpart.com & http://octopart.com/api/documentation. + +This solves the supplier, procurement side by specifiying the exact part of interest +but not the symbol or footprint selection for each part !
+ + + + + + +7451518 +IP +Artifact Created: 69.2.166.18 +1231995547 +randy_u + + +7457212 +IP +Comment Added: 66.162.122.39 +1232035877 +nobody + + +7533817 +IP +Comment Added: 70.20.101.22 +1232848173 +nobody + + +7557478 +IP +Comment Added: 69.2.166.18 +1233074097 +randy_u + + +7914831 +IP +Comment Added: 206.167.181.19 +1237004477 +nobody + + +9221531 +IP +Comment Added: 76.76.79.173 +1267321183 +bennett78 + + + + +http://sourceforge.net/support/tracker.php?aid=2536238 +2536238 +1 +761685 +100 +nobody +nobody +nobody +1232922935 +0 +5 +rotate key in libedit +
It would be nice if the rotate key (r) would also work in libedit. Now you need to press 'e' and choose the direction. Simply pressing 'r', just like in eeschema, works a lot quicker. + +Another suggestion: to place a pin, you first have to pick a location, then the properties dialog comes up, after pressing ok, the pin is still not placed, you have to pick the location *again*! +Why not placing the pin at the first picked location?
+0 + + +3957148 +stambaughw +1270749235 +
R key rotates drawing objects in library editor in release 20100313. The pin placement suggestion actually makes this two feature requests. If the second part is moved to a separate request, this request can be closed.
+ + + + + + +7538965 +IP +Artifact Created: 80.101.23.250 +1232922935 +nobody + + +9382162 +IP +Comment Added: 162.83.115.135 +1270749235 +stambaughw + + + + +http://sourceforge.net/support/tracker.php?aid=2540776 +2540776 +1 +1026580 +100 +randy_u +nobody +nobody +1233074687 +0 +5 +Auto ERC and Netlist Generation +
I would like an option (set via preferences; options dialog box) for EESchema automatically to perform an ERC (hidden if successful) and Netlist generation upon the exiting of EESchema - I wouldn't mind if it gives me a dialog box asking me if I am sure I want to do it - where if I select NO it will just exit. If the option is not set in then the program exits normally. + +I know ERC will fail if a component is not annotated - no need to add anything new there. If the ERC does fail the user should have the option of ignoring the failure and exiting (without updating the netlist) or aborting the exit and fixing the problem. + +I think this should be done before the save dialog.
+0 + + + + + + +7557546 +IP +Artifact Created: 69.2.166.18 +1233074687 +randy_u + + + + +http://sourceforge.net/support/tracker.php?aid=2542994 +2542994 +1 +1026580 +100 +tobias-weber +nobody +nobody +1233148072 +0 +5 +Ability to drag wires +
I like to drag existing wires in a way that connected wires drag with it. For example, I can drag parts by pressing "G" and the connected wires follow the moving part. But I cannot move/drag singe wires. I would like dragging the wires on a rectangular basis. + +That means: horizontal wires can only be dragged vertically and vertical wires can only be dragged horizontal. + +It makes the Rearrangement of parts and wires much easier. Usually when moving whole areas only a bit within EESCHEMA, wire connections break when moving and must be reconnected lateron. I'd rather drag the part and then rearrange some wire if nessecary by dragging instead of reconnecting them all. + +It also helps to move away wires when an additional wire should be added on a place where it's aleady packed. + +BTW: KICAD is an excellent project! +
+0 + + + + + + +7563142 +IP +Artifact Created: 217.5.214.130 +1233148072 +tobias-weber + + + + +http://sourceforge.net/support/tracker.php?aid=2545362 +2545362 +2 +1026581 +100 +nobody +nobody +jerryjacobs +1233232281 +1246881078 +5 +Version Management +
Guys, seriously, this thing needs some version management. I don't know how others are using KiCad but if you have multiple projects and several models/versions of projects, that in some cases depend certain versions of other projects, it's very painful to manage. +Maybe it's as simple as adding a project version number and incrementing it whenever you archive - regardless of how it's done I need some versioning support.
+0 + + +3691816 +jerryjacobs +1246881078 +
Look at GIT,Subversion,CVS
+ + + + + + +7571460 +IP +Artifact Created: 69.2.166.18 +1233232281 +nobody + + +8440173 +IP +Comment Added: 212.178.132.86 +1246881078 +jerryjacobs + + +8440174 +status_id +1 +1246881078 +jerryjacobs + + +8440175 +allow_comments +1 +1246881078 +jerryjacobs + + +8440176 +close_date +0 +1246881078 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2557155 +2557155 +1 +761685 +100 +matong +nobody +nobody +1233585544 +0 +5 +Module Editor, ruler +
Module Editor. +Please add the ruler or the information about length of graphic line, polygon etc.
+0 + + + + + + +7601961 +IP +Artifact Created: 85.128.50.246 +1233585545 +matong + + + + +http://sourceforge.net/support/tracker.php?aid=2580257 +2580257 +1 +1026579 +100 +brumbarchris +nobody +nobody +1234124716 +0 +5 +Change Layer names +
Following a discussion on the KiCAD Yahoo groups, I reached the conclusion that the sequence of layers, from top to bottom, would be as follows: + +Top Layer: Component +Next Layer: Inner_L14 +Next Layer: Inner_L13 +... +... +... +Next Layer: Inner_L1 +Bottom Layer: Copper + +This is very un-natural, as one would count the inner layers incrementally from top to bottom. Ideally, KiCAD would allow customizing layer names for a given project, but if this necessitates too much effort, then a more natural fixed layer naming scheme should be adopted, something like: + +Top Layer: Top_Copper +Next Layer: Inner1 +Next Layer: Inner2 +... +... +... +Next Layer: Inner14 +Bottom Layer: Bottom_Copper + +This should also be reflected in repositioning the layer order in the color window (attached, for reference). + +Regards, +Cristian
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=312611&aid= +312611 +layer_stack-up.PNG +layer stack-up +32477 +image/png +1234124717 +brumbarchris + + + + +7655726 +IP +Artifact Created: 212.2.180.1 +1234124717 +brumbarchris + + +7655727 +File Added +312611: layer_stack-up.PNG +1234124717 +brumbarchris + + + + +http://sourceforge.net/support/tracker.php?aid=2584336 +2584336 +1 +1026579 +516023 +cfdev +nobody +nobody +1234256302 +0 +5 +Unroute component +
Hi all, + +it's would be nice to have on right click menu (on component) "unroute component".Currently, to do this, I use the deletion of the block but it's not good for that. +(sample: popupmenu -> U10 -> Move,Drag....Unroute) + +thanks if you can do this. + +Cfdev
+0 + + + + + + +7675677 +IP +Artifact Created: 90.52.62.14 +1234256313 +cfdev + + + + +http://sourceforge.net/support/tracker.php?aid=2609766 +2609766 +1 +1026579 +100 +sebastianjardi +nobody +nobody +1234894292 +0 +5 +Not Scaled Printing in Linux, UBUNTU +
Hi: + +Second: I have found a bug in the Scale adjustment for printing in Linux, Ubuntu 8.04. + +When I try to print a PCB, it isn't print to scale 1:1, using Acurate Scale option. + +Then I use X Scale Adjust and Y Scale Adjust option to adjust the scale.After that, the Y Scale prints correct, but the X Scale don't have adjusted to X Scale Adjust value. Its seem to be adjusted to the Y Scale Adjust value. + +Thanks and Regards. + +Sebastián. +
+0 + + + + + + +7731278 +IP +Artifact Created: 79.153.201.43 +1234894292 +sebastianjardi + + + + +http://sourceforge.net/support/tracker.php?aid=2687297 +2687297 +1 +100 +100 +arius-marius +nobody +nobody +1237080965 +0 +5 +Dialog to create SVG file +
Would be nice having a file chooser being able to quickly navigate to a different folder other than the current project folder. +Also, if the file extension (*.svg) was not specified it could be appended automatically to the given file name. + +This goes for eeschema and pcbnew. + +-arius-
+0 + + + + + + +7918214 +IP +Artifact Created: 78.49.15.52 +1237080965 +arius-marius + + + + +http://sourceforge.net/support/tracker.php?aid=2689643 +2689643 +1 +100 +100 +yneko +nobody +nobody +1237270846 +0 +5 +Separate power pins +
As for logic ICs, connecting power pin onto the symbol is not suitable. Please make possible to separate power pins from their symbols, like EAGLE.
+0 + + +3665205 +daveplatt +1243643920 +
This is actually possible in kicad, although I don't think the way it's implemented is necessarily the same +as is true in Eagle. + +What you need to do, is create a component module which has two or more units... units that are *not* locked together as being identical. Draw one module unit with the logic, analog, etc. pins. Draw another unit which has just the power and ground pins, with a small rectangle symbol (e.g.) to anchor them. + +Now, to get a complete copy of the component on the board, place *two* of them. Use the "Edit component / unit" popup menu to change one of the two to "Unit B" (e.g. the one with the power pins). Now, use "Edit component / reference" on both of them, to manually annotate them with the same component name (e.g. U10). + +You can now drag U10B (e.g.), with the power pins, down to a corner of one of your sheets, placing it out of the way of your main schematic, and tie it (and other such components) to power busses. + +As an example: download the "MAXIM" library (which was converted from Eagle) and take a look at the MAX238 component. The A and B units are very different - the former has all of the data pins, and the latter has just power and ground.
+ + + + + + +7930892 +IP +Artifact Created: 203.141.143.22 +1237270846 +yneko + + +8327537 +IP +Comment Added: 204.176.49.46 +1243643921 +daveplatt + + + + +http://sourceforge.net/support/tracker.php?aid=2691772 +2691772 +1 +1026580 +100 +wolverine222 +nobody +nobody +1237382340 +0 +5 +Library refresh +
Hello, + +The kicad suite has been improving at a serious pace, and in the latest release candidate there was already a feature that is VERY handy - the "Reset to library defaults" in the component properties, despite not working correctly in the 20090216-RC6 yet. + +However, there is another feature that is related and would also be VERY helpfull. Since most of the times i edit the libraries directly in the .lib files (it's just easier to copy/paste the resistors, capacitors, etc), however i allways need to restart eeschema to reload the libraries. I believe that could be a button that would just re-read the library files. + +Thanks for the good work anyway.
+0 + + +3625046 +nobody +1240242119 +
And also the ability to reload ALL components to the library defaults would be a nice feature.
+ + + + + + +7945996 +IP +Artifact Created: 213.63.0.163 +1237382340 +wolverine222 + + +8185815 +IP +Comment Added: 213.63.0.163 +1240242119 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2728236 +2728236 +1 +100 +100 +nobody +nobody +nobody +1238763882 +0 +5 +embedded scriping +
Why not embed scripting engine (Python, Lua, Guile) ? +I think for such project is a must - develop API for all functions (common for all tools (sch,pcb,lib) - GUI, drawing primitives, etc) with binding to script engine, rewrite most functionality in higher-level language, made possibility to users to create scripts (creating sch/pcb elements, placing, routing). +Only basic primitives (line, ellipse, arc, polyline, polygon, text, group) enough for creation of any abject, complex objects can be created as group of primitives. Objects can have any number of attributes, available for user editing (coordinates, colors, layer, refdes).
+0 + + + + + + +8075067 +IP +Artifact Created: 194.187.230.100 +1238763882 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2731447 +2731447 +1 +1026579 +100 +nobody +nobody +nobody +1238860573 +0 +5 +Different clearance by trace +
Right now you can select a 'global' clearance value for track, and that is used during routing and ERC of the board. On power design there are different rules for different track, i.e. a 240 VAC track must have at least 4.8mm of clearance, which are of course too much for anything that's surface mounted (well, some inductor maybe :P) + +I'd like to see a user interface exactly like that of the track width to set the clearance for segment/track/net/everything
+0 + + + + + + +8086733 +IP +Artifact Created: 87.6.47.114 +1238860573 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2741292 +2741292 +1 +100 +100 +nobody +nobody +nobody +1239125484 +0 +5 +usability improvements to common standards +
- panning : + - 'c' key moves view center to cursor position; + - moving mouse with pressed right key does panning; +- mouse wheel : + - without pressed buttons shifts up-down; + - with 'Shift' - left-right; + - with 'Ctrl' - changes view scale; +- rotation : + - 'r' key rotates selected element/block clockwise by 45 degrees; + - 'Shift-r' rotates counterclockwise; +- scaling : + - '-'/'_' scales down; + - '='/'+' scales up; +
+0 + + +3641947 +nobody +1241103741 +
that would be very cool!
+ + +3650478 +nobody +1241843735 +
Common Standards? + +I think the mouse wheel priority without pressed key is wrong! +It should remain as it is: without pressed buttons zooms in and out of cursor position! +This is already implemented very well and is enough as it allows to get to any point very quickly! + +But lets add the following to the list: Ctrl-c, Ctrl-v, Ctrl-x for copy, paste and cut. +These of course require a standard based _Object Selection System_ where: + +The user is able to select items (in Schematic, PCB or Library editors) that then are being highlighted differently for the time they are selected! + +Ideally before selection dynamic highlighting of elements having the mouse pointer above them indicates a selectable item and it shows its selectability by some form of highlight! + +If shift or control is pressed: further refining of the selection should be possible! +If a right click is performed: access to methods of the selected objects should be given, and applied to the whole selection as applicable! + +A drag gesture should directly drag the element it is executed on +If items are selected and the drag initiates on one of the selected items these should be dragged all together. + +A right click on selected objects asks the Objects which methods can be applied all of them. + +The marque 'lasso' as it turns up currently should _only happen_ when the drag is initiated above clean deskspace (above nothing selectable)! It should not by default result in a question to move, but if a drag follows on one of the selected components the drag should be performed on all selected components! +
+ + + + + + +8105514 +IP +Artifact Created: 194.187.230.100 +1239125484 +nobody + + +8232701 +IP +Comment Added: 128.113.122.124 +1241103741 +nobody + + +8266604 +IP +Comment Added: 201.143.195.217 +1241843735 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2743328 +2743328 +1 +1026581 +100 +cfdev +nobody +nobody +1239176866 +0 +5 +Save the project as +
hi, + +it's possible to have in Kicad "Save the project and files as". + +this fonction will create an copy of the actual project and files, to an other name. + +sample: +my_project.pro +my_project.sh +my_project.bdr + +to + +my_New_project.pro +my_New_project.sh +my_New_project.bdr + +Thanks +
+0 + + + + + + +8111363 +IP +Artifact Created: 90.27.113.11 +1239176879 +cfdev + + + + +http://sourceforge.net/support/tracker.php?aid=2776401 +2776401 +2 +1026580 +100 +wolverine222 +bennett78 +bennett78 +1240242733 +1267318930 +5 +Annotation options +
It would be interesting to have an option to annotate the components in a diferent manner. +For example, include padding (R001, R002, R003), including the sheet number (R101, R201, etc) + +Currently, the only option to do this is to find the components that are annotated first and then letting them increment the numbers.
+0 + + +3655490 +nobody +1242476177 +
It is a good idea, many times I develop circuits with more than 1 sheets and its feature could help a lot. +
+ + +3915042 +bennett78 +1267318930 +
Sheets in EESchema are hierarchical, so the sugession doesn't make sense, there is no sheet 1,2,etc. +I would recommend using the find feature. + +I better request would be - next to each signal, provide a hot link to the next reference of this signal.
+ + + + + + +8185866 +IP +Artifact Created: 213.63.0.163 +1240242734 +wolverine222 + + +8289038 +IP +Comment Added: 187.10.92.142 +1242476177 +nobody + + +9221486 +IP +Comment Added: 76.76.79.173 +1267318930 +bennett78 + + +9221487 +status_id +1 +1267318930 +bennett78 + + +9221488 +assigned_to +100 +1267318930 +bennett78 + + +9221489 +allow_comments +1 +1267318930 +bennett78 + + +9221490 +close_date +0 +1267318930 +bennett78 + + + + +http://sourceforge.net/support/tracker.php?aid=2787280 +2787280 +1 +100 +100 +phili +nobody +nobody +1241533273 +0 +5 +Import/Export "dxf" for contours & drawings +
Is it possible to implement dxf import & export, particulary for contour boards and drawings ... It could be fine to have these stuff . Actually, the "plot" menu only purpose plotting to popscript, Gerber or HPGL they are very usefull format, but dxf could largely be too, particulary to develop mechanicals with 2D (or 3D ) DAO ( like Qcad for example ...) with compatibillity with electronics ... And I didn't find anything to import mechanical drawings ...
+0 + + +3667144 +nobody +1243892046 +
I second that, but while doing DXF, I'd also add an option to import raster format background (.bmp, .png, pnm, even JPEG). +I will be willing to contribute with coding if that can be done with reasonable effort. I have not looked at the code yet, so, I don't have an idea how that may fit into the existing desgn. +vleolml@gmail.com
+ + + + + + +8249366 +IP +Artifact Created: 82.250.108.40 +1241533273 +phili + + +8335322 +IP +Comment Added: 195.98.166.154 +1243892046 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2794887 +2794887 +1 +1026580 +100 +nobody +nobody +nobody +1242921753 +0 +5 +rubberband wires keeping othogonality when dragging devices +
It would be nice if when dragging a device or a wire segment in any direction , all the attached wires would extend only horizontaly and verticaly if orthogonality button is set.
+0 + + + + + + +8302677 +IP +Artifact Created: 90.4.144.48 +1242921753 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2794902 +2794902 +1 +1026579 +100 +nobody +nobody +nobody +1242922783 +0 +5 +add option "keep drill holes open" +
For hobbist that use to home made pcb with an hand drilling process, add an option to have fixed size uncoppered areas in all the drilled the pads center, (simulating drill holes on the film) + + As the copper would be etched in this unprotected area, it would help to center the drill for the manual operation + +AFAIK, this option is called "keep drill holes open" in ORCAD and is done by an external script in EAGLE
+0 + + +3704725 +nobody +1248185646 +
I agree with this - it's really difficult to drill manually a board created with Kicad, when the pads are the same size with the traces or less, or when they are embedded in a copper zone. +In CADSTAR I can solve this by selecting annulus pads (ring-shaped) instead of circle pads. This can be another option.
+ + + + + + +8302733 +IP +Artifact Created: 90.4.144.48 +1242922783 +nobody + + +8493240 +IP +Comment Added: 194.102.139.216 +1248185646 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2798092 +2798092 +1 +761685 +516023 +jerryjacobs +nobody +nobody +1243542428 +0 +5 +Zooming and Selecting Objects +
I created some movies to compare kicad vs eagle/pcb zooming. (View best with VideoLan Player) +http://www.bassmasters-heaven.nl/kicad/ + +Bad about kicad zooming: + + If cursor placed to a point and then zoom it "jumps" to the place and centers the cursor on drawing area. + + Big zonefills flash if zooming. ( Try coldfire demo ) + +Also to select a object that it will highlight like in eagle (and/or select multiple other objects (footprints,nets,etc). And then you can move it indepented from the other objects instead of irritating about move blocks.
+0 + + + + + + +8323760 +IP +Artifact Created: 84.25.219.10 +1243542428 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2802441 +2802441 +2 +1026582 +100 +over2there +nobody +jerryjacobs +1244362531 +1246878069 +5 +No single error messages any more - instead: summery +
Hi, as I use a lot of modules for my project and they have mdc-File I get an error message, that the mdc file is not found. But this forces me - when I open cvpcb - to click one million times "okay". This costs a lot of time. I would wish to have a text area where all error messages are displayed and I only need to click one time okay. +Shouldn't be a to big thing, or? + +By the way: I'm using the svn revision 1806.
+0 + + +3691333 +jerryjacobs +1246816783 +
Closed bug SVN 1871 by me
+ + + + + + +8350730 +IP +Artifact Created: 217.233.218.215 +1244362531 +over2there + + +8437683 +IP +Comment Added: 84.25.137.47 +1246816783 +jerryjacobs + + +8439971 +status_id +1 +1246878069 +jerryjacobs + + +8439972 +close_date +0 +1246878069 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2804192 +2804192 +1 +1026580 +516023 +cfdev +nobody +nobody +1244644327 +0 +5 +Copy Label +
Hi all, + +is it possible to have in the fonction of click right "copy the label" + +it's very good to avoid to make a mistakes about differents labels. + +Thanks +good day + +Cyril
+0 + + + + + + +8362261 +IP +Artifact Created: 90.52.202.205 +1244644328 +cfdev + + + + +http://sourceforge.net/support/tracker.php?aid=2804199 +2804199 +1 +1026580 +516023 +cfdev +nobody +nobody +1244644731 +0 +5 +Gaphic line discontinuous +
is it possible to have the choice between "line" "Discontinuous" "Dot" for graphical line ? +(wxSOLID , wxDOT_DASH ...) + + +thx +Cyril
+0 + + + + + + +8362283 +IP +Artifact Created: 90.52.202.205 +1244644731 +cfdev + + + + +http://sourceforge.net/support/tracker.php?aid=2804696 +2804696 +1 +1026579 +516023 +cfdev +nobody +nobody +1244710365 +0 +6 +Line To Arc +
hi, + +is it possible to transforme an Line(2pts) in Arc(3pts), Like ORCAD software. +it's an very good feature when we don't know the center of arc. +see attach file. + +thanks a lot +Cyril + +++
+0 + + +3675327 +cfdev +1244791763 +
ho, I saw this fonction in libedit !!!!!! good but, +why it's different in pcbnew ????
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=330592&aid= +330592 +arc.png + +15104 +image/png +1244710375 +cfdev + + + + +8364883 +IP +Artifact Created: 90.52.202.205 +1244710371 +cfdev + + +8364885 +File Added +330592: arc.png +1244710383 +cfdev + + +8367960 +IP +Comment Added: 90.52.202.205 +1244791763 +cfdev + + +8367991 +priority +5 +1244792347 +cfdev + + + + +http://sourceforge.net/support/tracker.php?aid=2807226 +2807226 +3 +1026580 +100 +briansidebotham +nobody +briansidebotham +1245166159 +1245166249 +5 +Relative Library path is ignored +
If when editing the Preferences->Library dialog, a relative path is used for the Default library file path, KiCad successfully navigates to the correct directory when the Add button is used to add a library. However, instead of adding the selected library name, it adds the complete file path instead. + +If the .pro preferences file is edited by hand the relative library path works fine.
+0 + + +3678261 +briansidebotham +1245166249 +
Added this to the feature tracker - was meant for the bug tracker!! +
+ + + + + + +8380470 +IP +Artifact Created: 87.74.132.43 +1245166160 +briansidebotham + + +8380477 +IP +Comment Added: 87.74.132.43 +1245166249 +briansidebotham + + +8380478 +status_id +1 +1245166249 +briansidebotham + + +8380479 +allow_comments +1 +1245166249 +briansidebotham + + +8380480 +close_date +0 +1245166249 +briansidebotham + + + + +http://sourceforge.net/support/tracker.php?aid=2810163 +2810163 +1 +1026579 +100 +reshpe63 +nobody +nobody +1245664383 +0 +5 +Clearance track-to-track, track-to-via, via-to-via +
Kicad (version 20090216) in the "Dimensions->Tracks and Vias" menu, has only one Clearance type for the ERC; is it possible to have the following clearance types: track-to-track, track-to-via, track-to-pad, via-to-via, via-to-pad, pad-to-pad?
+0 + + + + + + +8396740 +IP +Artifact Created: 87.25.117.224 +1245664383 +reshpe63 + + + + +http://sourceforge.net/support/tracker.php?aid=2810796 +2810796 +1 +1026580 +100 +hauptmech +nobody +nobody +1245749265 +0 +5 +Netlist creation uniques heirarchial annotation labels +
Trying to use two existing schematics as heirarchial sub-schematics of another design does not work. The sub-schematics already have annotation labels and PCB layouts that depend on them. + +One solution is to have the netlist generating logic add a unique letter for each subschematic.
+0 + + + + + + +8399627 +IP +Artifact Created: 118.90.106.51 +1245749265 +hauptmech + + + + +http://sourceforge.net/support/tracker.php?aid=2823288 +2823288 +1 +1026579 +100 +nobody +nobody +nobody +1247861927 +0 +5 +no hebrew +
i cant seem to write hebrew labels in the linux version
+0 + + + + + + +8482603 +IP +Artifact Created: 79.183.112.193 +1247861927 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2825238 +2825238 +1 +1026579 +516023 +cfdev +nobody +nobody +1248252878 +0 +5 +Show Layer +
Hi all, +to choice the colors to display a layer is not fast enough ! + +It's possible to have an menu with hotkey to show or not an Layer. +for example ctrl+1 show only the layer component. + +this feature is good when there is 4 or more layers...(see attach file) + +
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=336042&aid= +336042 +4layers.png + +57397 +image/png +1248252878 +cfdev + + + + +8496152 +IP +Artifact Created: 90.52.57.77 +1248252878 +cfdev + + +8496153 +File Added +336042: 4layers.png +1248252879 +cfdev + + + + +http://sourceforge.net/support/tracker.php?aid=2826465 +2826465 +1 +1026580 +100 +evbuilder +nobody +nobody +1248425788 +0 +5 +cmos4000 lib error +
4072 is listed as a dual 4-input NAND. Shoudn't this be a dual 4-input OR? +I think the 4012 is the dual 4-input NAND.
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=336371&aid= +336371 +cmos4000.lib +updated file +32803 +application/octet-stream +1248425788 +evbuilder + + + + +8503063 +IP +Artifact Created: 118.92.207.91 +1248425788 +evbuilder + + +8503064 +File Added +336371: cmos4000.lib +1248425788 +evbuilder + + + + +http://sourceforge.net/support/tracker.php?aid=2831480 +2831480 +1 +100 +100 +frohro +nobody +nobody +1249306303 +0 +5 +Graphic Text (Comment) Formatting +
Hi, + +I can't seem to make anything but a one line graphic text comment. I don't want multiple comments because They will eventually be deleted when all the issues are addressed. (I use them like sticky notes to note issues I need to address later.) Could this be added, or is there a better way to do this? + +Thanks, + +Rob
+0 + + + + + + +8534091 +IP +Artifact Created: 66.62.174.7 +1249306303 +frohro + + + + +http://sourceforge.net/support/tracker.php?aid=2832296 +2832296 +1 +1026580 +100 +nobody +nobody +nobody +1249422428 +0 +5 +Preferences Form Update +
I'd like to update the current Preferences menu into a tabbed (wxListbook) form to live in Edit->Preferences as is the norm for the majority of Linux applications I've come across. I'm willing to take this on myself and would welcome any suggestions. I've used Kicad extensively for school (schematic capture as well as PCB design and production) and want to help give back, but don't feel confident touching the more critical parts.
+0 + + +3718117 +superlou +1249423011 +
Sorry, thought I had logged in. Apparently hadn't. Does anyone know how to associate me with the above post?
+ + + + + + +8539061 +IP +Artifact Created: 67.87.133.3 +1249422428 +nobody + + +8539080 +IP +Comment Added: 67.87.133.3 +1249423011 +superlou + + + + +http://sourceforge.net/support/tracker.php?aid=2835205 +2835205 +1 +1026579 +100 +superlou +nobody +nobody +1249943856 +0 +5 +Show netnames on PCB traces +
Sorry to add to the pile of requests and it's something I'm hoping to work on in the future (but don't want to forget about it now). + +An option to show netnames on top of traces in PCBNew can help when you are routing and trying to avoid cross-talk between critical nets. Would be good to filter between user named nets and auto named nets to keep from cluttering the screen too much.
+0 + + + + + + +8555396 +IP +Artifact Created: 67.87.133.3 +1249943856 +superlou + + + + +http://sourceforge.net/support/tracker.php?aid=2836769 +2836769 +1 +761685 +100 +gregoryhicks +nobody +nobody +1250150798 +0 +5 +Front Panel Layer +
Add two front panel layers to enable silk screen and hole centers in a user defined panel. + +This could extend to sides and backs of various boxes and enclosures.
+0 + + + + + + +8564316 +IP +Artifact Created: 124.171.196.23 +1250150798 +gregoryhicks + + + + +http://sourceforge.net/support/tracker.php?aid=2839745 +2839745 +1 +1026582 +100 +nobody +nobody +nobody +1250617328 +0 +5 +Kicad Tutorial +
Much appreciated, however towards the end of the tutorial key images are missing making progress to the end difficult. Thanx
+0 + + + + + + +8583054 +IP +Artifact Created: 70.49.190.209 +1250617328 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2840152 +2840152 +2 +100 +100 +jerryjacobs +nobody +jerryjacobs +1250673424 +1257527868 +5 +Signal grouping +
Hi Jerry, + +I would have a feature request, but I don't think it's that easy. At the moment you can chose your pcb size and via size, etc. in the drop-down menu. How about grouping this pcb sizes and vias to groups, so you only have to change groups. Eg. one group "small signal" or "power signal". It would be great if I (as a user) could set, edit and delete such connection groups. For drawing pcbs i just select the group and here we go. Could this be possible? What do you think about this idea? + +Thanks +Michael
+0 + + +3799453 +jerryjacobs +1257527868 +
Work in progress -> Net classes.(design rules)
+ + + + + + +8585933 +IP +Artifact Created: 84.25.137.47 +1250673424 +jerryjacobs + + +8854788 +IP +Comment Added: 84.25.204.235 +1257527868 +jerryjacobs + + +8854789 +status_id +1 +1257527868 +jerryjacobs + + +8854790 +allow_comments +1 +1257527868 +jerryjacobs + + +8854791 +close_date +0 +1257527868 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2843726 +2843726 +1 +1026580 +100 +nobody +nobody +nobody +1251136992 +0 +5 +Highlight Nets +
It would be absolutely wonderful if there would be some highlight of nets (wires and/or busses). Viewing nets will gladly keep the program in great condition. Keep in mind this is a feature, a great feature that most programs of its kind currently have and certainly adds another professional look. Attached is an example of the project I am working on with KiCAD. + +When a user right clicks on a wire or bus shape, add one display member to the drop down box that says "View Net". +After the user clicks "View Net", all surrounding cables are highlighted with the shown picture color. + +Regards, +Juan Miguez +
+0 + + +3855931 +mrluzeiro +1263299782 +
Add highlight to PCBeditor too...
+ + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=340378&aid= +340378 +Highlight Nets.jpg +Example of Viewing Nets, highlighting wires in EESchema +64990 +image/jpeg +1251136994 +nobody + + + + +8601275 +IP +Artifact Created: 66.246.152.4 +1251136993 +nobody + + +8601276 +File Added +340378: Highlight Nets.jpg +1251136994 +nobody + + +9062435 +IP +Comment Added: 83.240.238.169 +1263299787 +mrluzeiro + + + + +http://sourceforge.net/support/tracker.php?aid=2856247 +2856247 +1 +1026579 +100 +spflanze +nobody +nobody +1252605360 +0 +5 +IPC-7351B Footprints +
I would like Pcbnew to interface directly to the database of footprints that come with the "IPC-7351B LP Viewer" available at: +http://pcbmatrix.com/Products/LPSoftware/LPViewer/ +http://landpatterns.ipc.org/default.asp +This library is vast and free. The ability to use it directly in Kicad would save a lot of labor.
+0 + + +3762903 +maxgaukler +1254121059 +
Sorry, but the library you mentioned is not compatible with kicad's license: +"This software, any upgrades, or license information cannot be distributed or re-sold. PCBM is the sole entity authorized to assign licenses to use this software."
+ + + + + + +8656285 +IP +Artifact Created: 66.92.40.104 +1252605360 +spflanze + + +8714423 +IP +Comment Added: 88.65.61.105 +1254121059 +maxgaukler + + + + +http://sourceforge.net/support/tracker.php?aid=2859048 +2859048 +2 +1026580 +100 +nobody +nobody +jerryjacobs +1252984232 +1257527600 +5 +Default reference numbering +
First, thank you for such a great project! + +I found that manually setting the reference numbers on a large number of resistors is very time consuming (in eeSchema). It would be so nice to have the +reference number of each component of an already existing type increase by one as one more component is placed in the schematic. I think most people anyway choose R1, R2, R3... by default, so why not have this simply done by default. The same can be done with transistors, Q1, Q2, ..., or capacitors, C1, C2, ... +it would save a lot of time, and I'm sure it would be a simple feature to add. + +Thank you again!
+0 + + +3799446 +jerryjacobs +1257527600 +
This is added, see the icon next to the Netlist generaton button/icon. The function is called schematic annotation (or automatic annotate)
+ + + + + + +8670292 +IP +Artifact Created: 216.99.58.108 +1252984232 +nobody + + +8854767 +IP +Comment Added: 84.25.204.235 +1257527600 +jerryjacobs + + +8854768 +status_id +1 +1257527600 +jerryjacobs + + +8854769 +allow_comments +1 +1257527600 +jerryjacobs + + +8854770 +close_date +0 +1257527600 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2865752 +2865752 +2 +1026579 +100 +nobody +nobody +jerryjacobs +1253801719 +1257527418 +5 +Undo and redo command +
It is very unsual that in win version of Kicad are no UNDO and REDO command, Please make this veru usefull function, Thanks
+0 + + +3799442 +jerryjacobs +1257527418 +
Already added. +See snapshots for testing, will be in next release.
+ + + + + + +8702814 +IP +Artifact Created: 213.155.231.66 +1253801719 +nobody + + +8854751 +IP +Comment Added: 84.25.204.235 +1257527418 +jerryjacobs + + +8854752 +status_id +1 +1257527418 +jerryjacobs + + +8854753 +allow_comments +1 +1257527418 +jerryjacobs + + +8854754 +close_date +0 +1257527418 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2865755 +2865755 +2 +1026579 +100 +nobody +nobody +jerryjacobs +1253802255 +1257527734 +5 +Group movement command +
If I use group movement command, there is inconveniently view. I see only a border of this area but I dont see devices inner this area. So I cant precioslly locate all group of parts. In EEschema is this command allright, so I dont know why is this "bug" in PCBnew
+0 + + +3799448 +jerryjacobs +1257527729 +
Added bug in TODO.txt
+ + + + + + +8702839 +IP +Artifact Created: 213.155.231.66 +1253802255 +nobody + + +8854773 +IP +Comment Added: 84.25.204.235 +1257527729 +jerryjacobs + + +8854775 +status_id +1 +1257527734 +jerryjacobs + + +8854776 +allow_comments +1 +1257527734 +jerryjacobs + + +8854777 +close_date +0 +1257527734 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2869825 +2869825 +1 +1026579 +100 +negative2404 +nobody +nobody +1254235765 +0 +5 +Internal nets in footprints +
I would be extremely useful feature to allow internal connection of pins in PCB footprint. +This would help in designing boards with devices that have internal pads connected (e.g. pusbuttons). +This would automatically solve feature request #2011581 as bridge would be a 0805/1205 footprint with internally connected pads. +Other solution would be to make the internal nets available in EESCHEMA components. +I don't know which is better or easier to implement but each have both advantages and disadvantages. +For example: +- PCB footptints shall be independent on chip type (e.g. DIP) so it would be better to have this in EESCHEMA +- EECHEMA components builds a schematic so pusbutton just connects 2 pins, but the PCB footprint consists usually of 2 pairs of connected pins so routing woule be easier if PCBNEW knows that these pins are connected. +- interconnection of pins in PCB footprints would be extremely nice because for adding a bridge, one could add a '1206 bridge' footprint and connect pins to a single net and PCB verification tool would report no error. + +If both of the ideas are implemente, there would be automatically new feature: macro circuits. One could make a set of commonly used circuits and its footprints which would speedup board design. + +It would be very kind of you if you consider the feature I have described. + +Kind regards.
+0 + + +3764535 +nobody +1254303703 +
Quick potential solution for internal nets in PCB layout could be assigning a kind of 'local net names' in each pin. e.g. assign pin1 and pin2 net name like $local_interconn would affect a connection of pin1 and 2. +I do not know whether the same solution is possible in EESCHEMA, but I think it is.
+ + + + + + +8718900 +IP +Artifact Created: 78.133.245.162 +1254235765 +negative2404 + + +8722799 +IP +Comment Added: 78.133.245.162 +1254303703 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2869830 +2869830 +1 +1026579 +100 +korp +nobody +nobody +1254235971 +0 +5 +Option for other origin than the fixed page origin +
It would be nice with an option in PCBNEW to relate to the origin set by "Offset adjust for drill and place files." or the latest relative coordinates reset instead of only the fixed page origin. It is useful especially when moving components by right clicking it, Footprint (Component), Edit. And also when editing the position, or start and end of graphical elements like lines, arcs etc.
+0 + + + + + + +8718909 +IP +Artifact Created: 194.71.159.2 +1254235972 +korp + + + + +http://sourceforge.net/support/tracker.php?aid=2875556 +2875556 +2 +1026580 +100 +nobody +nobody +jerryjacobs +1255077632 +1257527038 +5 +DragnDrop between windows +
There should be the ability to choose parts or the whole drawing and transfer it via Drag&Drop to another EESchema-Window. That would make re-using of former drawings more easy.
+0 + + +3799437 +jerryjacobs +1257527038 +
Added in TODO.txt
+ + + + + + +8753536 +IP +Artifact Created: 193.174.73.57 +1255077632 +nobody + + +8854728 +IP +Comment Added: 84.25.204.235 +1257527038 +jerryjacobs + + +8854729 +status_id +1 +1257527038 +jerryjacobs + + +8854730 +allow_comments +1 +1257527038 +jerryjacobs + + +8854731 +close_date +0 +1257527038 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2885937 +2885937 +2 +100 +100 +nobody +nobody +jerryjacobs +1256480473 +1257526931 +5 +Areas of improvements +
I am new to KiCAD, and maybe some of the futures were not discovered yet, but in my opinion it would be nice if the following areas are improved: + +EESchema: +- When in “Place a component†mode, there is not auto scrolling (up, down) with the mouse +- Interface for selecting components, ports etc. It is a bit inconvenient; every time a component is needed a menu appears and requires searching for a component. +- Some of the commands like Netlist generation are not showed on the menu + +CVpcb: +- Preview of the assigned to a component package + +PCBnew: +- Edit: Undo/Redo +- There seems to be some issues with the mouse-autoscroll in different modes. +- Selection on component just by clicking on it +- Move a component just by grabbing it with the mouse +- Mode for showing all netlist connections +- Cursor shape, just arrow is fine sometimes +- When selecting area might be useful not the menu move block to appear, what if it is intended to delete the selection +
+0 + + +3799435 +jerryjacobs +1257526931 +
Added in TODO.txt +Thank you for your request!
+ + + + + + +8815249 +IP +Artifact Created: 212.25.47.124 +1256480474 +nobody + + +8854713 +IP +Comment Added: 84.25.204.235 +1257526931 +jerryjacobs + + +8854714 +status_id +1 +1257526931 +jerryjacobs + + +8854715 +allow_comments +1 +1257526931 +jerryjacobs + + +8854716 +close_date +0 +1257526931 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2886974 +2886974 +2 +1026579 +516023 +nobody +nobody +jerryjacobs +1256632108 +1257526480 +5 +Undo +
At least a one-level undo function is needed. Could be implemented using autosave (backup) for the time being.
+0 + + +3799429 +jerryjacobs +1257526480 +
Done for next release, in SVN !
+ + + + + + +8820037 +IP +Artifact Created: 213.64.86.172 +1256632108 +nobody + + +8854687 +IP +Comment Added: 84.25.204.235 +1257526480 +jerryjacobs + + +8854688 +status_id +1 +1257526480 +jerryjacobs + + +8854689 +artifact_group_id +100 +1257526480 +jerryjacobs + + +8854690 +allow_comments +1 +1257526480 +jerryjacobs + + +8854691 +close_date +0 +1257526480 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2886977 +2886977 +2 +1026580 +100 +nobody +nobody +jerryjacobs +1256632365 +1257526319 +5 +Search in libraries +
While editing symbols, a search function that shows in what lib a symbol exists, would be desirable. + +Also, the text "OK" in the EESCHEMA add component dialog should rather say "search/ok" since it's used for searching.
+0 + + +3799423 +jerryjacobs +1257526319 +
Added in TODO list
+ + + + + + +8820046 +IP +Artifact Created: 213.64.86.172 +1256632365 +nobody + + +8854669 +IP +Comment Added: 84.25.204.235 +1257526319 +jerryjacobs + + +8854670 +status_id +1 +1257526319 +jerryjacobs + + +8854671 +allow_comments +1 +1257526319 +jerryjacobs + + +8854672 +close_date +0 +1257526319 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2890612 +2890612 +2 +1026579 +100 + +nobody +jerryjacobs +1257157587 +1257527268 +5 +footprint in automatic placement file +
We are an electronics company and are trying to switch from our CAD program to kicad. We strongly miss the footprint name for each components in the automatic placement files, as our pick & place needs it to work properly.
+0 + + +3799441 +jerryjacobs +1257527268 +
Added in TODO.txt
+ + + + + + +8839463 +IP +Artifact Created: 80.33.161.202 +1257157587 + + + +8854741 +IP +Comment Added: 84.25.204.235 +1257527268 +jerryjacobs + + +8854742 +status_id +1 +1257527268 +jerryjacobs + + +8854743 +allow_comments +1 +1257527268 +jerryjacobs + + +8854744 +close_date +0 +1257527268 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2909570 +2909570 +1 +1026580 +100 +stefanl38 +nobody +nobody +1260102963 +0 +5 +much more efficient way to add new devices on a schematic +
I would like to have the following feature in the schematic symbol placing + +ONE click on add device opens the library-browser where ALL symbols are listed as small pictures. (Don't tell me this would use to much memory). +The I can do drag and drop symbols directly in the schematic window. + +Or second best solution to have e second button "add n devices" opens the library browser and the software behaves like this: + +a double-click on the name OR the picture closes automatically close the browser window I can place the device on the schematic and +the browser-window opens automatically again. +Doubleclick for choose - leftclick for placing +Doubleclick for choose - leftclick for placing +Doubleclick for choose - leftclick for placing +etc. etc. +now I'm forced to do the following +1) click on schematic: window choose opens +2) Click on librarybrowser +3) Click on device name +4) Click on add to schematic +5) place device on schematic + +1) click on schematic: window choose opens +2) Click on librarybrowser +3) Click on device name +4) Click on add to schematic +5) place device on schematic + +1) click on schematic: window choose opens +2) Click on librarybrowser +3) Click on device name +4) Click on add to schematic +5) place device on schematic +etc. etc. + +hey that's uncomfortable like hell !! I'm wondering that nobody complaint about that ?!! + +OK guys I estimate changing this takes 1-2 hours. When do you have time to insert that ? + +best regards + +Stefan
+0 + + +3830779 +vovanium +1260373839 +
I would better like to use "palette" side panel like one in QCAD. :)
+ + + + + + +8948960 +IP +Artifact Created: 88.202.126.34 +1260102963 +stefanl38 + + +8959005 +IP +Comment Added: 195.208.204.245 +1260373839 +vovanium + + + + +http://sourceforge.net/support/tracker.php?aid=2910567 +2910567 +1 +1026580 +100 +nobody +nobody +nobody +1260266240 +0 +5 +Copy blocks from one file to another +
I can't find an easy way to copy/paste blocks from one schematic.sch to another-schematic.sch. + +could be cool to CTRL+C/CTRL+V between .sch files or to can import a schematic + +Maybe this is already possible, but it is not clear in the documentation + +regards, + +Marc BERLIOUX
+0 + + +3926095 +ultim +1268277825 +
+1 vote to copy blocks between sheets and schematics
+ + + + + + +8954372 +IP +Artifact Created: 81.56.216.19 +1260266240 +nobody + + +9269875 +IP +Comment Added: 193.170.138.226 +1268277826 +ultim + + + + +http://sourceforge.net/support/tracker.php?aid=2918627 +2918627 +1 +100 +100 +nobody +nobody +nobody +1261396160 +0 +5 +Block operations on one side only +
Unless I've missed something, block operations work on all layers at the same time. That makes the block operations useless. Wouldn't it be better if the only layers affected, were the ones that are currently visible?
+0 + + + + + + +8991238 +IP +Artifact Created: 213.64.86.172 +1261396160 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2918944 +2918944 +1 +1026579 +100 +nobody +nobody +nobody +1261432223 +0 +5 +Edit solder paste shape/size in module editor +
One major feature that kicad lacking is the capability to edit Solder Paste layer. + +As parts size shrinks, simply making solder paste equal to pad size in general is not sufficient for manufacturing. +Different part manufacturer may put different recommendation on relationship of pad size and solder paste size. This is especially true for the QFN package where the center heat sink in general needs a low percentage of solder paste coverage to prevent the chip from floating to one side during re-flow process. Also consider the poor flowing characteristic of no-lead solder paste, simply globally shrink the solder paste using other tools won't always work either. + +A feature to edit the shape of solder paste of each module in Module editor is needed. It may implemented by using polygon, circle or etc to define the area for solder paste.
+0 + + + + + + +8993056 +IP +Artifact Created: 63.240.163.139 +1261432223 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2922241 +2922241 +1 +1026579 +100 +opendous +nobody +nobody +1262004234 +0 +5 +Matched Length Traces +
Add the ability to modify the length of a trace segment when traces need to be length matched. + +How I see development proceeding: + +1) alter the microwave fixed length tool to support arbitrary dimensions (no size ratio restriction) +2) alter the microwave fixed length tool to output traces instead of pads +3a) move the above functionality to the track right-click menu so that any track segment can have its length altered +3b) add a secondary "trace clearance" option so that the designer can allow for trace length matching. Normal trace clearance uses a solid line so the secondary trace clearance could use a dashed line. +
+0 + + + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=357403&aid= +357403 +MLT_Test.tar.bz2 +An example design created with kicad-2009-02-16-final. Uses the microwave line tool to match trace lengths. +3100 +application/octet-stream +1262419981 +opendous + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=357404&aid= +357404 +MatchedLengthTraces-Example.jpg +Picture of the design in MLT_Test.tar.bz2 +27870 +image/jpeg +1262420029 +opendous + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=357405&aid= +357405 +MatchedLengthTraces-MLT-Clearance.jpg +A secondary "trace clearance" option would make room for trace length matching. +53051 +image/jpeg +1262420079 +opendous + + +http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=357406&aid= +357406 +MatchedLengthTraces-SegmentExtensionExample.jpg +Any trace segment can be "extended" to match length with other traces. +15778 +image/jpeg +1262420146 +opendous + + + + +9008141 +IP +Artifact Created: 216.221.38.241 +1262004235 +opendous + + +9032961 +File Added +357403: MLT_Test.tar.bz2 +1262419981 +opendous + + +9032963 +File Added +357404: MatchedLengthTraces-Example.jpg +1262420029 +opendous + + +9032964 +File Added +357405: MatchedLengthTraces-MLT-Clearance.jpg +1262420079 +opendous + + +9032965 +File Added +357406: MatchedLengthTraces-SegmentExtensionExample.jpg +1262420146 +opendous + + + + +http://sourceforge.net/support/tracker.php?aid=2922245 +2922245 +1 +1026579 +100 +opendous +nobody +nobody +1262004551 +0 +5 +Component Style Vias +
Add the ability to create vias that behave like components. + +When routing by hand it helps to plan via placement. This is much easier when your vias behave like normal 1-pin components. + +An option could exist to then delete all non-connected vias once layout is complete.
+0 + + + + + + +9008149 +IP +Artifact Created: 216.221.38.241 +1262004551 +opendous + + + + +http://sourceforge.net/support/tracker.php?aid=2929409 +2929409 +1 +1026580 +100 +peteb6 +nobody +nobody +1263150553 +0 +5 +PAN function +
There doesn't seem to be any PAN function in editing schematics? +All CAD programs I've ever used have zoom and pan. +These two are the most frequent things I use. +PAN functionality would be a major improvement over having to use scroll bars. +Thanks +
+0 + + + + + + +9056492 +IP +Artifact Created: 71.164.23.220 +1263150554 +peteb6 + + + + +http://sourceforge.net/support/tracker.php?aid=2932891 +2932891 +1 +1026579 +100 +nobody +nobody +nobody +1263565470 +0 +5 +Plot several copies of board in single PostScript sheet +
I'm making my pcb's with toner tranfser method and I'd like to have an ability to print several copies of board onto single sheet of paper.
+0 + + + + + + +9074317 +IP +Artifact Created: 95.56.69.159 +1263565471 +nobody + + + + +http://sourceforge.net/support/tracker.php?aid=2938296 +2938296 +1 +1026580 +100 +radioguy00 +nobody +nobody +1264301278 +0 +5 +Wider Pane in dialog boxes to display Library path +
The pame where library are listed (for example when browsing library) is too narrow and cannot be widened to see the full library path. This is especially a problem when there is a mix of libraries in different directory. Suggestion is to be enable to drag the separator bewteen fiedl to see the full path and save the new width for a later opening of the same dialog box.
+0 + + + + + + +9102038 +IP +Artifact Created: 216.246.120.157 +1264301278 +radioguy00 + + + + +http://sourceforge.net/support/tracker.php?aid=2952118 +2952118 +1 +1026579 +100 +brummig +nobody +nobody +1266246004 +0 +5 +Arcs in Gerbers +
Arcs are plotted in Gerbers as straight lines, but the number of lines is too small, resulting in visibly notchy board edges. Could the number of lines be increased, please? Ideally the number of straight lines should be user-configurable, of course, but just a significant increase in the hard-coded number would be very welcome.
+0 + + + + + + +9180319 +IP +Artifact Created: 83.216.148.11 +1266246004 +brummig + + + + +http://sourceforge.net/support/tracker.php?aid=2952227 +2952227 +1 +1026579 +100 +mrluzeiro +nobody +nobody +1266256580 +0 +5 +Add custom track and vias +
The custom track and vias dialog must be improved... also the possibilite to set a custom value while editing.. +
+0 + + + + + + +9180896 +IP +Artifact Created: 85.241.153.82 +1266256581 +mrluzeiro + + + + +http://sourceforge.net/support/tracker.php?aid=2957135 +2957135 +1 +1026579 +100 +nobody +nobody +nobody +1266921739 +0 +5 +3D export +
3D export for other CAD tools
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2957383 +2957383 +1 +1026580 +516023 +nobody +nobody +nobody +1266952959 +0 +5 +Remember last choicen sheet size in schematic editor +
Dear Mr. Jacobs, + +on the website http://iut-tice.ujf-grenoble.fr/cao/AUTHORS.txt I found your name and I was wondering if you could help me. +Either yourself of direct me to some one who may be able to answer my questions. + +Our company recently started using KiCad as an EDA tool. +If I start Eeschema application I find an A4 template in which I can enter my schematic. + +Is it possible to change this A4 template to an A3 size page ? + +Thanks in advance for your support. + + +kind regards + + +Dominicus Erens +Quantified Quality within reach + + +Chief EMC Engineer +Electronic Expertise \ EMC
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2959522 +2959522 +1 +1026579 +100 +nobody +nobody +nobody +1267175889 +0 +5 +Errors of translation +
In Russian PCBnew +1) Grammatics error in button ==To execute verification of planning rules===. +2) If select English language, but text of the buttons is in Russian language
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2959531 +2959531 +1 +100 +100 +nobody +nobody +nobody +1267176090 +0 +5 +New function KiCad (delete project) +
In main menu of KiCad to add a new function ===File - to Delete a project=== (delete file *.pro)
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2959619 +2959619 +1 +1026579 +100 +alidoig +nobody +nobody +1267188934 +0 +5 +Place multiple pads, based on their pitch +
Rather than placing new module pads individually, could there be an option to have the module editor place multiple pads, offset from each other by the same pitch (in X an Y), with the pin number auto incremented for each? + +This would make it a lot easier to create large parts, and should be much less prone to mistakes. I have had the pleasure of using this feature in another layout tool, and was seriously impressed by it. + +Thanks + +
+0 + + + + + + +9216817 +IP +Artifact Created: 92.24.45.200 +1267188935 +alidoig + + + + +http://sourceforge.net/support/tracker.php?aid=2959967 +2959967 +1 +1026582 +100 +paulgittings +nobody +nobody +1267242491 +0 +5 +Add splitter bar. +
It should be possible to resize the footprint listing pane in the main frame of CVPCB - splitter bar/sashwindows.
+0 + + + + + + +9218929 +IP +Artifact Created: 211.30.110.233 +1267242492 +paulgittings + + + + +http://sourceforge.net/support/tracker.php?aid=2959968 +2959968 +1 +1026582 +100 +paulgittings +nobody +nobody +1267242638 +0 +5 +CVPCB context menu +
It would be useful to have a context menu in CVPCB, with an option to view footprint (personal thing I dislike toolbars for common actions much prefer right click context menus).
+0 + + + + + + +9218936 +IP +Artifact Created: 211.30.110.233 +1267242638 +paulgittings + + + + +http://sourceforge.net/support/tracker.php?aid=2959969 +2959969 +1 +1026581 +100 +paulgittings +nobody +nobody +1267242792 +0 +5 +Library and footprint manager +
It would be useful if a library manager and a footprint manager could be accessed from kicad without the need to run one of the sub programs. The managers should allow for the editing, browsing of the relevant content.
+0 + + + + + + +9218937 +IP +Artifact Created: 211.30.110.233 +1267242792 +paulgittings + + + + +http://sourceforge.net/support/tracker.php?aid=2959970 +2959970 +1 +100 +100 +paulgittings +nobody +nobody +1267243156 +0 +5 +Re-order library buttons +
In both EEschema and PCBnew when setting library preferences the user is warned that the order of active libraries is important. However, there is no obvious way for the user to change the order. There should be "up", "down" buttons which activate when the user selects an active library in the list, clicking on the button will move the library in the list. + +Also, it would be useful if the dialog was expanded to show a listing of what was in the selected library. +
+0 + + + + + + +9218949 +IP +Artifact Created: 211.30.110.233 +1267243156 +paulgittings + + + + +http://sourceforge.net/support/tracker.php?aid=2961557 +2961557 +1 +1026579 +100 +nobody +nobody +nobody +1267482671 +0 +5 +Portuguese Translation errors +
1) Portuguese translaton errors on the Layers Box. +2) Changing language to English and still displays in Portuguese some of the layers
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2962280 +2962280 +1 +1026579 +100 +nobody +nobody +nobody +1267575909 +0 +5 +PCBnew Assign Ratsnest Colors to Net Classes. +
1. +Possiblity to assign a Ratsnest Colour to a Net Class. +Multiple colors allow a much better view of different (critical) Net Classes during module placement and during adding tracks. + +2. +Possibility (check-box?) for each Net Class, to DISABLE displaying the ratsnest for that Net Class. +This allows to unclutter the ratsnest on dense pcb design. + +3. +Possibility (click-button?) to uncheck ALL, so the ratsnest is displayed for all Net Classes.
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2963755 +2963755 +1 +1026580 +100 +nobody +nobody +nobody +1267741823 +0 +5 +Wizard for make Component +
Something similar (or better!) than this: +http://kicad.rohrbacher.net/quicklib.php
+0 + + +3953292 +thewarpi +1270473058 +
I would be nice to have a similar feature as Altium Designer with their IPC footprint wizard: http://wiki.altium.com/download/attachments/3080430/image028.jpg +1. Select package type: BGA, DPAK, SOIC, SOP... +2. Enter dimensions which is unique for that package (shown in the picture above) +3. Voila, you have the component with the exact dimensions.
+ + + + + + +9366578 +IP +Comment Added: 90.237.202.7 +1270473058 +thewarpi + + + + +http://sourceforge.net/support/tracker.php?aid=2964095 +2964095 +1 +1026580 +100 +mrluzeiro +nobody +nobody +1267783197 +0 +5 +Select multiple libs in Library editor to be removed +
If I load a lot of libs then if i need to remove,it can only be done one by one. +There should be a way of selected multiple libs to remove.
+0 + + + + + + +9240477 +IP +Artifact Created: 82.154.249.123 +1267783198 +mrluzeiro + + + + +http://sourceforge.net/support/tracker.php?aid=2971149 +2971149 +1 +100 +100 +nobody +nobody +nobody +1268730673 +0 +5 +Copy and placement multiple pcb/gerber in 1 pcb/gerber +
I would like to have a means to build ready-made cards to order one file. + +This situation arises when the project consists of several small boards. +For each file, manufacturers are taking the money. It pays off when a large number of boards, and if necessary a prototype or one or two products, it becomes very expensive. + +Perhaps for this function is better to add a fifth button KiCad "GERBER EDIT". + +The order of being able to be as follows: + +1. Developing its own or taken from the internet printed circuit boards, which should make. + +2. Then set the size of the workpiece. Consistently open the files with the boards and placed in the right quantity to the workpiece. The boards can move, delete, add to obtain the desired location. It will automatically be stored, the specified minimum distance between the boards. + +3. The boards can be represented conventionally in the form of rectangles. To mark the differences between their colors and / or numbers. Ie problem when linking would be to put the rectangles in the workpiece contour with minimal voids between them. Need the ability to move, resize the workpiece. + +4. Then the contours of each board avtomatichski erased and replaced with rectangular cutouts drawn given the minimum width for subsequent milling. + +5. A final automatic control clearances, etc. + +6. Forming files for the order in production. + +7. After manufacturing the workpiece is mechanically separated into individual boards.
+0 + + + + + + +9289278 +summary +COPY AND PLACEMENT MULTIPLE PCB/GERBER IN 1 PCB/GERBER +1268733578 +jerryjacobs + + + + +http://sourceforge.net/support/tracker.php?aid=2976031 +2976031 +1 +1026579 +100 +nobody +nobody +nobody +1269451741 +0 +5 +transformation track of several segments in one +
Very convenient to shift the track to the conservation angle. But if the track consists of several segments, this function does not work. + +I wish that some segments are automatically converted into one. + +Thank you.
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2980517 +2980517 +1 +1026579 +100 +nobody +nobody +nobody +1270124582 +0 +5 +Export HD bitmaps from 3Di +
Hi guys, + +it's could be cool to allow user to export bigger bitmap of 3D view. + +Actually, the bitmap is "just" a screen snap-shot, so the resolution is quite poor in many cases and not printable at all. + +Another solution is to allow user to save the 3D scene as a free 3D tools file (ie : Blender, POV ...ect...). + +In any case : thanks for this fantastic piece of code !
+0 + + +3950015 +jerryjacobs +1270125390 +
To enable such option to export to POV, Blender or other 3D format takes some time and effort. Maybe some other people will volunteer us and make something nice :-). + +Good luck, +Jerry
+ + +3950053 +sebc26 +1270127917 +
And about a bitmap file with bigger resolution ? + +It could be great to have a printable bitmap of 3D view ! + +Thanks.
+ + + + + + +9353135 +IP +Comment Added: 212.178.132.86 +1270125391 +jerryjacobs + + +9353294 +IP +Comment Added: 82.244.110.178 +1270127917 +sebc26 + + + + +http://sourceforge.net/support/tracker.php?aid=2981608 +2981608 +1 +761685 +100 +jerryjacobs +nobody +nobody +1270320252 +0 +5 +Library dialog alphabetical list +
The enhancement of the library dialog is much better, it would even better if it lists the libraries in alphabetical order.
+0 + + +3954008 +charras +1270545917 +
Libraries are shown in decreasing priority order, that is important fo select duplicate components. +In library dialog, alphabetic order is therefore a non sense.
+ + + + + + +9362095 +IP +Artifact Created: 84.25.204.235 +1270320253 +jerryjacobs + + +9369903 +assigned_to +1293228 +1270545767 +charras + + +9369907 +IP +Comment Added: 152.77.63.2 +1270545917 +charras + + + + +http://sourceforge.net/support/tracker.php?aid=2982081 +2982081 +1 +761685 +100 +thewarpi +nobody +nobody +1270473401 +0 +5 +Add all icon shortcuts to menu +
Please add all shortcuts which you find under the icons aswell in the menu. Examples +Library editor (found EESchema) could maybe be under a menu called Tools etc... + +Thanks!
+0 + + + + + + +9366589 +IP +Artifact Created: 90.237.202.7 +1270473401 +thewarpi + + + + +http://sourceforge.net/support/tracker.php?aid=2982117 +2982117 +1 +1026580 +100 +nobody +nobody +nobody +1270479736 +0 +5 +Show and sort by description in Library browser +
Would be nice with the posebility to show all descriptions of all components in the library browser and then even be able to sort by "part name" or sort by "description". + +Thanks!
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2982613 +2982613 +1 +1026579 +100 +nobody +nobody +nobody +1270557149 +0 +5 +List unconnects: net name +
Display of corresponding net along with unconnected pad would be nice (in dialog List unconnected).
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2982614 +2982614 +1 +1026579 +100 +nobody +nobody +nobody +1270557290 +0 +5 +List unconnects: ignore/filter +
Ability to ignore/filter certain components or even nets.
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2983714 +2983714 +1 +1026579 +100 +nobody +nobody +nobody +1270715726 +0 +5 +Remember active layers +
The layer setup (hide paste, silk, invisible text etc) should be saved in the project file.
+0 + + + + + + + + +http://sourceforge.net/support/tracker.php?aid=2983870 +2983870 +1 +1026579 +100 +nobody +nobody +nobody +1270732057 +0 +5 +Default board settings +
It would be very useful feature if PCBnew (and probably EEschema) would be able to load default values from file when creating new board (circuit in case of EESchema). +As example: Custom track widths, Custom VIA sizes, Net classes; +I believe most users use some default values for all boards theu develop (use common calsses GND, VCC, VDD etc and use the same values for these nets). +The same comes with custom net sizes. +Currently on new design all these values must be added manually while these could be loaded from template board (like default project settings are loaded from kicad.pro file). +
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delete mode 100644 Documentation/kicad_export.xml diff --git a/Documentation/kicad_export.xml b/Documentation/kicad_export.xml deleted file mode 100644 index 88dfdf9356..0000000000 --- a/Documentation/kicad_export.xml +++ /dev/null @@ -1,32286 +0,0 @@ - - - - - - - - - - -145591 -kicad -dickelbeck - - -http://sourceforge.net/projects/kicad/ -145591 -kicad -Kicad EDA -Kicad EDA is an open source (GPL) software for the creation of electronic schematic diagrams and printed circuit board artwork. -gpl -http://kicad.sourceforge.net -This software (using WXWIDGETS) is MULTI-PLATFORM. It is running under LINUX, Windows (XP or 2000), FreeBSD and Solaris. -Kicad written on C++ using Gcc, wxWidgets (wxwidgets.org), GTK (www.gtk.org) and Mesa (www.mesa3d.org). -Documentation maked in OpenOfficeOrg. -3D shapes of Pcbnew footprints maked in Wings3D (www.wings3d.com). -Kicad can solve problems of electronic hardware designers as free CAD package, complete and with a professional standard. -Kicad is a sofware suite which consists from - Eeschema :Schematic entry. - Pcbnew :Board editor. - Gerbview :GERBER viewer (photoplotter documents). - Cvpcb :footprint selector for components used in the circuit design. - Kicad: project manager. - -The original homepage of software is http://www.lis.inpg.fr/realise_au_lis/kicad/ -plyatov -1123423800 - - -http://sourceforge.net/users/kintel/ -145718 -kintel -Marius Kintel -kintel@users.sourceforge.net -No - - -http://sourceforge.net/users/diemer/ -154672 -diemer -Jonas Diemer -diemer@users.sourceforge.net -No - - -http://sourceforge.net/users/bennett78/ -464167 -bennett78 -Frank Bennett -bennett78@users.sourceforge.net -No - - -http://sourceforge.net/users/manneveru/ -639576 -manneveru -Michał Fita -manneveru@users.sourceforge.net -No - - -http://sourceforge.net/users/strangeril/ -1196510 -strangeril -Milan Horák -strangeril@users.sourceforge.net -No - - -http://sourceforge.net/users/vesa_solonen/ -1207241 -vesa_solonen -Vesa Solonen -vesa_solonen@users.sourceforge.net -No - - -http://sourceforge.net/users/raburton/ -1213654 -raburton -rab -raburton@users.sourceforge.net -No - - -http://sourceforge.net/users/dickelbeck/ -1222857 -dickelbeck -Dick Hollenbeck -dickelbeck@users.sourceforge.net -Yes - - -http://sourceforge.net/users/goutnet/ -1283799 -goutnet -Florian Delizy -goutnet@users.sourceforge.net -No - - -http://sourceforge.net/users/charras/ -1293228 -charras -jp-charras -charras@users.sourceforge.net -No - - -http://sourceforge.net/users/plyatov/ -1325376 -plyatov -Igor Plyatov -plyatov@users.sourceforge.net -Yes - - -http://sourceforge.net/users/f3nix/ -1459455 -f3nix -Mateusz Skowroński -f3nix@users.sourceforge.net -No - - -http://sourceforge.net/users/aircraft/ -1777188 -aircraft -aircraft -aircraft@users.sourceforge.net -No - - -http://sourceforge.net/users/faa/ -1805271 -faa -faa -faa@users.sourceforge.net -Yes - - -http://sourceforge.net/users/messo/ -1810278 -messo -Messo -messo@users.sourceforge.net -No - - -http://sourceforge.net/users/lifekidyeaa/ -1811176 -lifekidyeaa -Tim Hanson -lifekidyeaa@users.sourceforge.net -No - - -http://sourceforge.net/users/g_harland/ -1848371 -g_harland -Geoff Harland -g_harland@users.sourceforge.net -No - - -http://sourceforge.net/users/reniemarquet/ -1894170 -reniemarquet -Renie S. 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- -http://sourceforge.net/project/showfiles.php?group_id=145591&package_id=267495&release_id=584432 -kicad-library-1.0.zip -584432 -267495 -None -2409896 -1205615638 -1205604795 - - -http://sourceforge.net/project/showfiles.php?group_id=145591&package_id=290760&release_id=625123 -kicad-cs-r1243.zip -625123 -290760 -Platform-Independent -115204 -1220958431 -1220951217 - - -http://sourceforge.net/project/showfiles.php?group_id=145591&package_id=290760&release_id=625123 -kicad-cs-r1680.zip -625123 -290760 -Platform-Independent -126390 -1238759362 -1238752137 - - - - -http://sourceforge.net/projects/kicad/forums/forum/487027 -487027 -Open Discussion -Yes - - -No - - -http://sourceforge.net/projects/kicad/forums/forum/487027/topic/3242243?message=7283516 -7283516 -broran -bror eriksson -autorouter to KiCAD -3242243 -0 -0 -1240665685 -No -what about a Opensource auto router to KiCAD? Like Wat's available at http://web.ift.uib.no/~bruce/eda1.htm#nevin - - -http://sourceforge.net/projects/kicad/forums/forum/487027/topic/3170961?message=7068720 -7068720 -beerslayer -The Beerslayer -Import from OrCAD? -3170961 -0 -0 -1238824114 -No -Hi - I'm not personally a CAD user so I don't know the technical details, but my father uses OrCAD (v9, I believe) at his job. I'd like to see if perhaps Kicad will do the job he needs to do, but he has a LOT of old files in OrCAD format that he needs to be able to access and, in some cases, edit or modify. I believe the extension on these files is .prj, but I'm not 100% sure. - -Is there currently any way within Kicad to import these files directly? If not, is there another open source app that can do this? Or is there possibly some intermediate format that this version of OrCAD can export that Kicad (or other open source converter) can read? - -Failing all of that, does Kicad support any kind of add-on structure (other than hacking its own sources) for producing some sort of plugin that might offer this functionality? - - -http://sourceforge.net/projects/kicad/forums/forum/487027/topic/1332066?message=4944948 -4944948 -xcskier -skier -How to get wxmsw28u_gcc_custom.dll ? -1332066 -3285326 -0 -1209954241 -No -I've downloaded kicad-20080504-41027-win32.zip, -& unzipped it. - -Please tell me where I can find - -wxmsw28u_gcc_custom.dll - -Thank you -Dave -mcquate (at) sonic (dot) net - - -http://sourceforge.net/projects/kicad/forums/forum/487027/topic/1332066?message=3285326 -3285326 -nobody -Nobody/Anonymous -Welcome to Open Discussion -1332066 -0 -1 -1123520471 -No -Welcome to Open Discussion - - - - -http://sourceforge.net/projects/kicad/forums/forum/487028 -487028 -Help -Yes - - -No - - -http://sourceforge.net/projects/kicad/forums/forum/487028/topic/3480879?message=7801578 -7801578 -stefanl38 -Stefan L38 -most efficient way to add devices -3480879 -0 -0 -1260103227 -No -Hello, - -I would like to know what is the most efficient way to add devices to a schematic - -right now I know only of - -1) click on schematic: window choose opens -2) Click on librarybrowser -3) Click on device name -4) Click on add to schematic -5) place device on schematic - -five clicks that's 3 clicks too much. -How can I do this in that way ? - -Doubleclick for choose - leftclick for placing -Doubleclick for choose - leftclick for placing - -Or is there only the workaoriund of having a template where all important devices are placed in one edge and then copy and paste them ? - -best regards - -Stefan - - -http://sourceforge.net/projects/kicad/forums/forum/487028/topic/3334371?message=7503044 -7503044 -jenningsthecat -jenningsthecat -Net names display in PcbNew -3334371 -0 -0 -1247615452 -No -Is there a way to turn off the net names display in PcbNew? I've looked through all of the config menus and have been unable to find it. If I can't turn this 'feature' off I'll have to go back to an earlier version! - - -http://sourceforge.net/projects/kicad/forums/forum/487028/topic/3334254?message=7502873 -7502873 -jerryjacobs -Jerry Jacobs -RE: Net names display in PcbNew -3334254 -7502829 -0 -1247607325 -No -In last SVN version it is no problem to turn this off, -Look at Preferences -> Display -> Netnames. - - -http://sourceforge.net/projects/kicad/forums/forum/487028/topic/3334254?message=7502829 -7502829 -jenningsthecat -jenningsthecat -Net names display in PcbNew -3334254 -0 -1 -1247606519 -No -Is there a way to turn off the net names display in PcbNew? I've looked through all of the config menus and have been unable to find it. If I can't turn this 'feature' off I'll have to go back to an earlier version! - - -http://sourceforge.net/projects/kicad/forums/forum/487028/topic/3066958?message=6631783 -6631783 -jgmejiah -juan -Adding rats from pcbnew -3066958 -0 -0 -1236194765 -No -Hi, - -Is there any way to add rats from PCBnew? Do I always have to make a schematic (or a netlist) before using PCBnew? For some designs it could be faster to design just the PCB and I see no tool for adding rats. - -Thanks a lot - - -http://sourceforge.net/projects/kicad/forums/forum/487028/topic/2156310?message=5152057 -5152057 -cablik -Jan Cablik -Same length of the bus nets -2156310 -0 -0 -1218098684 -No -Hi, I'm new to KiCAD. At this moment I'm looking for an alternative to OrCAD 9.2. -I make designs with DDR2 memories and I need their bus signals to be aligned to the same length (with a small allowed tolerance). Is it possible with KiCAD to set a rule that autorouted and/or hand-drawn nets should be aligned to the same length (automatically, or notify me of the current and desired length}. I searched through the manuals but was not able to find anything about this. - -Jan - - -http://sourceforge.net/projects/kicad/forums/forum/487028/topic/1882263?message=4652136 -4652136 -di2 -di2 -fiducials -1882263 -0 -0 -1196442067 -No -Hi, -how do I make fiducials? -I need to make the clearance for the soldermask bigger than standard. -Thanks, -di2 - - -http://sourceforge.net/projects/kicad/forums/forum/487028/topic/1332067?message=3285327 -3285327 -nobody -Nobody/Anonymous -Welcome to Help -1332067 -0 -0 -1123520472 -No -Welcome to Help - - - - -http://sourceforge.net/projects/kicad/forums/forum/487029 -487029 -Developers -No - - -No - - -http://sourceforge.net/projects/kicad/forums/forum/487029/topic/1332068?message=3285328 -3285328 -nobody -Nobody/Anonymous -Welcome to Developers -1332068 -0 -0 -1123520472 -No -Welcome to Developers - - - - - - -http://sourceforge.net/?group_id=145591&atid=762476 -762476 -Bugs -Bug Tracking System -All site users -Yes -No -2592000 - - -1209600 -0 -0 -0 - - -5497 -Bug Fixed -This bug has been fixed -Active - - - - - - - -516020 -Windows XP - - -755196 -Linux - - -755197 -Mac - - -755198 -Any - - -1083286 - - - -1083307 -Windows Vista - - -1083308 -Windows 7 - - - - -761682 -PCBnew -nobody - - -1015285 -EESchema -nobody - - -1015286 -KiCad -nobody - - -1015287 -GerbView -nobody - - -1015288 -CVpcb -nobody - - - - -1 -Fixed - - -2 -Invalid - - -3 -Wont Fix - - -4 -Later - - -5 -Remind - - -6 -Works For Me - - -100 -None - - -101 -Duplicate - - -102 -Accepted - - -103 -Out of Date - - -104 -Postponed - - -105 -Rejected - - - - -1 -Open - - -2 -Closed - - -3 -Deleted - - -4 -Pending - - - - -http://sourceforge.net/support/tracker.php?aid=1635789 -1635789 -3 -761682 -100 -100 -cyrilbuttay -nobody -dickelbeck -1168860204 -1188591390 -5 -naming problem in EEschema -
Hi, - -I'm running kicad RC2 2007-01-03, and I noted the following (strange behaviour). I'm not a regular user of Kicad, so maybe it is not related to this version: - -When I add a resistor (R), if I click on "edit component/edit", I have a Chip Name field "R" and a value "R?" (in the "component properties" window). But if I click on "edit component/value", the windows that opens returns "R", and "edit component/reference" returns "R". - -Furthermore, in "edit component/edit", if I change the value from R? to, for example 1k, the reference of the component changes on the schematic, not its value, and if I change the "chip name" from "R" to 1k, I have an error message ("component [1k] not found"). - -Also, if I right click exactly in the middle of the resistor, the only choice I have under "edit component" is "edit", nothing else. Is that normal? - -Thank you for your work - -Regards - -Cyril
-0 - - -2466685 -dickelbeck -1187413511 -
Logged In: YES -user_id=1222857 -Originator: NO - -This seems to be fixed now. Please re-submit if still present in latest software.
- - -2469757 -dickelbeck -1187708591 -
Logged In: YES -user_id=1222857 -Originator: NO - -This seems to be fixed in later releases. Re-submit if its still a problem.
- - - - - - -4936480 -IP -Comment Added: 67.64.64.34 -1187413511 -dickelbeck - - -4947886 -IP -Comment Added: 67.64.64.34 -1187708591 -dickelbeck - - -4947900 -status_id -1 -1187708697 -dickelbeck - - -4947901 -close_date -0 -1187708697 -dickelbeck - - -4990238 -status_id -2 -1188591390 -dickelbeck - - -4990239 -close_date -1187708697 -1188591390 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=1786007 -1786007 -3 -761682 -755198 -100 -dickelbeck -nobody -dickelbeck -1188591968 -1228758316 -5 -Grid color change not working -
You can change the grid color on the Colors Preferences panel and it has no effect on the grid color. - -share/drawpanel.cpp is using g_GridColor and not g_PcbGridColor. - -
-0 - - -2511928 -dickelbeck -1191349907 -
Logged In: YES -user_id=1222857 -Originator: YES - -This bug has been fixed
- - - - - - -4990288 -IP -Artifact Created: 67.64.64.34 -1188591968 -dickelbeck - - -5114086 -status_id -1 -1191349742 -dickelbeck - - -5114087 -close_date -0 -1191349742 -dickelbeck - - -5114097 -IP -Comment Added: 67.64.64.34 -1191349907 -dickelbeck - - -7157900 -status_id -2 -1228758316 -dickelbeck - - -7157901 -close_date -1191349742 -1228758316 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=1798419 -1798419 -2 -1015288 -755198 -100 -bennett78 -nobody -sf-robot -1190237318 -1231208426 -5 -editor munges long pin names -
Netlist editor munges pin names -greater than 4 characters. - -to Reproduce: - read bugin.net - note name COLLECTOR, CATHODE, etc - write out.net - -Attached bug.zip -bugin.net -bugout.net
-0 - - -2502326 -dickelbeck -1190516244 -
Logged In: YES -user_id=1222857 -Originator: NO - -The data structures which hold the pin names only allow for 4 characters. Would you be happy if you could not input longer names, thus you would get an early warning that names are limited to 4 characters? Or should the data structure be expanded to handle longer names, and if so how long? - -As it stands, this is probably not a bug, but a feature request. -
- - -2503755 -bennett78 -1190655724 -
Logged In: YES -user_id=464167 -Originator: YES - -The long name should probably be truncated. It also seems to stomp -on the Reference Designator. - -This doesn't look like a problem in EEschem or pcbnew? (I didn't -check pcbnew) - -I did notice that a footprint can be assigned (backannotated?) in -EEschem, although not a nice as the footprint viewer in CVPCB. - -I think some users would prefer that the CVPCB function exist in EEschem.
- - -3285867 -sf-robot -1231208426 -
This Tracker item was closed automatically by the system. It was -previously set to a Pending status, and the original submitter -did not respond within 14 days (the time period specified by -the administrator of this Tracker).
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=246370&aid= -246370 -bug.zip -netlist in, out -649 -application/x-zip-compressed -1190237319 -bennett78 - - - - -5064071 -IP -Artifact Created: 199.3.246.231 -1190237319 -bennett78 - - -5064072 -File Added -246370: bug.zip -1190237319 -bennett78 - - -5077381 -IP -Comment Added: 67.64.64.34 -1190516244 -dickelbeck - - -5082760 -IP -Comment Added: 199.3.246.231 -1190655724 -bennett78 - - -7157875 -status_id -1 -1228758211 -dickelbeck - - -7157876 -close_date -0 -1228758211 -dickelbeck - - -7157892 -status_id -2 -1228758271 -dickelbeck - - -7157893 -close_date -1228758211 -1228758271 -dickelbeck - - -7368962 -IP -Comment Added: -1231208426 -sf-robot - - -7368963 -status_id -4 -1231208426 -sf-robot - - -7368964 -close_date -1228758271 -1231208426 -sf-robot - - - - -http://sourceforge.net/support/tracker.php?aid=1800438 -1800438 -1 -761682 -100 -100 -dickelbeck -nobody -nobody -1190516361 -0 -4 -Block copy is moving footprints on an invisible layer -
The block copy command is grabbing footprints from a layer which is currently set to invisible. This is a seriously dangerous bug, because it can wipe out hours of work. -
-0 - - -2582021 -nobody -1196925024 -
Logged In: NO - -Track, via and text can be move too.
- - - - - - -5077383 -IP -Artifact Created: 67.64.64.34 -1190516361 -dickelbeck - - -5354187 -priority -9 -1196875472 -dickelbeck - - -5356089 -IP -Comment Added: 217.150.32.243 -1196925024 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1812554 -1812554 -2 -1015285 -755198 -100 -sfabris -nobody -sf-robot -1192223155 -1208139613 -5 -Erc reports warnings about non connected wires -
Erc check report pins as non connected. -Netlist and Pcbnew show the pins as regolary connected. - -Tried both with win and Linux version, SVN build and last stable release. - -If necessary I can give more help to try to find the bug (if any). - -Thanks, - -Simone
-0 - - -2723115 -diemer -1206891097 -
Logged In: YES -user_id=154672 -Originator: NO - -Please provide a complete schematic or at least the exact output of ERC.
- - -2739523 -sf-robot -1208139613 -
Logged In: YES -user_id=1312539 -Originator: NO - -This Tracker item was closed automatically by the system. It was -previously set to a Pending status, and the original submitter -did not respond within 14 days (the time period specified by -the administrator of this Tracker).
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=249438&aid= -249438 -example.jpg -Example of what described. -68567 -image/jpeg -1192223155 -sfabris - - - - -5152236 -IP -Artifact Created: 151.65.2.75 -1192223155 -sfabris - - -5152237 -File Added -249438: example.jpg -1192223155 -sfabris - - -5833726 -IP -Comment Added: 82.83.232.41 -1206891097 -diemer - - -5833727 -status_id -1 -1206891097 -diemer - - -5833728 -close_date -0 -1206891097 -diemer - - -5895185 -IP -Comment Added: -1208139613 -sf-robot - - -5895186 -status_id -4 -1208139613 -sf-robot - - -5895187 -close_date -1206891097 -1208139613 -sf-robot - - - - -http://sourceforge.net/support/tracker.php?aid=1817455 -1817455 -2 -100 -516020 -100 -djsbriscoe -nobody -dickelbeck -1192994631 -1194011858 -5 -Tooltips and status bar info not displayed. -
Tooltips and status bar info is not displayed in EEschema ,CVPCB, PCBnew or gerbview. -I'm using the latest SVN snapshot in Windows 2000 sp4.
-0 - - -2537603 -djsbriscoe -1193571098 -
Logged In: YES -user_id=1047261 -Originator: YES - -Problem appears to have gone away in latest snapshots.
- - - - - - -5183404 -IP -Artifact Created: 82.18.200.240 -1192994631 -djsbriscoe - - -5207376 -IP -Comment Added: 82.18.206.122 -1193571098 -djsbriscoe - - -5229275 -status_id -1 -1194011858 -dickelbeck - - -5229276 -close_date -0 -1194011858 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=1820057 -1820057 -3 -1015288 -100 -100 -ckgrier2 -nobody -ckgrier2 -1193326522 -1193327717 -5 -Viewing Modules from Footprint list -
When using CVPCB to select footprints it is helpful to see the modules in the "View Selected Part" window. - -However, if the cursor is placed on the footprint list, and the user attempts to cursor through the available footprints, the window "focus" shifts to each new footprint as it is displayed. This is counter-intuitive, since the up and down cursor action doesn't seem to warrant a change in window "focus". - -I don't know if this is an wxWidgets thing... but telling the "view" window to update with a new footprint shouldn't cause the CVPCB window to loose focus. Pressing the down arrow three times should move the cursor down three lines.
-0 - - - - - - -5198599 -IP -Artifact Created: 74.160.34.198 -1193326522 -ckgrier2 - - -5198701 -status_id -1 -1193327717 -ckgrier2 - - -5198702 -close_date -0 -1193327717 -ckgrier2 - - - - -http://sourceforge.net/support/tracker.php?aid=1820072 -1820072 -2 -1015288 -100 -100 -ckgrier2 -nobody -strangeril -1193327535 -1193610551 -5 -Viewing Modules from Footprint list -
When using CVPCB to select footprints it is helpful to see the modules in the "View Selected Part" window. - -However, if the cursor is placed on the footprint list, and the user attempts to cursor through the available footprints, the window "focus" shifts to each new footprint as it is displayed. This is counter-intuitive, since the up and down cursor action doesn't seem to warrant a change in window "focus". - -I don't know if this is an wxWidgets thing... but telling the "view" window to update with a new footprint shouldn't cause the CVPCB window to loose focus. Pressing the down arrow three times should move the cursor down three lines.
-0 - - -2535325 -nobody -1193363773 -
Logged In: NO - -It happens on the Windos build from September 22. I don't see the same problem with the Linux build from Jan. 15th
- - -2535968 -strangeril -1193405929 -
Logged In: YES -user_id=1196510 -Originator: NO - -There is no official svn-snapshot from September 22th. - -Can you please test it with latest svn-snapshot (20071015-r336). - -I'll also test it on my computer at home so please be patient.
- - -2538007 -ckgrier2 -1193603868 -
Logged In: YES -user_id=1921682 -Originator: YES - -No issues now. It works. Thanks.
- - - - - - -5198680 -IP -Artifact Created: 74.160.34.198 -1193327535 -ckgrier2 - - -5200216 -IP -Comment Added: 68.158.5.158 -1193363773 -nobody - - -5202061 -IP -Comment Added: 194.108.201.110 -1193405929 -strangeril - - -5208799 -IP -Comment Added: 68.158.5.158 -1193603868 -ckgrier2 - - -5208991 -status_id -1 -1193610551 -strangeril - - -5208992 -close_date -0 -1193610551 -strangeril - - - - -http://sourceforge.net/support/tracker.php?aid=1823001 -1823001 -2 -1015288 -100 -100 -plyatov -charras -dickelbeck -1193774372 -1194011980 -5 -cvpcb closed when Netlist and Cmp files saved. -
The cvpcb program closed accidentally when user save the NetList and Components files. -The files saved successfully, but the program closed for unknown reason.
-0 - - -2541259 -charras -1193830078 -
Logged In: YES -user_id=1293228 -Originator: NO - -This is not a bug, this is a feature ... - -J-P. Charras
- - -2544149 -dickelbeck -1194011980 -
Logged In: YES -user_id=1222857 -Originator: NO - -Seems to be a difference of opinion, I'm closing the bug for now. It can be moved by reporter to the enhancement list if he wants, but it looks like nothing will be done about it.
- - - - - - -5217212 -IP -Artifact Created: 217.106.91.42 -1193774372 -plyatov - - -5219639 -IP -Comment Added: 86.193.9.209 -1193830078 -charras - - -5229278 -IP -Comment Added: 67.64.64.34 -1194011980 -dickelbeck - - -5229279 -status_id -1 -1194011980 -dickelbeck - - -5229280 -close_date -0 -1194011980 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=1828485 -1828485 -2 -1015286 -755198 -1 -lainal -dickelbeck -dickelbeck -1194551507 -1196874372 -1 -makefile.include: bad compiler directive -
Some rules refer to the compiler $(CC) instead of $(CXX). -With non-GCC compilers, this prevents C++ code to be built. -Same occurs in makefile.include files of the others targets, i.e. PCBNEW, EESCHEMA, CVPCB and GERBVIEW
-0 - - -2581362 -dickelbeck -1196874372 -
Logged In: YES -user_id=1222857 -Originator: NO - -I think I fixed this two weeks ago.
- - - - - - -5252962 -IP -Artifact Created: 217.226.73.94 -1194551507 -lainal - - -5253071 -priority -5 -1194553071 -lainal - - -5354058 -IP -Comment Added: 67.64.64.34 -1196874372 -dickelbeck - - -5354059 -status_id -1 -1196874372 -dickelbeck - - -5354060 -resolution_id -100 -1196874372 -dickelbeck - - -5354061 -assigned_to -100 -1196874372 -dickelbeck - - -5354062 -close_date -0 -1196874372 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=1828487 -1828487 -2 -761682 -100 -3 -lainal -nobody -dickelbeck -1194551771 -1196875751 -1 -3D-viewer ANSI C++ code boken -
In source file 3d_canvas.cpp, the constructor Pcb3D_GLCanvas::Pcb3D_GLCanvas should have a "const wxWindowsID id parameter". -The missing "const" prevents the compilation to succeeds on non-GCC C++ compilers
-0 - - -2551700 -nobody -1194596144 -
Logged In: NO - -Actioned in Revision 439
- - -2551702 -g_harland -1194596480 -
Logged In: YES -user_id=1848371 -Originator: NO - -Actioned in Revision 439
- - -2581402 -dickelbeck -1196875750 -
Logged In: YES -user_id=1222857 -Originator: NO - -submit a diff generated patch to the developers list and if it does not break the g++ compile, we will use it. Generally there's no commitment to support any non g++ compiler. Unless that person steps up, he is no where to be found currently.
- - - - - - -5252980 -IP -Artifact Created: 217.226.73.94 -1194551771 -lainal - - -5254740 -IP -Comment Added: 58.106.1.84 -1194596144 -nobody - - -5254744 -IP -Comment Added: 58.106.1.84 -1194596480 -g_harland - - -5354196 -IP -Comment Added: 67.64.64.34 -1196875750 -dickelbeck - - -5354197 -status_id -1 -1196875750 -dickelbeck - - -5354198 -resolution_id -100 -1196875751 -dickelbeck - - -5354199 -priority -5 -1196875751 -dickelbeck - - -5354200 -close_date -0 -1196875751 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=1828499 -1828499 -2 -1015286 -755198 -3 -lainal -nobody -dickelbeck -1194553011 -1196874162 -5 -EXCHG macro dedicated to GCC -
In include/macros.h, the definition of EXCHG(a,b) is not valid in other compilers than G++ which don't have the GCC's "typeof" extension. - -A small update I use is the following: - -#ifdef __GNUC__ -#define EXCHG(a,b) { typeof(a) __temp__ = (a); (a) = (b); (b) = __temp__; } -#else -/* --Dom: typeof not always existing outside gcc world */ -#define EXCHG(a,b) { \ -size_t __nb__ = sizeof( (a) ); \ -void *__temp__ = malloc( __nb__ ); \ -memcpy( __temp__ , (void*)&(b), __nb__ ); \ -memcpy( (void*)&(b), (void*)&(a), __nb__ ); \ -memcpy( (void*)&(a), __temp__ , __nb__ ); \ -free (__temp__); \ -} -#endif
-0 - - -2581355 -dickelbeck -1196874038 -
Logged In: YES -user_id=1222857 -Originator: NO - -duplicate of 1844285 -
- - - - - - -5253066 -IP -Artifact Created: 217.226.73.94 -1194553011 -lainal - - -5354013 -IP -Comment Added: 67.64.64.34 -1196874038 -dickelbeck - - -5354014 -resolution_id -100 -1196874038 -dickelbeck - - -5354033 -status_id -1 -1196874162 -dickelbeck - - -5354034 -close_date -0 -1196874162 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=1829931 -1829931 -2 -1015285 -755198 -1 -plyatov -diemer -diemer -1194788228 -1207252172 -5 -Incorrect area zooming in eeschema -
If user try to zoom an area (by middle mouse button dragging or from a context menu), then zoomed area displayed only partially. -If eeschema window is maximized then correct area zooming occurs more often. -This problem can be easy investigated on a rectangular objects, which user want to zoom. - -My system is: - Gentoo Linux - wxWidgets 2.6.4 - KiCad SVN r454
-0 - - -2728551 -diemer -1207252172 -
Logged In: YES -user_id=154672 -Originator: NO - -I just improved that behavior in r969, so the area shown after zooming includes at least the selected rectangle (rather than zooming too far in as it was the case in earlier versions). Zooming more accurately is not possible (currently), because we can only zoom in fixed steps. - --> Bug fixed.
- - - - - - -5261211 -IP -Artifact Created: 217.106.91.42 -1194788228 -plyatov - - -5856067 -IP -Comment Added: 82.83.174.232 -1207252172 -diemer - - -5856068 -status_id -1 -1207252172 -diemer - - -5856069 -resolution_id -100 -1207252172 -diemer - - -5856070 -artifact_group_id -755196 -1207252172 -diemer - - -5856071 -assigned_to -1293228 -1207252172 -diemer - - -5856072 -close_date -0 -1207252172 -diemer - - - - -http://sourceforge.net/support/tracker.php?aid=1830005 -1830005 -1 -100 -100 -100 -plyatov -charras -nobody -1194799913 -0 -5 -Duplicate pins was not detected in LibEdit -
If user makes a component with identical pins without enabled property "Common to parts" in different parts, then function "Test duplicate pins" always reports "Pins test OK!". - -This function must reports error if component contains pins with identical "Pin Number" and without enabled property "Common to parts".
-0 - - - - - - -5261621 -IP -Artifact Created: 217.106.91.42 -1194799914 -plyatov - - -5261672 -assigned_to -100 -1194800726 -plyatov - - - - -http://sourceforge.net/support/tracker.php?aid=1831005 -1831005 -2 -1015285 -755196 -6 -sunnysan -diemer -diemer -1194951225 -1206890913 -5 -ERC error to well connected grd -
When I do the erc test I got the ground connected to a wire which gives me a error. -ERC shows/thinks that the ground (GND) of the circuit is not connected, although I rewired it many times and even to deleted the ground to put a new one. -But the ERC still shows me the arrow (on the GND) thinking that it is not connected - -Sunny San - -My version of KiCad -Build Version: -KiCad (2007-05-25) - Unicode version -under Ubuntu 7.10 - -erc file content below - -ERC control (13/11/2007-10:37:36) - -***** Sheet 1 (Root) -ERC: Warning Pin power_in not driven (Net 1) (X= 7.750 inches, Y= 2.400 inches - - >> Errors ERC: 1
-0 - - -2636524 -nobody -1200571735 -
Logged In: NO - -I confirm the above behaviour, exactly the same problem. - -I have a GND power pin in three places (they are in the same net) and the are grouped by this three GND power items. - -I noticed in ERC that always warned the first one to be disconnected. Well I cleared wire and power and replaced both wire and power. Then ERC warned in one of the other two power items: there's always one power with warning. -
- - -2723112 -diemer -1206890913 -
Logged In: YES -user_id=154672 -Originator: NO - -That behavior is normal. ERC requires Power pins to be driven by something (e.g. a voltage regulator). If your circuit does not include such a device, you need to add a Power_Flag to the corresponding net, see attached file. This is also in the Manual (chapter 7 - ERC).
- - -2723114 -diemer -1206890952 -
Logged In: YES -user_id=154672 -Originator: NO - -That behavior is normal. ERC requires Power pins to be driven by something (e.g. a voltage regulator). If your circuit does not include such a device, you need to add a Power_Flag to the corresponding net, see attached file. This is also in the Manual (chapter 7 - ERC). -File Added: test003-fixed.sch
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=254078&aid= -254078 -test003.sch -schematic file -3351 -application/x-extension-sch -1194951225 -sunnysan - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=272502&aid= -272502 -test003-fixed.sch -schematic with power flag. -3874 -application/octet-stream -1206890952 -diemer - - - - -5268453 -IP -Artifact Created: 81.137.78.73 -1194951225 -sunnysan - - -5268454 -File Added -254078: test003.sch -1194951226 -sunnysan - - -5523226 -IP -Comment Added: 87.235.48.116 -1200571735 -nobody - - -5833705 -IP -Comment Added: 82.83.232.41 -1206890913 -diemer - - -5833706 -status_id -1 -1206890913 -diemer - - -5833707 -resolution_id -100 -1206890913 -diemer - - -5833708 -assigned_to -100 -1206890913 -diemer - - -5833709 -close_date -0 -1206890913 -diemer - - -5833715 -File Added -272502: test003-fixed.sch -1206890952 -diemer - - -5833716 -IP -Comment Added: 82.83.232.41 -1206890953 -diemer - - - - -http://sourceforge.net/support/tracker.php?aid=1832187 -1832187 -2 -761682 -100 -102 -ckgrier2 -dickelbeck -ckgrier2 -1195092530 -1200507454 -5 -Module Editor asks twice for Selection Clarification -
Using module Editor on Windows 10-29-07 version. - -Erasing graphic lines near pads, left-click pops up a Selection Clarification window (as expected). Selecting the line brings up a duplicate Clarifcation window, and requires a second selection. - -I don't know why it is asking twice, but it shouldn't. :) - -(Have not tested on Linux version yet.)
-0 - - -2581387 -dickelbeck -1196875114 -
Logged In: YES -user_id=1222857 -Originator: NO - -I added a fix so that if your mouse does not move, between the two clicks, (left mouse, then right mouse for popup menu) then it will not prompt you the 2nd time. - -Is this working for you? -
- - -2584396 -ckgrier2 -1197082665 -
Logged In: YES -user_id=1921682 -Originator: YES - -Sorry, but I can't build from source. :-( - -I'll check as soon as there's a new W32 build available.
- - -2635169 -ckgrier2 -1200507454 -
Logged In: YES -user_id=1921682 -Originator: YES - -This bug has been fixed
- - -2635170 -ckgrier2 -1200507454 -
Logged In: YES -user_id=1921682 -Originator: YES - -I tested it on Win32 with the 12/22 version and the double confirmation is resolved.
- - - - - - -5276109 -IP -Artifact Created: 64.132.121.34 -1195092530 -ckgrier2 - - -5354153 -IP -Comment Added: 67.64.64.34 -1196875114 -dickelbeck - - -5354154 -status_id -1 -1196875114 -dickelbeck - - -5354155 -resolution_id -100 -1196875114 -dickelbeck - - -5354156 -assigned_to -100 -1196875114 -dickelbeck - - -5354157 -close_date -0 -1196875114 -dickelbeck - - -5364056 -IP -Comment Added: 68.158.1.69 -1197082665 -ckgrier2 - - -5364057 -status_id -4 -1197082665 -ckgrier2 - - -5364058 -close_date -1196875114 -1197082665 -ckgrier2 - - -5519707 -IP -Comment Added: 68.217.12.91 -1200507454 -ckgrier2 - - -5519708 -IP -Comment Added: 68.217.12.91 -1200507454 -ckgrier2 - - -5519709 -status_id -1 -1200507454 -ckgrier2 - - -5519710 -close_date -0 -1200507454 -ckgrier2 - - - - -http://sourceforge.net/support/tracker.php?aid=1834473 -1834473 -2 -100 -100 -102 -whitis -charras -dickelbeck -1195471051 -1228757739 -9 -Fill zones a mess -
There are a lot of problems with fill zones. - - - Filling with traces is not a good way to do it. - You get crappy edges on diagonal edges, - around pads, etc. Even the program pcb does a - better job of this. - - - No thermals that I can see, even though "thermals" - is an option on fill. But how does the program - know what pads should get connected? And if you - draw thermals manually using traces (very tedious), - the program will probably avoid them next time - you zap and recrate the fill. Apparently, from - looking at the pic programmer, it does this via - the netlist. But it doesn't let you tell it what - net the plane belongs to (how does it guess or does - it just assume incorrectly it is ground). And - just because - a pad connects to ground does not mean you want a - thermal there. You may need to connect particular - pins to the ground system in very particular ways. - And what happens if the pad is so close to a trace that the normal thermal pattern would intersect the trace? - - - The program non-consensually creates an imaginary - fill zone line around its misconceived notion of the - board extents. It fails to include manually drawn - fill zones in this notion of the board extent. - If you have drawn a board edge, however, it - functions ok so it is Pins necessary to create a board - outline even if you don't know what the outline - is yet. - - - Fill zone does not fill up to and including zone - boundaries. Sometimes it draws outside the lines - but usually it leaves a gap based on the - "clearance" as if the zone margin was a trace. - You can set the clearance to zero but then you - get inadequate clearance around traces. - - - Fill zone avoids imaginary objects that only it - can see. You can't see or edit these objects. - They are apparently stray fill zone boundary - segments from fill zones that were drawn but never - closed. They do sometimes appear temporarily - while you are drawing a new fill boundary, if - you trigger a redraw with the scroll wheel - (zoom). They go away when you answer yes to - "delete current edge zone" but that deletes - all the useful edges as well. It is really easy - to end up with a dozen of these imaginary - edge zones in a few minutes by aborting drawing - a zone boundary or segment. You get them by - drawing one too many edges before you hit - "end zone". You get them by clicking the mouse - not realizing you are in zone mode. Even when - you trick the program into displaying them, they - can't be deleted? - - - - The program is way to cavalier about deleting - zone edges. It constantly asks you if you - want to delete them. And sometimes you have to - delete them to clean up the mess left behind. - This is REALLY BAD. Those edges could have taken - hours to draw on a decent board with lots of fill. - Would you consider it acceptable for the program - to delete all your traces, or worse yet force you - to delete them to clean up the programs mess, - so easily? - - - Is there any documentation on fill zones? The - broken help viewer with no search function makes - it very hard to tell. - - - sometimes delete zone deletes the zone edge - instead of the fill. Well, it doesn't completely - go away, it just becomes one of the invisable - phantom edges. The rectangular cutout between - the two SSOP28 modules in the attached file is one - example. - - - Even when you say yes to delete zone edges, it doesn't get rid of some of the bad ones even though it does get rid of some of the good ones. - - - If I delete the "zone" on the pic programmer, and try to refill it, it deletes the thermals and doesn't put them back. And furthermore, it only fills in -one small area, not the whole board. It treats the -existing ground traces as boundaries. - -The attached file has at least 7 phantom edge segments that aren't supposed to be plus one phantom rectangle that is supposed to be there but is invisible. - -Warning: I am going to critique some of the sample board layouts. Disengage ego. I was looking at them to figure out if you had somehow managed to do any decent ground/power/signal planes with the software. Well, the boards look like they were laid out by a technician, not an engineer. Some cleverness in playing connect the dots but from a signal integrity perspective, they suck. Lots of copper in ground planes but not where it needs to be. Ground planes as an afterthought, not designed in. It is "would you believe its a ground plane? No? Well would you believe I am saving a lot of etchant by leaving copper on the board?". The program apparently is unusable for serious ground plane (or other fill work) because the programmers haven't done ground right. They look impressive to the untrained eye. - -A lot of real boards can have multiple power planes for different nets on the same layer along with signals that are drawn like planes for better impedence. And sometimes the planes are joined in certain specific locations. They aren't simple (from a zone perspective) like interf_u.brd. In fact, the "ground plane" on interf_u is a joke. It doesn't actually connect to anything as far as I can tell. It might actually create crosstalk and make the board worse off. -Ground is carried by traces that are too small. And the decoupling capacitors are likely to have to high high frequency impedence. Is this a real board? Does it actually work? sonde_xilinx contains another ground plane that is connected to a few pins without thermals. -Aha, you "select net", then fill. That sort of works but it also fills in the left D connector. And now I can't find a way to unselect the net. test_xil_95108 contains, again, only one net as a plane. And ground distrubution to the CPLD is not so good. VCC and ground should be planes on opposite layers. Was this a non-plated through hole board? If so, maybe a few jumpers under the CPLD socket are in order. Or better yet, use machined pin socket and solder the VCC pins on the top. Pretend you are an electron trying to get from the ground pin on the RAM to the CPLD. It is a 6" journey through two vias or a 4" journey though two throughholes (the regulator pin). You are on shaky ground (no pun intended) with a JEDEC ram pinout that only has one ground pin for two dozen signal pins (bouncy bouncy bouncy). And ground on the TDA8702 which should have run 0.4" to pin 60 (where is the via to the red ground trace next to pin 60????) has to travel half the circumference of the board to get to pin 16 on the CPLD or through two vias and a skinny red trace and squeeze between two pins before it can get to pin 42. Why wasn't the red trace from U2:49 to U1:6 not fattened? And why does it detour around a via that could have been moved instead of cutting the corner? Just because you flood a lot of copper on the board doesn't mean you have a decent ground. Pins 14,15,17,18,19,20, 21, 23, and 57 are all unused. If they had been tied to ground, you would have more channels to route ground through. Better yet, distribute them more evenly around the chip so you can make channels where you need them, like pins 30 and 29 where you desperately need one. Since the outdated JEDEC RAM pinout won't let you run ground traces between the pins, fat ground traces should have -hugged the top and bottom signal traces. And you -had lots of room on the component side to run ground. -Especially to pins 49 and 42, even if you have to -stitch across the TDO line. And, shit, the TDO line should not have been routed between the CPLD and the RAM at all. Run TDO around the periphery of the -board, not ground. And you might have avoided breaking ground in a critical place for the jtag signals - via those over ground. And a ground trace could have been squeezed between pins 15, 16, and 17 of the RAM. Better yet, you should have put the ground plane on the component side of the board where it would have done some good. Also, when you break a ground plane to run a long trace through it, you are supposed to stitch the two broken pieces together with a traces on the opposite side (that red trace from pin 59 is problematic). Pin 49 is on stich, you need another near pin 42 and one near pin 32. Fill the area on the bottom layer under the CPLD with VCC and fill the top (entire board) with GND and stitch. If you don't have through hole plating when prototyping, use individual screw machine IC socket pins (use the IC as a carrier while you are soldering the bottom and flatten out the leads of a dip and use it to hold pins in place while you solder the top or get a socket that has no fill in the middle. - -Some grounding tips: - - Ground is usually the most important signal on - the board and often neglected. - - - High speed logic needs good ground layouts even - when clocked at 1hz. It isn't the frequency - that matters, it is the edge rate. - - - Program CPLDs and FPGAs for the slowest edge rate - you can use. Many micros let you do this too. - If the chip won't let you do this, consider - series resistors on long traces, when driving - cables, etc. Use a slow logic family to get - slow edge rates. - - - At high frequencies, ground currents returning - from a signal do not take the shortest route, they - take the route that most nearly follows the path - of the original signal. This is one reason - ground planes directly under the signal really - help. If you can't run a ground plane there, - run some individual grounds between the signals. - Think like an electron; electrons do. - - - For every signal, pretend you are an electron - traveling in a loop through the signal traces and - back through ground. How many inches did you - have to travel? How far did you have to deviate - from your original path on the return trip? How - many vias? How many tight squeezes? The - bigger the area between the two paths the more EMI - you generate, the more you are susceptible to - external EMI, the more ground bounce you have, - and signal integrity is poorer. - - - FPGAs and CPLDs are great. They let you move pins - to facilitate PCB layout. Use this not just for - signals but to improve ground as well. - Where possible, tie unused signals on ICs to - ground and use that to create a channel to route - ground under that pin. Also, on some CPLD/FPGA you - can configure that pin as an extra ground or - at least drive a 0 onto the pin so ground - currents have an extra path through the output FET. - Move signals on your CPLD/FPGA to make room for - ground. - - - consider using a physical layout schematic symbol - for your programmable logic. It will help you - choose signal pins that are easy to route and it - is easier to plan for extra ground routes. - - - When you break a ground plane to run a trace - perpendicular to high speed signals, stitch - the two pieces together with traces across the - break and multiple parallel vias (for example, - two vias on each side of the break). - - - VCC and ground on opposite planes work great. - You get a lot of distributed capacitance. Ideally, - the whole board would be like this is one reason - why people pay for 4 layer boards. But if you - are using a two sided board, you can still do - this under your micros and programmable logic - and other high speed ICs. It isn't just your - external signals to be concerned about, ground - currents from internal logic needs help, too. - - - - Loopback testing from one port on a FPGA, CPLDs, - and micros isn't a good way to test ground - networks. When the signal gets to it's - destination, ground is already home. Use two - boards so ground currents flow the way they - will in the real world. - - - Cables to the outside world: alternate ground - and signal leads. - - - I have seen some crappy microboards that have - only 1 ground pin for all the I/O signals on - each I/O connector or worse, 1 ground pin - for the whole board. My last micro had one - ground for every signal. - - - If you are driving a long cable, make sure - your driver chip has enough ground pins - near the signals you are drivings. If you - drive 8 data lines across a 10ft cable with an - HC245, the ground bounce on the cable will - kill you. Use two separate chips or series - resistors. - - - Program micros (or CPLDs or FPGAs) to toggle - a whole bunch of pins in the same direction - at the same time to stress test your board. - Hang long cables off your I/O ports to stress - test it. When you aren't trying to stress - test your board, do the opposite. Program - the pins to not change at the same time if you - can. You can, for example, update every other - pin on an 8 bit data bus in two separate - operations instead of updating all 8 bits at - once if you are driving a cable and have - time to spare. Try to balance the number - of signals changing high to low and low to high. - Alternating 0xFF and 0x00 is worse than alternating - 0x55 and 0xAA. - - - Pros use differential signaling, for high speed - logic, long cables, and analog signals that - travel any distance. That is part of the - reason SATA is replacing ATA (IDE). Skew is the - another big part. Those are a big part of - why they can run SATA at 1.5, 3, and 6 megabits - per second over a single pair when they have - trouble pumping that same data at 133 mhz over - 16 parallel lines, even after adding 40 ground - wires. Likewise for PCI express replacing - PCI and AGP. - - - Just connecting everything together with - a ground plane or fat ground traces isn't - always good. Sometimes you need to deliberately - create gaps in your ground. You don't want - your digital signals returning through your - analog ground pins, for example. In some - cases, you stitch together with capacitors - to let AC through while blocking DC. - Single point grounds are often used, for example, - on A/D converters. - - - Murphy's law dictates that on a 1 or 2 layer board, - you will end up with the least fill in ground - plane where you need it the most. - - - On solderless or soldered breadboard patterns, - cross connect the ground buses with jumper wires - between the ICs. - - - Termination, characteristic impedence, and - transmission line effects for needs to be - looked at for fast edge rate signals. - - - clock skew and signal skew needs to be looked at - for high speed logic, especially synchronous logic - (where data is updated on the active clock edge). - For bush league designs, update your data and - clock your data on opposite edges of the clock. - Much easier on the signal routing. But you - lose 50% speed. PCB software should be - able to measure, and match trace length. - - - Lazy techs and junior engineers think this stuff - doesn't matter. You see lots of failed - prototypes as a result. - - - -Maybe you should borrow some code from PCB. It does -a much better job at handling solid copper fill.
-0 - - -2581380 -dickelbeck -1196874952 -
Logged In: YES -user_id=1222857 -Originator: NO - -Your title would have been enough. - -This bug report is a mess. It is 100 times too long - -This verbose text should have been posted to the user's list, with an http reference to a concise bug report. - -I agree fully (1000,000%) that zone support is inadequate. I am trying to find a way to improve it immediately, my highest priority. Jean-Pierre said it was at the top of his list, but I see no progress to date. So I am giving him a little more time to do it or give it up. - - -
- - -2891530 -manneveru -1219588432 -
Logged In: YES -user_id=639576 -Originator: NO - -The pcb.sourceforge.net has nice support for zones, you can adjust clearance between zone and track on-the-fly by K and Shift-K key. But tracks drawing is much better in pcbnew.
- - -3204260 -dickelbeck -1228757739 -
Maybe the newest code improves zones, so many of your issues are fixed. - -Don't know that anyone here needs to spend volunteer time taking the criticism however, so I am closing this. If there are still issues with zone, please submit them in smaller finer granularity without criticism. - -No one will read a 300 line bug report, especially one filled with criticism. - -
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=254934&aid= -254934 -junk1.brd - -97191 -application/octet-stream -1195471051 -whitis - - - - -5291683 -IP -Artifact Created: 67.76.175.5 -1195471051 -whitis - - -5291684 -File Added -254934: junk1.brd -1195471051 -whitis - - -5354131 -IP -Comment Added: 67.64.64.34 -1196874952 -dickelbeck - - -5354132 -resolution_id -100 -1196874952 -dickelbeck - - -5354133 -assigned_to -100 -1196874952 -dickelbeck - - -5354188 -priority -5 -1196875537 -dickelbeck - - -6413506 -IP -Comment Added: 213.134.171.113 -1219588432 -manneveru - - -7157813 -IP -Comment Added: 67.64.64.34 -1228757739 -dickelbeck - - -7157814 -status_id -1 -1228757739 -dickelbeck - - -7157815 -close_date -0 -1228757739 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=1834766 -1834766 -2 -100 -100 -102 -whitis -nobody -dickelbeck -1195504839 -1196875262 -5 -Fill zones a mess -
There are a lot of problems with fill zones. - - - Filling with traces is not a good way to do it. - You get crappy edges on diagonal edges, - around pads, etc. Even the program pcb does a - better job of this. - - - No thermals that I can see, even though "thermals" - is an option on fill. But how does the program - know what pads should get connected? And if you - draw thermals manually using traces (very tedious), - the program will probably avoid them next time - you zap and recrate the fill. Apparently, from - looking at the pic programmer, it does this via - the netlist. But it doesn't let you tell it what - net the plane belongs to (how does it guess or does - it just assume incorrectly it is ground). And - just because - a pad connects to ground does not mean you want a - thermal there. You may need to connect particular - pins to the ground system in very particular ways. - And what happens if the pad is so close to a trace that the normal thermal pattern would intersect the trace? - - - The program non-consensually creates an imaginary - fill zone line around its misconceived notion of the - board extents. It fails to include manually drawn - fill zones in this notion of the board extent. - If you have drawn a board edge, however, it - functions ok so it is Pins necessary to create a board - outline even if you don't know what the outline - is yet. - - - Fill zone does not fill up to and including zone - boundaries. Sometimes it draws outside the lines - but usually it leaves a gap based on the - "clearance" as if the zone margin was a trace. - You can set the clearance to zero but then you - get inadequate clearance around traces. - - - Fill zone avoids imaginary objects that only it - can see. You can't see or edit these objects. - They are apparently stray fill zone boundary - segments from fill zones that were drawn but never - closed. They do sometimes appear temporarily - while you are drawing a new fill boundary, if - you trigger a redraw with the scroll wheel - (zoom). They go away when you answer yes to - "delete current edge zone" but that deletes - all the useful edges as well. It is really easy - to end up with a dozen of these imaginary - edge zones in a few minutes by aborting drawing - a zone boundary or segment. You get them by - drawing one too many edges before you hit - "end zone". You get them by clicking the mouse - not realizing you are in zone mode. Even when - you trick the program into displaying them, they - can't be deleted? - - - - The program is way to cavalier about deleting - zone edges. It constantly asks you if you - want to delete them. And sometimes you have to - delete them to clean up the mess left behind. - This is REALLY BAD. Those edges could have taken - hours to draw on a decent board with lots of fill. - Would you consider it acceptable for the program - to delete all your traces, or worse yet force you - to delete them to clean up the programs mess, - so easily? - - - Is there any documentation on fill zones? The - broken help viewer with no search function makes - it very hard to tell. - - - sometimes delete zone deletes the zone edge - instead of the fill. Well, it doesn't completely - go away, it just becomes one of the invisable - phantom edges. The rectangular cutout between - the two SSOP28 modules in the attached file is one - example. - - - Even when you say yes to delete zone edges, it doesn't get rid of some of the bad ones even though it does get rid of some of the good ones. - - - If I delete the "zone" on the pic programmer, and try to refill it, it deletes the thermals and doesn't put them back. And furthermore, it only fills in -one small area, not the whole board. It treats the -existing ground traces as boundaries. - -The attached file has at least 7 phantom edge segments that aren't supposed to be plus one phantom rectangle that is supposed to be there but is invisible. - -Warning: I am going to critique some of the sample board layouts. Disengage ego. I was looking at them to figure out if you had somehow managed to do any decent ground/power/signal planes with the software. Well, the boards look like they were laid out by a technician, not an engineer. Some cleverness in playing connect the dots but from a signal integrity perspective, they suck. Lots of copper in ground planes but not where it needs to be. Ground planes as an afterthought, not designed in. It is "would you believe its a ground plane? No? Well would you believe I am saving a lot of etchant by leaving copper on the board?". The program apparently is unusable for serious ground plane (or other fill work) because the programmers haven't done ground right. They look impressive to the untrained eye. - -A lot of real boards can have multiple power planes for different nets on the same layer along with signals that are drawn like planes for better impedence. And sometimes the planes are joined in certain specific locations. They aren't simple (from a zone perspective) like interf_u.brd. In fact, the "ground plane" on interf_u is a joke. It doesn't actually connect to anything as far as I can tell. It might actually create crosstalk and make the board worse off. -Ground is carried by traces that are too small. And the decoupling capacitors are likely to have to high high frequency impedence. Is this a real board? Does it actually work? sonde_xilinx contains another ground plane that is connected to a few pins without thermals. -Aha, you "select net", then fill. That sort of works but it also fills in the left D connector. And now I can't find a way to unselect the net. test_xil_95108 contains, again, only one net as a plane. And ground distrubution to the CPLD is not so good. VCC and ground should be planes on opposite layers. Was this a non-plated through hole board? If so, maybe a few jumpers under the CPLD socket are in order. Or better yet, use machined pin socket and solder the VCC pins on the top. Pretend you are an electron trying to get from the ground pin on the RAM to the CPLD. It is a 6" journey through two vias or a 4" journey though two throughholes (the regulator pin). You are on shaky ground (no pun intended) with a JEDEC ram pinout that only has one ground pin for two dozen signal pins (bouncy bouncy bouncy). And ground on the TDA8702 which should have run 0.4" to pin 60 (where is the via to the red ground trace next to pin 60????) has to travel half the circumference of the board to get to pin 16 on the CPLD or through two vias and a skinny red trace and squeeze between two pins before it can get to pin 42. Why wasn't the red trace from U2:49 to U1:6 not fattened? And why does it detour around a via that could have been moved instead of cutting the corner? Just because you flood a lot of copper on the board doesn't mean you have a decent ground. Pins 14,15,17,18,19,20, 21, 23, and 57 are all unused. If they had been tied to ground, you would have more channels to route ground through. Better yet, distribute them more evenly around the chip so you can make channels where you need them, like pins 30 and 29 where you desperately need one. Since the outdated JEDEC RAM pinout won't let you run ground traces between the pins, fat ground traces should have -hugged the top and bottom signal traces. And you -had lots of room on the component side to run ground. -Especially to pins 49 and 42, even if you have to -stitch across the TDO line. And, shit, the TDO line should not have been routed between the CPLD and the RAM at all. Run TDO around the periphery of the -board, not ground. And you might have avoided breaking ground in a critical place for the jtag signals - via those over ground. And a ground trace could have been squeezed between pins 15, 16, and 17 of the RAM. Better yet, you should have put the ground plane on the component side of the board where it would have done some good. Also, when you break a ground plane to run a long trace through it, you are supposed to stitch the two broken pieces together with a traces on the opposite side (that red trace from pin 59 is problematic). Pin 49 is on stich, you need another near pin 42 and one near pin 32. Fill the area on the bottom layer under the CPLD with VCC and fill the top (entire board) with GND and stitch. If you don't have through hole plating when prototyping, use individual screw machine IC socket pins (use the IC as a carrier while you are soldering the bottom and flatten out the leads of a dip and use it to hold pins in place while you solder the top or get a socket that has no fill in the middle. - -Some grounding tips: - - Ground is usually the most important signal on - the board and often neglected. - - - High speed logic needs good ground layouts even - when clocked at 1hz. It isn't the frequency - that matters, it is the edge rate. - - - Program CPLDs and FPGAs for the slowest edge rate - you can use. Many micros let you do this too. - If the chip won't let you do this, consider - series resistors on long traces, when driving - cables, etc. Use a slow logic family to get - slow edge rates. - - - At high frequencies, ground currents returning - from a signal do not take the shortest route, they - take the route that most nearly follows the path - of the original signal. This is one reason - ground planes directly under the signal really - help. If you can't run a ground plane there, - run some individual grounds between the signals. - Think like an electron; electrons do. - - - For every signal, pretend you are an electron - traveling in a loop through the signal traces and - back through ground. How many inches did you - have to travel? How far did you have to deviate - from your original path on the return trip? How - many vias? How many tight squeezes? The - bigger the area between the two paths the more EMI - you generate, the more you are susceptible to - external EMI, the more ground bounce you have, - and signal integrity is poorer. - - - FPGAs and CPLDs are great. They let you move pins - to facilitate PCB layout. Use this not just for - signals but to improve ground as well. - Where possible, tie unused signals on ICs to - ground and use that to create a channel to route - ground under that pin. Also, on some CPLD/FPGA you - can configure that pin as an extra ground or - at least drive a 0 onto the pin so ground - currents have an extra path through the output FET. - Move signals on your CPLD/FPGA to make room for - ground. - - - consider using a physical layout schematic symbol - for your programmable logic. It will help you - choose signal pins that are easy to route and it - is easier to plan for extra ground routes. - - - When you break a ground plane to run a trace - perpendicular to high speed signals, stitch - the two pieces together with traces across the - break and multiple parallel vias (for example, - two vias on each side of the break). - - - VCC and ground on opposite planes work great. - You get a lot of distributed capacitance. Ideally, - the whole board would be like this is one reason - why people pay for 4 layer boards. But if you - are using a two sided board, you can still do - this under your micros and programmable logic - and other high speed ICs. It isn't just your - external signals to be concerned about, ground - currents from internal logic needs help, too. - - - - Loopback testing from one port on a FPGA, CPLDs, - and micros isn't a good way to test ground - networks. When the signal gets to it's - destination, ground is already home. Use two - boards so ground currents flow the way they - will in the real world. - - - Cables to the outside world: alternate ground - and signal leads. - - - I have seen some crappy microboards that have - only 1 ground pin for all the I/O signals on - each I/O connector or worse, 1 ground pin - for the whole board. My last micro had one - ground for every signal. - - - If you are driving a long cable, make sure - your driver chip has enough ground pins - near the signals you are drivings. If you - drive 8 data lines across a 10ft cable with an - HC245, the ground bounce on the cable will - kill you. Use two separate chips or series - resistors. - - - Program micros (or CPLDs or FPGAs) to toggle - a whole bunch of pins in the same direction - at the same time to stress test your board. - Hang long cables off your I/O ports to stress - test it. When you aren't trying to stress - test your board, do the opposite. Program - the pins to not change at the same time if you - can. You can, for example, update every other - pin on an 8 bit data bus in two separate - operations instead of updating all 8 bits at - once if you are driving a cable and have - time to spare. Try to balance the number - of signals changing high to low and low to high. - Alternating 0xFF and 0x00 is worse than alternating - 0x55 and 0xAA. - - - Pros use differential signaling, for high speed - logic, long cables, and analog signals that - travel any distance. That is part of the - reason SATA is replacing ATA (IDE). Skew is the - another big part. Those are a big part of - why they can run SATA at 1.5, 3, and 6 megabits - per second over a single pair when they have - trouble pumping that same data at 133 mhz over - 16 parallel lines, even after adding 40 ground - wires. Likewise for PCI express replacing - PCI and AGP. - - - Just connecting everything together with - a ground plane or fat ground traces isn't - always good. Sometimes you need to deliberately - create gaps in your ground. You don't want - your digital signals returning through your - analog ground pins, for example. In some - cases, you stitch together with capacitors - to let AC through while blocking DC. - Single point grounds are often used, for example, - on A/D converters. - - - Murphy's law dictates that on a 1 or 2 layer board, - you will end up with the least fill in ground - plane where you need it the most. - - - On solderless or soldered breadboard patterns, - cross connect the ground buses with jumper wires - between the ICs. - - - Termination, characteristic impedence, and - transmission line effects for needs to be - looked at for fast edge rate signals. - - - clock skew and signal skew needs to be looked at - for high speed logic, especially synchronous logic - (where data is updated on the active clock edge). - For bush league designs, update your data and - clock your data on opposite edges of the clock. - Much easier on the signal routing. But you - lose 50% speed. PCB software should be - able to measure, and match trace length. - - - Lazy techs and junior engineers think this stuff - doesn't matter. You see lots of failed - prototypes as a result. - - - -Maybe you should borrow some code from PCB. It does -a much better job at handling solid copper fill.
-0 - - -2581399 -dickelbeck -1196875262 -
Logged In: YES -user_id=1222857 -Originator: NO - -duplicate of 1834473
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=255012&aid= -255012 -junk1.brd - -97191 -application/octet-stream -1195504839 -whitis - - - - -5293948 -IP -Artifact Created: 67.76.175.5 -1195504839 -whitis - - -5293949 -File Added -255012: junk1.brd -1195504839 -whitis - - -5354170 -IP -Comment Added: 67.64.64.34 -1196875262 -dickelbeck - - -5354171 -status_id -1 -1196875262 -dickelbeck - - -5354172 -resolution_id -100 -1196875262 -dickelbeck - - -5354173 -close_date -0 -1196875262 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=1844278 -1844278 -2 -761682 -755198 -3 -nobody -nobody -dickelbeck -1196794205 -1196874218 -5 -ANSI C++ code broken -
cotation.cpp:133 -> unresolved ambiguity for auto casting at atan2(...) -graphpcb:694 ->unresolved ambiguity for auto casting at atan2(...) - -One must force the cast of at least one parameter for the C++ compiler beeing able to choose the right function: -atan2( (float)...) -
-0 - - -2581347 -dickelbeck -1196873881 -
Logged In: YES -user_id=1222857 -Originator: NO - -a duplicate of 1844285 -
- - - - - - -5350127 -IP -Artifact Created: 217.226.108.197 -1196794205 -nobody - - -5353994 -IP -Comment Added: 67.64.64.34 -1196873881 -dickelbeck - - -5353995 -resolution_id -100 -1196873881 -dickelbeck - - -5353999 -resolution_id -105 -1196873947 -dickelbeck - - -5354039 -status_id -1 -1196874218 -dickelbeck - - -5354040 -close_date -0 -1196874218 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=1844285 -1844285 -2 -1015285 -755198 -3 -lainal -nobody -sf-robot -1196794647 -1198120809 -5 -ANSI C++ code broken -
*** libcmp.h:128-> suppress the trailing "," after the last member :PIN_DOWN, => PIN_DOWN -*** locate.cpp:880/843-> unresolved ambiguity for auto casting at sqrt(...) -*** symbdraw.cpp:584/768 ->unresolved ambiguity for auto casting at sqrt(...) -*** symbdraw.cpp:754/770/775 ->unresolved ambiguity for auto casting at atan2(...) -*** cleanup.cpp:259/260 ->unresolved ambiguity for auto casting at atan2(...) - -One must force the cast of at least one parameter for the C++ compiler beeing able to choose the right function: -atan2( (float)...) - -Prevent the target to compile on non-G++ compilers.
-0 - - -2581346 -nobody -1196873712 -
Logged In: NO - -The developers that I am aware of are all using g++. - -If you want to create a patch and add it as an attachment you are then a developer which uses a compiler other than g++, and as I said, we don't have any of those currently. - -So it is for you to fix, as the current crew is supporting g++ only. Only you can change that. -
- - -2605272 -sf-robot -1198120809 -
Logged In: YES -user_id=1312539 -Originator: NO - -This Tracker item was closed automatically by the system. It was -previously set to a Pending status, and the original submitter -did not respond within 14 days (the time period specified by -the administrator of this Tracker).
- - - - - - -5350189 -IP -Artifact Created: 217.226.108.197 -1196794647 -lainal - - -5353993 -IP -Comment Added: 67.64.64.34 -1196873712 -nobody - - -5354042 -status_id -1 -1196874271 -dickelbeck - - -5354043 -resolution_id -100 -1196874271 -dickelbeck - - -5354044 -close_date -0 -1196874271 -dickelbeck - - -5418052 -IP -Comment Added: -1198120809 -sf-robot - - -5418053 -status_id -4 -1198120809 -sf-robot - - -5418054 -close_date -1196874271 -1198120809 -sf-robot - - - - -http://sourceforge.net/support/tracker.php?aid=1844960 -1844960 -2 -761682 -755196 -1 -dickelbeck -charras -dickelbeck -1196875421 -1196986181 -3 -F1 after a FIND -
If you use the find dialog to find a part using reference number. Then immediately press F1 to zoom at that location (without moving the mouse in between), the cursor is jumping to someplace else. - -If you move the mouse just a little after the find but before the F1, then the cursor stays put. -
-0 - - -2581421 -dickelbeck -1196877128 -
Logged In: YES -user_id=1222857 -Originator: YES - -I tracked it down using D(printf();) in - -pcbnew/controle.cpp - -to this line: - - GetScreen()->m_Curseur = curpos; - -And curpos is coming from - - curpos = DrawPanel->CursorRealPosition( Mouse ); - -Please help.
- - -2583117 -dickelbeck -1196986181 -
Logged In: YES -user_id=1222857 -Originator: YES - -Jean-Pierre fixed this today. Bug was also in eeschema, also fixed now.
- - - - - - -5354182 -IP -Artifact Created: 67.64.64.34 -1196875422 -dickelbeck - - -5354293 -IP -Comment Added: 67.64.64.34 -1196877128 -dickelbeck - - -5359585 -IP -Comment Added: 67.64.64.34 -1196986181 -dickelbeck - - -5359586 -status_id -1 -1196986181 -dickelbeck - - -5359587 -resolution_id -100 -1196986181 -dickelbeck - - -5359588 -close_date -0 -1196986181 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=1845333 -1845333 -2 -761682 -100 -103 -nobody -charras -jerryjacobs -1196925468 -1267478894 -5 -one size via -
For a board I can make many different via. But when drill file was made only one size for all via set. - -When I use more the 8 different via, program lost last size.
-0 - - -3917392 -jerryjacobs -1267478894 -
Net classes to manage dimensions and settings added with last version.
- - - - - - -5356106 -IP -Artifact Created: 217.150.32.243 -1196925468 -nobody - - -5359595 -resolution_id -100 -1196986276 -dickelbeck - - -5359596 -priority -5 -1196986276 -dickelbeck - - -5359597 -assigned_to -100 -1196986276 -dickelbeck - - -9227679 -IP -Comment Added: 84.25.204.235 -1267478894 -jerryjacobs - - -9227680 -status_id -1 -1267478894 -jerryjacobs - - -9227681 -resolution_id -102 -1267478894 -jerryjacobs - - -9227682 -allow_comments -1 -1267478894 -jerryjacobs - - -9227683 -close_date -0 -1267478894 -jerryjacobs - - -9227684 -priority -7 -1267478903 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=1867321 -1867321 -1 -1015285 -755196 -100 -wolverine222 -nobody -nobody -1199839703 -0 -5 -PADS netlist generator not working -
When generating a PADS netlist from a hierarquical schematic only the parts in the top schematic appear in the netlist. All the nets appear correctly, only the parts are missing. - -I've searched a bit and saw that a temporary file is generated from wich the PADS netlist is created. That file is missing the parts too (or already, according to the process). - -I attached an example of a netlist generated. you can see that there are nets that refer parts wich are not defined.
-0 - - -2635175 -ckgrier2 -1200507643 -
Logged In: YES -user_id=1921682 -Originator: NO - -Have you tried multiple versions of KiCad to see if this is isolated to newer releases? Are you using Win32?
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=261412&aid= -261412 -example.net -Just an example of the problem -5104 -application/octet-stream -1199839703 -wolverine222 - - - - -5486957 -IP -Artifact Created: 89.180.104.94 -1199839703 -wolverine222 - - -5486958 -File Added -261412: example.net -1199839704 -wolverine222 - - -5519721 -IP -Comment Added: 68.217.12.91 -1200507643 -ckgrier2 - - - - -http://sourceforge.net/support/tracker.php?aid=1873100 -1873100 -2 -1015287 -100 -100 -mungewell -nobody -dickelbeck -1200507258 -1228758121 -5 -Corrupted gerbv image - elements not shown properly -
Hi all, -I've been using Kicad for a while in a 'mucking around' sense, supporting the capture and layout done by contractors of ours. - -I have noticed that gerbv is failing to correctly represent gerbers that they have sent for inspection. The gerbers were created by Protel DXP. - -What appears to be happening is that a single gerber layer contains multiple elements which should be 'xor'ed drawn to create image, however gerbv is 'or'ing the elements together to produce a solid block of colour. - -I have attached a screen shot to my files showing the issue. - -The hidden elements of the gerber are visible as the gerbv layer is zoomed in/out, suggesting that they are drawn and then overdrawn/masked by other elements in the layer. - -On the left in the screenshot is another 'free' (beer) viewer which correctly renders the same layer. It has a mode setting 'colours merged' which will result in the same 'solid block' output as gerbv, normal setting is 'colours solid'. - -Cheers, -Mungewell.
-0 - - -2637081 -dickelbeck -1200585043 -
Logged In: YES -user_id=1222857 -Originator: NO - -I noticed you are using a 12-Jan-06 version of Kicad's Gerbview, correct? - -Please verify that the problem exists on the newest release. -
- - -2653036 -mungewell -1201742381 -
Logged In: YES -user_id=39509 -Originator: YES - -The latest Windows version (2007-11-29) of Kicad/Gerbview also shows this problem. I am attempting to view gerbers generated by Protel DXP. I will attach a small example gerber. - -It looks like the flood fill is 'OR'ing areas rather than 'XOR'ing. Clicking the 'Show polygons in sketch mode' shows the individual elements of the design. -Mungewell.
- - -2653037 -mungewell -1201742443 -
Logged In: YES -user_id=39509 -Originator: YES - -File Added: SCT_SC1302vc.GTL
- - -3204277 -dickelbeck -1228758121 -
I am also seeing things like this and plan to fix it within the next 30 days or so. - -Dick -
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=262474&aid= -262474 -gerbv_failure.PNG -screeenshot showing issue -86260 -image/png -1200507258 -mungewell - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=264393&aid= -264393 -SCT_SC1302vc.GTL -Example gerber showing problem -11466 -application/octet-stream -1201742443 -mungewell - - - - -5519685 -IP -Artifact Created: 68.146.205.60 -1200507258 -mungewell - - -5519686 -File Added -262474: gerbv_failure.PNG -1200507260 -mungewell - - -5524196 -IP -Comment Added: 67.64.64.34 -1200585043 -dickelbeck - - -5574453 -IP -Comment Added: 68.146.205.60 -1201742381 -mungewell - - -5574454 -File Added -264393: SCT_SC1302vc.GTL -1201742443 -mungewell - - -5574455 -IP -Comment Added: 68.146.205.60 -1201742443 -mungewell - - -7157862 -IP -Comment Added: 67.64.64.34 -1228758121 -dickelbeck - - -7157863 -status_id -1 -1228758121 -dickelbeck - - -7157864 -close_date -0 -1228758121 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=1874663 -1874663 -2 -761682 -100 -100 -linuxcart -nobody -linuxcart -1200664792 -1200999964 -5 -Pad net assignation not working. -
Hello: - -I'm using kicad build from svn(20080110) and I have this problem: - -I place a footprint with 2 pads only used for mechanical stability. They should be solded but they don't need to belong to any net. - -I want to assign them to the ground net in the pcbnew editor. In order to do this I right click on the pad, and in the pad submenu I choose edit pad. - -I write GND(ground net name) in the net field and press ok in that dialog. - -If I open the pad edit dialog again the GND field is correct but if I try to route that pad is not realising that it's bound to the GND net. I've used the routing tool and the net highlight tool. - -A workaround is changing the pad net, exiting pcbnew and starting it again. - -Thanks.
-0 - - -2642323 -linuxcart -1200999963 -
Logged In: YES -user_id=1667631 -Originator: YES - -This bug is solved in development version dated 21st January, revision 662. - -Checkout here and seems to work. - -Thanks.
- - - - - - -5528577 -IP -Artifact Created: 87.218.11.210 -1200664792 -linuxcart - - -5541395 -IP -Comment Added: 87.218.11.210 -1200999963 -linuxcart - - -5541396 -status_id -1 -1200999964 -linuxcart - - -5541397 -close_date -0 -1200999964 -linuxcart - - - - -http://sourceforge.net/support/tracker.php?aid=1875712 -1875712 -2 -761682 -100 -100 -nobody -nobody -jerryjacobs -1200826020 -1267475861 -5 -Lost pads on postscript plot -
With PCBNEW i have some invisible pads on the postscript plot. There is no such problem in printing or 3D mode. - -The pads are elliptic (size: 0.1x0.2). It is not systematic. Some other pads of this shape are visible (same module type, other part reference). - -A workaround for me was changing the pads shape from elliptic to round. - - -System: -PCBNEW (2007-07-09) installed under Fedora8 - - -Thanks for this nice piece of software. - -Br, -Oliver
-0 - - -2640436 -nobody -1200833671 -
Logged In: NO - -Little remark: - -Only in filled mode these pads are not visible. If you change the plot mode to outline plot the lost pads are visible again. - -Br, -Oliver
- - -2727776 -pixostat -1207212768 -
Logged In: YES -user_id=2053322 -Originator: NO - -I found same problem (on PCBNEW 2008-02-20 Unicode and 2007-10-29 Unicode installed over Win XP Prof SP2). -The same workaround was for me good. -These pads are visible on normally print preview, on gerber files also but lost only in filled postscript plot. -There is no dependency on negativ/positiv plot. -I'm not sure but it looks that there are diferrence between cooper and component layers. -Same pads like on component layer are lost on both solder mask layers. -I found these lost pads only in multipin components (modules with 16 and 48 pin). -Lost pads was eliptic shape with baddly set diameter to 120milx120mil - when I corected it to round shape all goes OK. -When I change diameter of one of those critical pads to x=120mil and y=200mil - the pad is still lost, but in place of that pad are ploted two very thin vertical lines of summary lenght smaller than y size of pad (maby it was one line divided into two by drill in pad). -If I good remember, some time ago it has been similiar error with plot of square pads of SMD modules. -
- - -3917337 -jerryjacobs -1267475823 -
Closing old bug
- - - - - - -5533859 -IP -Artifact Created: 77.186.12.144 -1200826020 -nobody - - -5534096 -IP -Comment Added: 77.186.12.144 -1200833671 -nobody - - -5852681 -IP -Comment Added: 83.22.21.218 -1207212768 -pixostat - - -9227425 -IP -Comment Added: 84.25.204.235 -1267475823 -jerryjacobs - - -9227426 -status_id -1 -1267475861 -jerryjacobs - - -9227427 -allow_comments -1 -1267475861 -jerryjacobs - - -9227428 -close_date -0 -1267475861 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=1883241 -1883241 -2 -1015285 -100 -100 -nobody -nobody -dickelbeck -1201752639 -1201870380 -5 -Can`t create new library file. -
KiCad (2007-11-19) - Unicode version -Debian Etch/Lenny - -When I open symbol editor for make new symbol. I can`t save created symbol into new library via button named as "Create a new library an save current component into". Program not do anythink. A can save new symbol only into exist library. - -In old version it works well. -
-0 - - - - - - -5575194 -IP -Artifact Created: 81.9.81.5 -1201752639 -nobody - - -5580223 -status_id -1 -1201870379 -dickelbeck - - -5580224 -close_date -0 -1201870380 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=1889107 -1889107 -2 -1015285 -100 -103 -sb-sf -nobody -stambaughw -1202421356 -1268752334 -5 -Libedit: mouse pointer jumps -
Windows version 2007-11-29. Clicking on "show as de Morgan normal part" or "show as deMorgan converted part" icon causes mouse pointer to jump to another icon - "auto zoom", "zoom -" or another.
-0 - - -2661823 -sb-sf -1202421939 -
Logged In: YES -user_id=1653090 -Originator: YES - -actally mouse pointer jumps to cursor ("cross") position, which can be below icons when 50 mils grid selected.
- - -3931576 -stambaughw -1268752334 -
Problem doesn't exist in release 2010-03-14 (svn-R2456)
- - - - - - -5604877 -IP -Artifact Created: 194.19.225.133 -1202421356 -sb-sf - - -5604912 -IP -Comment Added: 194.19.225.133 -1202421940 -sb-sf - - -9290213 -IP -Comment Added: 162.83.115.135 -1268752334 -stambaughw - - -9290214 -status_id -1 -1268752334 -stambaughw - - -9290215 -resolution_id -100 -1268752334 -stambaughw - - -9290216 -allow_comments -1 -1268752334 -stambaughw - - -9290217 -close_date -0 -1268752334 -stambaughw - - - - -http://sourceforge.net/support/tracker.php?aid=1896790 -1896790 -2 -1015285 -516020 -1 -klui_ -stambaughw -stambaughw -1203414023 -1235595423 -5 -Ctrl-Z affects background eeSchema instead of library editor -
Also after mouse pressed "undo" button mouse cursor jumps into working area in library editor.
-0 - - -2731753 -diemer -1207504422 -
Logged In: YES -user_id=154672 -Originator: NO - -Confirmed for svn r970: Ctrl-Z in libedit affects the eeschema, not the library.
- - -3551124 -stambaughw -1235595423 -
This bug has been fixed
- - -3551125 -stambaughw -1235595423 -
Fixed in SVN 1619.
- - - - - - -5656286 -IP -Artifact Created: 217.26.177.9 -1203414023 -klui_ - - -5867374 -IP -Comment Added: 82.83.218.100 -1207504422 -diemer - - -7793808 -IP -Comment Added: 162.83.115.135 -1235595423 -stambaughw - - -7793809 -IP -Comment Added: 162.83.115.135 -1235595423 -stambaughw - - -7793810 -status_id -1 -1235595423 -stambaughw - - -7793811 -assigned_to -100 -1235595423 -stambaughw - - -7793812 -allow_comments -1 -1235595423 -stambaughw - - -7793813 -close_date -0 -1235595423 -stambaughw - - -7793816 -resolution_id -100 -1235595466 -stambaughw - - - - -http://sourceforge.net/support/tracker.php?aid=1909165 -1909165 -2 -761682 -100 -1 -nobody -nobody -jerryjacobs -1204847492 -1267476220 -5 -Spurious lines in postscript output -
When I plot my circuit I get a spurious line in the output. Looking at the postscript there are actually about 10 lines very close together near the top of the output starting at about 8050,7700.
-0 - - -2699096 -nobody -1204847546 -
Logged In: NO - -Sorry, forgot to mention I'm using PCBNEW (2007-05-25) - Unicode version
- - -3917342 -jerryjacobs -1267476220 -
This bug has been fixed
- - -3917343 -jerryjacobs -1267476220 -
Closing old bug works for newer version.
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=269389&aid= -269389 -Piezo Preamp.zip -File that creates the offending output -9111 -application/zip -1204847492 -nobody - - - - -5728806 -IP -Artifact Created: 84.92.181.41 -1204847492 -nobody - - -5728808 -File Added -269389: Piezo Preamp.zip -1204847492 -nobody - - -5728810 -IP -Comment Added: 84.92.181.41 -1204847546 -nobody - - -9227450 -IP -Comment Added: 84.25.204.235 -1267476220 -jerryjacobs - - -9227451 -IP -Comment Added: 84.25.204.235 -1267476220 -jerryjacobs - - -9227452 -status_id -1 -1267476220 -jerryjacobs - - -9227453 -resolution_id -100 -1267476220 -jerryjacobs - - -9227454 -allow_comments -1 -1267476220 -jerryjacobs - - -9227455 -close_date -0 -1267476220 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=1910828 -1910828 -2 -1015285 -755198 -1 -nobody -nobody -diemer -1205126316 -1207503771 -5 -Missing pin on FPGA XC3S400PQ208 -
Pin 46 (IO_L19P_6) is missing in the kicad/library/xilinx.lib file. -Attached is a corrected version. - -Just hoping to spare anyone else from a mishap.. -
-0 - - -2731749 -diemer -1207503771 -
Logged In: YES -user_id=154672 -Originator: NO - -This bug has been fixed
- - -2731750 -diemer -1207503771 -
Logged In: YES -user_id=154672 -Originator: NO - -Fixed in svn r926
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=269742&aid= -269742 -XC3S400-PQ208.lib -Corrected XC3S400-PQ208 -10093 -application/octet-stream -1205126316 -nobody - - - - -5739363 -IP -Artifact Created: 81.227.98.60 -1205126316 -nobody - - -5739364 -File Added -269742: XC3S400-PQ208.lib -1205126316 -nobody - - -5867344 -IP -Comment Added: 82.83.218.100 -1207503771 -diemer - - -5867345 -IP -Comment Added: 82.83.218.100 -1207503771 -diemer - - -5867346 -status_id -1 -1207503771 -diemer - - -5867347 -resolution_id -100 -1207503771 -diemer - - -5867348 -artifact_group_id -100 -1207503771 -diemer - - -5867349 -close_date -0 -1207503771 -diemer - - - - -http://sourceforge.net/support/tracker.php?aid=1914445 -1914445 -2 -1015285 -755198 -3 -fhsplitt -lifekidyeaa -diemer -1205515332 -1207501101 -5 -Old EESCHEMA cannot handle 20080312-r884 schematic -
Hi, - -under Windows XP, EESCHEMA ver. 2007-11-29-c aborts with an error message ("Component & position error at line 100, aborted") when attempting to open a schematic modified with EESCHEMA ver. 20080312-r884. - -Regards, - -Fred
-0 - - -2728513 -diemer -1207250167 -
Logged In: YES -user_id=154672 -Originator: NO - -It looks like the EESCHEMA file format has changed around SVN r750 (February 2008), due to changes regarding GLabels and Hierarchich Scheets. Seems like we have lost backwards-compatibility there. - -I don't know if it is possible to regain backwards compatibility though. We should at least improve handling of newer file formats, printing out a proper warning.
- - -2731707 -diemer -1207501101 -
Logged In: YES -user_id=154672 -Originator: NO - -This bug has been fixed
- - -2731708 -diemer -1207501101 -
Logged In: YES -user_id=154672 -Originator: NO - -EESchema now warns on a file format version mismatch. There probably won't be an export to an older file format, as people can simply upgrade their KiCAD.
- - - - - - -5759050 -IP -Artifact Created: 84.188.119.251 -1205515332 -fhsplitt - - -5855932 -IP -Comment Added: 82.83.225.88 -1207250167 -diemer - - -5855933 -category_id -100 -1207250167 -diemer - - -5855934 -assigned_to -100 -1207250167 -diemer - - -5867199 -IP -Comment Added: 82.83.218.100 -1207501101 -diemer - - -5867200 -IP -Comment Added: 82.83.218.100 -1207501101 -diemer - - -5867201 -status_id -1 -1207501101 -diemer - - -5867202 -resolution_id -100 -1207501101 -diemer - - -5867203 -artifact_group_id -100 -1207501101 -diemer - - -5867204 -close_date -0 -1207501101 -diemer - - - - -http://sourceforge.net/support/tracker.php?aid=1915932 -1915932 -1 -761682 -100 -100 -a-lunev -nobody -nobody -1205709579 -0 -5 -problem with fractional numbers editing -
Fractional numbers are displayed in the following format: integer part point fractional part. For instance 1.05 is displayed. -If I try to edit 1.05 to e.g. 1.06 the result is incorrect. The only way to change it to 1.06 is to enter 1,06. I.e. a comma instead of point.
-0 - - -2708667 -a-lunev -1205709778 -
Logged In: YES -user_id=1930733 -Originator: YES - -It appears in PCBNEW.
- - -2729555 -nobody -1207323646 -
Logged In: NO - -PLEASE CORRECT THIS BUG!!! pherhaps is only a compiling problem! It's very annoying! I still use the older versions for this bug, and so, I can't try new versions. - -
- - - - - - -5766036 -IP -Artifact Created: 89.19.165.61 -1205709580 -a-lunev - - -5766041 -IP -Comment Added: 89.19.165.61 -1205709779 -a-lunev - - -5859718 -IP -Comment Added: 151.57.45.144 -1207323647 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1918746 -1918746 -2 -1015285 -755198 -1 -raburton -nobody -raburton -1205873804 -1206900315 -5 -eeschema: extremely slow redraw when grid is turned on -
Forwarded from: http://bugs.debian.org/469516 - -Information from original submitter: - -- Start eeschema. -- Switch on the grid (button to top left of viewport). -- Move another window in front and force eeschema to redraw. - -Redrawing pegs both CPUs on my dual-processor system at 100% for several -seconds at a time. -A little investigation using 'xtrace' shows that eeschema performs -one SetClipRectangles and one PolyPoint request for EVERY SINGLE -grid point. - -
-0 - - -2723164 -diemer -1206895886 -
Logged In: YES -user_id=154672 -Originator: NO - -Hi, - -I just tried the latest SVN revision 948, and it seems way faster than an -older version I tried (2007-05-25). It still takes some noticeable fractions -of a second to redraw, but it's much better. - -Bug Fixed? - -Best regards -Jonas
- - -2723217 -raburton -1206900314 -
Logged In: YES -user_id=1213654 -Originator: YES - -This bug has been fixed
- - -2723218 -raburton -1206900315 -
Logged In: YES -user_id=1213654 -Originator: YES - -Does appear to be much improved. Thanks Dick!
- - - - - - -5778090 -IP -Artifact Created: 81.86.139.246 -1205873804 -raburton - - -5833865 -IP -Comment Added: 82.83.232.41 -1206895886 -diemer - - -5833866 -status_id -1 -1206895886 -diemer - - -5833867 -resolution_id -100 -1206895886 -diemer - - -5833868 -close_date -0 -1206895886 -diemer - - -5834059 -IP -Comment Added: 81.86.139.246 -1206900315 -raburton - - -5834060 -IP -Comment Added: 81.86.139.246 -1206900315 -raburton - - -5834061 -status_id -4 -1206900315 -raburton - - -5834062 -close_date -1206895886 -1206900315 -raburton - - - - -http://sourceforge.net/support/tracker.php?aid=1924526 -1924526 -2 -1015285 -755196 -1 -nobody -nobody -diemer -1206382642 -1206891172 -5 -window crashes when right clicking -
Kicad 20080320-r918 binary for Linux. running on SuSE10.0 - -When selecting component values to move or rotate, for example resistor values, normally depicted R in centre of the component, by right clicking on the schematic part the whole window crashes.
-0 - - -2716468 -nobody -1206390557 -
Logged In: NO - -Solved in 20080321 version (jp Charras)
- - -2723119 -diemer -1206891172 -
Logged In: YES -user_id=154672 -Originator: NO - -closing bug, jp fixed it.
- - - - - - -5807111 -IP -Artifact Created: 213.41.157.207 -1206382642 -nobody - - -5807613 -IP -Comment Added: 86.219.151.178 -1206390558 -nobody - - -5833734 -IP -Comment Added: 82.83.232.41 -1206891172 -diemer - - -5833735 -status_id -1 -1206891172 -diemer - - -5833736 -resolution_id -100 -1206891172 -diemer - - -5833737 -close_date -0 -1206891172 -diemer - - - - -http://sourceforge.net/support/tracker.php?aid=1925399 -1925399 -2 -761682 -516020 -103 -strangeril -nobody -jerryjacobs -1206467671 -1267477100 -5 -Pad displacement after changing its' diameter in mm -
When I change grid to milimeters and want to change pad diameter operation results in pad displaced from its' original position and also disconnected from its' net. -Only Windows version, reported to me that error occurs since r880. Tested on r931, error reproduced. - -In inch grid the same operation results in error message "Incorrect value for pad offset" although offset was not changed.
-0 - - -3917360 -jerryjacobs -1267477100 -
Works with newer (version) revision.
- - - - - - -5812339 -IP -Artifact Created: 213.211.40.159 -1206467671 -strangeril - - -9227547 -IP -Comment Added: 84.25.204.235 -1267477100 -jerryjacobs - - -9227548 -status_id -1 -1267477100 -jerryjacobs - - -9227549 -resolution_id -100 -1267477100 -jerryjacobs - - -9227550 -allow_comments -1 -1267477100 -jerryjacobs - - -9227551 -close_date -0 -1267477100 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=1929364 -1929364 -2 -1015285 -100 -1 -diemer -nobody -diemer -1206883167 -1207082901 -5 -Undo of "Delete PinSheet" does not work properly -
Hi, - -I can undo a "Delete PinSheet", however, when I try to delete another pin of that Sheet, I get a popup: - -"DeleteSheetLabel error: m_Parent != DRAW_SHEET_STRUCT_TYPE" - -The Dangling test also seems to fail. - -When I try that again, eeschema crashes. - -This was tested with SVN revision 944.
-0 - - -2725977 -diemer -1207082901 -
Logged In: YES -user_id=154672 -Originator: YES - -I just noticed that Jean-Pierre fixed it in svn r949, the crash is gone. In addition, I just fixed the incorrectly shown dangling ends in svn r962. That should do it.
- - - - - - -5833369 -IP -Artifact Created: 82.83.232.41 -1206883167 -diemer - - -5845506 -IP -Comment Added: 82.83.196.111 -1207082901 -diemer - - -5845507 -status_id -1 -1207082901 -diemer - - -5845508 -resolution_id -100 -1207082901 -diemer - - -5845509 -close_date -0 -1207082901 -diemer - - - - -http://sourceforge.net/support/tracker.php?aid=1930983 -1930983 -2 -1015285 -100 -1 -fhsplitt -nobody -diemer -1207036755 -1207083025 -5 -20080313-r890: "place hierarchical sheet" issues -
KiCAD 20080313-r890 under Windows XP SP2: - -(1) When attempting to "place a hierarchical sheet", the sheet shows up with a default file name that cannot be changed consistently. Sometimes, when the *.sch is reopened, a new (default?) filename reappears next to the rectangle for the hierarchical sheet. -(2) EEschema crashes when a non-existing file name is specified for a hierarchical sheet. - -
-0 - - -2725981 -diemer -1207083025 -
Logged In: YES -user_id=154672 -Originator: NO - -This bug has been fixed
- - -2725982 -diemer -1207083025 -
Logged In: YES -user_id=154672 -Originator: NO - -According to the changelog and a quick test, this was fixed by Jean-Pierre in svn r948.
- - - - - - -5842669 -IP -Artifact Created: 84.188.107.169 -1207036755 -fhsplitt - - -5845540 -IP -Comment Added: 82.83.196.111 -1207083025 -diemer - - -5845541 -IP -Comment Added: 82.83.196.111 -1207083025 -diemer - - -5845542 -status_id -1 -1207083025 -diemer - - -5845543 -resolution_id -100 -1207083025 -diemer - - -5845544 -category_id -100 -1207083025 -diemer - - -5845545 -close_date -0 -1207083025 -diemer - - - - -http://sourceforge.net/support/tracker.php?aid=1933550 -1933550 -2 -761682 -516020 -103 -fhsplitt -nobody -jerryjacobs -1207241172 -1267476627 -5 -localization issue - decimal points -
I am running PCBNEW under Windows XP with German language settings with the exception of having specified decimal points instead of commas (the comma is the standard German language decimal separator). Everything works well with most recent 2007 PCBNEW version. The module editor of all 2008 PCBNEW versions shows decimal points when I attempt to edit pads, but will not accept any input unless I use commas as a decimal separator. -Suggestion: either stick to the OS settings or simply stay with decimal points. - - -
-0 - - -2749019 -wrth -1208891926 -
Logged In: YES -user_id=1044669 -Originator: NO - -The same to me. All properties in PCBNEW which have a input box containing values with decimal points displays it with '.' but you have to input them with ','. The main problem is, when you change only one value, ALL other values on particular property page are set WRONG. - -Example: -when editting pad, all properties are displayed with DOT (some of them: Pad Drill 0.8128mm, Pad Size X=1.5748, Pad Size Y=2.286). -When you change only 'Pad Drill'(for example = 0,9mm - with comma as decimal point) other values are set to the number before decimal point -> Pad Size X = 1.0008mm, Pad Size Y=1.9990mm. - -I have also noticed that when I change the language to 'English' it works fine, but I have to use '.' as decimal point. I used to work in Polish language. - -This bug is very irritating. I can work with English interface, no problem, but it was very comfortable to use the numeric keyboard when setting parameters. Now I have to use numeric keyboard to input numbers and press '.' with my left hand on standard keyboard. - -
- - -2767215 -rohel01 -1210321780 -
Logged In: YES -user_id=2082876 -Originator: NO - -This bug is also registered as bug 1915932. I'll comment here since this one is better documented. As previously said, this bug affects both PCBNEW and the module editor. - -It is very annoying : EVERY change in one specific value requires us to modify all other value aswell (replacing the dot by a comma). Failing to do so results in the LOSS of these settings. - -I think this bug should be raised to a higher priority. Beside the significant time waste, "vanishing" text strings can prevent new users from enjoying the professionnal quality of KiCad. - -
- - -2769079 -nobody -1210493154 -
Logged In: NO - -MA CAZZO! Lo mettete a posto o no sto cazzo di problema, CAZZO!!! CAZZO!!! -
- - -2769141 -nobody -1210498977 -
Logged In: NO - -MA CAZZO! Lo mettete a posto o no sto cazzo di problema, CAZZO!!! CAZZO!!! -
- - -3204294 -dickelbeck -1228758494 -
Is this still a problem, or has it been fixed in latest code? -
- - -3208732 -fhsplitt -1229021211 -
The decimal separator issue seems to have been fixed with the 20080715 release. - -
- - - - - - -5855300 -IP -Artifact Created: 84.188.81.203 -1207241172 -fhsplitt - - -5933964 -IP -Comment Added: 89.206.7.227 -1208891926 -wrth - - -5991330 -IP -Comment Added: 86.196.170.29 -1210321780 -rohel01 - - -5996888 -IP -Comment Added: 90.131.8.231 -1210493154 -nobody - - -5997028 -IP -Comment Added: 90.131.8.231 -1210498977 -nobody - - -7157914 -IP -Comment Added: 67.64.64.34 -1228758494 -dickelbeck - - -7157915 -status_id -1 -1228758494 -dickelbeck - - -7157916 -close_date -0 -1228758494 -dickelbeck - - -7178310 -IP -Comment Added: 84.188.65.75 -1229021211 -fhsplitt - - -7178311 -status_id -4 -1229021211 -fhsplitt - - -7178312 -close_date -1228758494 -1229021211 -fhsplitt - - -9227498 -status_id -1 -1267476627 -jerryjacobs - - -9227499 -resolution_id -100 -1267476627 -jerryjacobs - - -9227500 -allow_comments -1 -1267476627 -jerryjacobs - - -9227501 -close_date -0 -1267476627 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=1934104 -1934104 -1 -100 -100 -100 -fhsplitt -nobody -nobody -1207287314 -0 -5 -PCBNEW - moving/deleting selected components -
Moving or deleting a group of selected identical components (30 LEDs in this case) which are still on top of each other before being manually or automatically positioned is impossible. - -Version: 2000313-r890 under Windows XP Home SP - -
-0 - - -2728971 -nobody -1207288106 -
Logged In: NO - -Hi, - -I figured out why the components could not be moved or deleted: In the module definition, the component was offset from the center of the coordinate system. - -Regards, - -Fred -
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=273154&aid= -273154 -marked_LED_group.jpeg - -52607 -image/pjpeg -1207287314 -fhsplitt - - - - -5857622 -IP -Artifact Created: 84.188.105.6 -1207287314 -fhsplitt - - -5857623 -File Added -273154: marked_LED_group.jpeg -1207287315 -fhsplitt - - -5857641 -IP -Comment Added: 84.188.105.6 -1207288106 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1945676 -1945676 -3 -1015285 -755196 -100 -jerryjacobs -nobody -jerryjacobs -1208523570 -1208948004 -5 -Libedit - exit and not save bug -
If i want to exit the libedit and changed a component it asks if i would save changes, when i say no it jumps back to libedit and doesn't exit libedit. When is say save changes it saves and exit... - -Jerry -20080416-r982 svn build used (made myself)
-0 - - -2749697 -jerryjacobs -1208948004 -
Logged In: YES -user_id=2066563 -Originator: YES - -.......Rewrite, -I did not read the dialog well it was no bug i was it myself.. - -Close this... - -Jerry
- - - - - - -5915530 -IP -Artifact Created: 84.25.181.171 -1208523570 -jerryjacobs - - -5936199 -IP -Comment Added: 84.25.41.149 -1208948004 -jerryjacobs - - -5936200 -status_id -1 -1208948004 -jerryjacobs - - -5936201 -close_date -0 -1208948004 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=1947613 -1947613 -1 -761682 -755198 -100 -diemer -nobody -nobody -1208762619 -0 -5 -Track/segment delete shortcuts don't work -
From MK in users-ML: "how do I delete a trace? Backspace should do it but it does not. Any trick to doing it? Right click and selecting from the dialog works but too many steps." - -I checked with SVN r890 under Linux: I cannot delete tracks or segments using Backspace or Delete.
-0 - - -3221287 -f3nix -1229891282 -
For these shortcuts to work the "Add tracks and vias" tool must be turned on. I do not know if this is a bug or feature though... - -HTH, -Mateusz -
- - -3221302 -f3nix -1229892094 -
The same applies to the delete module shortcut. You have to select "Add modules" tool to delete modules with these shortcuts...
- - - - - - -5927289 -IP -Artifact Created: 134.169.117.46 -1208762620 -diemer - - -7252504 -IP -Comment Added: 83.12.84.19 -1229891282 -f3nix - - -7252505 -artifact_group_id -100 -1229891282 -f3nix - - -7252558 -IP -Comment Added: 83.12.84.19 -1229892094 -f3nix - - - - -http://sourceforge.net/support/tracker.php?aid=1947987 -1947987 -2 -761682 -100 -6 -diemer -nobody -diemer -1208789631 -1230461737 -5 -Track operations crashes -
Some PCBnew Track operations may crash the program... - -From Users-ML: - -> > - Board cleanup function (from menu) crashes program. A bug? -> -> Can't seem to find that function, can you be a bit more specific? - -It is called from (PCBnew): -Menu/Miscellaneous/Track operations -It seems that turning on 'Delete unconnected tracks' causes a crash for me. - -or maybe 'Connect to pads" but after the board is cleaned it does not crash anymore. -I think the cleaning algorithm crashes sometimes when it finds something. -You need things to cleanup to make it crash.
-0 - - -2748323 -diemer -1208847446 -
Logged In: YES -user_id=154672 -Originator: YES - -Attached a board that causes the crash. Select all four options of "Track operations" to provoke the crash. -File Added: crash.brd
- - -3221295 -f3nix -1229891534 -
Hello Jonas, -could You please confirm that the crash still occurs with latest svn? It works for me... - -Thanks, -Mateusz -
- - -3251156 -diemer -1230461737 -
Yep, I cannot reproduce this bug in the latest SVN 1488. It must have been fixed in the meantime.
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=275446&aid= -275446 -crash.brd -Board that causes the crash -210857 -application/octet-stream -1208847446 -diemer - - - - -5928814 -IP -Artifact Created: 134.169.117.46 -1208789631 -diemer - - -5931524 -File Added -275446: crash.brd -1208847446 -diemer - - -5931525 -IP -Comment Added: 134.169.117.46 -1208847446 -diemer - - -7252531 -IP -Comment Added: 83.12.84.19 -1229891534 -f3nix - - -7252532 -resolution_id -100 -1229891534 -f3nix - - -7309321 -IP -Comment Added: 82.83.228.128 -1230461737 -diemer - - -7309322 -status_id -1 -1230461737 -diemer - - -7309323 -close_date -0 -1230461737 -diemer - - - - -http://sourceforge.net/support/tracker.php?aid=1954396 -1954396 -1 -761682 -755198 -100 -kajtek1 -nobody -nobody -1209495807 -0 -5 -Moving tracks with zero length wrong -
By doing multiple track movements and merges you end up with some track having zero length. Especially on track corners. -Then, moving this corner moves all tracks correctly except the one with zero length which moves twice as far as the others ending up separated from the corner.
-0 - - -2757284 -kajtek1 -1209521433 -
Logged In: YES -user_id=1935577 -Originator: YES - -The same thing happens to via if you move a corner of a track that contains a via. Via moves twice as far. -If you drag a via instead of moving a track, it works correctly.
- - - - - - -5960069 -IP -Artifact Created: 68.5.128.151 -1209495808 -kajtek1 - - -5961057 -IP -Comment Added: 68.5.128.151 -1209521434 -kajtek1 - - - - -http://sourceforge.net/support/tracker.php?aid=1955681 -1955681 -2 -100 -516020 -100 -f3nix -nobody -f3nix -1209674066 -1214154252 -7 -Translated strings are not picked up on Windows version -
Hi, -the current CMake policy is to install the "internat" folder into a "share" folder (eg. "c:\kicad\share\internat"). - -The problem is that when this folder is there, KiCad does not pick up the translated strings. - -When I move the "internat" folder to "c:\kicad" everything works as expected. - -Cheers, -Mateusz -
-0 - - -2813841 -f3nix -1214154195 -
Logged In: YES -user_id=1459455 -Originator: YES - -This bug has been fixed
- - -2813842 -f3nix -1214154195 -
Logged In: YES -user_id=1459455 -Originator: YES - -Fixed in svn revision 1132.
- - - - - - -5966627 -IP -Artifact Created: 83.12.84.19 -1209674066 -f3nix - - -6161467 -IP -Comment Added: 156.17.237.127 -1214154195 -f3nix - - -6161468 -IP -Comment Added: 156.17.237.127 -1214154195 -f3nix - - -6161469 -status_id -1 -1214154252 -f3nix - - -6161470 -close_date -0 -1214154252 -f3nix - - - - -http://sourceforge.net/support/tracker.php?aid=1956732 -1956732 -2 -1015285 -755196 -100 -durgadas -nobody -dickelbeck -1209823924 -1214839186 -5 -Filled rectangles and circles are not plotted as filled -
Ran into a problem generating (plotting) postscript schematics. Any rectangles or circles that I had selected as filled were not getting filled in the postscript file. Here's the patch I'm using, although it may not be the best solution: - -
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=276716&aid= -276716 -kicad.patch -Patch I am currently using -5217 -text/x-patch -1209823925 -durgadas - - - - -5972135 -IP -Artifact Created: 209.180.51.97 -1209823925 -durgadas - - -5972136 -File Added -276716: kicad.patch -1209823926 -durgadas - - -6188368 -status_id -1 -1214839186 -dickelbeck - - -6188369 -close_date -0 -1214839186 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=1956740 -1956740 -2 -1015285 -755196 -1 -durgadas -nobody -jerryjacobs -1209825061 -1267479170 -5 -eeschema core dumps when right click on ref field -
Sometimes I crash eeschema by right-clicking on the reference (or maybe value?) field of a component. Seems like the more I zoom in the less likely it is to happen. I've attached a stack trace, seems like somewhere between the right-click event and actually trying to choose a menu to pop-up it gets an invalid object pointer? or chooses the wrong context? - -Certain components do seem to do it more often, but it is possible to make it work even on troublesome components.
-0 - - -2776006 -mrblister -1210959788 -
Logged In: YES -user_id=98708 -Originator: NO - -I can reproduce this every time on 20080320-r918/Linux. Crash only occurs when right clicking on value field. Right click on reference field or anywhere else within component brings up the edit menu.
- - -2807094 -nobody -1213422465 -
Logged In: NO - -Confirmed. eeschema will crash when right click on any field placed inside the component's area.
- - -2872201 -nobody -1218437629 -
Logged In: NO - -Yes. Also confirm this on -r918 linux. - -This should get looked into since it renders the whole thing nearly useless since the context menus are essential for basic functionality. - -Test case: - -place an R component and rotate 90, menu is fine. Place a second , right-click to rotate and bam, no more eeschema. Pretty ugly. - -It seems to have something to do with multiple instance of a cmpt. - -gentoo linux, 2.6.20 , wxGTK-2.8.8.1 , gcc-4.2.3 - -Thx - -
- - -2872211 -nobody -1218438149 -
Logged In: NO - -In my resistor example I have found that I do not get the crash if I select R each time. I do get the crash if I select R from the history list.
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=276719&aid= -276719 -kicad.crash -gdb stack traceback -2163 -application/octet-stream -1209825061 -durgadas - - - - -5972179 -IP -Artifact Created: 209.180.51.97 -1209825061 -durgadas - - -5972180 -File Added -276719: kicad.crash -1209825062 -durgadas - - -6018628 -IP -Comment Added: 81.174.132.135 -1210959788 -mrblister - - -6134105 -IP -Comment Added: 202.12.97.118 -1213422465 -nobody - - -6347801 -IP -Comment Added: 79.94.116.247 -1218437630 -nobody - - -6347826 -IP -Comment Added: 79.94.116.247 -1218438149 -nobody - - -9227703 -status_id -1 -1267479170 -jerryjacobs - - -9227704 -resolution_id -100 -1267479170 -jerryjacobs - - -9227705 -allow_comments -1 -1267479170 -jerryjacobs - - -9227706 -close_date -0 -1267479170 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=1959867 -1959867 -1 -100 -100 -100 -kajtek1 -nobody -nobody -1210202731 -0 -5 -Module Editor deletes multiple lines -
I modified a module in Module Editor (PCBnew -r982) by drawing a new outline (graphic line) next to existing one and then tried to delete the old lines one by one. -Deleting seemed to work fine but when I repainted the screen all of the new lines except one were also deleted. -The lines did not share the same end points so I do not know why whould it do that. -The new lines were close to the old ones but not overlaying.
-0 - - - - - - -5986610 -IP -Artifact Created: 206.135.71.2 -1210202731 -kajtek1 - - - - -http://sourceforge.net/support/tracker.php?aid=1961821 -1961821 -2 -1015285 -100 -103 -nobody -nobody -jerryjacobs -1210497072 -1267477859 -5 -Not printing the hierachical sheet when printing the main -
If you place a hierarchical sheet in your main sheet and you select "print-> Print all sheets", the first sheet is printed twice.
-0 - - -2790718 -cfdev -1212070089 -
Logged In: YES -user_id=1876469 -Originator: NO - -I confirme this ! for Print all sheets in version : 20080429-r1010 win32 -the first sheet is printed twice and in smaller format ! - -visibly the format of the scheme has changed because I try to re open the scheme with the stable version, but it is not possible... :( - -thank you to fixe it.
- - -3917377 -jerryjacobs -1267477858 -
Printing is reworked, should work now.
- - - - - - -5996981 -IP -Artifact Created: 217.250.48.116 -1210497072 -nobody - - -6069668 -IP -Comment Added: 90.52.144.92 -1212070089 -cfdev - - -9227587 -IP -Comment Added: 84.25.204.235 -1267477858 -jerryjacobs - - -9227588 -status_id -1 -1267477859 -jerryjacobs - - -9227589 -resolution_id -100 -1267477859 -jerryjacobs - - -9227590 -allow_comments -1 -1267477859 -jerryjacobs - - -9227591 -close_date -0 -1267477859 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=1963635 -1963635 -1 -1015285 -100 -100 -diemer -nobody -nobody -1210751073 -0 -7 -Multipart/multisheet entries in cvpcb (netlist) -
From Rok via devel-ML: - -Hi - -If there is an multipart element shared accross multiple sheets, there -are as many entries in cvpcb as there are sheets. So if you have 4 part element -U14 which is used on 3 sheets, there is 3 entries for U14 in CVPCB. - -SVN build 1065. - -Rok
-0 - - - - - - -6008095 -IP -Artifact Created: 134.169.117.46 -1210751074 -diemer - - - - -http://sourceforge.net/support/tracker.php?aid=1963636 -1963636 -1 -1015285 -100 -100 -diemer -nobody -nobody -1210751119 -0 -7 -Ploting multi instance of the same sheet -
From Rok via devel-ML: - -If you try to plot multisheet schematic with multi instance same name -schematic (same filename, different sheetname) only the last one is visible - -I guess it is overwriten. - -I would need all sheets because there are different designators on -different instances of the sheets. - -Rok
-0 - - -2821565 -lomarcan -1214821325 -
Logged In: YES -user_id=115128 -Originator: NO - -Uhm at a first glance it seems also that the plotting routine iterates on screens, not sheets (unlike the BOM builder). That may be the problem too. -
- - - - - - -6008096 -IP -Artifact Created: 134.169.117.46 -1210751121 -diemer - - -6187419 -IP -Comment Added: 88.149.185.186 -1214821325 -lomarcan - - - - -http://sourceforge.net/support/tracker.php?aid=1963864 -1963864 -2 -1015285 -755198 -1 -rokmarko -nobody -rokmarko -1210776738 -1213115185 -7 -Part number of multipart element is not saved -
Part number of multipart element is not saved. In multipart element you can select which part you are using. This inforamation is never stored, even when you leave a child sheet and reopens edited one. - -Rok
-0 - - -2803429 -rokmarko -1213115185 -
Logged In: YES -user_id=1126317 -Originator: YES - -This bug has been fixed
- - -2803430 -rokmarko -1213115185 -
Logged In: YES -user_id=1126317 -Originator: YES - -by jean-pierre
- - - - - - -6010015 -IP -Artifact Created: 193.77.104.223 -1210776738 -rokmarko - - -6010017 -summary -Part number of multipart is not saved -1210776774 -rokmarko - - -6010023 -priority -5 -1210776814 -rokmarko - - -6118914 -IP -Comment Added: 193.77.104.223 -1213115185 -rokmarko - - -6118915 -IP -Comment Added: 193.77.104.223 -1213115185 -rokmarko - - -6118916 -status_id -1 -1213115185 -rokmarko - - -6118917 -resolution_id -100 -1213115185 -rokmarko - - -6118918 -close_date -0 -1213115185 -rokmarko - - - - -http://sourceforge.net/support/tracker.php?aid=1974672 -1974672 -2 -1015285 -516020 -1 -ddeeds -charras -f3nix -1211887135 -1229886384 -5 -White text/graphic on black background does not print -
I work with a black background for schematics and normally use white for the pin name and pin number. But when I print a schematic using the Black Color Print mode, any text or graphic that is white does not print even though it is not the same color as the background. -
-0 - - -3221209 -f3nix -1229886384 -
This bug has been fixed
- - -3221210 -f3nix -1229886384 -
Fixed in SVN r1167. -Thanks!
- - - - - - -6057386 -IP -Artifact Created: 96.226.65.105 -1211887135 -ddeeds - - -7252153 -IP -Comment Added: 83.12.84.19 -1229886384 -f3nix - - -7252154 -IP -Comment Added: 83.12.84.19 -1229886384 -f3nix - - -7252155 -status_id -1 -1229886384 -f3nix - - -7252156 -resolution_id -100 -1229886384 -f3nix - - -7252157 -assigned_to -100 -1229886384 -f3nix - - -7252158 -close_date -0 -1229886384 -f3nix - - - - -http://sourceforge.net/support/tracker.php?aid=1975710 -1975710 -2 -1015285 -516020 -103 -oecherexpat -nobody -jerryjacobs -1211933961 -1267477708 -5 -BOM creation incorrect when using extra fields -
BOM creation has issues when using component's extra fields: A column for sheet number and sheet name is created but not filled in on single-sheet schematics. The contents of all other columns is shifted (see attached file)
-0 - - -3917373 -jerryjacobs -1267477708 -
BOM creation is reworked, it has been tested and works.
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=279267&aid= -279267 -BOM-Test.lst -BOM *.lst with 4 components file created using extra fields -214 -application/octet-stream -1211933961 -oecherexpat - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=324710&aid= -324710 -IsCheckedStack - -1523 -application/octet-stream -1240890652 -bennett78 - - - - -6060902 -IP -Artifact Created: 222.153.213.254 -1211933961 -oecherexpat - - -6060903 -File Added -279267: BOM-Test.lst -1211933961 -oecherexpat - - -8220614 -File Added -324710: IsCheckedStack -1240890652 -bennett78 - - -9227569 -IP -Comment Added: 84.25.204.235 -1267477708 -jerryjacobs - - -9227570 -status_id -1 -1267477708 -jerryjacobs - - -9227571 -resolution_id -100 -1267477708 -jerryjacobs - - -9227572 -allow_comments -1 -1267477708 -jerryjacobs - - -9227573 -close_date -0 -1267477708 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=1977700 -1977700 -2 -761682 -100 -6 -nobody -nobody -f3nix -1212061969 -1229893485 -5 -Crash on Add Graphic Line or Polygon in Module editor -
Reproducible crash : -- Open Module Editor -- Create new module -- Draw line or polygon -- End it (double click, escape ...) -- Crash - -Add graphic arc, or add graphic circle are unaffected. - -Versions affected : -- 20080521 SVN-R1081 -- 20080320-r918-linux - -System : Ubuntu 8.04 - -
-0 - - -3221318 -f3nix -1229893485 -
Hi. I've tested the r918, r1081 and r1461. This crash is unreproducible. -I'm closing it for now. -Feel free to reopen it if the bug is still hitting You. -Thanks.
- - - - - - -6068976 -IP -Artifact Created: 196.200.83.190 -1212061969 -nobody - - -7252625 -IP -Comment Added: 83.12.84.19 -1229893485 -f3nix - - -7252626 -status_id -1 -1229893485 -f3nix - - -7252627 -resolution_id -100 -1229893485 -f3nix - - -7252628 -close_date -0 -1229893485 -f3nix - - - - -http://sourceforge.net/support/tracker.php?aid=1980555 -1980555 -1 -1015285 -100 -100 -nobody -nobody -nobody -1212236732 -0 -5 -Numerical inputs dot/semicolon mixup -
Hi, - -while its still fine in 'Release 20070709', I'm having troubles with numerical input fields in '20080522-r1100-win32' running on an english Windows Vista in with German currency/math settings. - -Every time I'm asked for a numerical input, like size of a label, preexisting inputs get converted to use a dot instead of a semicolon ( 0.04 instead of 0,04). Now when I dont replace the dot with a semicolon again the input will be taken as '0.0' no matter what I enter. - -Workaround: Replace . with , every time you open the dialog - -This Bug seems to apply to all kicad programs.
-0 - - -2797960 -nobody -1212604728 -
Logged In: NO - -I have the same problem. German windows with german localization.
- - -2805563 -nobody -1213285361 -
Logged In: NO - -I have the same problem. - -Windows XP
- - -2859474 -nobody -1217591717 -
Logged In: NO - -If you use the englisch language setting ist works with the ".". It seems to be a problem with the locale or language setting. When parsing the entered values the decimal separator from current language is used but at the time of filling the dialog the current language is ignored. You can only notice the bug if the decimal seperator from the selced language has another character as the ".".
- - - - - - -6079077 -IP -Artifact Created: 87.152.79.22 -1212236732 -nobody - - -6096470 -IP -Comment Added: 138.246.7.133 -1212604728 -nobody - - -6127687 -IP -Comment Added: 91.96.10.165 -1213285361 -nobody - - -6309618 -IP -Comment Added: 195.179.9.148 -1217591718 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1994698 -1994698 -2 -1015285 -516020 -103 -landyacht79 -nobody -jerryjacobs -1213581680 -1267476677 -5 -Wires don't connect -
I am running Kicad 2007-11-29-c on a Windows Vista Ultimate 64 bit laptop. When I am entering a schematic and adding wires, many times the wires do not connect to the component pins. How do I resolve this?
-0 - - -3127115 -nobody -1225402272 -
I realize a similar behavier using Windows XP, 32 bits. Vcc and GND power pins do not connect to other pins!
- - -3917352 -jerryjacobs -1267476677 -
Should work with newer version.
- - - - - - -6138956 -IP -Artifact Created: 68.81.85.143 -1213581680 -landyacht79 - - -6843557 -IP -Comment Added: 200.232.90.170 -1225402273 -nobody - - -9227505 -IP -Comment Added: 84.25.204.235 -1267476677 -jerryjacobs - - -9227506 -status_id -1 -1267476677 -jerryjacobs - - -9227507 -resolution_id -100 -1267476677 -jerryjacobs - - -9227508 -allow_comments -1 -1267476677 -jerryjacobs - - -9227509 -close_date -0 -1267476677 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=1995664 -1995664 -3 -761682 -100 -100 -nobody -nobody -jerryjacobs -1213668348 -1267477757 -5 -Net placed inside eeschema not correctly connected in pbcnew -
Nets created in eeschema will sometimes not properly connect in pcbnew. DRC does not return an error, but pcbnew will think all of those nets are all interconnected. pcbnew shows me all pins highlighted - -this happens with and without using bus entries. - -(reference picture) -the bus entries on the left of the tlc chips will all connect to each other in pcbnew. -also on the right side of the tlc, the connections 5-8 for the pin header used to be net names too to not make it too complicated. I placed a wire with 10 units length on the tlc and another wire on the pin header and named both nets the same (RED_5 to RED_8 for example) - -using version 20080522-r1100-win32 - -I cant verify if this happens in an older release as it the project wont load in an older version. - -Sometimes I was able to correct it by placing the wire and net again on both sides, but sometimes I cant get it fixed at all without drawing the wires from a to b. -(thats why I replaced the net labels on the connections) - -I redrew the whole schematic because i had the same problem the first time, its only got worse the second time, even thought it was layed out exaclty the same. only difference i used more underscores in the names of the components. - - - -add.: pulled the old layout from a backup, didnt restore the full project, thats why the tlc is not showing up, but this way you should get an idea how it used to be layed out. pcbnew then would think they are all connected. same procedures works on another sheet
-1 - - -2809937 -nobody -1213723828 -
Logged In: NO - -might have found the cause, might be a space in the name of the hierarchical sheet. the file name was "current-sink.sch" and the entered name was "current sink" -ever since i changed that it seems to connect the wires correctly.
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=281630&aid= -281630 -referencepics.zip -screenshot of connections -62966 -application/x-download -1213668348 -nobody - - - - -6143220 -IP -Artifact Created: 87.152.88.152 -1213668348 -nobody - - -6143221 -File Added -281630: referencepics.zip -1213668349 -nobody - - -6146151 -IP -Comment Added: 87.152.87.89 -1213723828 -nobody - - -9227577 -status_id -1 -1267477757 -jerryjacobs - - -9227578 -is_private -0 -1267477757 -jerryjacobs - - -9227579 -close_date -0 -1267477757 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=1995665 -1995665 -1 -1015288 -100 -100 -nobody -nobody -nobody -1213668650 -0 -5 -sm1206 and sm805 size mixup? -
when laying out my board, I noticed sm805 has the exact with and length (when viewed with the component viewer) as sm1206 and sm1206 is oversized.
-0 - - -2818745 -nobody -1214551914 -
Logged In: NO - -It's not a mixup, it's simply that there is an ambiguity with smd sizes... -IIRC the size can be either imperial (numbers in mils) or metric (tenth of mm). -So actually the 0805 imperial is exactly the same as the 1206 metric (or it's the other way? just make the calc) - -To add injury to damage, in some metric country (like here in Italy) we use imperial sizes! So if you ask a 1206 package (thinking in metric) you get a 'big' component, since suppliers give you a 1206 imperial! - -I think that's you problem, it's just industry's fault.
- - - - - - -6143236 -IP -Artifact Created: 87.152.88.152 -1213668650 -nobody - - -6178504 -IP -Comment Added: 80.207.56.82 -1214551914 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2003834 -2003834 -2 -1015285 -755198 -100 -nobody -nobody -dickelbeck -1214553263 -1214839186 -5 -Postscript plot generates wrong fill code -
Using r918, a filled polygon plot generates the following: - -newpath 7075 3992 moveto -7225 3992 lineto -7225 3967 lineto -7075 3967 lineto -closepath fill stroke -newpath 7225 3992 moveto -7225 3992 lineto -stroke - -(I know, it's a rectangle, but filled rectangles don't work, as in another bug) - -There are two issues here: -1) the second path is spurious (it's just a dot in a corner on the previous path), simply it isn't needed -2) the fill operator flushes the path (executes an implicit newpath), so the following stroke is a no-op; as a result the polygon is filled but not outlined! - -The correct postscript idiom is (iirc it's stated in the red book): - -closepath gsave fill grestore stroke - -(I'm fixing this using a sed script) -
-0 - - -2818766 -lomarcan -1214553366 -
Logged In: YES -user_id=115128 -Originator: NO - -Actually I submitted this, I wasn't logged in :D
- - - - - - -6178570 -IP -Artifact Created: 88.149.185.186 -1214553263 -nobody - - -6178575 -IP -Comment Added: 88.149.185.186 -1214553366 -lomarcan - - -6188366 -status_id -1 -1214839186 -dickelbeck - - -6188367 -close_date -0 -1214839186 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=2010222 -2010222 -2 -761682 -516020 -103 -oecherexpat -nobody -jerryjacobs -1215137001 -1267476831 -5 -Length of value field gets trunk'd when design is saved -
The length of the value filed gets trunk'd to 16 characters when the design is saved as PCB and re-opened. It is at full length when reading in the netlist.
-0 - - -3917357 -jerryjacobs -1267476831 -
All dialog are redone, this should now work.
- - - - - - -6202081 -IP -Artifact Created: 222.153.213.254 -1215137001 -oecherexpat - - -9227524 -IP -Comment Added: 84.25.204.235 -1267476831 -jerryjacobs - - -9227525 -status_id -1 -1267476831 -jerryjacobs - - -9227526 -resolution_id -100 -1267476831 -jerryjacobs - - -9227527 -allow_comments -1 -1267476831 -jerryjacobs - - -9227528 -close_date -0 -1267476831 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2018936 -2018936 -2 -1015285 -755196 -105 -alpheb -nobody -jerryjacobs -1216154966 -1267479022 -5 -eeschema redraw errors under compiz -
Here is a bug report filled in Launchpad. - -eeschema redraw errors under compiz -Filed here by: Alexander Rice -When: 2008-03-04 - -Binary package hint: kicad - -Eeschema works fine with kwin, but tends to leave 'shadows' of components and the cursor when using compiz. - -Using: - -Eeschema Build Version: -EESchema (2007-05-25) - Unicode version - -Compiz 1:0.6.2 - - - -Yoann CONGAL wrote 24 minutes ago: - - * eeschema-with-compiz.png (32.3 KiB, image/png) -http://launchpadlibrarian.net/16047058/eeschema-with-compiz.png - -Thanks for your report. - -Here is a screenshot of what I see under compiz' - -To reproduce it : -Move the cursor fast over the window. Some seconds later, cursor "ghost" will appear. - Yoann CONGAL wrote 18 minutes ago: (permalink) - -Same bug here (Hardy and EESchema Build Version:EESchema (2007-11-29-a) - Unicode version) -
-0 - - -2838087 -alpheb -1216156609 -
Logged In: YES -user_id=1890423 -Originator: YES - -I forgot to give the launchpad bug link : - -https://bugs.launchpad.net/ubuntu/+source/kicad/+bug/198353 - -Regards, - -Yoann CONGAL
- - -3917394 -jerryjacobs -1267479022 -
Compiz gives this kind of errors also with different programs, disable compiz.
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=284833&aid= -284833 -eeschema-with-compiz.png -screenshot -33042 -image/png -1216154966 -alpheb - - - - -6242717 -IP -Artifact Created: 81.64.68.143 -1216154966 -alpheb - - -6242723 -File Added -284833: eeschema-with-compiz.png -1216154966 -alpheb - - -6242826 -IP -Comment Added: 81.64.68.143 -1216156609 -alpheb - - -9227694 -IP -Comment Added: 84.25.204.235 -1267479022 -jerryjacobs - - -9227695 -status_id -1 -1267479022 -jerryjacobs - - -9227696 -resolution_id -100 -1267479022 -jerryjacobs - - -9227697 -allow_comments -1 -1267479022 -jerryjacobs - - -9227698 -close_date -0 -1267479022 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2020699 -2020699 -2 -1015285 -516020 -103 -nobody -nobody -jerryjacobs -1216307329 -1267476585 -5 -Library causes application to crash -
Submitted By: Kristen Wegner - branta.canadensis@gmail.com - -Context: While application "eeschema.exe" is loading part libraries ("Loading ..." is displayed in status bar.) Cannot see which library is the culprit. - -Assumption: Corrupt or incompatible library (?) causes application to crash. - -Error: Unhandled exception at 0x7c911639 in eeschema.exe: 0xC0000005: Access violation reading location 0x05512385. - -Threads: - -> 28012 Win32 Thread 7c911639 Normal - 21188 Win32 Thread 7c90eb94 Normal - 27008 Win32 Thread 7c90eb94 Normal - 28296 Win32 Thread 7c90eb94 Normal - 26748 Win32 Thread 7c90eb94 Above Normal - 27732 Win32 Thread 7c961be3 Normal - -Call Stack: - -> ntdll.dll!7c911639() - ntdll.dll!7c910732() - ntdll.dll!7c911538() - ntdll.dll!7c911596() - ntdll.dll!7c9106eb() - kernel32.dll!7c81095f() - eeschema.exe!007211d0() - eeschema.exe!005c93ce() - ntdll.dll!7c9106eb() - msvcrt.dll!77c2c3c9() - msvcrt.dll!77c2c3ce() - eeschema.exe!005c93ce() - msvcrt.dll!77c2c3c9() - eeschema.exe!005af6ad() - msvcrt.dll!77c2c3e7() - msvcrt.dll!77c2c42e() - eeschema.exe!005add71() - eeschema.exe!005ae46c() - eeschema.exe!005ae5d7() - eeschema.exe!006667a5() - eeschema.exe!0056f953() - eeschema.exe!007214d8() - msvcrt.dll!77c2c2de() - eeschema.exe!006669a2() - eeschema.exe!007ea9c8() - eeschema.exe!006670c7() - msvcrt.dll!77c2c3ce() - msvcrt.dll!77c2c3e7() - eeschema.exe!005add71() - eeschema.exe!005ae46c() - eeschema.exe!005bfea8() - msvcrt.dll!77c2c2de() - eeschema.exe!005ae4a7() - eeschema.exe!00502e61() - eeschema.exe!007ea701() - ntdll.dll!7c91056d() - msvcrt.dll!77c2c2de() - msvcrt.dll!77c2c2e3() - ntdll.dll!7c91094e() - kernel32.dll!7c80f30b() - eeschema.exe!00401ead() - msvcrt.dll!77c2c42e() - eeschema.exe!007f84c1() - eeschema.exe!006dc08b() - msvcrt.dll!77c2c2e3() - msvcrt.dll!77c2c3ce() - eeschema.exe!005be2cf() - eeschema.exe!007d7e21() - ntdll.dll!7c91094e() - eeschema.exe!00401466() - eeschema.exe!007ea278() - msvcrt.dll!77c39d60() - msvcrt.dll!77c34e2f() - eeschema.exe!0040124b() - eeschema.exe!004012b8() - kernel32.dll!7c816fd7() -
-0 - - -3917350 -jerryjacobs -1267476584 -
Should work with newer version.
- - - - - - -6250308 -IP -Artifact Created: 75.69.128.102 -1216307329 -nobody - - -9227489 -IP -Comment Added: 84.25.204.235 -1267476584 -jerryjacobs - - -9227490 -status_id -1 -1267476585 -jerryjacobs - - -9227491 -resolution_id -100 -1267476585 -jerryjacobs - - -9227492 -allow_comments -1 -1267476585 -jerryjacobs - - -9227493 -close_date -0 -1267476585 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2025712 -2025712 -2 -761682 -755198 -1 -jerryjacobs -nobody -jerryjacobs -1216816979 -1217638357 -5 -[SVN-REV-1170] 3D Viewer Crashes X11 -
Dear Developers, -I checked out the latest SVN version ( do this mostly one time a week for testing ). - -If i now run PCBnew and select the 3D Viewer my complete X11 crashes. I tried to find it using GDB and logging it: - -Reading symbols from /usr/local/bin/pcbnew...done. -Starting program: /usr/local/bin/pcbnew -[Thread debugging using libthread_db enabled] -[New Thread 0xb5fb3a30 (LWP 5581)] - -Program received signal SIGHUP, Hangup. -[Switching to Thread 0xb5fb3a30 (LWP 5581)] -0xb76764a7 in __close_nocancel () from /lib/libpthread.so.0 - - -I hope we can fix this before "new release" - - -Jerry
-0 - - -2860348 -jerryjacobs -1217638322 -
Logged In: YES -user_id=2066563 -Originator: YES - -Fixed with version 1167
- - - - - - -6272735 -IP -Artifact Created: 84.25.41.149 -1216816979 -jerryjacobs - - -6311914 -IP -Comment Added: 84.25.41.149 -1217638322 -jerryjacobs - - -6311915 -resolution_id -100 -1217638322 -jerryjacobs - - -6311918 -status_id -1 -1217638357 -jerryjacobs - - -6311919 -artifact_group_id -100 -1217638357 -jerryjacobs - - -6311920 -close_date -0 -1217638357 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2043168 -2043168 -1 -761682 -755198 -100 -nobody -nobody -nobody -1218207622 -0 -5 -ps plot broken with layer alignment in 2008-7-15 -
Hi, - -I added some layer alignment elements to my board. This broke the postscript plot in pcbnew. The offending code is: - -57500 60270 1250 cir150 -27200 41470 1250 cir150 - -cir150 is not defined. Reason seems to be that in plot_rtn.cpp:PlotCircle the fill and the width argument are interchanged in the call of PlotCirclePS. - -This bug is fixed in trunk. - -Is there a chance of a bugfix release anytime soon?
-0 - - - - - - -6338559 -IP -Artifact Created: 81.17.210.28 -1218207623 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2055599 -2055599 -2 -100 -755198 -1 -queueram -nobody -jerryjacobs -1218955519 -1267476154 -1 -kicad-doc 1.1 tarball extracts to "kicad" directory -
The kicad-doc 1.0 tarball extracted a directory named "kicad-doc". The kicad-doc 1.1 extracts to a directory named "kicad" which conflicts with the name of the directory that the kicad 20080715 extracts to. Workarounds are to rename the directory between extractions, or to check out the files from SVN. It would be preferable to avoid doing either of these though, especially for package generation. This might just be something to take care of at the next release.
-0 - - -2945330 -werner2101 -1223119775 -
It would even be nice if the tarballs extracts to a directory which contains the version number. - -kicad-20080825.tar.bz2 should extract to kicad-20080825 -kicad-doc-1.1.tar.bz2 should extract to kicad-doc-1.1 - -This is the used by almost all other projects. - -Regards -Werner -
- - -3917340 -jerryjacobs -1267476154 -
This bug has been fixed
- - -3917341 -jerryjacobs -1267476154 -
Closing old bug works for newer versions.
- - - - - - -6376058 -IP -Artifact Created: 12.210.191.117 -1218955519 -queueram - - -6376059 -priority -5 -1218955540 -queueram - - -6608635 -IP -Comment Added: 87.179.55.254 -1223119775 -werner2101 - - -9227442 -IP -Comment Added: 84.25.204.235 -1267476154 -jerryjacobs - - -9227443 -IP -Comment Added: 84.25.204.235 -1267476154 -jerryjacobs - - -9227444 -status_id -1 -1267476154 -jerryjacobs - - -9227445 -resolution_id -100 -1267476154 -jerryjacobs - - -9227446 -allow_comments -1 -1267476154 -jerryjacobs - - -9227447 -close_date -0 -1267476154 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2069722 -2069722 -2 -761682 -755198 -100 -manneveru -a-lunev -a-lunev -1219499897 -1219626635 -8 -PCB edge always printed when PCB edge layer not selected -
I have created my own PCB design and I want to laser print copper layers for thermal transfer process. - -But when in print dialogue I select only Elements layer (I have SMD design), the edge of the board is printed, even when I do not want this! - -The Gerber plot dialogue has select box, which allow to disable PCB edge, and this works. Problem with Gerber is that I don't have alignment targets in Gerber files (I don't know whether it is a bug or not, probably this could be enabled for Gerber too), so I print from GerbView is usable, but problematic to place on laminate. - -For me this is a bug in software at level of printing architecture, not a feature request.
-0 - - -2892123 -a-lunev -1219626635 -
Logged In: YES -user_id=1930733 -Originator: NO - -It is resolved by adding 'Exclude Edges_Pcb layer' check box in 'Print' dialog.
- - -2892377 -manneveru -1219647913 -
Logged In: YES -user_id=639576 -Originator: YES - -Am I understand correctly that this is on trunk? If yes I will try to rebuild code from svn.
- - -2892581 -a-lunev -1219664037 -
Logged In: YES -user_id=1930733 -Originator: NO - -Yes, update your work copy from svn and rebuild newpcb.
- - - - - - -6409778 -IP -Artifact Created: 213.134.171.113 -1219499897 -manneveru - - -6415467 -IP -Comment Added: 89.19.165.61 -1219626635 -a-lunev - - -6415468 -status_id -1 -1219626635 -a-lunev - - -6415469 -assigned_to -100 -1219626635 -a-lunev - - -6415470 -close_date -0 -1219626635 -a-lunev - - -6416441 -IP -Comment Added: 217.147.104.41 -1219647913 -manneveru - - -6417259 -IP -Comment Added: 77.73.25.202 -1219664038 -a-lunev - - - - -http://sourceforge.net/support/tracker.php?aid=2069872 -2069872 -1 -1015285 -516020 -100 -nobody -nobody -nobody -1219508603 -0 -5 -Sheet pin text size reduced after changing to an output -
When editing a sheet pin on a hierarchical sheet from an input (the default) to an output, the text size is changed to something tginy and cannot be changed back.
-0 - - -2890639 -nobody -1219511261 -
Logged In: NO - -This also occurs when adding pins to a new schematic libary - pin names and number have a size of 0.000" are not shown.
- - -2890641 -nobody -1219511332 -
Logged In: NO - -Issue is in Kicad 20080429-r1010.
- - -2890656 -nobody -1219512578 -
Logged In: NO - -Correction: Issue is in Kicad 20080429-r1010 when overwritten with release 20080522-r1100-win32.
- - - - - - -6410135 -IP -Artifact Created: 68.158.174.138 -1219508603 -nobody - - -6410234 -IP -Comment Added: 68.158.174.138 -1219511262 -nobody - - -6410243 -IP -Comment Added: 68.158.174.138 -1219511332 -nobody - - -6410285 -IP -Comment Added: 68.158.174.138 -1219512578 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2070228 -2070228 -2 -100 -516020 -100 -manneveru -nobody -dickelbeck -1219525585 -1220985253 -7 -bitmaps/CMakeLists.txt is broken for Win32 -
I am trying to build 2008-08-04 on my Windows machine. I even made new tutorial how to do that with CMake and Visual Studio 2005 Express (link on wiki). - -But bitmaps/CMakeLists.txt contains apostrophe character instead of quote marks. - -Currently is: -COMMAND cmake -E copy '${PATH}/${BASENAME}.xpm' '${CPP_BITMAP}' - -Should be: - -COMMAND cmake -E copy \"${PATH}/${BASENAME}.xpm\" \"${CPP_BITMAP}\" - -With changed line it is working. I am not making any change in repository, because I do not know rules yet.
-0 - - -2892378 -manneveru -1219647976 -
Logged In: YES -user_id=639576 -Originator: YES - -I submitted a patch for VC++ 2005 on kicad-devel group file area.
- - - - - - -6410811 -IP -Artifact Created: 213.134.171.113 -1219525585 -manneveru - - -6416444 -IP -Comment Added: 217.147.104.41 -1219647976 -manneveru - - -6494387 -status_id -1 -1220985253 -dickelbeck - - -6494388 -close_date -0 -1220985253 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=2072876 -2072876 -2 -1015285 -516020 -1 -gembler -charras -f3nix -1219637635 -1229886606 -5 -Libedit Places Edited Pin Instead of Creating New Pin -
To reproduce: - -1) Create new part and add pins -2) End Add Pins mode and edit any newly created pin -3) Switch back to Add Pins mode -4) Add a new pin -- the new pin placed is actually the pin just edited - -EESchema 20080715 - unicode version for Win XP -
-0 - - -3221214 -f3nix -1229886605 -
Fixed in SVN r1217. -Thanks.
- - - - - - -6416060 -IP -Artifact Created: 198.144.208.125 -1219637635 -gembler - - -7252179 -IP -Comment Added: 83.12.84.19 -1229886605 -f3nix - - -7252180 -status_id -1 -1229886606 -f3nix - - -7252181 -resolution_id -100 -1229886606 -f3nix - - -7252182 -assigned_to -100 -1229886606 -f3nix - - -7252183 -close_date -0 -1229886606 -f3nix - - - - -http://sourceforge.net/support/tracker.php?aid=2074534 -2074534 -2 -1015285 -100 -100 -gembler -nobody -stambaughw -1219705179 -1270579506 -5 -Libedit Cannot Delete Rectangle -
To reproduce: - -1) In Libedit, select component FILTER in device.lib -2) Delete the rectangle -3) The rectangle reappears - -EESchema 20080715 - unicode version on Win XP -
-0 - - -3221322 -f3nix -1229893773 -
Hello, -could You please confirm that the bug exists in the latest version? -I've tested the latest svn snapshot and I can't reproduce it. -Thanks.
- - -3954363 -stambaughw -1270579505 -
Fixed in release version 20100314.
- - - - - - -6420363 -IP -Artifact Created: 198.144.208.125 -1219705179 -gembler - - -7252638 -IP -Comment Added: 83.12.84.19 -1229893773 -f3nix - - -9371345 -IP -Comment Added: 162.83.115.135 -1270579506 -stambaughw - - -9371346 -status_id -1 -1270579506 -stambaughw - - -9371347 -allow_comments -1 -1270579506 -stambaughw - - -9371348 -close_date -0 -1270579506 -stambaughw - - - - -http://sourceforge.net/support/tracker.php?aid=2081148 -2081148 -2 -1015285 -100 -101 -nobody -f3nix -f3nix -1219957952 -1229885270 -5 -Libedit Cannot Delete Rectangle -
To reproduce: - -1) In Libedit, select component FILTER in device.lib -2) Delete the rectangle -3) The rectangle reappears - -EESchema 20080715 - unicode version on Win XP -
-0 - - -3221198 -f3nix -1229885270 -
Duplicate of bug #2074534
- - -3221231 -f3nix -1229887969 -
This artifact has been marked as a duplicate of artifact 2074534 with reason: -No explanation provided.
- - - - - - -6438357 -IP -Artifact Created: 65.57.245.11 -1219957952 -nobody - - -7252087 -IP -Comment Added: 83.12.84.19 -1229885270 -f3nix - - -7252088 -status_id -1 -1229885270 -f3nix - - -7252089 -resolution_id -100 -1229885270 -f3nix - - -7252090 -close_date -0 -1229885270 -f3nix - - -7252092 -assigned_to -100 -1229885304 -f3nix - - -7252266 -IP -Comment Added: 83.12.84.19 -1229887969 -f3nix - - -7252267 -status_id -3 -1229887970 -f3nix - - - - -http://sourceforge.net/support/tracker.php?aid=2086372 -2086372 -2 -1015287 -755198 -100 -ok1rrmartin -nobody -ok1rrmartin -1220256170 -1220746067 -5 -Gerbview internal error -
Gerbview -> Preferences -> Show Current Hotkey List results in WinEDA_GerberFrame::Process_Config internal error
-0 - - - - - - -6451619 -IP -Artifact Created: 80.250.30.141 -1220256171 -ok1rrmartin - - -6480996 -status_id -1 -1220746067 -ok1rrmartin - - -6480997 -close_date -0 -1220746067 -ok1rrmartin - - - - -http://sourceforge.net/support/tracker.php?aid=2086382 -2086382 -2 -100 -100 -2 -ok1rrmartin -nobody -jerryjacobs -1220256550 -1267478687 -5 -Strings that can't be translated -
Both EESchema and Pcbnew contain strings that can't be translated in Preferences -> Show Current Hotkey List. They seems to be 'hardwired' into code.
-0 - - - - - - -6451636 -IP -Artifact Created: 80.250.30.141 -1220256550 -ok1rrmartin - - -9227662 -status_id -1 -1267478687 -jerryjacobs - - -9227663 -resolution_id -100 -1267478687 -jerryjacobs - - -9227664 -allow_comments -1 -1267478687 -jerryjacobs - - -9227665 -close_date -0 -1267478687 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2098306 -2098306 -2 -1015286 -100 -103 -nobody -nobody -jerryjacobs -1220778351 -1267478339 -5 -[Crash] On project save -
Kicad Project manager hangs up if i want to write a new project or save the nameless project. Also if in the settings the last project doesn't exist anymore kicad does not check if the project is existing .... - -[20080906 SVN 1239 BUILD]
-0 - - - - - - -6482318 -IP -Artifact Created: 84.25.41.149 -1220778351 -nobody - - -9227641 -status_id -1 -1267478339 -jerryjacobs - - -9227642 -resolution_id -100 -1267478339 -jerryjacobs - - -9227643 -allow_comments -1 -1267478339 -jerryjacobs - - -9227644 -close_date -0 -1267478339 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2136527 -2136527 -2 -1015285 -100 -1 -nobody -nobody -f3nix -1222712335 -1229889196 -5 -EESCHEMA freez... -
EESCHEMA freez while editing board in PCBNEW. ("Dual mode", first part location good, but at second eeschema freez out.. =( ). - -Debian Kernel: 2.6.18-6-686 -KiCad: 0.0.20071129a-1 - -contact: marcziselektronika@gmail.com - -Please let me know if I can help. - -KiCad is amazing ! -GOGOGO !
-0 - - -2942669 -nobody -1222896656 -
Okay, -I feel really dummy... I just realized, in Debi testing I have a very old kicad.... -I just finished installing the brand new kicad... and the problem of course gone... - -THANK YOU VERY MUCH KICAD ! - -
- - - - - - -6583629 -IP -Artifact Created: 89.133.34.50 -1222712335 -nobody - - -6594860 -IP -Comment Added: 89.133.34.50 -1222896656 -nobody - - -7252362 -status_id -1 -1229889196 -f3nix - - -7252363 -resolution_id -100 -1229889196 -f3nix - - -7252364 -close_date -0 -1229889196 -f3nix - - - - -http://sourceforge.net/support/tracker.php?aid=2146251 -2146251 -2 -100 -100 -100 -werner2101 -nobody -dickelbeck -1223120207 -1228757391 -5 -wxwidgets 2.8 required -
I've tried to build kicad for openSUSE 10.2. It provides wxwidgets version 2.6.3.3. - -Refering the install.txt file this should be ok. - -The build fails with the following message: --------- -Scanning dependencies of target 3d-viewer -[ 0%] Building CXX object 3d-viewer/CMakeFiles/3d-viewer.dir/3d_aux.cpp.o -In file included from /usr/src/packages/BUILD/kicad/3d-viewer/3d_aux.cpp:18: -/usr/src/packages/BUILD/kicad/include/common.h:9:25: error: wx/aboutdlg.h: No such file or directory -/usr/src/packages/BUILD/kicad/include/common.h:11:34: error: wx/generic/aboutdlgg.h: No such file or directory -/usr/src/packages/BUILD/kicad/include/common.h:611: error: variable or field 'InitKiCadAbout' declared void -/usr/src/packages/BUILD/kicad/include/common.h:611: error: 'wxAboutDialogInfo' was not declared in this scope -/usr/src/packages/BUILD/kicad/include/common.h:611: error: 'info' was not declared in this scope -make[2]: *** [3d-viewer/CMakeFiles/3d-viewer.dir/3d_aux.cpp.o] Error 1 -make[1]: *** [3d-viewer/CMakeFiles/3d-viewer.dir/all] Error 2 -make: *** [all] Error 2 --------- - -The about dialog class has been added with wxwidgets version 2.8 - -Regards -Werner
-0 - - -3204252 -dickelbeck -1228757391 -
The latest tree now requires 2.8 of wxWidgets. You may need to build wxWidgets from source if your distro does not have a recent version. This is not a bug, we are allowed to move the project forward with the latest technology coming from wxWidgets. - -
- - - - - - -6608652 -IP -Artifact Created: 87.179.55.254 -1223120207 -werner2101 - - -7157787 -IP -Comment Added: 67.64.64.34 -1228757391 -dickelbeck - - -7157788 -status_id -1 -1228757391 -dickelbeck - - -7157789 -close_date -0 -1228757391 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=2149301 -2149301 -2 -761682 -755196 -100 -galzsolt -nobody -galzsolt -1223291776 -1252529061 -5 -Printing doesn't work well -
I'am using Debian Etch 4.0. In PCBnew when I try to print boards, lines aren't continusly in the printed document and on the paper also incorrect. Lines looks like they are crashed and pads are squared instead of rouded or oval. I tryed it in Ubuntu 8.04 and the result is the same. I had never this problem in windows XP, but I want to use linux because of its licence.
-0 - - -3035482 -nobody -1224662589 -
I have the same problem with Ubunutu 8.04 on two different PC.
- - -3095951 -nobody -1225138465 -
Same thing for me on debian sid and ubuntu. -I talked about that on kicad-users mailing list (see message #3753 for some pictures) - -vko
- - -3158041 -nobody -1225992336 -
Me too. But in the meantime, you can use the plot function wich will pake a .ps file.
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=296268&aid= -296268 -Printing_400001_VNH-brd.pdf -It shows my problem. -54699 -application/pdf -1223291776 -galzsolt - - - - -6615784 -IP -Artifact Created: 82.141.181.16 -1223291776 -galzsolt - - -6615785 -File Added -296268: Printing_400001_VNH-brd.pdf -1223291776 -galzsolt - - -6776288 -IP -Comment Added: 193.194.132.79 -1224662589 -nobody - - -6825049 -IP -Comment Added: 213.41.32.234 -1225138465 -nobody - - -6882232 -IP -Comment Added: 91.150.229.252 -1225992336 -nobody - - -8653076 -status_id -1 -1252529061 -galzsolt - - -8653077 -allow_comments -1 -1252529061 -galzsolt - - -8653078 -close_date -0 -1252529061 -galzsolt - - - - -http://sourceforge.net/support/tracker.php?aid=2167848 -2167848 -2 -761682 -100 -1 -nobody -charras -f3nix -1224060288 -1229886890 -5 -crash on module editor - module properties -
Reproducible crash on Kicad 20080825 on windows XP. Bug does not afflict previous version and Linux version. - -- Open module editor -- Load module from library -- Open module -- Open module properties -- Click OK -Crash of PCBnew -
-0 - - -2988636 -nobody -1224060622 -
Federico Dami - -federico.dami@alice.it
- - -3215834 -nobody -1229523603 -
I confirm -
- - -3215836 -nobody -1229523664 -
I confirm -
- - -3221218 -f3nix -1229886890 -
Fixed in SVN r1279. -Thanks!
- - -3221219 -f3nix -1229886965 -
Fixed in SVN r1282. -Thanks!
- - - - - - -6695236 -IP -Artifact Created: 81.80.37.124 -1224060289 -nobody - - -6695286 -IP -Comment Added: 81.80.37.124 -1224060622 -nobody - - -7216581 -IP -Comment Added: 90.49.22.52 -1229523603 -nobody - - -7216588 -IP -Comment Added: 90.49.22.52 -1229523664 -nobody - - -7252202 -IP -Comment Added: 83.12.84.19 -1229886890 -f3nix - - -7252203 -status_id -1 -1229886890 -f3nix - - -7252204 -resolution_id -100 -1229886890 -f3nix - - -7252205 -assigned_to -100 -1229886890 -f3nix - - -7252206 -close_date -0 -1229886890 -f3nix - - -7252209 -IP -Comment Added: 83.12.84.19 -1229886965 -f3nix - - - - -http://sourceforge.net/support/tracker.php?aid=2171561 -2171561 -1 -1015285 -100 -100 -josh_eeg -nobody -nobody -1224161383 -0 -5 -I am drawing the component MYCONN3 per tutorial instructions -
I am drawing the component MYCONN3 per tutorial instructions... but the box tool is not drawing a box it is acting like a rectangular selection and moveing my pins... -I am using the newest stable window$ build.
-0 - - -3221242 -f3nix -1229888664 -
Hi. You should not drag with pressed mouse button. You should only click on the start and end point of the rectangle. - -HTH -Mateusz
- - - - - - -6712426 -IP -Artifact Created: 65.200.157.178 -1224161383 -josh_eeg - - -7252324 -IP -Comment Added: 83.12.84.19 -1229888664 -f3nix - - - - -http://sourceforge.net/support/tracker.php?aid=2179610 -2179610 -2 -100 -516020 -103 -nobody -nobody -jerryjacobs -1224419959 -1267478642 -5 -Grid does not show correct -
The grid does not show correct on Windows Vista Premium 32 bit. Didn't have any problems in Windows XP Pro. -Using a Dell Vostro laptop with ATI express 1150 video card. -Any questions: allembedded(at)gmail.com
-0 - - -3917389 -jerryjacobs -1267478641 -
No problems with new version 2010-02-28-RC5.
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=297942&aid= -297942 -kicad_grid_problem.jpg -Screen dump -211860 -image/pjpeg -1224419959 -nobody - - - - -6747106 -IP -Artifact Created: 78.27.53.49 -1224419959 -nobody - - -6747107 -File Added -297942: kicad_grid_problem.jpg -1224419960 -nobody - - -9227657 -IP -Comment Added: 84.25.204.235 -1267478641 -jerryjacobs - - -9227658 -status_id -1 -1267478641 -jerryjacobs - - -9227659 -resolution_id -100 -1267478641 -jerryjacobs - - -9227660 -allow_comments -1 -1267478641 -jerryjacobs - - -9227661 -close_date -0 -1267478642 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2311317 -2311317 -2 -1015285 -100 -100 -nobody -nobody -dickelbeck -1227041284 -1234193061 -5 -Saving Netlist defaults to ".net*" -
Build v1409 recently downloaded (Mac OS X 10.5). When I generate a netlist from inside EESCHEMA it wants to save it as a .net* file. Then, of course, PCBNEW will not read it until I manually rename the file to .net -
-0 - - -3514910 -dickelbeck -1234193462 -
This seems to be a bug in the wxWidgets library or the Mac OS X's file globbing handler. There should be no reason the mask cannot have two '*'s in it. - -The wildcard part of the mask component should be discarded when the user picks an actual file. For now, we work around this bug by removing the 2nd mask. -
- - - - - - -6997474 -IP -Artifact Created: 76.235.68.246 -1227041285 -nobody - - -7660948 -status_id -1 -1234193061 -dickelbeck - - -7660950 -allow_comments -1 -1234193061 -dickelbeck - - -7660951 -close_date -0 -1234193061 -dickelbeck - - -7661511 -IP -Comment Added: 67.64.64.34 -1234193463 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=2320616 -2320616 -2 -1015288 -755196 -2 -josh_eeg -nobody -jerryjacobs -1227271923 -1267478301 -5 -button in eeschema for cvpcb causes error -
button in eeschema for cvpcb causes error... but the button in the main kicad window for it works fine. -this was proably just some kind of link and forgoten from the old version...
-0 - - -3221247 -f3nix -1229888951 -
Please provide more information. Which version of Kicad are You using?
- - - - - - -7015213 -IP -Artifact Created: 65.200.157.178 -1227271923 -josh_eeg - - -7252343 -IP -Comment Added: 83.12.84.19 -1229888951 -f3nix - - -9227632 -status_id -1 -1267478301 -jerryjacobs - - -9227633 -resolution_id -100 -1267478301 -jerryjacobs - - -9227634 -allow_comments -1 -1267478301 -jerryjacobs - - -9227635 -close_date -0 -1267478301 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2322351 -2322351 -2 -1015285 -755198 -1 -lomarcan -dickelbeck -diemer -1227295164 -1227524789 -5 -Fields moving on anchor repositioning -
When moving the anchor point in the module editor only the reference and the value stay 'fixed' (have their coordinate moved in relation with the new anchor). So, for example, the footprint field moves away (since it keeps the same coordinate but using the new reference!!)
-0 - - -3184370 -diemer -1227524789 -
Seems to have been fixed by Lorenzo in svn 1414 (checked in by dick).
- - - - - - -7018194 -IP -Artifact Created: 87.6.39.198 -1227295164 -lomarcan - - -7043474 -IP -Comment Added: 134.169.117.46 -1227524789 -diemer - - -7043475 -status_id -1 -1227524789 -diemer - - -7043476 -resolution_id -100 -1227524789 -diemer - - -7043477 -assigned_to -100 -1227524789 -diemer - - -7043478 -close_date -0 -1227524789 -diemer - - - - -http://sourceforge.net/support/tracker.php?aid=2354212 -2354212 -1 -1015285 -516020 -100 -nobody -nobody -nobody -1227819286 -0 -5 -Numerical inputs dot/semicolon mixup -
Hi, -I'm having troubles with -numerical input fields in '20080906-r1238-win32' running on an english -Windows Vista in with German currency/math settings. - -Every time I'm asked for a numerical input, like size of a label, -preexisting inputs get converted to use a dot instead of a semicolon ( 0.04 -instead of 0,04). Now when I dont replace the dot with a semicolon again -the input will be taken as '0.0' no matter what I enter. - -Workaround: Replace . with , every time you open the dialog - -This Bug seems to apply to all kicad programs.
-0 - - -3198363 -nobody -1228293625 -
For me, this bug does not occur on the "release" versions (like 20080715). So maybe it's a compiler setting. You could change your input settings in the Vista system configuration, but that's no real solution.
- - - - - - -7074056 -IP -Artifact Created: 91.96.8.52 -1227819286 -nobody - - -7114944 -IP -Comment Added: 217.250.51.45 -1228293625 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2359892 -2359892 -2 -761682 -100 -1 -jdoire -charras -f3nix -1227993952 -1229884827 -5 -description of icons is shifted down -
on page 3-10 of the pcbnew manual, the description of icons is shift down by one, for example the "Draw arcs on technical layers" is beside the text icon.
-0 - - -3221190 -f3nix -1229884827 -
This bug has been fixed
- - -3221191 -f3nix -1229884827 -
Fixed in SVN r1437. -Thanks!
- - - - - - -7084347 -IP -Artifact Created: 66.11.173.63 -1227993952 -jdoire - - -7084349 -summary -description of icons is shift down -1227994038 -jdoire - - -7252052 -IP -Comment Added: 83.12.84.19 -1229884827 -f3nix - - -7252053 -IP -Comment Added: 83.12.84.19 -1229884827 -f3nix - - -7252054 -status_id -1 -1229884827 -f3nix - - -7252055 -resolution_id -100 -1229884827 -f3nix - - -7252056 -assigned_to -100 -1229884827 -f3nix - - -7252057 -close_date -0 -1229884827 -f3nix - - - - -http://sourceforge.net/support/tracker.php?aid=2359898 -2359898 -2 -761682 -100 -101 -jdoire -f3nix -f3nix -1227994157 -1229885352 -5 -description of icons is shift down -
on page 3-10 of the pcbnew manual, the description of icons is shift down by one, for example the "Draw arcs on technical layers" is beside the text icon.
-0 - - -3221195 -f3nix -1229884991 -
Duplicate of 2359892
- - -3221228 -f3nix -1229887893 -
This artifact has been marked as a duplicate of artifact 2359892 with reason: -No explanation provided.
- - - - - - -7084357 -IP -Artifact Created: 66.11.173.63 -1227994157 -jdoire - - -7252068 -IP -Comment Added: 83.12.84.19 -1229884991 -f3nix - - -7252069 -status_id -1 -1229884991 -f3nix - - -7252070 -resolution_id -100 -1229884991 -f3nix - - -7252071 -close_date -0 -1229884991 -f3nix - - -7252094 -status_id -2 -1229885352 -f3nix - - -7252095 -assigned_to -100 -1229885352 -f3nix - - -7252096 -close_date -1229884991 -1229885352 -f3nix - - -7252254 -IP -Comment Added: 83.12.84.19 -1229887893 -f3nix - - -7252255 -status_id -3 -1229887893 -f3nix - - - - -http://sourceforge.net/support/tracker.php?aid=2388871 -2388871 -2 -761682 -516020 -100 -cfdev -nobody -dickelbeck -1228401171 -1228757110 -5 -Pcbnew to FreeRouter -
Version : 20080825c -OS : windowsXP, other don't tested -program : Pcbnew - - -hello, - -I try to use the export specctra fonction with FreeRouter, but the border egde in component are not detected by FreeRouter or when the exporting file ?! - -see the pictures attached for more details! - -thanks -Cfdev.
-0 - - -3204243 -dickelbeck -1228757108 -
The edges layer is for board edges and that boundary must be contiguous with itself. Your circles are not contiguous, and they indicate you want holes in the board. If you want holes, use a hole, not a board edge. - -Dick -
- - -3206768 -cfdev -1228927884 -
ok, -should I use an pad to do what I want ? to do an hole ? - -thanks for you reply
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=304000&aid= -304000 -pcbnewToFreeRouter.zip -pictures -61190 -application/zip -1228401171 -cfdev - - - - -7128309 -IP -Artifact Created: 90.52.207.22 -1228401171 -cfdev - - -7128310 -File Added -304000: pcbnewToFreeRouter.zip -1228401172 -cfdev - - -7157759 -IP -Comment Added: 67.64.64.34 -1228757109 -dickelbeck - - -7157760 -status_id -1 -1228757110 -dickelbeck - - -7157761 -close_date -0 -1228757110 -dickelbeck - - -7170899 -IP -Comment Added: 90.52.207.22 -1228927884 -cfdev - - - - -http://sourceforge.net/support/tracker.php?aid=2397258 -2397258 -2 -761682 -100 -100 -nobody -nobody -sf-robot -1228589321 -1231208426 -5 -Error Type 4, Track near Pad -
Error Type 4, Track near Pad, so how can i connect a pad with some kind of copper to another one then?? :) - -W2K SP4, placing an SMD and trying to 'hand-wire' a little board. Each time i like to connect a pad with a wire i get this weird error-message. (yes and the connection IS thinner than the pad...) - -Tried to browse the man and FAQ's - nothing found btw, there is a help-contact missing!! ;) and within the docs a list of known errors! - -Another one, how to correct the lqfp44 permanently in the parallax-library(P8X32-Q) ? - -
-0 - - -3204299 -dickelbeck -1228758721 -
Can you provide an example board, with a JPG showing where the problem is? The track and the pad will need to be part of the same net, this usually means starting the track from the pad. The error may be from a neighboring pad, not from the one you think. Study the error message carefully in the marker please to verify. -
- - -3285868 -sf-robot -1231208426 -
This Tracker item was closed automatically by the system. It was -previously set to a Pending status, and the original submitter -did not respond within 14 days (the time period specified by -the administrator of this Tracker).
- - - - - - -7142986 -IP -Artifact Created: 87.234.37.11 -1228589322 -nobody - - -7157929 -IP -Comment Added: 67.64.64.34 -1228758721 -dickelbeck - - -7157930 -status_id -1 -1228758721 -dickelbeck - - -7157931 -close_date -0 -1228758721 -dickelbeck - - -7368965 -IP -Comment Added: -1231208426 -sf-robot - - -7368966 -status_id -4 -1231208426 -sf-robot - - -7368967 -close_date -1228758721 -1231208426 -sf-robot - - - - -http://sourceforge.net/support/tracker.php?aid=2441116 -2441116 -1 -100 -100 -100 -bachkhois -nobody -nobody -1229533045 -0 -5 -Segmentation fault since upgraded to Ubuntu 8.10 -
The KiCad's 3D-Viewer on my PC encounters Segmentation Fault since I upgraded to Ubuntu 8.10. The error didn't happen on Ubuntu 8.04 -
-0 - - - - - - -7217728 -IP -Artifact Created: 118.69.163.146 -1229533045 -bachkhois - - - - -http://sourceforge.net/support/tracker.php?aid=2489509 -2489509 -2 -100 -755196 -101 -nobody -f3nix -f3nix -1231220004 -1232608624 -5 -Build from download (but not svn) dies -
Build from download (not svn) dies on FindSubversion.cmake but works OK when I build from -a svn get. It seems that the Cmake process expects -to be built in a 'svn' working copy. I get the process -to work by commenting the following lines from -CMakeLists.txt - -#if(UNIX) -# include(CreateSVNVersionHeader) -# create_svn_version_header() -#endif(UNIX) - ---------------------------------------- -> svn --version -svn, version 1.5.0 (dev build) - compiled Jun 7 2008, 01:10:17 --------------------------------------------- - - -If I download the tar.bz2 and build as prescribed: - - mkdir -p build/release - cd build/releasecmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=/home/ken/kicad ../../ - -I get the following message: - -CMake Error at /usr/share/cmake/Modules/FindSubversion.cmake:81 (MESSAGE): -Command "/usr/bin/svn info /home/ken/tools/kicad/kicad" failed with output: - - svn: '/home/ken/tools/kicad/kicad' is not a working copy - -Call Stack (most recent call first): - CMakeModules/CreateSVNVersionHeader.cmake:5 (Subversion_WC_INFO) - CMakeLists.txt:118 (create_svn_version_header) -
-0 - - - - - - -7369746 -IP -Artifact Created: 66.159.224.125 -1231220004 -nobody - - -7505153 -status_id -1 -1232608623 -f3nix - - -7505154 -resolution_id -100 -1232608624 -f3nix - - -7505155 -assigned_to -100 -1232608624 -f3nix - - -7505156 -allow_comments -1 -1232608624 -f3nix - - -7505157 -close_date -0 -1232608624 -f3nix - - - - -http://sourceforge.net/support/tracker.php?aid=2492717 -2492717 -2 -100 -755196 -2 -nobody -nobody -jerryjacobs -1231361803 -1267478242 -5 -Build from download (but not svn) dies -
Build from download (not svn) dies on FindSubversion.cmake but works OK when I build from -a svn get. It seems that the Cmake process expects -to be built in a 'svn' working copy. I get the process -to work by commenting the following lines from -CMakeLists.txt - -#if(UNIX) -# include(CreateSVNVersionHeader) -# create_svn_version_header() -#endif(UNIX) - ---------------------------------------- -> svn --version -svn, version 1.5.0 (dev build) - compiled Jun 7 2008, 01:10:17 --------------------------------------------- - - -If I download the tar.bz2 and build as prescribed: - - mkdir -p build/release - cd build/releasecmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=/home/ken/kicad ../../ - -I get the following message: - -CMake Error at /usr/share/cmake/Modules/FindSubversion.cmake:81 (MESSAGE): -Command "/usr/bin/svn info /home/ken/tools/kicad/kicad" failed with output: - - svn: '/home/ken/tools/kicad/kicad' is not a working copy - -Call Stack (most recent call first): - CMakeModules/CreateSVNVersionHeader.cmake:5 (Subversion_WC_INFO) - CMakeLists.txt:118 (create_svn_version_header) -
-0 - - - - - - -7382057 -IP -Artifact Created: 66.159.224.125 -1231361803 -nobody - - -9227626 -status_id -1 -1267478242 -jerryjacobs - - -9227627 -resolution_id -100 -1267478242 -jerryjacobs - - -9227628 -allow_comments -1 -1267478242 -jerryjacobs - - -9227629 -close_date -0 -1267478242 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2493551 -2493551 -2 -761682 -516020 -100 -cfdev -nobody -cfdev -1231410333 -1244792053 -5 -NetList and Pcbnew -
Version : 20080825c -OS : windowsXP, other don't tested -program : Pcbnew - - -hello, - -when the General net connection is show, there is an difference with the routing mode ? (see Attach File) - -the connection on routing mode is correct but not the other! - - -can you fixed it - -Thanks
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=308253&aid= -308253 -PB_interco.PNG - -44909 -image/png -1231410333 -cfdev - - - - -7388038 -IP -Artifact Created: 90.27.240.57 -1231410333 -cfdev - - -7388039 -File Added -308253: PB_interco.PNG -1231410333 -cfdev - - -8367971 -status_id -1 -1244792053 -cfdev - - -8367972 -allow_comments -1 -1244792053 -cfdev - - -8367973 -close_date -0 -1244792053 -cfdev - - - - -http://sourceforge.net/support/tracker.php?aid=2602865 -2602865 -1 -761682 -516020 -100 -dandumit -nobody -nobody -1234712274 -0 -5 -Change Same Modules make PCBNEW Crash -
Hi, - -A very handy function makes PCBNEW crash. -Over one module : right click mouse : -footprint>edit>change module>change same modules -On that text box it seems to update all modules from board but after that application crashes. - -REgards, -Daniel
-0 - - - - - - -7714397 -IP -Artifact Created: 89.34.224.194 -1234712274 -dandumit - - - - -http://sourceforge.net/support/tracker.php?aid=2610468 -2610468 -1 -761682 -516020 -100 -reniemarquet -nobody -nobody -1234909731 -0 -5 -Copy block in Modedit broken (20090216-RC1) -
In 20090216-RC1, - -Copying a block with pads, the modedit frezen and broken PcbNew. - -Note: tested in Win XP (SP2) and Win 2000
-0 - - - - - - -7733151 -IP -Artifact Created: 200.157.229.6 -1234909731 -reniemarquet - - - - -http://sourceforge.net/support/tracker.php?aid=2614648 -2614648 -1 -761682 -516020 -100 -reniemarquet -nobody -nobody -1235006901 -0 -5 -Button Cancel in Add Field don't work (20090216-RC1 -
In 20090216-RC1 (tested in Win XP), - -In PcbNew, right click a module, go to dialog Module Properties, click Add Field, the button Cancel -don't work, the new field is created with text = text.
-0 - - - - - - -7742210 -IP -Artifact Created: 189.25.221.16 -1235006901 -reniemarquet - - - - -http://sourceforge.net/support/tracker.php?aid=2625090 -2625090 -1 -1015288 -755198 -100 -arius-marius -nobody -nobody -1235245689 -0 -5 -CVpcb - language selection -
Hi, - -I have used KiCAD under WinXP in revision 1604. - -It is not possible to change the language for the CVpcb frame on the fly as it is possible for all the other frames like KiCad, Eeschema, ... - -/********************************************************/ -void WinEDA_CvpcbFrame::SetLanguage( wxCommandEvent& event ) -/********************************************************/ -{ - int id = event.GetId(); - - wxGetApp().SetLanguageIdentifier( id ); - wxGetApp().SetLanguage(); -} - -... could be possibly changed to ... - -/********************************************************/ -void WinEDA_CvpcbFrame::SetLanguage( wxCommandEvent& event ) -/********************************************************/ -{ - wxGetApp().SetLanguageIdentifier( event.GetId() ); - if ( wxGetApp().SetLanguage() ) - { - wxLogDebug( wxT( "Recreating menu bar due to language change." ) ); - ReCreateMenuBar(); - Refresh(); - } -} - --arius-
-0 - - -3546155 -arius-marius -1235247615 -
The proposed solution works fine and allowes switching between the languages. - --arius-
- - -3546675 -arius-marius -1235304619 -
File Added: cvpcb_language-selection.patch
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=314638&aid= -314638 -cvpcb_language-selection.patch -Patch -618 -application/octet-stream -1235304619 -arius-marius - - - - -7764533 -IP -Artifact Created: 78.55.181.244 -1235245689 -arius-marius - - -7764686 -IP -Comment Added: 78.55.181.244 -1235247616 -arius-marius - - -7768469 -File Added -314638: cvpcb_language-selection.patch -1235304619 -arius-marius - - -7768470 -IP -Comment Added: 92.227.128.196 -1235304619 -arius-marius - - - - -http://sourceforge.net/support/tracker.php?aid=2625434 -2625434 -2 -761682 -516020 -1 -arius-marius -nobody -jerryjacobs -1235253500 -1267476991 -5 -Crash after trying to edit a line/drawing -
PCBnew in revision 1604 on WinXP - -1) Start PCBnew -2) Select layer: Edges_Pcb -3) Select tool for drawing a graphical line or polygon -4) Click into the drawing area to set the beginning of the line but do not stop the drawing tool -5) Right click to get the popup menu shown and select "Edit Drawing" -> PCBnew crashes at this point - --arius-
-0 - - -3917358 -jerryjacobs -1267476991 -
Tested with new version.
- - - - - - -7765097 -IP -Artifact Created: 78.55.181.244 -1235253500 -arius-marius - - -9227539 -IP -Comment Added: 84.25.204.235 -1267476991 -jerryjacobs - - -9227540 -status_id -1 -1267476991 -jerryjacobs - - -9227541 -resolution_id -100 -1267476991 -jerryjacobs - - -9227542 -allow_comments -1 -1267476991 -jerryjacobs - - -9227543 -close_date -0 -1267476991 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2628615 -2628615 -1 -761682 -100 -100 -arius-marius -nobody -nobody -1235333230 -0 -5 -Error message after right click into zone -
A right click into a zone to start filling leads to different error messages: -a) "WinEDA_PcbFrame::OnRightClick() Error: unknown DrawType 20907816" -b) "WinEDA_PcbFrame::OnRightClick() Error: illegal DrawType 0" - -1) I have two resistors on the board both together connected with wires. -2) I have drawn a zone outline around the components. -3) Right clicked into the zone area and selected from context menu "Fill or Refill All Zones". -4) Selected from context menu "Remove Filled Areas in All Zones" -5) Right click into the zone area leads sometimes to the mentioned error messages with different numbers for the draw type. - -Repeat step 3) to 5) until the error shows if not already occured. - --arius-
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=314677&aid= -314677 -project.zip - -3714 -application/zip -1235333230 -arius-marius - - - - -7770529 -IP -Artifact Created: 92.227.128.196 -1235333230 -arius-marius - - -7770530 -File Added -314677: project.zip -1235333230 -arius-marius - - - - -http://sourceforge.net/support/tracker.php?aid=2630243 -2630243 -1 -100 -100 -100 -nobody -nobody -nobody -1235398324 -0 -5 -Unconnected pads issue -
After connecting pads with tracks, some of the connections are not recognized anymore. The connecting track is highlighted when clicking on it, but ratsnest and DRC still show the two pads as unconnected. This is not a "magnetic pads" issue, it occurs also when the tracks start exactly at the right coordinates. Google for "kicad unconnected pads", and you will find some interesting threads about it. Occurs in all versions so far.
-0 - - - - - - -7774964 -IP -Artifact Created: 89.217.201.158 -1235398324 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2653411 -2653411 -2 -1015285 -100 -2 -nobody -nobody -jerryjacobs -1235962821 -1267477927 -5 -No fields in component editor (RC4)! -
Just testing RC4 and found a great field list for schematic components. -But there is (hopefully) a bug here: The "fields" tab in the properties is completely gone! I don't think this is a feature as most users would use this to put things like stock IDs and manufacturers partnumbers in here which need to be edited at part creation time. - -
-0 - - -3568308 -oecherexpat -1236726657 -
Thanks for the help, it is NO bug.
- - -3570255 -cfdev -1236855442 -
hi, - -it's not a bug! -the fields tab has changed for an list. I use too the fields to put the manufacturers number ...Now to enter this you can click on "Add field" and specifie what you want and it will be added to the list. - -++
- - - - - - -7824590 -IP -Artifact Created: 222.153.213.254 -1235962821 -nobody - - -7887467 -IP -Comment Added: 222.153.213.254 -1236726657 -oecherexpat - - -7897539 -IP -Comment Added: 90.52.151.208 -1236855442 -cfdev - - -9227593 -status_id -1 -1267477927 -jerryjacobs - - -9227594 -resolution_id -100 -1267477927 -jerryjacobs - - -9227595 -allow_comments -1 -1267477927 -jerryjacobs - - -9227596 -close_date -0 -1267477927 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2656502 -2656502 -1 -1015285 -100 -100 -imrehg -nobody -nobody -1236060552 -0 -5 -wrong reference "transistors" library -
In the template/kicad.pro the "transistors" library is referenced as "transistor", thus resulting in error message when starting eeschema.
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=315928&aid= -315928 -template.patch -patch -289 -application/octet-stream -1236060552 -imrehg - - - - -7832744 -IP -Artifact Created: 140.109.113.62 -1236060552 -imrehg - - -7832745 -File Added -315928: template.patch -1236060552 -imrehg - - - - -http://sourceforge.net/support/tracker.php?aid=2660689 -2660689 -2 -761682 -100 -103 -rom4ik -nobody -jerryjacobs -1236156431 -1267476762 -5 -Unconnected pads in RC4 -
Symptoms are the same as for ID: 2630243. Repeatable only when using RC4 - -Problem: To route one track it is necessary to route it two times. - -Steps: -1. After the first routing http://img240.imageshack.us/img240/1061/step1.png -2. After the second routing http://img8.imageshack.us/img8/2830/step2q.png -3. Context menu for the track(s) http://img14.imageshack.us/img14/1943/step3j.png - -If the PCB is saved after the step 1 and loaded again - all OK. -
-0 - - -3559481 -rom4ik -1236156570 -
File Added: step2.PNG
- - -3559483 -rom4ik -1236156599 -
File Added: step3.PNG
- - -3917353 -jerryjacobs -1267476762 -
Don't have this problem.
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=316114&aid= -316114 -step1.PNG - -8772 -image/png -1236156431 -rom4ik - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=316116&aid= -316116 -step2.PNG - -9073 -image/png -1236156570 -rom4ik - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=316117&aid= -316117 -step3.PNG - -10277 -image/png -1236156599 -rom4ik - - - - -7842333 -IP -Artifact Created: 81.26.156.254 -1236156431 -rom4ik - - -7842334 -File Added -316114: step1.PNG -1236156431 -rom4ik - - -7842346 -File Added -316116: step2.PNG -1236156570 -rom4ik - - -7842347 -IP -Comment Added: 81.26.156.254 -1236156570 -rom4ik - - -7842355 -File Added -316117: step3.PNG -1236156599 -rom4ik - - -7842356 -IP -Comment Added: 81.26.156.254 -1236156599 -rom4ik - - -9227512 -IP -Comment Added: 84.25.204.235 -1267476762 -jerryjacobs - - -9227513 -status_id -1 -1267476762 -jerryjacobs - - -9227514 -resolution_id -100 -1267476762 -jerryjacobs - - -9227515 -allow_comments -1 -1267476762 -jerryjacobs - - -9227516 -close_date -0 -1267476762 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2661362 -2661362 -1 -1015288 -516020 -100 -jacobeluz -nobody -nobody -1236168613 -0 -5 -CVpcb open problem -
in CVpcb when klicking the open netlist it do nothing
-0 - - - - - - -7843625 -IP -Artifact Created: 212.179.61.36 -1236168613 -jacobeluz - - - - -http://sourceforge.net/support/tracker.php?aid=2680621 -2680621 -2 -761682 -516020 -1 -oecherexpat -nobody -jerryjacobs -1236726994 -1267476309 -5 -Print issue under RC4 -
When printing (not plotting) PCB documentation with more than 1 layer, the background is printed black. -For instance: Silkscreen and primary copper enabled -> background turns black on preview. Doesn't need to be a copper layer, same appears with silkscreen and solder mask enabled. - -Tested under WinXP-SP3 and 20090216-RC4
-0 - - -3917346 -jerryjacobs -1267476309 -
Closing old bug works for newer version.
- - - - - - -7887489 -IP -Artifact Created: 222.153.213.254 -1236726994 -oecherexpat - - -9227464 -IP -Comment Added: 84.25.204.235 -1267476309 -jerryjacobs - - -9227465 -status_id -1 -1267476309 -jerryjacobs - - -9227466 -resolution_id -100 -1267476309 -jerryjacobs - - -9227467 -close_date -0 -1267476309 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2680640 -2680640 -1 -1015285 -100 -100 -oecherexpat -nobody -nobody -1236727590 -0 -5 -Number of fields is fixed to 9 in BOM -
An unlimited number of fields can be created for schematic symbols. When it comes to generating the BOM, only "footprint" and the first 8 fields can be selected to be printed. - -Field names are nowhere mentioned in the generated BOM, it's left to the user to make them common. This is very flexible but might lead to mistakes. A suggestion would be to have editable but global field names which could replace the "field x" labels.
-0 - - - - - - -7887535 -IP -Artifact Created: 222.153.213.254 -1236727590 -oecherexpat - - - - -http://sourceforge.net/support/tracker.php?aid=2689603 -2689603 -1 -1015285 -100 -100 -yneko -nobody -nobody -1237267149 -0 -5 -mis-connecting of VCCs of two different voltage -
Please see this message; -http://tech.groups.yahoo.com/group/kicad-users/message/4878 - -Place one 74HC00, name it U1, click "Show hidden pins", and connect its Vcc to "+3.3V" power port and GND to "GND". -Place one 74HC04, name it U2, connect its Vcc to "+5V" power port and GND to "GND". -14pin of U1 and 14pin of U2 are connected on netlist, but they should be separated normally.
-0 - - - - - - -7930780 -IP -Artifact Created: 203.141.143.22 -1237267149 -yneko - - - - -http://sourceforge.net/support/tracker.php?aid=2692073 -2692073 -1 -1015285 -100 -100 -wolverine222 -nobody -nobody -1237391885 -0 -5 -"reset to library defaults" fails in RC6 -
The "reset to library defaults" in component properties does not change the value of the fields, only its position.
-0 - - - - - - -7947011 -IP -Artifact Created: 213.63.0.163 -1237391885 -wolverine222 - - - - -http://sourceforge.net/support/tracker.php?aid=2724843 -2724843 -1 -761682 -100 -100 -lomarcan -nobody -nobody -1238581664 -0 -5 -Offset thermaled pads don't register as 'connected' -
An oval pad (maybe rectangular too) with offset hole, when thermaled, do not always register as connected (see screen shot)
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=320638&aid= -320638 -bad_thermal.png -Screenshot of anomaly -54135 -image/png -1238581664 -lomarcan - - - - -8064289 -IP -Artifact Created: 88.149.185.186 -1238581664 -lomarcan - - -8064290 -File Added -320638: bad_thermal.png -1238581665 -lomarcan - - - - -http://sourceforge.net/support/tracker.php?aid=2738052 -2738052 -1 -761682 -755196 -100 -nobody -nobody -nobody -1239037729 -0 -5 -"Remove: StructType 19 Inattendu" on deleting zone -
Attempting to delete a zone outline in 20090216-final release causes the error "Remove: StructType 19 Inattendu". The zone is not deleted. - -Steps to reproduce: - -Open a new board, create zone outline, attempt to delete zone outline.
-0 - - - - - - -8098147 -IP -Artifact Created: 82.71.75.78 -1239037729 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2773272 -2773272 -1 -1015285 -755198 -100 -nobody -nobody -nobody -1240095334 -0 -5 -Annotation disregards U?A -
When Assigning power to only U?A but not U?B and the other units of a device and then connecting special power to that, eeschema ignores this upon annotation. Meaning it then often places the A-unit somewhere else which cuts the power connection. - -Also, as Brian Sidebotham suggested in the Newsgroup eeschema should also ideally not touch the A, B, C, D ... assignments at all during annotate. In the analog world this can cause problems because we purposely assign units per thermal tracking within chips, for crosstalk mitigation, and other reasons. - -Regards, - -Joerg Schulze-Clewing -joergsch@analogconsultants.com
-0 - - - - - - -8176350 -IP -Artifact Created: 75.26.197.12 -1240095334 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2775460 -2775460 -1 -100 -755196 -100 -bennett78 -bennett78 -nobody -1240198444 -0 -4 -minor make install bug -
# svn info -Path: . -URL: https://kicad.svn.sourceforge.net/svnroot/kicad/trunk/kicad -Repository Root: https://kicad.svn.sourceforge.net/svnroot/kicad -Repository UUID: 16bec504-3128-0410-b3e8-8e38c2123bca -Revision: 1734 -Node Kind: directory -Schedule: normal -Last Changed Author: charras -Last Changed Rev: 1734 -Last Changed Date: 2009-04-19 10:03:48 -0600 (Sun, 19 Apr 2009) -# pwd -/s/opt/svn/kicad/trunk/kicad -# make -f makefile.gtk install -make[1]: Entering directory `/s/opt/svn/kicad/trunk/kicad/internat' -cp -R cs /usr/local/kicad/share/internat -cp -R de /usr/local/kicad/share/internat -cp -R es /usr/local/kicad/share/internat -cp -R fr /usr/local/kicad/share/internat -cp -R hu /usr/local/kicad/share/internat -cp -R it /usr/local/kicad/share/internat -cp -R ko /usr/local/kicad/share/internat -cp -R pl /usr/local/kicad/share/internat -cp -R pt /usr/local/kicad/share/internat -cp -R ru /usr/local/kicad/share/internat -cp -R sl /usr/local/kicad/share/internat -make[1]: Leaving directory `/s/opt/svn/kicad/trunk/kicad/internat' -make: *** modules: No such file or directory. Stop. -make[1]: Entering directory `/s/opt/svn/kicad/trunk/kicad/template' -cp -R kicad.pro /usr/local/kicad/share/template -make[1]: Leaving directory `/s/opt/svn/kicad/trunk/kicad/template' -make: *** library: No such file or directory. Stop. -make: *** [install-res] Error 2 -# ls internat/ -total 68 -4 ca/ 4 cs/ 4 es/ 4 hu/ 4 ko/ 4 nl/ 4 pt/ 4 sl/ 4 zh_CN/ -4 CMakeLists.txt 4 de/ 4 fr/ 4 it/ 4 makefile 4 pl/ 4 ru/ 4 sv/ -# ls template/ -total 16 -4 CMakeLists.txt 8 kicad.pro 4 makefile -
-0 - - -3635295 -bennett78 -1240755923 -
This bug has been fixed
- - -3635296 -bennett78 -1240755923 -
works ok using cmake
- - - - - - -8182864 -IP -Artifact Created: 76.76.79.173 -1240198444 -bennett78 - - -8214866 -IP -Comment Added: 76.76.79.173 -1240755923 -bennett78 - - -8214867 -IP -Comment Added: 76.76.79.173 -1240755923 -bennett78 - - -8214868 -assigned_to -100 -1240755923 -bennett78 - - - - -http://sourceforge.net/support/tracker.php?aid=2779049 -2779049 -1 -1015285 -755197 -100 -nobody -nobody -nobody -1240442409 -0 -5 -Osx addpart hangs -
In Osx 10.5.6, -Kicad r-1736 Eeschema hangs, when creating new part-> Add pins. - -About dialog does not work. - -
-0 - - -3635203 -hyarion -1240749162 -
(using r-17361) -it seems to only be a problem when adding the first pin... -a quick workaround: -1) save your component without adding any pins -2) close eeschema (this way we know that the library will be reloaded) -2) open up the library in a texteditor and a pin to the component and save it -3) open up eeschema and add new pins - -The about dialog in the help menu works but not the one in the program menu
- - - - - - -8197557 -IP -Artifact Created: 195.148.50.152 -1240442410 -nobody - - -8214499 -IP -Comment Added: 85.24.222.45 -1240749164 -hyarion - - - - -http://sourceforge.net/support/tracker.php?aid=2783715 -2783715 -2 -100 -100 -1 -imrehg -nobody -imrehg -1241018427 -1241597747 -5 -make install error: missing file footprints_doc -
make install fails because of missing file in current revision (1743) and for some time now (I tried 1741 earlier and that fails as well). Here's the log cut to the relevant part: - -[......] --- Installing: /tmp/kicad-svn/pkg/usr/share/doc/kicad/help/file_formats --- Installing: /tmp/kicad-svn/pkg/usr/share/doc/kicad/help/file_formats/file_formats.pdf -CMake Error at doc/help/cmake_install.cmake:48 (FILE): - file INSTALL cannot find file - "/tmp/kicad-svn/src/kicad-doc/doc/help/footprints_doc" - to install. -Call Stack (most recent call first): - cmake_install.cmake:38 (INCLUDE) -
-0 - - -3639270 -imrehg -1241020580 -
checking out the svn tree, in rev1734 the directory was moved but the CMake files weren't changed. attached proposed fix. -(git format-patch format, sorry! :)
- - -3648338 -imrehg -1241597747 -
This bug has been fixed
- - -3648339 -imrehg -1241597747 -
rev1745 fixed this
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=324972&aid= -324972 -fix-2783715.patch -proposed fix -1592 -application/octet-stream -1241020404 -imrehg - - - - -8226988 -IP -Artifact Created: 118.168.179.18 -1241018427 -imrehg - - -8227109 -File Added -324972: fix-2783715.patch -1241020404 -imrehg - - -8227118 -IP -Comment Added: 118.168.179.18 -1241020580 -imrehg - - -8251861 -IP -Comment Added: 140.109.112.215 -1241597747 -imrehg - - -8251862 -IP -Comment Added: 140.109.112.215 -1241597747 -imrehg - - -8251863 -status_id -1 -1241597747 -imrehg - - -8251864 -resolution_id -100 -1241597747 -imrehg - - -8251865 -allow_comments -1 -1241597747 -imrehg - - -8251866 -close_date -0 -1241597747 -imrehg - - - - -http://sourceforge.net/support/tracker.php?aid=2788629 -2788629 -2 -1015285 -755198 -1 -henryvt -nobody -jerryjacobs -1241729593 -1267478792 -5 -Clock pins incorrect in 74LS393 -
The clock pins are currently common to both halves of the 74LS393. The attached patch fixes this. (svn diff to 1754)
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=326162&aid= -326162 -74393.patch -svn diff aginst svn rev 1754 -996 -text/x-diff -1241729594 -henryvt - - - - -8257099 -IP -Artifact Created: 75.8.123.171 -1241729594 -henryvt - - -8257100 -File Added -326162: 74393.patch -1241729595 -henryvt - - -9227669 -status_id -1 -1267478792 -jerryjacobs - - -9227670 -resolution_id -100 -1267478792 -jerryjacobs - - -9227671 -allow_comments -1 -1267478792 -jerryjacobs - - -9227672 -close_date -0 -1267478792 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2790760 -2790760 -2 -761682 -755196 -6 -nobody -nobody -jerryjacobs -1242145667 -1267479205 -5 -very slow PCBNEW -
moving, rotating, placing modules is very slow when version 2.16 of package libgtk2.0-0 (debian package) is used -package description: http://packages.debian.org/search?suite=all&section=all&arch=any&searchon=names&keywords=libgtk2.0-0 -with version 2.12 and 2.14 PCBNEW is OK, with 2.16 PCBNEW is slow, other GTK+ applications are OK
-0 - - -3658430 -jerryjacobs -1242851376 -
I have no problems here: -Debian 64Bits (Testing/Unstable), GTK2+ 2.16.1, KiCad SVN 1771
- - -3791082 -nobody -1256658858 -
Problem disappears. It was caused probably by inconsistency in libraries versions.
- - - - - - -8274835 -IP -Artifact Created: 147.229.200.42 -1242145667 -nobody - - -8300617 -IP -Comment Added: 84.25.219.10 -1242851376 -jerryjacobs - - -8821252 -IP -Comment Added: 147.229.220.96 -1256658858 -nobody - - -9227707 -status_id -1 -1267479205 -jerryjacobs - - -9227708 -resolution_id -100 -1267479205 -jerryjacobs - - -9227709 -allow_comments -1 -1267479205 -jerryjacobs - - -9227710 -close_date -0 -1267479205 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2797109 -2797109 -2 -761682 -755198 -100 -bennett78 -nobody -bennett78 -1243378709 -1244414173 -7 -ratsnest on connected nets -
The attached 4 layer design example has 2 pins connected to a GND plane zone on an internal -layer using 2 through hole vias. The ratsnest still shows an non-connection between the two pins. -Freeroute doesn't show the extra ratsnests. But I wonder if the via type is correct! - -Using a two sided board seems to work ok.
-0 - - -3669588 -bennett78 -1244139351 -
All nets (connections) to Zones show as disconnects until zone fills are enabled -and then agree with DRC. However the rat's nest is hard to see with zones filled. - -Filled zones show keepout areas but should not be necessary to detect connectivity. -I suggest that vias to named zones be considered good enough to establish a -connection and not showup in the rats nest.
- - -3671567 -bennett78 -1244414173 -
Workaround - select from left toolbar "don't show filled area in zones" then run DRC - -Note: turning general rats nest on/off via left toolbar misses a Redraw event for off! -Requiring a redraw button push.
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=328554&aid= -328554 -rats.zip -eeschema, netl and brd file -3436 -application/zip -1243378709 -bennett78 - - - - -8316899 -IP -Artifact Created: 76.76.79.173 -1243378709 -bennett78 - - -8316900 -File Added -328554: rats.zip -1243378710 -bennett78 - - -8344692 -IP -Comment Added: 76.76.79.173 -1244139351 -bennett78 - - -8352444 -IP -Comment Added: 76.76.79.173 -1244414173 -bennett78 - - -8352445 -status_id -1 -1244414173 -bennett78 - - -8352446 -allow_comments -1 -1244414173 -bennett78 - - -8352447 -close_date -0 -1244414173 -bennett78 - - - - -http://sourceforge.net/support/tracker.php?aid=2797788 -2797788 -2 -761682 -755198 -1 -nobody -diemer -jerryjacobs -1243502912 -1267478119 -5 -Module Editor: Display Grid Button not working -
In r1783 the "Display Grid" Button in the footprint editor (module editor) isn't working as expected: When pressed, the grid disappears as desired. However, there is no way to re-enable the grid by pressing the button again.
-0 - - -3663728 -paxer -1243505015 -
Here is a patch: - - -Index: pcbnew/tool_modedit.cpp -=================================================================== ---- pcbnew/tool_modedit.cpp (revision 1783) -+++ pcbnew/tool_modedit.cpp (working copy) -@@ -203,8 +203,10 @@ - - m_OptionsToolBar->AddTool( ID_TB_OPTIONS_SHOW_GRID, wxEmptyString, - wxBitmap( grid_xpm ), -- _( "Display Grid OFF" ) ); -+ _( "Display Grid OFF" ), wxITEM_CHECK ); - -+ m_OptionsToolBar->ToggleTool( ID_TB_OPTIONS_SHOW_GRID, m_Draw_Grid ); -+ - m_OptionsToolBar->AddTool( ID_TB_OPTIONS_SHOW_POLAR_COORD, wxEmptyString, - wxBitmap( polar_coord_xpm ), - _( "Display Polar Coord ON" ), wxITEM_CHECK ); -
- - -3663803 -diemer -1243510744 -
Applied patch in r1785
- - - - - - -8321166 -IP -Artifact Created: 134.169.117.87 -1243502912 -nobody - - -8321316 -IP -Comment Added: 134.169.117.87 -1243505015 -paxer - - -8321498 -artifact_group_id -100 -1243509895 -diemer - - -8321499 -assigned_to -100 -1243509895 -diemer - - -8321576 -IP -Comment Added: 134.169.117.46 -1243510744 -diemer - - -8321577 -resolution_id -100 -1243510744 -diemer - - -9227613 -status_id -1 -1267478119 -jerryjacobs - - -9227614 -allow_comments -1 -1267478119 -jerryjacobs - - -9227615 -close_date -0 -1267478119 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2801809 -2801809 -2 -1015285 -755198 -1 -cfdev -nobody -cfdev -1244217274 -1270653409 -5 -Translation bug -
Hi, -see the attach file ;) -EESCHEMA stable 20090216-Final - -++
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=329867&aid= -329867 -Translation_bug.png - -14071 -image/png -1244217274 -cfdev - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=331195&aid= -331195 -rename_file.png - -12283 -image/png -1245165180 -cfdev - - - - -8347302 -IP -Artifact Created: 90.52.202.205 -1244217274 -cfdev - - -8347303 -File Added -329867: Translation_bug.png -1244217274 -cfdev - - -8380400 -File Added -331195: rename_file.png -1245165180 -cfdev - - -9374967 -status_id -1 -1270653409 -cfdev - - -9374968 -resolution_id -100 -1270653409 -cfdev - - -9374969 -close_date -0 -1270653409 -cfdev - - - - -http://sourceforge.net/support/tracker.php?aid=2802877 -2802877 -2 -1015285 -755198 -1 -cfdev -nobody -cfdev -1244462389 -1244791484 -5 -Properties of libEdit -
hi - -In the properties of libEdit, the tab "DOC" and the field "Doc" are visibly an not good nomination. (see the attach file) -"Description" are better ?
-0 - - -3672100 -nobody -1244467832 -
Bug closed on svn trunk 1810
- - -3672102 -nobody -1244467848 -
Bug closed on svn trunk 1810
- - -3675325 -cfdev -1244791484 -
This bug has been fixed
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=330161&aid= -330161 -Properties_LibEdit.png - -9736 -image/png -1244462390 -cfdev - - - - -8354126 -IP -Artifact Created: 90.52.202.205 -1244462390 -cfdev - - -8354127 -File Added -330161: Properties_LibEdit.png -1244462390 -cfdev - - -8354925 -IP -Comment Added: 84.25.137.47 -1244467832 -nobody - - -8354930 -IP -Comment Added: 84.25.137.47 -1244467848 -nobody - - -8367952 -IP -Comment Added: 90.52.202.205 -1244791484 -cfdev - - -8367953 -status_id -1 -1244791484 -cfdev - - -8367954 -resolution_id -100 -1244791484 -cfdev - - -8367955 -allow_comments -1 -1244791484 -cfdev - - -8367956 -close_date -0 -1244791484 -cfdev - - - - -http://sourceforge.net/support/tracker.php?aid=2803506 -2803506 -2 -1015285 -755198 -1 -cfdev -nobody -cfdev -1244554724 -1244789299 -5 -Mirror of an bloc of bus connection -
hi, - -I saw an bug when I mirrored an bloc of bus... see the attach file - -thx
-0 - - -3674999 -jerryjacobs -1244748173 -
Bug fixed SVN-1812 - -2009-june-11 UPDATE Jean-Pierre Charras <jean-pierre.charras@gipsa-lab.inpg.fr> -================================================================================ -++Eeschema: - Added text justification for graphic texts in libedit - Minor bug 2803506 fixed (error when mirroring bus entries) - Some code cleaning. - Better locating algo for arcs in libedit
- - -3675316 -cfdev -1244789210 -
well done
- - -3675317 -cfdev -1244789299 -
This bug has been fixed
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=330328&aid= -330328 -bus_mirrors.png - -8713 -image/png -1244554725 -cfdev - - - - -8358315 -IP -Artifact Created: 90.52.202.205 -1244554725 -cfdev - - -8358316 -File Added -330328: bus_mirrors.png -1244554725 -cfdev - - -8366664 -IP -Comment Added: 84.25.137.47 -1244748173 -jerryjacobs - - -8367900 -IP -Comment Added: 90.52.202.205 -1244789210 -cfdev - - -8367901 -IP -Comment Added: 90.52.202.205 -1244789299 -cfdev - - -8367902 -status_id -1 -1244789299 -cfdev - - -8367903 -resolution_id -100 -1244789299 -cfdev - - -8367904 -allow_comments -1 -1244789299 -cfdev - - -8367905 -close_date -0 -1244789299 -cfdev - - - - -http://sourceforge.net/support/tracker.php?aid=2807228 -2807228 -1 -1015285 -100 -100 -briansidebotham -nobody -nobody -1245166312 -0 -5 -Adding a library with a relative library path -
If when editing the Preferences->Library dialog, a relative path is used -for the Default library file path, KiCad successfully navigates to the -correct directory when the Add button is used to add a library. However, -instead of adding the selected library name, it adds the complete file path -instead. - -If the .pro preferences file is edited by hand the relative library path -works fine.
-0 - - - - - - -8380481 -IP -Artifact Created: 87.74.132.43 -1245166312 -briansidebotham - - - - -http://sourceforge.net/support/tracker.php?aid=2807295 -2807295 -1 -1015285 -100 -100 -nobody -nobody -nobody -1245174876 -0 -5 -Error in cursor position -
I just dled the latest build for the osx (nice that there is a mac build, thanks). However when moving parts and adding wires, I have to offset the cursor in order for it to be at the proper place. basically I have to go about 45 degrees NE of where it should be. This makes doing anything quite a chore. - -Also shouldn't it create automatically the noname.pro, the first time kikad is run?
-0 - - - - - - -8380891 -IP -Artifact Created: 189.137.59.158 -1245174876 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2810360 -2810360 -2 -761682 -516020 -1 -lodentoni -nobody -jerryjacobs -1245686902 -1267478558 -5 -negative plot is complete black -
Hi, -there is a problem with generating negative plots in postscript format. If I try to plot layers which contain text items the generated *.ps file shows a complete black board. -I discussed it on mikrocontroller.net. We found out that in the .ps file are wrong lines ("0.000 0.000 0.000 setrgbcolor"), if they were deleted, the negative plot did work. - -I use FreePDFXP to generate PDFs from the .ps file.
-0 - - -3917388 -jerryjacobs -1267478558 -
Board plots correct with 2010-02-28-RC5
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=331946&aid= -331946 -Filmtest.brd -example file -205076 -application/octet-stream -1245686903 -lodentoni - - - - -8397600 -IP -Artifact Created: 193.174.73.86 -1245686903 -lodentoni - - -8397601 -File Added -331946: Filmtest.brd -1245686904 -lodentoni - - -9227652 -IP -Comment Added: 84.25.204.235 -1267478558 -jerryjacobs - - -9227653 -status_id -1 -1267478558 -jerryjacobs - - -9227654 -resolution_id -100 -1267478558 -jerryjacobs - - -9227655 -allow_comments -1 -1267478558 -jerryjacobs - - -9227656 -close_date -0 -1267478558 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2813170 -2813170 -1 -1015285 -755196 -100 -sergeiste -nobody -nobody -1246094130 -0 -5 -senselsess/unhelpful error message -
I have a multi-level block/schematics (3 levels of hierarchy). - -If I'm running "Schematic Annotation" on the whole schematics, I'm getting the a popup window with the following error message: - -Multiple item C1 (unit 1) -. - -The version is: Build: (20090216-final) (SUSE-10.3). - -Since 'eeschema' is capable of detecting multiple "C1" items, it knows in which subblocks/files th eitem is present, so to make this message sensible/helpful it should tell the use where to look for the mistake he/she has made - it doesn't at the moment. - -If necessary, I'll upload the schematics, but as far as I can tell from the message the bug is not specific WRT my schematics, i.e. it will manifest itself in any similar case.
-0 - - - - - - -8412887 -IP -Artifact Created: 87.69.49.127 -1246094130 -sergeiste - - - - -http://sourceforge.net/support/tracker.php?aid=2813187 -2813187 -2 -1015285 -755196 -1 -sergeiste -nobody -jerryjacobs -1246097678 -1267478210 -5 -'eeschema' segfaults when requested to create BOM -
This is apparently a regression - it happens in kicad-2009-02-16-final and it doesn't happen in kicad-full-version-2008-08-25c-final. - -BOM == Bill of materials. - -The details. - -If I start 'eeschema' afresh, with no editor to browse BOM set, in kicad-full-version-2008-08-25c-final 'eeschema' first asks about the editor location, I then enter full path to the editor, them it creates BOM. - -In case of kicad-2009-02-16-final 'eeschema' does not ask about editor location and just crashes with segmentation fault.
-0 - - -3917382 -jerryjacobs -1267478210 -
BOM creation reworked, should work now.
- - - - - - -8412998 -IP -Artifact Created: 87.69.49.127 -1246097678 -sergeiste - - -8412999 -priority -5 -1246097774 -sergeiste - - -9227619 -IP -Comment Added: 84.25.204.235 -1267478210 -jerryjacobs - - -9227620 -status_id -1 -1267478210 -jerryjacobs - - -9227621 -resolution_id -100 -1267478210 -jerryjacobs - - -9227622 -priority -8 -1267478210 -jerryjacobs - - -9227623 -allow_comments -1 -1267478210 -jerryjacobs - - -9227624 -close_date -0 -1267478210 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2813190 -2813190 -1 -1015285 -755196 -100 -sergeiste -nobody -nobody -1246098758 -0 -5 -wrong BOM generation for hierarchical block -
As a simple case I have two blocks, let's call the 'father', 'son', and 'son' is instantiated four times into 'father'. - -If I choose to generate BOM (Bill of materials) for 'father', I'm getting it only for the 'father', but not for the sons. This is senseless - I need BOM for the whole thing in order to correctly create the list of components I need to order. - -And such hierarchical BOM generation should be the default.
-0 - - - - - - -8413014 -IP -Artifact Created: 87.69.49.127 -1246098758 -sergeiste - - - - -http://sourceforge.net/support/tracker.php?aid=2813197 -2813197 -1 -1015285 -755196 -100 -sergeiste -nobody -nobody -1246099870 -0 -5 -wrong BOM generation for hierarchical block -
As a simple case I have two blocks, let's call the 'father', 'son', and 'son' is instantiated four times into 'father'. - -If I choose to generate BOM (Bill of materials) for 'father', I'm getting it only for the 'father', but not for the sons. This is senseless - I need BOM for the whole thing in order to correctly create the list of components I need to order. - -And such hierarchical BOM generation should be the default.
-0 - - - - - - -8413045 -IP -Artifact Created: 87.69.49.127 -1246099870 -sergeiste - - - - -http://sourceforge.net/support/tracker.php?aid=2813200 -2813200 -1 -1015285 -755196 -100 -sergeiste -nobody -nobody -1246100364 -0 -5 -'eeschema' allows instances with the same name -
When I add sons to top level block using "Place the hierarchical sheet", a form with two fields pops up - the fields are file name and sheet name. - -While the file name can be any, and can be repetitive (several instances of the same subblock), sheet name, which is instance name, should be unique in a given sheet. - -In a hierarchical design items are identifies as - -top_level.instance_name_1.instance_name_2...instance_name_N.item_name - -where item_name is node, component, etc. - -I.e. at each hierarchical level instance names should be unique - otherwise it's impossible to differentiate between the instances. It's the same as if in a family twins are born, they are given different names - twins in this case are like different instances of the same subblock.
-0 - - - - - - -8413057 -IP -Artifact Created: 87.69.49.127 -1246100364 -sergeiste - - - - -http://sourceforge.net/support/tracker.php?aid=2813959 -2813959 -2 -1015287 -516020 -102 -cfdev -nobody -cfdev -1246280321 -1270653742 -6 -Gerber import incorrect -
Hi, -To replace the missing import dxf or svg..., I tried to import the gerber generate by ORCAD in GerbView in first, and export to pcbnew in second... - -I was 2 bugs : --when I load the gbr file in GerbView this is an different with the GC-prevue (gerber tool free).the circle is normally not complet, but GerbView draw an entire circle !!?? - --Wen I export this gbr file to pcbnew with GerbView, Pcbnew draws an polygone ?! - -see the attach file -++ -
-0 - - -3955347 -cfdev -1270653742 -
Only -> Gerbview to pcbnew It's Ok
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=332785&aid= -332785 -Gerber_import.png -gerber import -30100 -image/png -1246280321 -cfdev - - - - -8417218 -IP -Artifact Created: 90.52.63.25 -1246280321 -cfdev - - -8417219 -File Added -332785: Gerber_import.png -1246280321 -cfdev - - -8417222 -priority -5 -1246280371 -cfdev - - -9227667 -summary -Import Gerber wasn't correct ?! -1267478761 -jerryjacobs - - -9374996 -IP -Comment Added: 92.153.22.228 -1270653742 -cfdev - - -9374997 -status_id -1 -1270653742 -cfdev - - -9374998 -resolution_id -100 -1270653742 -cfdev - - -9374999 -close_date -0 -1270653742 -cfdev - - - - -http://sourceforge.net/support/tracker.php?aid=2819678 -2819678 -2 -100 -100 -1 -mnurolcay -nobody -jerryjacobs -1247238686 -1267478824 -5 -start up error -
Im using the latest svn revision of Kicad, im getting an error for all start ups what says "the project file not found bla bla". Just attached screenshot
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=334524&aid= -334524 -kicad.png -Kicad start up error -37077 -image/png -1247238687 -mnurolcay - - - - -8455879 -IP -Artifact Created: 78.161.89.148 -1247238687 -mnurolcay - - -8455880 -File Added -334524: kicad.png -1247238687 -mnurolcay - - -9227674 -status_id -1 -1267478824 -jerryjacobs - - -9227675 -resolution_id -100 -1267478824 -jerryjacobs - - -9227676 -allow_comments -1 -1267478824 -jerryjacobs - - -9227677 -close_date -0 -1267478824 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2825880 -2825880 -2 -761682 -516020 -100 -cfdev -nobody -cfdev -1248340641 -1270653964 -4 -[PCBNEW]Preview of print -
PCBNEW stable version 20090216 final - -I have 4 layers, In preview of print, the interne layers 2 and 3 are inverse ! -to show this I have annotate all layers. it's an small bug ok. - -++
-0 - - - - - - -8499477 -IP -Artifact Created: 90.52.57.77 -1248340641 -cfdev - - -8499478 -priority -5 -1248340658 -cfdev - - -9375018 -status_id -1 -1270653964 -cfdev - - -9375019 -allow_comments -1 -1270653964 -cfdev - - -9375020 -close_date -0 -1270653964 -cfdev - - - - -http://sourceforge.net/support/tracker.php?aid=2828243 -2828243 -1 -1015285 -100 -100 -brummig -nobody -nobody -1248765255 -0 -5 -Component Footprint Dialog Faulty -
Selecting Edit Component...Footprint from the context menu displays in a simple dialog the current text of the component footprint (eg SM0603). If one clicks OK the footprint is retained, but if one clicks Cancel the entire text is deleted from the footprint field (rather than any edits being ignored). - -EESCHEMA 20090216-final running on WinXP/SP3, but probably also affects the previous EESCHEMA release as that was when I first noticed that I appeared to be randomly losing footprint assignments.
-0 - - - - - - -8513812 -IP -Artifact Created: 83.216.148.11 -1248765255 -brummig - - - - -http://sourceforge.net/support/tracker.php?aid=2831506 -2831506 -1 -100 -755196 -100 -frohro -nobody -nobody -1249308323 -0 -5 -Path Names with spaces don't work for Component Docs -
If you want to like a PDF datasheet to a library component, there is a nice way to do this in the library editor, however it seems not to work if your path contains spaces in it. For example this path fails: - -/home/frohro/Araya Classes/Prop & Rad/DG8SAQ VNA/AD9859.pdf - -Rob
-0 - - - - - - -8534214 -IP -Artifact Created: 66.62.174.7 -1249308323 -frohro - - - - -http://sourceforge.net/support/tracker.php?aid=2836106 -2836106 -1 -761682 -516020 -100 -brummig -nobody -nobody -1250069065 -0 -5 -CombineAreas() Error -
After moving a node on a copper layer zone PCBNew displayed a message box: - -Error -! BOARD::CombineAreas() error: unexpected outside contour descriptor -[OK] - -Clicking OK caused the message box to be redisplayed, seemingly ad-infinitum. PCBNew had to be shut down forcibly with the task manager. - -Windows XP/SP3/PCBNew 20090216-final/WxWidgets 2.8.10 Unicode -
-0 - - - - - - -8561142 -IP -Artifact Created: 83.216.148.11 -1250069065 -brummig - - - - -http://sourceforge.net/support/tracker.php?aid=2836748 -2836748 -1 -761682 -755196 -100 -bioname -charras -nobody -1250147319 -0 -5 -dialog_edit_module_for_modedit_base.cpp -
CMake Error in pcbnew/CMakeLists.txt: - Cannot find source file "dialog_edit_module_for_modedit_base.cpp". Tried - extensions .c .C .c++ .cc .cpp .cxx .m .M .mm .h .hh .h++ .hm .hpp .hxx .in - .txx -At revision 1921. (1920) -found: -pcbnew/dialog_edit_module_for_Modedit_base.cpp
-1 - - -3724387 -bioname -1250147737 -
also -dialog_edit_module_for_Modedit.cpp -pls update pcbnew/CMakeLists.txt
- - -3724427 -bioname -1250151142 -
pls update files: -CMakeLists.txt -+ dialog_edit_module_for_Modedit_base.cpp -- dialog_edit_module_for_modedit_base.cpp -+ dialog_edit_module_for_Modedit.cpp -- dialog_edit_module_for_modedit.cpp - -dialog_edit_module_for_Modedit.cpp --#include "dialog_edit_module_for_modedit.h" -+#include "dialog_edit_module_for_Modedit.h" - -dialog_edit_module_for_Modedit.h --#include "dialog_edit_module_for_modedit_base.h" -+#include "dialog_edit_module_for_Modedit_base.h" - -modedit.cpp --#include "dialog_edit_module_for_modedit.h" -+#include "dialog_edit_module_for_Modedit.h" -
- - - - - - -8564217 -IP -Artifact Created: 194.110.126.3 -1250147319 -bioname - - -8564237 -IP -Comment Added: 194.110.126.3 -1250147737 -bioname - - -8564327 -IP -Comment Added: 194.110.126.3 -1250151142 -bioname - - -8564328 -artifact_group_id -100 -1250151142 -bioname - - -8564329 -assigned_to -100 -1250151142 -bioname - - -8564330 -is_private -0 -1250151142 -bioname - - - - -http://sourceforge.net/support/tracker.php?aid=2839630 -2839630 -1 -761682 -516020 -100 -nobody -nobody -nobody -1250604186 -0 -5 -connecting net to GND zone - -
after refilling a GND zone in layer Inner_L1 on a 4 layer PCB, net "Sheet4A1" is connected to ground plane !! - -
-0 - - -3740337 -zougloub -1252015312 -
Hi, - -I can also reproduce the problem. -Procedure : - - load the model supplied by "nobody" - - click "add zones" - - perform a refill of zones - - diplay the L1 layer - -Then you can see on the bottom left part that the signal Sheet4A1 is connected to the ground plane. - -When using a 32-segment/360° arcs approximation in the fill zone, the bug does not appear when filling the zone. -
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=339609&aid= -339609 -Inner_L1-refilling-PB.brd -board -188296 -application/octet-stream -1250604186 -nobody - - - - -8582448 -IP -Artifact Created: 207.134.5.122 -1250604186 -nobody - - -8582449 -File Added -339609: Inner_L1-refilling-PB.brd -1250604187 -nobody - - -8634128 -IP -Comment Added: 207.134.5.122 -1252015312 -zougloub - - - - -http://sourceforge.net/support/tracker.php?aid=2840150 -2840150 -2 -1015288 -755198 -100 -jerryjacobs -nobody -jerryjacobs -1250673352 -1250785911 -5 -Close component view closes cvpcb bug -
Hi Jerry, - -I have one more problem with Kicad (rev. 1931). If you close the component-preview window of cvpcb, cvpcb also closes itself. Can you please fix this? - -Thanks -Michael
-0 - - -3730097 -nobody -1250778881 -
fix by charras. Thanks!
- - -3730181 -jerryjacobs -1250785910 -
Closed by Jean-Pierre Charras
- - - - - - -8585931 -IP -Artifact Created: 84.25.137.47 -1250673352 -jerryjacobs - - -8590274 -IP -Comment Added: 87.163.116.176 -1250778881 -nobody - - -8590548 -IP -Comment Added: 84.25.137.47 -1250785911 -jerryjacobs - - -8590549 -status_id -1 -1250785911 -jerryjacobs - - -8590550 -close_date -0 -1250785911 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2840153 -2840153 -2 -761682 -100 -100 -jerryjacobs -nobody -jerryjacobs -1250673511 -1250785966 -5 -PCBnew svn 1931 text size edit error and then closes -
Hi, - -also in PCBnew rev. 1931 is a bug: When you edit a module, and set the text size, and make it more little a message box occures: "Text size will be claimed". Then pcbnew closes itself. Hope you can also help me with this issue. - -Thanks a lot - -Michael
-0 - - -3730098 -nobody -1250778910 -
fixed by charras. Thanks!
- - -3730183 -jerryjacobs -1250785966 -
Closed by Jean-Pierre Charras
- - - - - - -8585937 -IP -Artifact Created: 84.25.137.47 -1250673511 -jerryjacobs - - -8590276 -IP -Comment Added: 87.163.116.176 -1250778910 -nobody - - -8590552 -IP -Comment Added: 84.25.137.47 -1250785966 -jerryjacobs - - -8590553 -status_id -1 -1250785966 -jerryjacobs - - -8590554 -allow_comments -1 -1250785966 -jerryjacobs - - -8590555 -close_date -0 -1250785966 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2840154 -2840154 -2 -761682 -100 -100 -jerryjacobs -nobody -jerryjacobs -1250673612 -1250786005 -5 -PCBnew netlist bad module to delete closes pcbnew -
Hi Jerry, - -sorry for sending you so much bugs. But I have one more problem: If you read the netlist for the pcb and set bad modules to delete, you are ask if it's okay. If you press okay, pcbnew just closes. - -Sorry for sending you so much bugs, but you are my kicad-contact-person number one. - -Michael
-0 - - -3730100 -nobody -1250778956 -
Fixed by Charras. Thanks. Michael
- - -3730184 -jerryjacobs -1250786005 -
Closed by Jean-Pierre Charras
- - - - - - -8585938 -IP -Artifact Created: 84.25.137.47 -1250673612 -jerryjacobs - - -8590278 -IP -Comment Added: 87.163.116.176 -1250778956 -nobody - - -8590556 -IP -Comment Added: 84.25.137.47 -1250786005 -jerryjacobs - - -8590557 -status_id -1 -1250786005 -jerryjacobs - - -8590558 -allow_comments -1 -1250786005 -jerryjacobs - - -8590559 -close_date -0 -1250786005 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2849000 -2849000 -1 -100 -100 -100 -nobody -nobody -nobody -1251888110 -0 -5 -Bottommask Soldering stop: Viapads not print -
I just want to order a pcb, and my manufaturare tells me that the bottom pads are not okay. Eg. Via Pads are not printed. TOP is all right! Could you please fix this very very fast? - -Thank you a lot! - -Michael - -Please look at the attachment -
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=341463&aid= -341463 -crisdriver1rc2v2-loetstopp.zip - -3054 -application/zip -1251888111 -nobody - - - - -8628341 -IP -Artifact Created: 217.233.178.203 -1251888110 -nobody - - -8628342 -File Added -341463: crisdriver1rc2v2-loetstopp.zip -1251888111 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2870835 -2870835 -1 -1015285 -755198 -100 -nobody -nobody -nobody -1254326956 -0 -5 -Direction wrong in global/hierarchical label properties -
I do not know whether the radio buttons "right up left down" are supposed to refer to the text or to the connection point. Either way, they are wrong 50% of the time. The text actually goes "left up right down" while the connection point goes "right down left up". - -My preference would be to refer to the connection point, and simply relabel the radio buttons in the order "right down left up". - --- Pat Maupin
-0 - - - - - - -8723638 -IP -Artifact Created: 209.217.155.166 -1254326956 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2874346 -2874346 -1 -1015285 -100 -100 -sb-sf -nobody -nobody -1254950934 -0 -5 -Annotation exchanges parts and breaks circuit -
If component parts contains different component elements (such as relay coil in one part and contacts in other) annotation can change part numbers and replace coil part with contacts part. Annotation should not change parts in heterogeneous components, other words if part created with "Edit pins part per part" turned on.
-0 - - -3775275 -nobody -1255285282 -
False. -This is option "Parts are locked" that must be checked
- - - - - - -8747123 -IP -Artifact Created: 91.135.22.160 -1254950934 -sb-sf - - -8760464 -IP -Comment Added: 90.9.167.135 -1255285282 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2883987 -2883987 -1 -761682 -100 -100 -nobody -nobody -nobody -1256223796 -0 -5 -Can't import *ses -
I tried to use the online Freerouter and it worked out fine. My problem is that whenever I try to import the generated *.ses file I get the following error-message: -Expecting 'number' in file C:\...\project.ses on line 62 at offset 21 -BOARD may be corrupted, do not save it. -Fix problem and try again. -What's the problem?
-0 - - - - - - -8805288 -IP -Artifact Created: 129.187.5.225 -1256223796 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2885162 -2885162 -2 -100 -100 -1 -nobody -nobody -jerryjacobs -1256346001 -1267476032 -5 -Documentation Needs Updating.... -
Hi, - -The help files say Shift Left Mouse Button mirrors, but that seems out of date. Similar problems with other button mouse combinations. The pages for these updates are 8 and 9. - -Rob
-0 - - -3917339 -jerryjacobs -1267476032 -
Done some time ago by jean-pierre
- - - - - - -8810426 -IP -Artifact Created: 66.62.174.2 -1256346001 -nobody - - -9227434 -IP -Comment Added: 84.25.204.235 -1267476032 -jerryjacobs - - -9227435 -status_id -1 -1267476032 -jerryjacobs - - -9227436 -resolution_id -100 -1267476032 -jerryjacobs - - -9227437 -allow_comments -1 -1267476032 -jerryjacobs - - -9227438 -close_date -0 -1267476032 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2885164 -2885164 -2 -1015285 -755196 -100 -frohro -nobody -frohro -1256346382 -1256676494 -5 -ERC Arrows don't change color when Options Change -
Hi, -I was successful changing the arrow color in EESchema only once. Now it is stuck with the red color I chose, no matter what I select in the preferences. I'll upload the schematic file. - -Rob
-0 - - -3791314 -frohro -1256676492 -
This appears to be fixed as of r2056 at least in svn.
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=347967&aid= -347967 -VNA.sch -Schematic that the color won't change in. -71449 -application/octet-stream -1256346382 -frohro - - - - -8810440 -IP -Artifact Created: 66.62.174.2 -1256346382 -frohro - - -8810441 -File Added -347967: VNA.sch -1256346382 -frohro - - -8822232 -IP -Comment Added: 66.62.165.3 -1256676492 -frohro - - -8822233 -status_id -1 -1256676494 -frohro - - -8822234 -allow_comments -1 -1256676494 -frohro - - -8822235 -close_date -0 -1256676494 -frohro - - - - -http://sourceforge.net/support/tracker.php?aid=2886059 -2886059 -2 -761682 -100 -100 -frohro -nobody -frohro -1256497453 -1256676045 -5 -3D Viewer doesn't show text mirrored correctly. -
The text on the 3D viewer copper layer isn't shown reading correctly when mirrored. (You should be able to rotate the board around and see it correctly, but it doesn't show that way. It is still backwards.) - -Rob
-0 - - -3791308 -frohro -1256676043 -
This appears to be fixed at least in r2056.
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=348134&aid= -348134 -$savepcb-drc.rpt -Here is an example file. -170 -application/octet-stream -1256497454 -frohro - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=348171&aid= -348171 -M0DFI.lib -library file needed -18101 -application/octet-stream -1256523211 -frohro - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=348172&aid= -348172 -attiny.lib -another library file needed for the example -15083 -application/octet-stream -1256523249 -frohro - - - - -8815683 -IP -Artifact Created: 66.62.174.2 -1256497453 -frohro - - -8815684 -File Added -348134: $savepcb-drc.rpt -1256497454 -frohro - - -8816447 -File Added -348171: M0DFI.lib -1256523212 -frohro - - -8816448 -File Added -348172: attiny.lib -1256523249 -frohro - - -8822203 -IP -Comment Added: 66.62.165.3 -1256676043 -frohro - - -8822204 -status_id -1 -1256676045 -frohro - - -8822205 -allow_comments -1 -1256676045 -frohro - - -8822206 -close_date -0 -1256676045 -frohro - - - - -http://sourceforge.net/support/tracker.php?aid=2886431 -2886431 -1 -1015285 -755196 -100 -frohro -nobody -nobody -1256557413 -0 -5 -Powers with different names, & same pin names are connected. -
I have four regulators for different analog and digital power supplies on my circuit supplying the same voltage. So I made them up by copying one and changing the names of the powers, however, I did not change the pin names because they all are the same voltage. EESchema makes them all connected at least according to ERC. I think this is unexpected behavior that could cause circuit errors. - -You can find the circuit in my last bug report, number 2886059. The problems are with AVDD_RF AVDD_LO and +1.8VD_LO and +1.8VD_RF being connected. - -Rob
-0 - - -3790971 -charras -1256648597 -
I do not see any schematic file and library cache file uploaded. -Any *must* give the version of kicad you are using.
- - -3791323 -frohro -1256676964 -
This is still there as of r2056.
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=348442&aid= -348442 -VNA.sch -This is the correct file, not the one in the previous bug, but the libraries are still needed. -75102 -application/octet-stream -1256677093 -frohro - - - - -8817272 -IP -Artifact Created: 66.62.174.2 -1256557414 -frohro - - -8820768 -IP -Comment Added: 81.255.31.5 -1256648597 -charras - - -8822271 -IP -Comment Added: 66.62.165.3 -1256676964 -frohro - - -8822274 -File Added -348442: VNA.sch -1256677093 -frohro - - - - -http://sourceforge.net/support/tracker.php?aid=2888951 -2888951 -2 -100 -100 -1 -frohro -nobody -stambaughw -1256839106 -1268752763 -5 -Zoom scroll jumps around now.... -
Since the last development release I note that when you use the scroll wheel to zoom, the center point that you are zooming in seems to move about 25% of the time now. This used to work fine, but something changed between february 2009 release and r2056.
-0 - - -3931587 -stambaughw -1268752763 -
Fixed in R2312
- - - - - - -8829748 -IP -Artifact Created: 66.62.165.3 -1256839106 -frohro - - -9290247 -IP -Comment Added: 162.83.115.135 -1268752763 -stambaughw - - -9290248 -status_id -1 -1268752763 -stambaughw - - -9290249 -resolution_id -100 -1268752763 -stambaughw - - -9290250 -allow_comments -1 -1268752763 -stambaughw - - -9290251 -close_date -0 -1268752763 -stambaughw - - - - -http://sourceforge.net/support/tracker.php?aid=2897050 -2897050 -2 -761682 -100 -2 -nobody -nobody -jerryjacobs -1258095928 -1267478063 -5 -Layer Setup dialog controls are sticked together -
all Layer setup dialog controls appears in the left-top corner of its area - all in the same position
-0 - - - - - - -8874192 -IP -Artifact Created: 195.122.227.150 -1258095928 -nobody - - -9110321 -resolution_id -100 -1264531786 -charras - - -9227602 -status_id -1 -1267478063 -jerryjacobs - - -9227603 -allow_comments -1 -1267478063 -jerryjacobs - - -9227604 -close_date -0 -1267478063 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2897763 -2897763 -3 -1015288 -516020 -100 -nobody -nobody -jerryjacobs -1258221864 -1267476064 -5 -path with spaces does not allow saving of .net -
On a windows install, if the directory path has a period in it, saving the .net file fails. CVPCB screen disappears but the executable remains in the task manager. Adding module libraries to CVPCB and footprint associations cannot be done if the project has a period in the directory path.
-1 - - - - - - -8878348 -IP -Artifact Created: 24.108.210.16 -1258221864 -nobody - - -9227439 -status_id -1 -1267476064 -jerryjacobs - - -9227440 -is_private -0 -1267476064 -jerryjacobs - - -9227441 -close_date -0 -1267476064 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2897772 -2897772 -1 -1015288 -516020 -100 -nobody -nobody -nobody -1258223571 -0 -5 -path with spaces does not allow saving of .net -
On a windows install, if the directory path has a period in it, saving the .net file fails. CVPCB screen disappears but the executable remains in the task manager. Adding module libraries to CVPCB and footprint associations cannot be done if the project has a period in the directory path.
-0 - - - - - - -8878407 -IP -Artifact Created: 24.108.210.16 -1258223571 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2903063 -2903063 -2 -761682 -755196 -6 -crasic -nobody -jerryjacobs -1259063690 -1259173359 -5 -Zoom-in with an arc Causes Xorg to crash -
Relevant information: - -Radeon mobile x300 video card -Kernel 2.6.31 -Xorg 1.7.1.902 (confirmed with other 1.7.1.x xorgs as well) -Kicad 20090216-final (also confirmed with latest svn build) - -Description: -In PCBNEW, upon zooming in to zoom 50 or higher. Xorg crashes reporting a segmentation fault. (PCBnew goes with it as well, obviously) - -This only happens when there is an graphical Arc on the drawing layer OR edges layer of the pcboard. Otherwise everything works as usual. - -This only started happening on update from Xorg 1.6.9 - -I'm tempted to think its an xorg issue since it only started after an update. But considering how many bugs are reported on xorg, I wanted to report it here in order to get some insight on the issue and to have a more specific issue to report to the xorg devels (like segfault on this or that system call) rather than just "crashes on kicad zoom in". - -Potentially something changed in the xorg api from 1.6 to 1.7 so it might be some kicad library misbehaving. But I know next to nothing about X so I cant confirm. - -I'm on running arch, and most of these packages havent trickled down to more stable distro's so I havent confirmed if it happens on other distro's/hardware. -
-0 - - -3815988 -jerryjacobs -1259079594 -
In Fedora 12 virtual machine with Xorg 1.7.1 and svn 2117 no problems. -On my slackware 12.2 with Nvidia driver and Xorg 1.4.2 no problems. -On ubuntu 9.10 with nvidia driver (dont know X version) no problems. - -I think there is somethings wrong maybe with the packages/libraries that are incompatible, or a driver issue. Or just a bad Xorg build ...
- - -3816329 -crasic -1259102641 -
It seems the issue is the radeon driver, I just tried with a generic vesa driver and there is no issue. - -Its strange that the issue is so specific... Its only happened in PCBnew and under these conditions specific conditions. Any idea as to what exactly crashes the driver would help in reporting the bug to radeon developers. - -
- - -3817302 -jerryjacobs -1259173359 -
This bug is closed because there is no real bug inside pcbnew with other setups and VESA driver, seems a bug inside driver of ATI Radeon.
- - - - - - -8911102 -IP -Artifact Created: 67.180.26.5 -1259063690 -crasic - - -8911825 -IP -Comment Added: 84.25.204.235 -1259079594 -jerryjacobs - - -8912901 -IP -Comment Added: 67.180.26.5 -1259102641 -crasic - - -8915494 -IP -Comment Added: 84.25.204.235 -1259173359 -jerryjacobs - - -8915495 -status_id -1 -1259173359 -jerryjacobs - - -8915496 -resolution_id -100 -1259173359 -jerryjacobs - - -8915497 -assigned_to -100 -1259173359 -jerryjacobs - - -8915498 -allow_comments -1 -1259173359 -jerryjacobs - - -8915499 -close_date -0 -1259173359 -jerryjacobs - - -9332816 -assigned_to -2066563 -1269776551 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2904058 -2904058 -2 -1015285 -100 -100 -sb-sf -nobody -charras -1259184904 -1264441962 -5 -Selecting pointer icon doesn't deselct active tool -
Selecting upper right icon with arrow doesn't deselect current selected tool. Tool icon remains selected, while pointer icon selects too. The only way to "drop" active tool is "End tool" item in right-click drop-down menu.
-0 - - -3817491 -sb-sf -1259184992 -
P.S. tested on svn revision 2117
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=352566&aid= -352566 -screenshot.jpg - -4517 -image/jpeg -1259184905 -sb-sf - - - - -8916003 -IP -Artifact Created: 91.135.22.160 -1259184904 -sb-sf - - -8916007 -File Added -352566: screenshot.jpg -1259184905 -sb-sf - - -8916010 -IP -Comment Added: 91.135.22.160 -1259184992 -sb-sf - - -9106723 -status_id -1 -1264441962 -charras - - -9106724 -allow_comments -1 -1264441962 -charras - - -9106725 -close_date -0 -1264441962 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2906754 -2906754 -2 -761682 -516020 -1 -sb-sf -nobody -jerryjacobs -1259672887 -1259783630 -5 -Board ratsnest unconditionally displayed after block command -
After block command (move/copy) ratsnest displayed independently of "Show board ratsnest" icon pressed/released state. Ratsnest disappears only after single component move or checking-unchecking "Show board ratsnest" icon - -svn rev. 2117
-0 - - -3824708 -sb-sf -1259750526 -
seems like bug introduced into ratsnest.cpp in rev. 1901: http://kicad.svn.sourceforge.net/viewvc/kicad/trunk/kicad/pcbnew/ratsnest.cpp?r1=1860&r2=1901 -calling function with DC == 0 causes VISIBLE flag to remain set. Removing back DC from condition seems bug to be solved.
- - -3825121 -jerryjacobs -1259783630 -
This bug has been fixed
- - -3825122 -jerryjacobs -1259783630 -
Seems to be fixed revision 2125
- - - - - - -8932547 -IP -Artifact Created: 91.135.22.160 -1259672891 -sb-sf - - -8936331 -IP -Comment Added: 91.135.22.160 -1259750526 -sb-sf - - -8937922 -IP -Comment Added: 84.25.204.235 -1259783630 -jerryjacobs - - -8937923 -IP -Comment Added: 84.25.204.235 -1259783630 -jerryjacobs - - -8937924 -status_id -1 -1259783630 -jerryjacobs - - -8937925 -resolution_id -100 -1259783630 -jerryjacobs - - -8937926 -allow_comments -1 -1259783630 -jerryjacobs - - -8937927 -close_date -0 -1259783630 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2906799 -2906799 -2 -761682 -516020 -105 -sb-sf -nobody -jerryjacobs -1259675337 -1267478082 -5 -Hotkeys doesn't work in some cases -
Delete track/Delete segment hotkeys doesn't work in Cancel tool mode (right toolbar Icon with arrow selected) while they are still available throw right click pop-up menu. In Placement of tracks and vias mode hotkeys work as desired. - -svn rev 2117.
-0 - - - - - - -8932664 -IP -Artifact Created: 91.135.22.160 -1259675337 -sb-sf - - -9110320 -resolution_id -100 -1264531704 -charras - - -9227607 -status_id -1 -1267478082 -jerryjacobs - - -9227608 -allow_comments -1 -1267478082 -jerryjacobs - - -9227609 -close_date -0 -1267478082 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2907870 -2907870 -1 -1015285 -516020 -100 -tregare -nobody -nobody -1259805175 -0 -5 -ERC Randomly reports connections as missing. -
While working on a schematic, I ran ERC and it informed me I had missing connections(errors). I corrected those and saved, made sure the markers were cleared and re-ran ERC, different pins/connections were showing as missing. corrected those , cleared markers and saved. Re-Ran the ERC, the connections I had just fixed were showing as errors. - -this is rather frustrating.
-0 - - -3825365 -tregare -1259805213 -
the version is 20090216-final
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=353672&aid= -353672 -74xx_tester.erc - -324 -application/octet-stream -1259805175 -tregare - - - - -8938868 -IP -Artifact Created: 12.153.241.168 -1259805175 -tregare - - -8938869 -File Added -353672: 74xx_tester.erc -1259805176 -tregare - - -8938870 -IP -Comment Added: 12.153.241.168 -1259805213 -tregare - - - - -http://sourceforge.net/support/tracker.php?aid=2909237 -2909237 -1 -100 -755196 -100 -werner2101 -nobody -nobody -1260007258 -0 -5 -sourceforge file download outdated -
The files on SF are outdated: -https://sourceforge.net/projects/kicad/files/ - -It's hard to find the current version of kicad. -This led to an rpm packaging error on openSUSE: -http://bugzilla.novell.com/show_bug.cgi?id=549936 - -The kicad-library does not work with the current kicad -package. -kicad-library 1.0 is incompatible with the latest kicad package which is located at http://iut-tice.ujf-grenoble.fr/cao/kicad-sources-2009-02-16.tar.gz - -Please consider to publish updated and compatible packages on SF. - -Regards -Werner Hoch - - -
-0 - - - - - - -8947082 -IP -Artifact Created: 87.179.12.225 -1260007258 -werner2101 - - - - -http://sourceforge.net/support/tracker.php?aid=2909498 -2909498 -2 -1015285 -755196 -103 -nobody -nobody -jerryjacobs -1260076874 -1267476506 -5 -Plotting PostScript omits unhidden field text -
I have a schematic containing single-pin connectors (component CONN_1). By default the 'Value' field is not shown (the Show Text check box is clear). I edited the 'Value' field and checked the Show Text checkbox. In EESchema the Value field becomes visible. When I plot the schematic as PostScript the Value field is not shown. When I plot the schematic as SVG the Value field is shown. - -I am using Build Version: KiCad (2007-11-29-a) - Unicode version. This is the packaged version shipped with my distro. I have not looked for this bug (or a bug fix) in a later version. - -This is not a big problem for me, but since I noticed it I thought it might be useful to report it. Great piece of software!! Thanks.
-0 - - -3828259 -jerryjacobs -1260093266 -
Please have a look at a newer release, or try to compile yourself to do more bug hunting to make next release more bugfree. Thanks for you comment, i will have a look at this with latest source.
- - -3917349 -jerryjacobs -1267476506 -
Working with newer version.
- - - - - - -8948540 -IP -Artifact Created: 119.199.147.51 -1260076874 -nobody - - -8948697 -IP -Comment Added: 84.25.204.235 -1260093266 -jerryjacobs - - -9227478 -IP -Comment Added: 84.25.204.235 -1267476506 -jerryjacobs - - -9227479 -status_id -1 -1267476506 -jerryjacobs - - -9227480 -resolution_id -100 -1267476506 -jerryjacobs - - -9227481 -allow_comments -1 -1267476506 -jerryjacobs - - -9227482 -close_date -0 -1267476506 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2909776 -2909776 -1 -1015285 -516020 -100 -hyperflexed -nobody -nobody -1260140067 -0 -5 -Rendering glitch with wire to bus connections -
Windows Version. - -Steps to reproduce: -1. Create a bus -2. Add wire to bus entries to bus -3. Holding down CTRL + SHIFT, group select the bus and wire to bus connections (drag a rectangle) to delete -4. Note that the wire to bus connectors still remain visible -5. Zoom in and out and note that the wire to bus connectors disappear
-0 - - - - - - -8950304 -IP -Artifact Created: 74.14.150.113 -1260140067 -hyperflexed - - - - -http://sourceforge.net/support/tracker.php?aid=2910563 -2910563 -1 -761682 -100 -100 -nobody -nobody -nobody -1260265541 -0 -5 -Highlighted pads don't follow component when moving -
When you move a component with highlit pads, -these don't move with the component - -Ubuntu 9.04 -PCBNew Build: (20080825c-final) - -Marc BERLIOUX
-0 - - - - - - -8954348 -IP -Artifact Created: 81.56.216.19 -1260265542 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2912231 -2912231 -1 -761682 -516020 -100 -sb-sf -nobody -nobody -1260476427 -0 -5 -use netlist for module selection fails -
All my library elements has Footprint field filled with appropriate module name. So I don't need .cmp file - all necessary information already exist in netlist. Last svn builds issues warning "File <name.cmp> not found, use netlist for lib module selection, but after that issue error Compnent [C1]: footprint <> not found. I can insert modules into board manually, so library setup is correct. Reported against svn rev. 2146 - -Official release issue the same warning about .cmp file absence but loads modules correctly.
-0 - - - - - - -8962855 -IP -Artifact Created: 91.135.22.160 -1260476427 -sb-sf - - - - -http://sourceforge.net/support/tracker.php?aid=2914663 -2914663 -2 -1015285 -100 -100 -nobody -nobody -charras -1260868639 -1264531598 -5 -Mirror image in GUI -
I am using last version of kicad-16022009 and the whole GUI is mirrored including the menus and components and layout. I can mirror each component separately but it means that I will get mirror image of what I see in the PCB... -I installed it on windows XP and I am attaching a screenshot.
-0 - - -3834806 -vovanium -1260872122 -
Looks like someone's joke. -This is probably not a problem with KiCad, but with Windows or at least with wxWidgets. Better scan your computer for malware.
- - -3834882 -st7 -1260882620 -
No joke. Only after I change language from default to English the problem is solved. I guess that's because I have an Hebrew enabled XP (we are writing from left to right).
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=355271&aid= -355271 -mirrored-kicad.JPG -screenshot -172148 -image/jpeg -1260868639 -nobody - - - - -8974976 -IP -Artifact Created: 91.207.90.10 -1260868639 -nobody - - -8974977 -File Added -355271: mirrored-kicad.JPG -1260868639 -nobody - - -8975127 -IP -Comment Added: 195.208.204.245 -1260872122 -vovanium - - -8975429 -IP -Comment Added: 87.70.136.223 -1260882620 -st7 - - -9110304 -status_id -1 -1264531598 -charras - - -9110305 -allow_comments -1 -1264531598 -charras - - -9110306 -close_date -0 -1264531598 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2916161 -2916161 -2 -100 -100 -100 -werner2101 -nobody -charras -1261046648 -1264531597 -5 -Broken examples: supports.mod library not found -
Hi there, - -when using kicad-2009-02-16 with the current kicad-library, then the examples from kicad cannot be viewed. -Kicad tells that the library /usr/share/kicad/modules/supports.mod is missing. - -This library was renamed to sockets.mod on 2008-11-22 in the SVN commit -Rev1415 "Some cleanup and library update" - -see also: -https://bugzilla.novell.com/show_bug.cgi?id=549936 - -I'm using kicad library from SVN. Downloaded on 2009-12-05. - -workaround: -create symbolic links from supports.mod and supports.mdc to sockets.mod an sockets.mdc - -Regards -Werner Hoch
-0 - - - - - - -8981142 -IP -Artifact Created: 87.179.3.175 -1261046648 -werner2101 - - -9110301 -status_id -1 -1264531597 -charras - - -9110302 -allow_comments -1 -1264531597 -charras - - -9110303 -close_date -0 -1264531597 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2917077 -2917077 -2 -761682 -100 -105 -brummig -nobody -charras -1261149206 -1265461604 -5 -Arcs in 3D Viewer -
Arcs of greater than 90 degrees display as 90 degree arcs in the 3D viewer. To recreate this, try creating a board edge using two 180 degree arcs and then displaying in the 3D viewer. Note that arcs greater than 90 degrees are created by creating an arc of 90 degrees and then editing the arc. - -PCBNew 20090216-final/Windows XP SP3.
-0 - - - - - - -8984532 -IP -Artifact Created: 83.216.148.11 -1261149206 -brummig - - -9149239 -status_id -1 -1265461604 -charras - - -9149240 -resolution_id -100 -1265461604 -charras - - -9149241 -allow_comments -1 -1265461604 -charras - - -9149242 -close_date -0 -1265461604 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2919213 -2919213 -1 -100 -100 -100 -nobody -nobody -nobody -1261471796 -0 -5 -'Move block' includes locked components -
'Move block' should exclude components that have been locked.
-0 - - - - - - -8994282 -IP -Artifact Created: 213.64.86.172 -1261471796 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2919215 -2919215 -1 -100 -100 -100 -nobody -nobody -nobody -1261471934 -0 -5 -F10 dual function -
Pressing F10 activates the File menu (WindowsXP) even if this key has been configured for other use. That means F10 has to be pressed twice (to decativate then menu and activate the other command).
-0 - - - - - - -8994286 -IP -Artifact Created: 213.64.86.172 -1261471934 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2919219 -2919219 -2 -761682 -516020 -100 -nobody -nobody -charras -1261472432 -1264531597 -5 -'Drag via' rendering -
While draging a via, new positions are drawn, but none are erased.
-0 - - - - - - -8994309 -IP -Artifact Created: 213.64.86.172 -1261472433 -nobody - - -9110298 -status_id -1 -1264531597 -charras - - -9110299 -allow_comments -1 -1264531597 -charras - - -9110300 -close_date -0 -1264531597 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2919697 -2919697 -2 -761682 -516020 -100 -nobody -nobody -charras -1261525561 -1264531597 -5 -Fillzone crash -
When trying to fill a zone in windows under Windows Vista with 20090216 or kicad-20091222-r2174 windows binary, pcbnew probably loops through an array 'beyond the array' - -This causes pcbnew to crash due to memory violation
-0 - - - - - - -8996536 -IP -Artifact Created: 85.225.172.198 -1261525561 -nobody - - -9110295 -status_id -1 -1264531597 -charras - - -9110296 -allow_comments -1 -1264531597 -charras - - -9110297 -close_date -0 -1264531597 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2929252 -2929252 -2 -761682 -755196 -100 -nobody -nobody -charras -1263125460 -1264441828 -5 -error in the creation of trails Build: (20100108 SVN-R2200)- -
when I try to create a derivation of a path of 1.6 mm to 0.4 mm an example it returns me an error in the track width, in previous versions it did not and it helps me a lot in the manual routing
-0 - - - - - - -9055736 -IP -Artifact Created: 201.78.215.139 -1263125460 -nobody - - -9106720 -status_id -1 -1264441828 -charras - - -9106721 -allow_comments -1 -1264441828 -charras - - -9106722 -close_date -0 -1264441828 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2929256 -2929256 -3 -761682 -755196 -100 -nobody -nobody -charras -1263125891 -1264531934 -5 -error creating tracks Build: (20100108 SVN-R2200) -
creating trails rastness lines keep coming, and need a redraw to make it disappear, one idea would be to create a procedure after the creation of the trail it to automatically redraw the
-0 - - - - - - -9055755 -IP -Artifact Created: 201.78.215.139 -1263125892 -nobody - - -9106717 -status_id -1 -1264441828 -charras - - -9106718 -allow_comments -1 -1264441828 -charras - - -9106719 -close_date -0 -1264441828 -charras - - -9110329 -status_id -2 -1264531934 -charras - - -9110330 -close_date -1264441828 -1264531934 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2929257 -2929257 -3 -761682 -755196 -100 -nobody -nobody -charras -1263125927 -1264531934 -5 -error tracks rastness Build: (20100108 SVN-R2200) -
creating trails rastness lines keep coming, and need a redraw to make it disappear, one idea would be to create a procedure after the creation of the trail it to automatically redraw the
-0 - - - - - - -9055756 -IP -Artifact Created: 201.78.215.139 -1263125928 -nobody - - -9106714 -status_id -1 -1264441828 -charras - - -9106715 -allow_comments -1 -1264441828 -charras - - -9106716 -close_date -0 -1264441828 -charras - - -9110327 -status_id -2 -1264531934 -charras - - -9110328 -close_date -1264441828 -1264531934 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2929277 -2929277 -2 -761682 -755196 -100 -nobody -nobody -charras -1263129201 -1264441828 -5 -error tracks rastness Build: (20100108 SVN-R2200) -
creating trails rastness lines keep coming, and need a redraw to make it disappear, one idea would be to create a procedure after the creation of the trail it to automatically redraw the
-0 - - - - - - -9055857 -IP -Artifact Created: 201.78.236.149 -1263129202 -nobody - - -9106711 -status_id -1 -1264441828 -charras - - -9106712 -allow_comments -1 -1264441828 -charras - - -9106713 -close_date -0 -1264441828 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2929278 -2929278 -2 -761682 -755196 -100 -nobody -nobody -charras -1263129648 -1264441828 -5 -Errtype(27) -
I'm trying to use manual routing and when I try to leave a trail of 0.047 inch to 0.023 of one he accuses Errtype (27), but not this wrong my tracks because it is only a low current output and not have the space to use the tracks wide while in the main circuit of the tracks need wide. thanks
-0 - - - - - - -9055875 -IP -Artifact Created: 201.78.236.149 -1263129648 -nobody - - -9106708 -status_id -1 -1264441828 -charras - - -9106709 -allow_comments -1 -1264441828 -charras - - -9106710 -close_date -0 -1264441828 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2929862 -2929862 -2 -761682 -755196 -105 -nobody -nobody -charras -1263223272 -1264441827 -5 -maximum number of undo -
currently the maximum number of undo is not enough, that about 10 ideal for a media card would be in the range of 99, because it is often necessary. thanks
-0 - - - - - - -9059082 -IP -Artifact Created: 201.78.138.205 -1263223272 -nobody - - -9106705 -status_id -1 -1264441827 -charras - - -9106706 -allow_comments -1 -1264441827 -charras - - -9106707 -close_date -0 -1264441827 -charras - - -9110326 -resolution_id -100 -1264531852 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2933074 -2933074 -1 -761682 -516020 -100 -elw_2 -nobody -nobody -1263586966 -0 -6 -Gray export Picture in the 3D -
Will I export the 3D Modell into a png or a jpg the Picture is gray (bad English, but my German is better ;)) -Wenn ich die 3D Darstellung in eine png oder jpg Datei umwandeln möchte, bekomme ich nicht das Bild zusehen, sondern immer nur ein graues Bild (siehe Anhang) - -OS: Windows 7 x64 Professionell and Windows Vista x64 Ultimate
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=359101&aid= -359101 -Zusatzplatine_Labornetzteil_01.jpg - -18546 -image/jpeg -1263586966 -elw_2 - - - - -9075520 -IP -Artifact Created: 88.208.165.253 -1263586966 -elw_2 - - -9075521 -File Added -359101: Zusatzplatine_Labornetzteil_01.jpg -1263586966 -elw_2 - - -9075522 -priority -5 -1263586998 -elw_2 - - - - -http://sourceforge.net/support/tracker.php?aid=2934980 -2934980 -2 -1015285 -100 -1 -briansidebotham -nobody -charras -1263909957 -1266067012 -5 -Eeschema crashes when alias already exists -
eeschema (library editor) crashes when a library part is saved when there is an alias specified that already exists in the library. This happens often when you start a new component from an old component, make a few changes and forget to delete the aliases. Upon saving eeschema crashes irrecoverably.
-0 - - -3863226 -jerryjacobs -1263914319 -
Hello Brian. - -Which: -Application version, or Subversion revision. -Can you reproduce the problem?
- - -3863320 -briansidebotham -1263918673 -
Hi Jerry, - -Latest SVN version (R2243) and previous SVN versions all exhibit the same. R2243 needs HK_UNDO and HK_REDO added to the hotkey enum to compile. - -To reproduce, start eeschema and load a library entry which has an alias set. Modify the value field of the component to generate a new library entry and click save, eeschema crashes. - -Do the same again, having deleted the alias or changed the alias name and eeschema doesn't crash.
- - - - - - -9085187 -IP -Artifact Created: 87.74.132.43 -1263909957 -briansidebotham - - -9085365 -IP -Comment Added: 84.25.204.235 -1263914319 -jerryjacobs - - -9085778 -IP -Comment Added: 87.74.132.43 -1263918673 -briansidebotham - - -9174774 -status_id -1 -1266067012 -charras - - -9174775 -resolution_id -100 -1266067012 -charras - - -9174776 -allow_comments -1 -1266067012 -charras - - -9174777 -close_date -0 -1266067012 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2936252 -2936252 -2 -100 -100 -100 -nobody -nobody -charras -1264075778 -1264441827 -5 -pcbnew zoom -
após as alterações realizadas no pcbnew depois da (20100115 SVN-R2224) quando se da um zoom na placa e rola a tela para baixo ela quadricula tudo deformando a imagem , até nessa versao nao havia esse problema
-0 - - - - - - -9106702 -status_id -1 -1264441827 -charras - - -9106703 -allow_comments -1 -1264441827 -charras - - -9106704 -close_date -0 -1264441827 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2936255 -2936255 -2 -761682 -755196 -100 -nobody -nobody -charras -1264075865 -1264441827 -5 -zoom pcbnew ubuntu 9,04 -
after the changes made after the Pcbnew (20100115 SVN-R2224) when the zoom on the board and roll the screen down it all raster image warping, even in this version there was no such problem
-0 - - - - - - -9106699 -status_id -1 -1264441827 -charras - - -9106700 -allow_comments -1 -1264441827 -charras - - -9106701 -close_date -0 -1264441827 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2940466 -2940466 -2 -761682 -755196 -2 -nobody -nobody -charras -1264539394 -1266067083 -5 -error in the library after the release kicad-20100115-r2224- -
in ubuntu 9.04 erro -pcbnew: relocation error: pcbnew: symbol _ZTI12wxAuiToolBar, version WXU_2.8 not defined in file libwx_gtk2u_aui-2.8.so.0 with link time reference - -until this version worked well kicad-20100115-r2224-linux
-0 - - -3868964 -jerryjacobs -1264542632 -
Did you tried with a clean checkout, or after invoking cmake . to gegenerate new makefiles so that it doesn't tries to link against aui because this is in wxwidgets base? - -Good luck.
- - - - - - -9110758 -IP -Comment Added: 84.25.204.235 -1264542632 -jerryjacobs - - -9174782 -status_id -1 -1266067083 -charras - - -9174783 -resolution_id -100 -1266067083 -charras - - -9174784 -allow_comments -1 -1266067083 -charras - - -9174785 -close_date -0 -1266067083 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2942887 -2942887 -2 -1015285 -100 -1 -nobody -nobody -charras -1264878664 -1265095172 -5 -Duplicate Pin 23 in CONN_25X2 in conn.lib -
Duplicate pin 23 "P23" at location (-0,400, -0,100) conflicts with pin 23 "P23" at location (-0,400, -0,100). - -Pin 25 is without name P25
-0 - - - - - - -9133380 -status_id -1 -1265095172 -charras - - -9133381 -resolution_id -100 -1265095172 -charras - - -9133382 -allow_comments -1 -1265095172 -charras - - -9133383 -close_date -0 -1265095172 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2943571 -2943571 -2 -100 -516020 -6 -nobody -nobody -jerryjacobs -1265012437 -1265029032 -5 -Missing dll -
I overwrote my existing/working latest prod version with r2270 but then I get the missing dll error below. Any ideas -wxbase28u_gcc.custom.dll
-0 - - -3874731 -jerryjacobs -1265029031 -
This bug has been fixed
- - -3874732 -jerryjacobs -1265029032 -
This is not much information. -Did you compiled yourself or did you downloaded from the http://kicad.1301.cz snapshot builds? -You should download also the dll package then ! -http://kicad.1301.cz/dlls/kicad-wx28-dlls.zip - -Bug closed, not a real bug ;-)
- - - - - - -9129496 -IP -Comment Added: 84.25.204.235 -1265029031 -jerryjacobs - - -9129497 -IP -Comment Added: 84.25.204.235 -1265029032 -jerryjacobs - - -9129498 -status_id -1 -1265029032 -jerryjacobs - - -9129499 -resolution_id -100 -1265029032 -jerryjacobs - - -9129500 -allow_comments -1 -1265029032 -jerryjacobs - - -9129501 -close_date -0 -1265029032 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2945885 -2945885 -2 -761682 -100 -1 -brummig -nobody -charras -1265283119 -1265461667 -5 -Oval Pads Fail DRC Incorrectly -
One end of an oval pad needs to be *twice* the clearance set in the DRC dialog from the nearest copper in order to pass the DRC. The other end passes the DRC as expected. - -PCBNew 20090216 running on XP Pro/SP3
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=361600&aid= -361600 -DRCFail.pdf -Shows how one end of an oval pad incorrectly fails the DRC -135507 -application/pdf -1265283119 -brummig - - - - -9140960 -IP -Artifact Created: 83.216.148.11 -1265283119 -brummig - - -9140961 -File Added -361600: DRCFail.pdf -1265283119 -brummig - - -9149243 -status_id -1 -1265461667 -charras - - -9149244 -resolution_id -100 -1265461667 -charras - - -9149245 -allow_comments -1 -1265461667 -charras - - -9149246 -close_date -0 -1265461667 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2947745 -2947745 -1 -100 -755196 -100 -nobody -nobody -nobody -1265623700 -0 -5 -folder kicad -
a suggestion for the sake of organization is to put configuration files in $ HOME / .kicad / files at least it is all together now is all in $ HOME / files that makes up the settings
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2952213 -2952213 -2 -761682 -100 -1 -mrluzeiro -nobody -charras -1266255566 -1267187204 -5 -Design Rules Editor GUI layout -
In Design Rules Editor, NetClassEditor, the layout of gui (Add,Remove,Move up keys) are hide by the framegrid of "net classes" -Can you make the frame "membership" a little more short? - -I'm using xubuntu64 and last SVN release. - -Also: -in Global Design Rules, the custom via and track options the grid passes the frame size.. - -my monitor resolution is 1366x768 -
-0 - - - - - - -9180818 -IP -Artifact Created: 85.241.153.82 -1266255566 -mrluzeiro - - -9216781 -status_id -1 -1267187204 -charras - - -9216782 -resolution_id -100 -1267187204 -charras - - -9216783 -allow_comments -1 -1267187204 -charras - - -9216784 -close_date -0 -1267187204 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2953214 -2953214 -1 -761682 -516020 -100 -oecherexpat -nobody -nobody -1266368034 -0 -5 -Font on new layer manager toolbar is too small -
As the topic says: Font on new layer manager toolbar is too small (see attached screenshot) -WinXP-SP3, en. Kicad (20100209 RC2)-RC2
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=363224&aid= -363224 -ScreenShot004.png -Font on new layer manager toolbar is too small -21363 -image/png -1266368035 -oecherexpat - - - - -9185418 -IP -Artifact Created: 222.153.213.254 -1266368035 -oecherexpat - - -9185419 -File Added -363224: ScreenShot004.png -1266368035 -oecherexpat - - - - -http://sourceforge.net/support/tracker.php?aid=2955025 -2955025 -2 -1015285 -100 -1 -brummig -nobody -charras -1266595523 -1267187204 -5 -DATE Field Has Odd Update Behaviour -
The DATE field only seems to update when annotating circuits, but of course a circuit can change in other ways too. Should it not update when any change is made? One slight problem is how to deal with non-changes (eg clicking OK to a dialog but not changing any fields) and changes that get reversed. That could perhaps be solved by calculating the file CRC and comparing it between what is was when the file was opened and what it is on saving. - -The current behaviour is not explained in the help (which just says "The date is automatically updated"), and has resulted in posts on the users group.
-0 - - - - - - -9194324 -IP -Artifact Created: 83.216.148.11 -1266595523 -brummig - - -9216777 -status_id -1 -1267187204 -charras - - -9216778 -resolution_id -100 -1267187204 -charras - - -9216779 -allow_comments -1 -1267187204 -charras - - -9216780 -close_date -0 -1267187204 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2959609 -2959609 -2 -761682 -516020 -105 -alidoig -nobody -charras -1267187557 -1267431383 -5 -Invisible text still showing -
When either the reference or value text field are defined as invisible within the module properties dialogue, they are only greyed-out in PCBNEW (as happens in the module editor) rather than being made invisible. The only way to make them invisible is to turn the whole referene or value layer off, which defeats the purpose of being able to define them on a mode-by-module basis. - -I am running RC4.
-0 - - -3916382 -charras -1267431523 -
Pcbnew dispkay invisible texts on screen only (you must have to edit or change status of these texts) -Select the BLACK color to really hide them. -
- - - - - - -9216789 -IP -Artifact Created: 92.24.45.200 -1267187557 -alidoig - - -9224868 -status_id -1 -1267431383 -charras - - -9224869 -resolution_id -100 -1267431383 -charras - - -9224870 -allow_comments -1 -1267431383 -charras - - -9224871 -close_date -0 -1267431383 -charras - - -9224886 -IP -Comment Added: 152.77.63.2 -1267431523 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2959625 -2959625 -2 -1015285 -516020 -1 -alidoig -nobody -charras -1267189425 -1267473049 -5 -Mirror Block does not work in Component Editor -
If you try to mirror a block in the Component Library Editor, the block is instead moved twice the distance from the anchor point in both X and Y, with no mirroring at all. -Mirroring in eeschema itself is fine. I am using Windows RC4. - -
-0 - - - - - - -9216835 -IP -Artifact Created: 92.24.45.200 -1267189425 -alidoig - - -9227212 -status_id -1 -1267473049 -charras - - -9227213 -resolution_id -100 -1267473049 -charras - - -9227214 -allow_comments -1 -1267473049 -charras - - -9227215 -close_date -0 -1267473049 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2959926 -2959926 -2 -100 -100 -1 -nobody -nobody -charras -1267234136 -1267473304 -5 -PCBnew text "Hide Layers Manager" shown wrong. -
PCBnew 20100221 RC4 -(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) - -"Hide Layers Manager" shown wrong. -1. Start PCBnew -2. Click Preferences, click Hide Layers Manager -3. Click File, click Quit -4. Start PCBnew -5. Click Preferences -6. "Hide Layers Manager" should read "Show Layers Manager"
-0 - - - - - - -9227234 -status_id -1 -1267473304 -charras - - -9227235 -resolution_id -100 -1267473304 -charras - - -9227236 -allow_comments -1 -1267473304 -charras - - -9227237 -close_date -0 -1267473304 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2959928 -2959928 -1 -100 -100 -100 -nobody -nobody -nobody -1267234307 -0 -5 -PCBnew Locked modules are not locked. -
PCBnew 20100221 RC4 -(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) - -If a module is locked, it should be locked until it is unlocked. -1. Activate "Manual and automatic move or place of modules" -2. Click right mouse button on a module -3. Click Lock module -4. Click right mouse button on the module -5. Select Footprint ... > Move -6. The footprint can be moved -7. Move/Drag/Rotate+/Rotate-/Flip/Edit/Delete Module should not work if LOCKED
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2959930 -2959930 -2 -100 -100 -1 -nobody -nobody -charras -1267234423 -1268128371 -5 -PCBnew inconsistent Layer names sequence. -
PCBnew 20100221 RC4 -(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) - -The sequence of Layer names is inconsistent. -In Layers Manager the top down sequence of Layer names, should be the same sequence as in Design Rules > Layers Setup.
-0 - - - - - - -9253091 -status_id -1 -1268128371 -charras - - -9253092 -resolution_id -100 -1268128371 -charras - - -9253093 -allow_comments -1 -1268128371 -charras - - -9253094 -close_date -0 -1268128371 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2959932 -2959932 -1 -100 -100 -100 -nobody -nobody -nobody -1267234492 -0 -5 -Inconsistent menu text Zoom. -
EESchema 20100221 RC4 -(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) - -Click View > "Zoom In" should read "Zoom in F1" -Click View > "Zoom Out" should read "Zoom out F2" -Click View > "Fit on Screen Home" should read "Zoom fit Home" -Click Right mouse button > "Zoom auto Home" should read "Zoom fit Home" -Button Tooltip > "Zoom auto <Home>" should read "Zoom fit <Home>" - - -PCBnew 20100221 RC4 -(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) - -Click View > "Zoom in" should read "Zoom in F1" -Click View > "Zoom out" should read "Zoom out F2" -Click View > "Fit on Screen Home" should read "Zoom fit Home" -Click Right mouse button > "Zoom auto Home" should read "Zoom fit Home" -Button Tooltip > "Zoom auto <Home>" should read "Zoom fit <Home>"
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2960099 -2960099 -2 -100 -100 -1 -nobody -nobody -charras -1267267929 -1267430848 -5 -PCBnew Window "Display settings" has no Name. -
PCBnew 20100221 RC4 -(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) - -Please refer to attached screen capture. - -1. Start PCBnew -2. Click Preferences -3. Click Display -4. The window Name is missing, should read "Display settings".
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=364663&aid= -364663 -KiCad Window -Display settings- has no Name.PNG -Window Name is missing. -21306 -image/x-png -1267267929 -nobody - - - - -9224842 -status_id -1 -1267430848 -charras - - -9224843 -resolution_id -100 -1267430848 -charras - - -9224844 -allow_comments -1 -1267430848 -charras - - -9224845 -close_date -0 -1267430848 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2960100 -2960100 -2 -100 -100 -105 -nobody -nobody -charras -1267268277 -1267430338 -5 -PCBnew Drop-Down-Box Zoom inconsistent. -
PCBnew 20100221 RC4 -(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) - -Please refer to attached screen capture. - -01. Start PCBnew -02. Drop-Down-Box Zoom is empty -03. Click down-arrow to the right side of the Drop-Down-Box Zoom -04. Zoom list is shown -05. Text "Auto" should read "Fit" - -06. Select "Auto", press left mouse button -07. Drop-Down-Box Zoom is empty, should read "Fit" - -08. Select "Zoom 7", press left mouse button -09. Drop-Down-Box Zoom shows "Zoom 7" -10. Press Home-key, do NOT move the mouse -11. Drop-Down-Box Zoom shows "Zoom 7", should read "Fit" - -12. Move the mouse -13. Drop-Down-Box Zoom is empty, should read "Fit" - -14. Select "Zoom 7", press left mouse button -15. Drop-Down-Box Zoom shows "Zoom 7" -16. Click "Zoom auto <Home>", do NOT move the mouse -17. Drop-Down-Box Zoom shows "Zoom 7", should read "Fit" - -18. Move the mouse -19. Drop-Down-Box Zoom is empty, should read "Fit"
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=364665&aid= -364665 -KiCad Drop-Down-Box Zoom.PNG -Drop-Down-Box Zoom update is inconsistent. -21756 -image/x-png -1267268277 -nobody - - - - -9224832 -status_id -1 -1267430338 -charras - - -9224833 -resolution_id -100 -1267430338 -charras - - -9224834 -allow_comments -1 -1267430338 -charras - - -9224835 -close_date -0 -1267430338 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2960364 -2960364 -2 -761682 -100 -1 -nobody -nobody -charras -1267301366 -1267530698 -5 -PCBnew Design Rules Editor inconsistent Column Names. -
PCBnew 20100221 RC4 -(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) - -Please refer to attached screen capture. - -In Membership: area, the Column Names "Net" and "Class" are displayed inconsistently. -This happens during dragging the column line when resizing the column width.
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=364726&aid= -364726 -KiCad Net Classes Editor screen capture.PNG -Column Names mostly missing. -25899 -image/x-png -1267301366 -nobody - - - - -9229249 -status_id -1 -1267530698 -charras - - -9229250 -resolution_id -100 -1267530698 -charras - - -9229251 -allow_comments -1 -1267530698 -charras - - -9229252 -close_date -0 -1267530698 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2960432 -2960432 -2 -761682 -516020 -105 -nobody -nobody -charras -1267312828 -1267430338 -5 -Addition to ID: 2960100 -
Please note that the behaviour as described in ID: 2960100 was observed when ecc83-pp_v2.brd was opened in PCBnew. - -When interf_u.brd is opened in PCBnew, the described behaviour is similar when the window is NOT maximized to full screen. If the window IS maximised the behavior is different than described in ID: 2960100.
-0 - - - - - - -9224828 -status_id -1 -1267430338 -charras - - -9224829 -resolution_id -100 -1267430338 -charras - - -9224830 -allow_comments -1 -1267430338 -charras - - -9224831 -close_date -0 -1267430338 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2960554 -2960554 -2 -761682 -516020 -1 -nobody -nobody -charras -1267349419 -1267443620 -5 -PCBnew Ratsnest color is wrong (Layers Manager). -
PCBnew 20100221 RC4 -(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) - -Ratsnest color is WHITE but Layers Manager show RED. -Please refer to attached screen capture.
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=364784&aid= -364784 -KiCad ratsnest color wrong.PNG - -49823 -image/x-png -1267349419 -nobody - - - - -9225359 -status_id -1 -1267443620 -charras - - -9225360 -resolution_id -100 -1267443620 -charras - - -9225361 -allow_comments -1 -1267443620 -charras - - -9225362 -close_date -0 -1267443620 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2960683 -2960683 -2 -1015285 -755196 -1 -jerryjacobs -bennett78 -charras -1267370546 -1267523818 -9 -Bill of materials single parts per line crashes -
After revision 2397 when i select Output format: Single Part per line and click ok and select file in the browser it crashes. -Gnu Debugger gives me the line of code at frame 3. I can reproduce this problem with my schematics and the one from the demos. When I select List or Text for speadsheat it works. See below. - -(gdb) frame 3 -#3 0x00000000004b38d6 in DIALOG_BUILD_BOM::PrintComponentsListByPart (this=0x1898910, f=0x19d85a0, - aList=std::vector of length 34, capacity 64 = {...}) at /home/jerry/builds/kicad/kicad-trunk/eeschema/build_BOM.cpp:872 -872 printf("%c%-20s", s_ExportSeparatorSymbol, CONV_TO_UTF8( cmpFields[FIELD1]) ); - -(gdb) where -#0 0x0000003a9f8af180 in wxMBConvUTF8::WC2MB(char*, wchar_t const*, unsigned long) const () from /usr/lib64/libwx_baseu-2.8.so.0 -#1 0x0000003a9f8b0abd in wxMBConv::cWC2MB(wchar_t const*) const () from /usr/lib64/libwx_baseu-2.8.so.0 -#2 0x00000000004a6cd6 in wxMBConv::cWX2MB (this=0x3a9fb67550, psz=0x5200000057 <Address 0x5200000057 out of bounds>) - at /usr/include/wx-2.8/wx/strconv.h:111 -#3 0x00000000004b38d6 in DIALOG_BUILD_BOM::PrintComponentsListByPart (this=0x1898910, f=0x19d85a0, - aList=std::vector of length 34, capacity 64 = {...}) at /home/jerry/builds/kicad/kicad-trunk/eeschema/build_BOM.cpp:872 -#4 0x00000000004b119f in DIALOG_BUILD_BOM::CreatePartsList (this=0x1898910, aFullFileName=..., aIncludeSubComponents=false) - at /home/jerry/builds/kicad/kicad-trunk/eeschema/build_BOM.cpp:172 -#5 0x00000000004b0ef1 in DIALOG_BUILD_BOM::Create_BOM_Lists (this=0x1898910, aTypeFile=2, aIncludeSubComponents=false, - aExportSeparatorSymbol=44 ',', aRunBrowser=false) at /home/jerry/builds/kicad/kicad-trunk/eeschema/build_BOM.cpp:126 -#6 0x00000000004fdebb in DIALOG_BUILD_BOM::OnOkClick (this=0x1898910, event=...) - at /home/jerry/builds/kicad/kicad-trunk/eeschema/dialog_build_BOM.cpp:182 -#7 0x0000003a9f8f2070 in wxEvtHandler::ProcessEventIfMatches(wxEventTableEntryBase const&, wxEvtHandler*, wxEvent&) () - from /usr/lib64/libwx_baseu-2.8.so.0
-0 - - - - - - -9222800 -IP -Artifact Created: 84.25.204.235 -1267370546 -jerryjacobs - - -9227042 -status_id -1 -1267469305 -charras - - -9227043 -close_date -0 -1267469305 -charras - - -9229000 -status_id -4 -1267523818 -charras - - -9229001 -resolution_id -100 -1267523818 -charras - - -9229002 -allow_comments -1 -1267523818 -charras - - -9229003 -close_date -1267469305 -1267523818 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2960706 -2960706 -2 -761682 -100 -1 -nobody -nobody -charras -1267373095 -1267465935 -5 -PCBnew Pad Properties show wrong Layer Names. -
PCBnew 20100221 RC4 -(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) - -Layer Names in Pad Properties are different (old?) Layer Names. -Please refer to attached screen capture.
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=364843&aid= -364843 -KiCad Pad Properties wrong Layer Names.PNG - -59990 -image/x-png -1267373096 -nobody - - - - -9226877 -status_id -1 -1267465935 -charras - - -9226878 -resolution_id -100 -1267465935 -charras - - -9226879 -allow_comments -1 -1267465935 -charras - - -9226880 -close_date -0 -1267465935 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2960893 -2960893 -2 -761682 -100 -1 -mrluzeiro -nobody -charras -1267396316 -1267523694 -5 -Plot to postscrip and pcb page layout -
@SVN R2400 - -I've selected a custom page layout size (frame) and I ploted it to Postscript (non A4) -and the generated file doesn't show the PCB... (probable a canvas problem? or coordinates? maybe plot expects only A4 frames?) -
-0 - - - - - - -9223916 -IP -Artifact Created: 85.241.171.1 -1267396316 -mrluzeiro - - -9228991 -status_id -1 -1267523694 -charras - - -9228992 -resolution_id -100 -1267523694 -charras - - -9228993 -allow_comments -1 -1267523694 -charras - - -9228994 -close_date -0 -1267523694 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2960923 -2960923 -2 -761682 -100 -105 -nobody -nobody -charras -1267401523 -1267430196 -5 -PCBnew Mask_Front not shown (Layers Manager). -
PCBnew 20100221 RC4 -(KiCad-2010-02-17-RC4-WinXP_full_with_components_doc_autoinstall.zip) - -Solder stop mask pads "Mask_Front (Solder mask Cmp)" are not shown. -Please refer to attached screen capture. - -1. In Pad Properties, Layers: "Solder mask Cmp" is checked (on). - -2. In Pad Properties, Clearances: are all zeros. - -3. In Module properties > Properties, Mask clearances local values: are all zeros. - -4. In Preferences > Dimensions > Pads Mask Clearance, Solder mask clearance is 0,0100. - -5. In Design Rule Editor > Net Classes Editor, Default Clearance is 0,0100. - -6. In Layers Manager > Render, Pads Front is unchecked (off). Therefore pads are not visable and clearance outlines are not visable. - -7. In Layers Manager > Layer, Mask_Front is checked (on). Color is Magenta. Refer to attached screen capture. - -8. Solder stop mask pads are not shown, which I believe is wrong. - -Solder stop mask pads "Mask_Front (Solder mask Cmp)" should be visable in Magenta colour!!??
-0 - - -3916354 -charras -1267430139 -
Layer manager>render is set to NO SHOW pads front, so they are not displayed. -Therefore you do not see pads on mask front. -No bug here.
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=364897&aid= -364897 -KiCad Mask_Front should be visable.PNG - -45553 -image/x-png -1267401523 -nobody - - - - -9224816 -IP -Comment Added: 152.77.63.2 -1267430140 -charras - - -9224819 -status_id -1 -1267430196 -charras - - -9224820 -resolution_id -100 -1267430196 -charras - - -9224821 -allow_comments -1 -1267430196 -charras - - -9224822 -close_date -0 -1267430196 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2961071 -2961071 -2 -761682 -516020 -1 -nobody -nobody -charras -1267435954 -1267442510 -5 -3D viewer does not operate -
KiCad-2010-02-28-RC5-WinXP pcbnew: When we press a button "Browse Shapes" ("Open module editor" > "Module Properties" > "3D settings" > "Browse Shapes") and select an object for viewing 3D viewer does not operate.
-0 - - - - - - -9225314 -status_id -1 -1267442510 -charras - - -9225315 -resolution_id -100 -1267442510 -charras - - -9225316 -allow_comments -1 -1267442510 -charras - - -9225317 -close_date -0 -1267442510 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2961086 -2961086 -2 -1015285 -516020 -1 -nobody -nobody -charras -1267437095 -1267442510 -5 -Delete Bus Entry -
KiCad-2010-02-28-RC5-WinXP eeschema: When we Delete Bus Entry, his image does not disappear and should be done "Redraw view" order disappeared it.
-0 - - - - - - -9225310 -status_id -1 -1267442510 -charras - - -9225311 -resolution_id -100 -1267442510 -charras - - -9225312 -allow_comments -1 -1267442510 -charras - - -9225313 -close_date -0 -1267442510 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2961122 -2961122 -1 -100 -516020 -100 -nobody -nobody -nobody -1267441138 -0 -5 -Maximize size of window -
KiCad-2010-02-28-RC5-WinXP: When we start any program (cvpcb, eeschema, gerbview, kicad or pcbnew) they always open in Restore Down size of window, but never in Maximize size of window, even if ones were closed before this in Maximize size of window.
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2961163 -2961163 -2 -1015285 -516020 -105 -nobody -nobody -charras -1267446007 -1267465840 -5 -module after "clear annotation" error -
KiCad-2010-02-28-RC5-WinXP eeschema and cvpcb: If we have already completed the scheme, and want for example, add a new resistor which location after the resistors R1 and R2, then after the "Reset existing annotation", "Clear annotation", "Annotation" and "Netlist generation" we see in cvpcb the new resistor R3 without the module and we appointed a new module for him. That is correct. -If we add a new resistor, located between R1 and R2 (R1 => R1, the new resistor => R2, R2 => R3), then after the "Reset existing annotation", "Clear annotation", "Annotation" and "Netlist generation " we see in cvpcb, that the module, which previously belonged to the R2 now illegal belongs to the new resistor (which is now R2), and the old resistor R2 (which is now R3) was left without module. This is wrong. -For me, it is important to "Reset existing annotation", "Clear annotation", so the board described in http://tech.groups.yahoo.com/group/kicad-users/message/5624 for me is not suitable.
-0 - - - - - - -9226861 -status_id -1 -1267465840 -charras - - -9226862 -resolution_id -100 -1267465840 -charras - - -9226863 -allow_comments -1 -1267465840 -charras - - -9226864 -close_date -0 -1267465840 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2961186 -2961186 -2 -1015285 -516020 -6 -alidoig -nobody -charras -1267448954 -1267466507 -5 -Edit Pins per part Setting gets changed -
I have noticed that compenents created with the previous release of Kicad that have more than 1 unit (as convert) that required "edit Pins per part" enabled, appear to ignore the "edit pins per part" setting in RC5. I hadn't checked this in previous release candiadates, sorry. - -When modifying component to have "edit pins per part" enabled using RC5, and after correcting one of the a pin names of UnitB (lets call this pin 4), trying to edit any other pin on the part always brought up the dialogue as if I was trying to edit pin4 again. The only way I could rename all the pins correctly was to save the component after each change. - -One more oddity... If you edit a component that does not have "edit pins per part" enabled and then edit a part that did have it enabled, the "edit pins per part" setting reverts back to being disabled too. - -My appologies if this is a bit confusing.
-0 - - -3917203 -charras -1267466399 -
Works fine in RC5 for me
- - - - - - -9225543 -IP -Artifact Created: 81.149.216.219 -1267448955 -alidoig - - -9226897 -IP -Comment Added: 90.41.62.219 -1267466399 -charras - - -9226898 -status_id -1 -1267466507 -charras - - -9226899 -resolution_id -100 -1267466507 -charras - - -9226900 -allow_comments -1 -1267466507 -charras - - -9226901 -close_date -0 -1267466507 -charras - - -9227041 -resolution_id -5 -1267469261 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2961194 -2961194 -3 -1015285 -516020 -101 -alidoig -nobody -alidoig -1267450187 -1267450301 -5 -Edit Pins per part Setting gets changed -
I have noticed that compenents created with the previous release of Kicad that have more than 1 unit (as convert) that required "edit Pins per part" enabled, appear to ignore the "edit pins per part" setting in RC5. I hadn't checked this in previous release candiadates, sorry. - -When modifying component to have "edit pins per part" enabled using RC5, and after correcting one of the a pin names of UnitB (lets call this pin 4), trying to edit any other pin on the part always brought up the dialogue as if I was trying to edit pin4 again. The only way I could rename all the pins correctly was to save the component after each change. - -One more oddity... If you edit a component that does not have "edit pins per part" enabled and then edit a part that did have it enabled, the "edit pins per part" setting reverts back to being disabled too. - -My appologies if this is a bit confusing.
-0 - - -3916761 -alidoig -1267450301 -
Sorry, I must have somehow clicked update twice.
- - - - - - -9225585 -IP -Artifact Created: 81.149.216.219 -1267450187 -alidoig - - -9225590 -IP -Comment Added: 81.149.216.219 -1267450301 -alidoig - - -9225591 -status_id -1 -1267450301 -alidoig - - -9225592 -resolution_id -100 -1267450301 -alidoig - - -9225593 -allow_comments -1 -1267450301 -alidoig - - -9225594 -close_date -0 -1267450301 -alidoig - - - - -http://sourceforge.net/support/tracker.php?aid=2961343 -2961343 -2 -1015285 -516020 -105 -nobody -nobody -charras -1267459730 -1267465817 -5 -horizontal and vertical wires and buses only -
KiCad-2010-02-28-RC5-WinXP eeschema: If we set on "Draw horizontal and vertical wires and buses only" and after that try make "Drag Component", connecting wires stretched over component like rubber threads, but not as "horizontal and vertical wires and buses only".
-0 - - - - - - -9226854 -status_id -1 -1267465817 -charras - - -9226855 -resolution_id -100 -1267465817 -charras - - -9226856 -allow_comments -1 -1267465817 -charras - - -9226857 -close_date -0 -1267465817 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2961374 -2961374 -1 -1015285 -516020 -100 -nobody -nobody -nobody -1267462410 -0 -5 -Set Bus Entry -
KiCad-2010-02-28-RC5-WinXP eeschema: It would be better to replace "Set Bus Entry" to "Turn Bus Entry" for more comprehensible.
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2961845 -2961845 -1 -1015285 -755196 -6 -nobody -nobody -charras -1267526986 -1267682840 -5 -eeschema does not restore library settings correctly -
A current version of Kicad (r2413), Ubuntu Karmic build does restore library setting correctly. - -After a program restart the settings have disappeared and the locally specified (in the .pro file) is not loaded. Also the "User Defined Search Path" is not restored. - -pcbnew does not expose the problem.
-0 - - -3923867 -jtaprogge -1268131008 -
As it seems the problem only occurs when the local library is not in the same directory as the project. - -Steps to reproduce: - 1. Create new project. - 2. Create new library in parent directory. - 3. Add library to project. - 4. Restart eeschema. - -At this point the library is now longer part of the project.
- - - - - - -9236281 -status_id -1 -1267682840 -charras - - -9236282 -resolution_id -100 -1267682840 -charras - - -9236283 -close_date -0 -1267682840 -charras - - -9253337 -status_id -4 -1268131008 -jtaprogge - - -9253338 -IP -Comment Added: 138.131.217.79 -1268131008 -jtaprogge - - - - -http://sourceforge.net/support/tracker.php?aid=2962142 -2962142 -2 -1015285 -755196 -1 -bennett78 -nobody -charras -1267560208 -1267630846 -7 -Crash SaveEEFile on demo -
Crash saving whole schematic project Revision: 2416 -[Debug] 12:56:24: LoadLibraries () requested component library sort order: -[Debug] 12:56:24: Real component library sort order: -[Debug] 12:56:24: end LoadLibraries () -[Debug] 12:56:24: LoadOneEEProject() load schematic cache library file </s/opt/svn/kicad/trunk/kicad/demos/kit-dev-coldfire-xilinx_5213/kit-dev-coldfire-xilinx_5213.cache.lib> -SaveEEFile, /s/opt/svn/kicad/trunk/kicad/demos/kit-dev-coldfire-xilinx_5213/kit-dev-coldfire-xilinx_5213.sch -SaveEEFile, in_out_conn.sch -SaveEEFile, xilinx.sch -[Debug] 12:56:26: Alias <+3,3V> not found in component <GND> alias list in library <> -[Debug] 12:56:26: Alias <+3,3V> not found in component <DIODE> alias list in library <> -[Debug] 12:56:26: Alias <+3,3V> not found in component <C> alias list in library <> -[Debug] 12:56:26: Alias <+3,3V> not found in component <CONN_1> alias list in library <> -[Debug] 12:56:26: Alias <+3,3V> not found in component <LT1129_QPACK> alias list in library <> -[Debug] 12:56:26: Alias <+3,3V> not found in component <CONN_1> alias list in library <> -[Debug] 12:56:26: Alias <CAPAPOL> not found in component <+3.3V> alias list in library <> -[Debug] 12:56:26: Alias <+3,3V> not found in component <CP> alias list in library <> -[Debug] 12:56:26: Alias <+3,3V> not found in component <CONN_4X2> alias list in library <> -[Debug] 12:56:26: Alias <MAX202> not found in component <CONN_4X2> alias list in library <> -Segmentation fault -
-0 - - - - - - -9230611 -IP -Artifact Created: 76.76.79.173 -1267560209 -bennett78 - - -9233723 -status_id -1 -1267630846 -charras - - -9233724 -resolution_id -100 -1267630846 -charras - - -9233725 -allow_comments -1 -1267630846 -charras - - -9233726 -close_date -0 -1267630846 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2963369 -2963369 -2 -761682 -755198 -1 -brummig -nobody -charras -1267707950 -1267968551 -5 -Copperless Pads (Drill Holes) Do Not Obey Design Rules -
If you create a pad with no copper layers (for example as a drill hole for a mounting bolt), PCBNew will not apply the track spacing rule. Consequently a copper fill (zone) will go right up to the edge of the drill hole. If the board has plated-through holes, then when the board is manufactured by default *all* holes will be plated, including the copper-less pad holes. If there is a copper fill around the copper-less pad on another layer, the two layers will be connected by the plating and the board will be scrap. However, as far kicad is concerned the two layers will not be connected, so it will not even issue a warning in the DRC check.
-0 - - -3919620 -brummig -1267711045 -
I forgot to mention that this problem has tripped up others in the user group.
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=365393&aid= -365393 -LethalHole.png -This board passes the DRC, but it will be manufactured with a plated through hole in the centre of the silk-screen donut that will short 5V to ground. -8036 -image/png -1267707950 -brummig - - - - -9237417 -IP -Artifact Created: 83.216.148.11 -1267707950 -brummig - - -9237418 -File Added -365393: LethalHole.png -1267707950 -brummig - - -9237523 -IP -Comment Added: 83.216.148.11 -1267711045 -brummig - - -9246437 -status_id -1 -1267968551 -charras - - -9246438 -resolution_id -100 -1267968551 -charras - - -9246439 -allow_comments -1 -1267968551 -charras - - -9246440 -close_date -0 -1267968551 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2964094 -2964094 -1 -1015288 -755196 -100 -mrluzeiro -nobody -nobody -1267782356 -0 -5 -cvPCB freezes 100%cpu when loading my file -
When I load the file in attachment in cvPCB the program freezes (100% CPU) and never recover back. -I suspect could be because my installed libs? -I'm using last SVN version (but I think this problems comes from very long time.. ) - -In any way i consider it a bug because the program cannot crashs in that way. if there is something wrong should display a error log =) -
-0 - - -3922328 -mrluzeiro -1267980214 -
I've cheked and it seams that are related to the libs huge list that have to open.
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=365493&aid= -365493 -R2K10_Arduino_Expansion.net -File that makes my cvPCB crashes -7943 -application/octet-stream -1267782357 -mrluzeiro - - - - -9240463 -IP -Artifact Created: 82.154.249.123 -1267782357 -mrluzeiro - - -9240464 -File Added -365493: R2K10_Arduino_Expansion.net -1267782357 -mrluzeiro - - -9246935 -IP -Comment Added: 85.241.175.179 -1267980214 -mrluzeiro - - - - -http://sourceforge.net/support/tracker.php?aid=2965646 -2965646 -2 -761682 -516020 -1 -alidoig -nobody -charras -1268079849 -1268128370 -5 -Cancelling text operation hides text -
I have just noticed that if I move some text, but press excape to abort the operation, the text does not return to its original location. Furthermore, redrawing the screen hides the text altogether and the only way I have found to gett it back is to save the board and reload it again. - -Drawing objects are fine and component text are both fine, it is just graphical text on any layer I have had problems with. I have been through the bugs list to see if this has been reported already, so my appologies if it has. - -I am still running RC5 on windows.
-0 - - - - - - -9250806 -IP -Artifact Created: 92.24.45.200 -1268079849 -alidoig - - -9253084 -status_id -1 -1268128370 -charras - - -9253085 -resolution_id -100 -1268128370 -charras - - -9253086 -allow_comments -1 -1268128370 -charras - - -9253087 -close_date -0 -1268128370 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2966482 -2966482 -2 -1015285 -100 -103 -nobody -nobody -charras -1268143915 -1268161419 -5 -Editing a component changes its orientation -
If you change the orientation of a component using the context menu, and then later edit the component using Edit Component...Edit, the component will change its orientation even if the orientation was not changed in the dialog. Lethal if you don't spot it! - -EESchema 20090216-final / XP SP3
-0 - - -3924071 -brummig -1268144159 -
Report filed by brummig (I thought I was logged in when I filed it).
- - - - - - -9254157 -IP -Comment Added: 83.216.148.11 -1268144160 -brummig - - -9255367 -status_id -1 -1268161419 -charras - - -9255368 -resolution_id -100 -1268161419 -charras - - -9255369 -allow_comments -1 -1268161419 -charras - - -9255370 -close_date -0 -1268161419 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2969055 -2969055 -1 -100 -100 -100 -nobody -nobody -nobody -1268355419 -0 -5 -3d viewer does not work on win 7 -
3d viewer does not work on win 7 -a white screen is come up gives the note " error in GL command
-0 - - -3928432 -charras -1268466504 -
Works for me (with W7 32 bits version) -Are you using a W7 64 bits version?
- - - - - - -9278614 -IP -Comment Added: 90.41.187.165 -1268466504 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2969856 -2969856 -1 -100 -100 -100 -nobody -nobody -nobody -1268482568 -0 -5 -locking and graphics heavy -
Hello I'm using the svn version and eesquema and Pcbnew are with the graphics too slow (video 128mb) and stop responding and must constantly be forced to leave tested on 2 computers (ubuntu 9.04) - -This happens in grand schemes in my case the page was completely filled using labels to plug in
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2970719 -2970719 -1 -100 -755196 -100 -nobody -nobody -nobody -1268669413 -0 -5 -Design checl rules menu - segmentation failed ! -
After making some design in PCBNEW, I wanted to go in the design check rules menu and the software crashed ! I start a new design and make the same operations ! When i wanted to change de classes of the differents net ! Both seems to be segmentation failure ! it is the last version uploaded the 3-14 !
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2970757 -2970757 -2 -1015285 -516020 -1 -alidoig -nobody -charras -1268674533 -1268741218 -5 -Component text does not rotate with component -
Bah, trust me to have the first bug report of the final release. - -If you create a new component with drawing text, then try to rotate the finished component in EESCHEMA, the text does not rotate with the component. -My workaround is to add text as a field, in which case it does rotate fine. - -Sorry. - -KiCad-2010-03-14-SVN2456-final
-0 - - - - - - -9285978 -IP -Artifact Created: 89.240.57.123 -1268674533 -alidoig - - -9289626 -status_id -1 -1268741218 -charras - - -9289627 -resolution_id -100 -1268741218 -charras - - -9289628 -allow_comments -1 -1268741218 -charras - - -9289629 -close_date -0 -1268741218 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2970765 -2970765 -1 -761682 -755196 -100 -yageek -nobody -nobody -1268675018 -0 -9 -Segmentation failed - final 20100314 -
Segmentation failed with the design rules menu ! The application crashes when I try to load the menu after I have done some design with the pcb !
-0 - - -3932340 -yageek -1268815163 -
More precisly, the bug happens when I want to change a signal from one class to another ! pcbnew crashes and i have a segmentation failed ! The version is kicad-2010-03-14-final (SVN 2456) - -
- - -3933888 - -1268947847 -
Same trouble here, tested with 3 versions : Ubuntu (wx statically linked), WinXP, from sources (wx dynamic). -Problem occured after afftecting a netclass in a given pcbnew project. Since then, design rule menu issues a segfault each time it should be displayed. -I can provide my faulty design file (.brd) if needed.
- - -3937115 -paulgittings -1269250993 -
Having the same issue. I've been working on a board for awhile and now when I attempt to access the "Design Rules"->"Design Rules" menu PCBNew just disappears. -I've tried up-grading to the current SVN version (20100322 SVN-R2470) to see if it would resolve the issue but the problem still remains. -I using 64-bit Ubunut 9.04.
- - -3937122 -paulgittings -1269251489 -
Don't know if this helps but this is the log message when pcbnew seg faults: - -Mar 22 20:25:05 studypc kernel: [ 7352.589879] pcbnew[10112]: segfault at 119 ip 00007ffea362fa90 sp 00007fff88c7c778 error 4 in libwx_baseu-2.8.so.0.6.0[7ffea3580000+144000] -
- - -3953594 - -1270498521 -
For me, release svn-2505 seems to have fixed this bug.
- - -3954025 -paulgittings -1270547618 -
Works for me as well in svn-2506. - -Thanks to all involved in fixing it! - -Cheers, -Paul -
- - - - - - -9286003 -IP -Artifact Created: 80.13.200.215 -1268675018 -yageek - - -9293255 -IP -Comment Added: 80.13.200.215 -1268815163 -yageek - - -9293256 -priority -5 -1268815163 -yageek - - -9294475 -priority -6 -1268839551 -yageek - - -9298870 -IP -Comment Added: 86.67.51.130 -1268947847 - - - -9309722 -IP -Comment Added: 211.30.110.233 -1269250993 -paulgittings - - -9309751 -IP -Comment Added: 211.30.110.233 -1269251489 -paulgittings - - -9367791 -IP -Comment Added: 86.67.51.130 -1270498521 - - - -9369975 -IP -Comment Added: 211.30.110.233 -1270547618 -paulgittings - - - - -http://sourceforge.net/support/tracker.php?aid=2970825 -2970825 -2 -1015285 -516020 -1 -alidoig -nobody -charras -1268683004 -1268741218 -5 -Block move/copy does not include graphic text -
Not much I can add to the summary - doing a block move in EESCHEMA does not include graphic text. -When you select a block,only components and graphic lines are highlighted. - -I rolled back to the previous release candidate, and it did the same. Soryr for not spotting this before the release.
-0 - - -3930583 -alidoig -1268683884 -
It turns out that new text is being included in the block command and it is only older text created with a previous release candidate that isn't, - -I can't remember exactly which release candidate was used to create the text, but it might have been around RC2. - -Tomorrow, I should be able to roll back to 2009-02-16 then forward to make sure it is only an incompatibility with one of the recent release candidates, in which case this should be a non-issue. Fingers crossed.
- - -3930595 -alidoig -1268685017 -
Right, hopefully last one on this tonight. - -Unfortunately it is nothing to do with old text - it is rotated graphic text that isn't getting included in the block commands. - -Of course, when I tried to block move new text I didn't think to rotate it first! - -KiCad-2010-03-14-SVN2456-final.
- - - - - - -9286373 -IP -Artifact Created: 89.240.57.123 -1268683004 -alidoig - - -9286416 -IP -Comment Added: 89.240.57.123 -1268683884 -alidoig - - -9286473 -IP -Comment Added: 89.240.57.123 -1268685017 -alidoig - - -9289622 -status_id -1 -1268741218 -charras - - -9289623 -resolution_id -100 -1268741218 -charras - - -9289624 -allow_comments -1 -1268741218 -charras - - -9289625 -close_date -0 -1268741218 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2971633 -2971633 -1 -761682 -755196 -100 -nobody -nobody -nobody -1268781424 -0 -5 -erro on save file -
today I had a problem with Pcbnew, worked on a plate for 4 hours and closed for my lunch the project was saved every 10 to 15 minutes and when I reopen it it was the same as before I started working on it in these 4 hours that the stranger is the auto save saved the plate in the middle of service i gave you a little advance I'm using ubuntu 9.04 version ppa.
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2973475 -2973475 -1 -761682 -755198 -100 -pisulski -nobody -nobody -1269033485 -0 -4 -Proposal to introduce so-called reference pointpoint -
I think it will be a goog idea introduce reference point. It is point used tu draw line with knew coordinates. -Where i will use it? for example for drawing PCB dimennsions. - -Sorry for my grammar
-0 - - - - - - -9303043 -IP -Artifact Created: 77.255.38.194 -1269033486 -pisulski - - -9303044 -priority -5 -1269033561 -pisulski - - - - -http://sourceforge.net/support/tracker.php?aid=2974272 -2974272 -1 -761682 -755196 -100 -nobody -nobody -nobody -1269210917 -0 -5 -error in dimensions -
do any one scheme, have exported to svg or even print, note that the dimensions will leave dferentes both svg as the printer - - -Note: once again after having saved the file I open it again and he had not saved and autosave (10 minutes) saved the changes
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2974273 -2974273 -1 -1015285 -755196 -100 -nobody -nobody -nobody -1269211031 -0 -5 -stop responding and locks everything -
schematic editor stopped responding and hangs it on ubuntu 9.04
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2974276 -2974276 -1 -761682 -755196 -100 -nobody -nobody -nobody -1269211211 -0 -5 -Pcbnew when you start trails -
command when you start hiking, I click the mouse and pull it almost always starts trails somewhere different and empty
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2974983 -2974983 -1 -761682 -755196 -100 -nobody -nobody -nobody -1269308934 -0 -5 -error layer edge when printing svg -
when I order prints in svg layers appear to put the edge inskape not recognize you need to choose property in the completion and color of the pen in any place and then solid and then he prints that layer
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2975062 -2975062 -1 -1015285 -755198 -100 -lomarcan -nobody -nobody -1269328968 -0 -5 -Bounding box for hierarchical sheet is wrong -
A hier. sheet is treated as is if it were wider than it really is i.e. right clicking somewhat on the right of a sheet shows the context menu for the sheet (even if there is NOTHING under the cursor)
-0 - - - - - - -9313221 -IP -Artifact Created: 80.207.56.82 -1269328968 -lomarcan - - - - -http://sourceforge.net/support/tracker.php?aid=2975063 -2975063 -2 -1015285 -755198 -1 -lomarcan -nobody -charras -1269329044 -1269791589 -5 -Move for a pinsheet can't be canceled -
When moving a pinsheet inside a hier. sheet symbol, pressing ESC confirms the move instead of canceling it
-0 - - - - - - -9313222 -IP -Artifact Created: 80.207.56.82 -1269329044 -lomarcan - - -9313234 -category_id -100 -1269329229 -lomarcan - - -9313235 -artifact_group_id -100 -1269329229 -lomarcan - - -9333281 -status_id -1 -1269791589 -charras - - -9333282 -resolution_id -100 -1269791589 -charras - - -9333283 -allow_comments -1 -1269791589 -charras - - -9333284 -close_date -0 -1269791589 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2975065 -2975065 -2 -1015285 -755198 -1 -lomarcan -nobody -charras -1269329087 -1269791589 -5 -Dragging a hierarchical sheet is broken -
It just move the sheet without dragging the wires.
-0 - - - - - - -9313227 -IP -Artifact Created: 80.207.56.82 -1269329087 -lomarcan - - -9313232 -category_id -100 -1269329195 -lomarcan - - -9313233 -artifact_group_id -100 -1269329195 -lomarcan - - -9333277 -status_id -1 -1269791589 -charras - - -9333278 -resolution_id -100 -1269791589 -charras - - -9333279 -allow_comments -1 -1269791589 -charras - - -9333280 -close_date -0 -1269791589 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2975066 -2975066 -2 -1015285 -755198 -1 -lomarcan -nobody -charras -1269329171 -1269791589 -5 -Hierarchical sheet operations cannot be undone -
They simply don't go in the undo stack. Pressing undo reverts other operations before.
-0 - - - - - - -9313231 -IP -Artifact Created: 80.207.56.82 -1269329171 -lomarcan - - -9333273 -status_id -1 -1269791589 -charras - - -9333274 -resolution_id -100 -1269791589 -charras - - -9333275 -allow_comments -1 -1269791589 -charras - - -9333276 -close_date -0 -1269791589 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2975068 -2975068 -1 -1015285 -755198 -100 -lomarcan -nobody -nobody -1269329437 -0 -1 -Hierarchical sheet resize -
An option to resize the sheet from the top could be useful. Otherwise you need to move all the pinsheet down to make space for the new ones.
-0 - - - - - - -9313238 -IP -Artifact Created: 80.207.56.82 -1269329437 -lomarcan - - -9313240 -priority -5 -1269329454 -lomarcan - - - - -http://sourceforge.net/support/tracker.php?aid=2975069 -2975069 -1 -1015285 -755198 -100 -lomarcan -nobody -nobody -1269329548 -0 -5 -Track cleanup after insertion of wire with INS -
Found because hier. sheet drag didn't work :P you have an array of wires like this: - ---- |> ---- |> Sheet ---- |> - -I used the W tool to add the missing part of wire in the first, the repeated -with INS. The first wire was 'fused' as one, the other ones remained with -dangling ends.
-0 - - - - - - -9313241 -IP -Artifact Created: 80.207.56.82 -1269329548 -lomarcan - - - - -http://sourceforge.net/support/tracker.php?aid=2975070 -2975070 -1 -1015285 -755198 -100 -lomarcan -nobody -nobody -1269329620 -0 -1 -Delete wire/delete node not intuitive -
The whole delete wire/delete node operation isn't really clear. The most -useful thing to do for a DEL keypress is to delete till the end or a junction -not the WHOLE wire (and not even always the whole, it depends on how it was -drawn to begin with). Example: - -A 1 B 2 C 3 D ----*---*---*--- (wire with junction) - -Pressing DEL on the A segment should delete only A, not the whole ABCD, or ABC, -or AB. Also the junction cleanup could be improved, often some 'corner' junction -remain or even some 'floating' ones. -
-0 - - - - - - -9313244 -IP -Artifact Created: 80.207.56.82 -1269329620 -lomarcan - - -9313245 -priority -5 -1269329646 -lomarcan - - - - -http://sourceforge.net/support/tracker.php?aid=2975071 -2975071 -1 -1015285 -755198 -100 -lomarcan -nobody -nobody -1269329698 -0 -1 -Power symbol drag -
Sometime G for a drag on a power symbol doesn't move the symbol itself but -only the wire. Something similar happen when ctrl dragging to the edge of a -part, they may be related issues.
-0 - - - - - - -9313246 -IP -Artifact Created: 80.207.56.82 -1269329698 -lomarcan - - -9313247 -priority -5 -1269329715 -lomarcan - - - - -http://sourceforge.net/support/tracker.php?aid=2975072 -2975072 -1 -1015285 -755198 -100 -lomarcan -nobody -nobody -1269329833 -0 -1 -Cut in eeschema? -
How do you cut in eeschema? Moving the cursor while moving scroll the view and warps the mouse (so the toolbar isn't accessible) and the accelerator key (S-DEL or C-X or whatever) isn't bound.
-0 - - - - - - -9313249 -IP -Artifact Created: 80.207.56.82 -1269329833 -lomarcan - - -9313251 -priority -5 -1269329848 -lomarcan - - - - -http://sourceforge.net/support/tracker.php?aid=2976225 -2976225 -1 -761682 -755196 -100 -nobody -nobody -nobody -1269476599 -0 -5 -breaking trails (rastnet) when trying to move or drag node s -
breaking trails (rastnet) when trying to move or drag node segment
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2976887 -2976887 -2 -761682 -755198 -105 -nobody -nobody -charras -1269592044 -1269887463 -5 -show on/off mask layer doesn't work ! -
hi all, - -sorry but show on/off mask layer doesn't work ! -see the file attach - -best regards
-0 - - -3946801 -charras -1269887463 -
Pads (on front and/ or back side) have their specific show/hide control. - this is not the show/hide layers options because pads are usually on more than one layer.
- - -3946860 -jerryjacobs -1269891110 -
I agree with Jean-Pierre, this is also with Highly proffesional EDA packages like Altium. It also has capability to have multi-layer pads. This is normal behaivour.
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=368271&aid= -368271 -show_layers.png - -20288 -image/png -1269592045 -nobody - - - - -9338776 -IP -Comment Added: 90.41.69.61 -1269887463 -charras - - -9338777 -status_id -1 -1269887463 -charras - - -9338778 -resolution_id -100 -1269887463 -charras - - -9338779 -allow_comments -1 -1269887463 -charras - - -9338780 -close_date -0 -1269887463 -charras - - -9338979 -IP -Comment Added: 84.25.204.235 -1269891110 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2976893 -2976893 -2 -761682 -755198 -1 -cfdev -charras -charras -1269593105 -1269887747 -7 -svg export doesn't work with the mask layer -
hi, - -I have created an pad rect with only the mak layer, and when I export it to svg from pcbnew, -and I open the svg with Inkscape there is only the outline of a rectangle?? - -see attach file - -best regards, - -Cyril
-0 - - -3941127 -cfdev -1269597266 -
In fact, it's the rectangle that don't display correctly - -kicad code svg : - <g - style="fill:black; stroke:black; stroke-width:1" - id="g8" /> - <g - style="fill:#a000a0;fill-opacity:1;stroke:#a000a0;stroke-linecap:round;stroke-linejoin:round;stroke-opacity:1;stroke-width:1" - transform="translate(0 0) scale(1 1)" - id="g350"> - <path - d="M42616 25116 L44584 25116" - id="path352" - style="fill:#a000a0;fill-opacity:1;stroke:#a000a0;stroke-opacity:1" /> - <path - d="M44584 25116 L44584 27084" - id="path354" - style="fill:#a000a0;fill-opacity:1;stroke:#a000a0;stroke-opacity:1" /> - <path - d="M44584 27084 L42616 27084" - id="path356" - style="fill:#a000a0;fill-opacity:1;stroke:#a000a0;stroke-opacity:1" /> - <path - d="M42616 25116 L42616 27084" - id="path358" - style="fill:#a000a0;fill-opacity:1;stroke:#a000a0;stroke-opacity:1" /> - </g> - - - -Inkscape code : - - <rect - style="opacity:0.87999998;fill:#a000a0;fill-opacity:1;fill-rule:nonzero;stroke:#a000a0;stroke-width:0.89313447;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" - id="rect4152" - width="1968.0778" - height="1968.0377" - x="42616.004" - y="25115.973" /> -
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=368273&aid= -368273 -TestSerigraphie-Mask_Front.svg - -14876 -image/svg+xml -1269593105 -cfdev - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=368274&aid= -368274 -mask_svg.png - -95359 -image/png -1269593133 -cfdev - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=368275&aid= -368275 -TestSerigraphie.brd - -37315 -application/octet-stream -1269593215 -cfdev - - - - -9325483 -IP -Artifact Created: 92.153.128.34 -1269593105 -cfdev - - -9325484 -File Added -368273: TestSerigraphie-Mask_Front.svg -1269593105 -cfdev - - -9325485 -File Added -368274: mask_svg.png -1269593133 -cfdev - - -9325488 -File Added -368275: TestSerigraphie.brd -1269593215 -cfdev - - -9325492 -priority -5 -1269593243 -cfdev - - -9325493 -assigned_to -100 -1269593243 -cfdev - - -9325595 -IP -Comment Added: 92.153.128.34 -1269597267 -cfdev - - -9338800 -status_id -1 -1269887747 -charras - - -9338801 -resolution_id -100 -1269887747 -charras - - -9338802 -allow_comments -1 -1269887747 -charras - - -9338803 -close_date -0 -1269887747 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2977619 -2977619 -1 -100 -755196 -100 -nobody -nobody -nobody -1269696992 -0 -5 -Layers manager toolbar is not resized -
In GerbView and PCBnew, the layers manager toolbar is not resized with the window, it keeps its initial size and masks the task bar. - -screen resolution : 1440*900 -version : 2010-03-14 on Ubuntu 9.10
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=368413&aid= -368413 -Gerbview-20100314-reduced.png -Layers manager tolbar in Gerbview -91477 -image/png -1269696993 -nobody - - - - - - -http://sourceforge.net/support/tracker.php?aid=2977970 -2977970 -2 -1015285 -755198 -1 -jerryjacobs -charras -charras -1269776502 -1269791588 -5 -Print/Plot dialog for SVG sheet or symbol file browser -
Exporting a symbol in eeschema libedit for png is able to select a path and filename with a file browser dialog. This is not possible in SVG plot/print and if I open eeschema without a new project and try to plot a SVG from the kicad-newlib then I'm not able to find where it writes the SVG file to the harddisk. - -For me this is more a "bug" than a future request. -Correct me if i'm wrong. - -Regards, -Jerry
-0 - - - - - - -9332813 -IP -Artifact Created: 84.25.204.235 -1269776502 -jerryjacobs - - -9333269 -status_id -1 -1269791588 -charras - - -9333270 -resolution_id -100 -1269791588 -charras - - -9333271 -allow_comments -1 -1269791588 -charras - - -9333272 -close_date -0 -1269791588 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2978373 -2978373 -2 -761682 -100 -6 -cfdev -nobody -charras -1269849435 -1269887708 -5 -Delete bloc with zones doesn't work -
hi everybody, - -When I want to remove an bloc with all options checked, the zones always exist ?
-0 - - - - - - -9336252 -IP -Artifact Created: 92.153.128.34 -1269849435 -cfdev - - -9338796 -status_id -1 -1269887708 -charras - - -9338797 -resolution_id -100 -1269887708 -charras - - -9338798 -allow_comments -1 -1269887708 -charras - - -9338799 -close_date -0 -1269887708 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2979337 -2979337 -2 -1015285 -755198 -1 -lomarcan -nobody -charras -1269952647 -1270132369 -5 -Find part doesn't work for subparts -
You can't specify the subpart qualifier when searching i.e. U9 finds all the subparts in U9, but U9A doesn't find anything.
-0 - - - - - - -9341989 -IP -Artifact Created: 80.207.56.82 -1269952647 -lomarcan - - -9353468 -status_id -1 -1270132369 -charras - - -9353469 -resolution_id -100 -1270132369 -charras - - -9353470 -allow_comments -1 -1270132369 -charras - - -9353471 -close_date -0 -1270132369 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2979953 -2979953 -2 -761682 -1083307 -1 -khame -nobody -charras -1270036341 -1270058393 -5 -Can't generate Gerber file in normal user mode -
Under Windows Vista (sp2) with Kicad build 20100314SVN-R2460-final: - - - If you try to plot Gerber files in User mode you can only have empty files (No error displayed). PostScript plotting is good. - - - If you try to plot Gerber files after launching Kicad in Administrator mode the Gerber plotting is good. - -Maybe for the gerber plotting there is an access on a configuration file with higher permissions requirements.
-0 - - - - - - -9348319 -IP -Artifact Created: 88.160.11.132 -1270036342 -khame - - -9349426 -status_id -1 -1270058393 -charras - - -9349427 -resolution_id -100 -1270058393 -charras - - -9349428 -allow_comments -1 -1270058393 -charras - - -9349429 -close_date -0 -1270058393 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2980243 -2980243 -2 -761682 -516020 -2 -herg -nobody -herg -1270069556 -1270127105 -5 -Module attributes incorrectly populated -
I have a module with attributes: -T0 83 2736 600 600 0 120 N I 21 N"TSSOP16" -T1 126 1866 600 600 0 120 N V 21 N"VAL**" - -I then use CVpcb to link this module to: - ( /4BB25547 $noname U6 ADG888 {Lib=ADG888} - -I then read the netlist into PCBnew, and in the .brd: -T0 83 2736 600 600 0 120 N I 21 N"U6" -T1 126 1866 600 600 0 120 N V 21 N"ADG888" - -As you can see, I intended to make the reference designator visible, and the value invisible. The result is the opposite. -
-0 - - -3950041 -herg -1270127104 -
Upon further review, it looks like I misinterpreted the documentation: - -Module fields - - * The field that has the module name becomes the reference designator (R1 for a resistor). The field that contains: - - VAL** - -reflects the Part name that pointed to the module.
- - - - - - -9350444 -IP -Artifact Created: 98.191.170.34 -1270069556 -herg - - -9353243 -IP -Comment Added: 98.191.170.34 -1270127105 -herg - - -9353244 -status_id -1 -1270127105 -herg - - -9353245 -resolution_id -100 -1270127105 -herg - - -9353246 -close_date -0 -1270127105 -herg - - - - -http://sourceforge.net/support/tracker.php?aid=2980726 -2980726 -2 -761682 -516020 -105 -pisulski -nobody -charras -1270153957 -1270217732 -5 -Visibility/unvisibility in editor library is not available -
first problem.Visibility option in Library editor is not available in case when i Want to unvisibility pin name. -Second problem: Enter key forces to go to the next field. He should confirm the change. -Third problem. In new version Kicad don`t work funktionality: WHen i take some module in new pcb, kicad show me the element in eeschema window.
-0 - - - - - - -9355121 -IP -Artifact Created: 77.253.92.138 -1270153957 -pisulski - - -9358632 -status_id -1 -1270217732 -charras - - -9358633 -resolution_id -100 -1270217732 -charras - - -9358634 -allow_comments -1 -1270217732 -charras - - -9358635 -close_date -0 -1270217732 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2980729 -2980729 -2 -1015285 -100 -105 -pisulski -nobody -charras -1270154331 -1270217732 -5 -Group rotate not work -
When I select few element's in eeschema and when i klik "R" key - it is no action.
-0 - - - - - - -9355128 -IP -Artifact Created: 77.253.92.138 -1270154331 -pisulski - - -9358628 -status_id -1 -1270217732 -charras - - -9358629 -resolution_id -100 -1270217732 -charras - - -9358630 -allow_comments -1 -1270217732 -charras - - -9358631 -close_date -0 -1270217732 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2980736 -2980736 -2 -1015285 -100 -6 -pisulski -nobody -charras -1270154599 -1270217641 -5 -Filed Don1't change their position. -
When i edit some component and i change position "reference" filed and "component name" filed, I aktualize my component in eeschema windoot this 2 filed dont change position.
-0 - - -3950601 -vovanium -1270157168 -
This is a feature -- ref and value position in library is only actual when you newly place a symbol on the scheme, then you may freely move ref and value on the scheme and their positions will be saved with the schematics.
- - - - - - -9355146 -IP -Artifact Created: 77.253.92.138 -1270154599 -pisulski - - -9355362 -IP -Comment Added: 91.76.122.230 -1270157169 -vovanium - - -9358623 -status_id -1 -1270217641 -charras - - -9358624 -resolution_id -100 -1270217641 -charras - - -9358625 -allow_comments -1 -1270217641 -charras - - -9358626 -close_date -0 -1270217641 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2981754 -2981754 -2 -761682 -755196 -1 -dionysos-sf -nobody -charras -1270372677 -1270496092 -9 -PCBnew crash when trying to add a net in a netclass -
I created a new netclass (50_ohms) where I tried to add some nets. -I selected my netclass in the right list with the selector, then selected a net name in the left list and then clicked on the button ">>>". -Pcbnew crashes. - -Here is the backtrace of gdb: - -Program received signal SIGSEGV, Segmentation fault. -wxStringBase::compare (this=0x1294bc8, str=...) at src/common/string.cpp:948 -948 return ::wxDoCmp(data(), length(), str.data(), str.length()); -(gdb) bt -#0 wxStringBase::compare (this=0x1294bc8, str=...) at src/common/string.cpp:948 -#1 0x000000000047dbf1 in ?? () -#2 0x000000000047e3e6 in DIALOG_DESIGN_RULES::makePointers(std::vector<NETCUP*, std::allocator<NETCUP*> >*, wxString const&) () -#3 0x000000000047e841 in DIALOG_DESIGN_RULES::FillListBoxWithNetNames(wxListCtrl*, wxString const&) () -#4 0x0000000000482f4c in DIALOG_DESIGN_RULES::OnRightToLeftCopyButton(wxCommandEvent&) () -#5 0x0000003a730f2070 in wxEvtHandler::ProcessEventIfMatches (entry=<value optimized out>, handler=<value optimized out>, event=...) - at src/common/event.cpp:1231 -#6 0x0000003a730f21df in wxEvtHandler::SearchDynamicEventTable (this=0x122bde0, event=...) at src/common/event.cpp:1413 -#7 0x0000003a730f30e2 in wxEvtHandler::ProcessEvent (this=0x122bde0, event=...) at src/common/event.cpp:1289 -#8 0x000000346162f3c9 in gtk_button_clicked_callback (button=0x122bde0) at src/gtk/button.cpp:53 -#9 0x0000003faa80ba8e in IA__g_closure_invoke (closure=0x122bbc0, return_value=0x0, n_param_values=1, param_values=0x12d7e80, invocation_hint= - 0x7fffffffbe40) at gclosure.c:767 -#10 0x0000003faa8214b0 in signal_emit_unlocked_R (node=<value optimized out>, detail=<value optimized out>, instance=<value optimized out>, - emission_return=<value optimized out>, instance_and_params=<value optimized out>) at gsignal.c:3317 -#11 0x0000003faa82225f in IA__g_signal_emit_valist (instance=<value optimized out>, signal_id=<value optimized out>, detail=<value optimized out>, - var_args=0x7fffffffc030) at gsignal.c:2980 -#12 0x0000003faa8227a3 in IA__g_signal_emit (instance=<value optimized out>, signal_id=<value optimized out>, detail=<value optimized out>) - at gsignal.c:3037 -#13 0x000000346008d6f5 in gtk_real_button_released (button=0x11c1190 [GtkButton]) at gtkbutton.c:1707 -#14 0x0000003faa80ba8e in IA__g_closure_invoke (closure=0xb40b90, return_value=0x0, n_param_values=1, param_values=0x12d3940, invocation_hint= - 0x7fffffffc250) at gclosure.c:767 -#15 0x0000003faa8207dc in signal_emit_unlocked_R (node=<value optimized out>, detail=<value optimized out>, instance=<value optimized out>, - emission_return=<value optimized out>, instance_and_params=<value optimized out>) at gsignal.c:3177 -#16 0x0000003faa82225f in IA__g_signal_emit_valist (instance=<value optimized out>, signal_id=<value optimized out>, detail=<value optimized out>, - var_args=0x7fffffffc440) at gsignal.c:2980 -#17 0x0000003faa8227a3 in IA__g_signal_emit (instance=<value optimized out>, signal_id=<value optimized out>, detail=<value optimized out>) - at gsignal.c:3037 -#18 0x000000346008bf57 in gtk_button_button_release (widget=<value optimized out>, event=<value optimized out>) at gtkbutton.c:1599 -#19 0x0000003460153ae3 in _gtk_marshal_BOOLEAN__BOXED (closure=0xba75d0, return_value=0x7fffffffc6f0, n_param_values=<value optimized out>, - param_values=0x12c7400, invocation_hint=<value optimized out>, marshal_data=<value optimized out>) at gtkmarshalers.c:84 -#20 0x0000003faa80b9d9 in IA__g_closure_invoke (closure=0xba75d0, return_value=0x7fffffffc6f0, n_param_values=2, param_values=0x12c7400, - invocation_hint=0x7fffffffc6b0) at gclosure.c:767 -#21 0x0000003faa820b8d in signal_emit_unlocked_R (node=<value optimized out>, detail=<value optimized out>, instance=<value optimized out>, - emission_return=<value optimized out>, instance_and_params=<value optimized out>) at gsignal.c:3285 -#22 0x0000003faa8220fa in IA__g_signal_emit_valist (instance=<value optimized out>, signal_id=<value optimized out>, detail=<value optimized out>, - var_args=0x7fffffffc8a0) at gsignal.c:2990 -#23 0x0000003faa8227a3 in IA__g_signal_emit (instance=<value optimized out>, signal_id=<value optimized out>, detail=<value optimized out>) - at gsignal.c:3037 -#24 0x000000346027633f in gtk_widget_event_internal (widget=0x11c1190 [GtkButton], event=0x10a45f0) at gtkwidget.c:4775 -#25 0x000000346014a844 in IA__gtk_propagate_event (widget=0x11c1190 [GtkButton], event=0x10a45f0) at gtkmain.c:2417 -#26 0x000000346014b983 in IA__gtk_main_do_event (event=0x10a45f0) at gtkmain.c:1622 -#27 0x000000345fc5feac in gdk_event_dispatch (source=<value optimized out>, callback=<value optimized out>, user_data=<value optimized out>) - at gdkevents-x11.c:2372 -#28 0x0000003faa43923e in g_main_dispatch (context=0xb2c210) at gmain.c:1960 -#29 IA__g_main_context_dispatch (context=0xb2c210) at gmain.c:2513 -#30 0x0000003faa43cc28 in g_main_context_iterate (context=0xb2c210, block=<value optimized out>, dispatch=<value optimized out>, - self=<value optimized out>) at gmain.c:2591 -#31 0x0000003faa43d075 in IA__g_main_loop_run (loop=0x128cd90) at gmain.c:2799 -#32 0x000000346014beb7 in IA__gtk_main () at gtkmain.c:1218 -#33 0x00000034615e5c58 in wxEventLoop::Run (this=0x7fffffffcc70) at src/gtk/evtloop.cpp:76 -#34 0x000000346163ad51 in wxDialog::ShowModal (this=0x7fffffffccb0) at src/gtk/dialog.cpp:146 -#35 0x000000000045ccb3 in WinEDA_PcbFrame::ShowDesignRulesEditor(wxCommandEvent&) () -#36 0x0000003a730f2070 in wxEvtHandler::ProcessEventIfMatches (entry=<value optimized out>, handler=<value optimized out>, event=...) - at src/common/event.cpp:1231 -#37 0x0000003a730f3034 in wxEventHashTable::HandleEvent (this=<value optimized out>, event=..., self=0xb9efc0) at src/common/event.cpp:906 -#38 0x0000003a730f3117 in wxEvtHandler::ProcessEvent (this=0xb9efc0, event=...) at src/common/event.cpp:1293 -#39 0x0000003a730f30a0 in wxEvtHandler::ProcessEvent (this=0xb9f2f8, event=...) at src/common/event.cpp:1300 -#40 0x00000034616552e6 in gtk_menu_clicked_callback (widget=<value optimized out>, menu=0x11cc720) at src/gtk/menu.cpp:653 -#41 0x0000003faa80ba8e in IA__g_closure_invoke (closure=0x11ccd20, return_value=0x0, n_param_values=1, param_values=0x10ac8c0, invocation_hint= - 0x7fffffffd3b0) at gclosure.c:767 -#42 0x0000003faa820ec3 in signal_emit_unlocked_R (node=<value optimized out>, detail=<value optimized out>, instance=<value optimized out>, - emission_return=<value optimized out>, instance_and_params=<value optimized out>) at gsignal.c:3247 -#43 0x0000003faa82225f in IA__g_signal_emit_valist (instance=<value optimized out>, signal_id=<value optimized out>, detail=<value optimized out>, - var_args=0x7fffffffd5a0) at gsignal.c:2980 -#44 0x0000003faa8227a3 in IA__g_signal_emit (instance=<value optimized out>, signal_id=<value optimized out>, detail=<value optimized out>) - at gsignal.c:3037 -#45 0x000000346027d4ee in IA__gtk_widget_activate (widget=0x11c79e0 [GtkImageMenuItem]) at gtkwidget.c:4806 -#46 0x00000034601647bd in IA__gtk_menu_shell_activate_item (menu_shell=0x11c5340 [GtkMenu], menu_item=0x11c79e0 [GtkImageMenuItem], - force_deactivate=<value optimized out>) at gtkmenushell.c:1139 -#47 0x000000346016646a in gtk_menu_shell_button_release (widget=0x11c5340 [GtkMenu], event=<value optimized out>) at gtkmenushell.c:678 -#48 0x0000003460153ae3 in _gtk_marshal_BOOLEAN__BOXED (closure=0xba75d0, return_value=0x7fffffffd8f0, n_param_values=<value optimized out>, - param_values=0xf15cd0, invocation_hint=<value optimized out>, marshal_data=<value optimized out>) at gtkmarshalers.c:84 -#49 0x0000003faa80ba8e in IA__g_closure_invoke (closure=0xba75d0, return_value=0x7fffffffd8f0, n_param_values=2, param_values=0xf15cd0, - invocation_hint=0x7fffffffd8b0) at gclosure.c:767 -#50 0x0000003faa820b8d in signal_emit_unlocked_R (node=<value optimized out>, detail=<value optimized out>, instance=<value optimized out>, - emission_return=<value optimized out>, instance_and_params=<value optimized out>) at gsignal.c:3285 -#51 0x0000003faa8220fa in IA__g_signal_emit_valist (instance=<value optimized out>, signal_id=<value optimized out>, detail=<value optimized out>, - var_args=0x7fffffffdaa0) at gsignal.c:2990 -#52 0x0000003faa8227a3 in IA__g_signal_emit (instance=<value optimized out>, signal_id=<value optimized out>, detail=<value optimized out>) - at gsignal.c:3037 -#53 0x000000346027633f in gtk_widget_event_internal (widget=0x11c5340 [GtkMenu], event=0xd11b30) at gtkwidget.c:4775 -#54 0x000000346014a844 in IA__gtk_propagate_event (widget=0x11c5340 [GtkMenu], event=0xd11b30) at gtkmain.c:2417 -#55 0x000000346014b983 in IA__gtk_main_do_event (event=0xd11b30) at gtkmain.c:1622 -#56 0x000000345fc5feac in gdk_event_dispatch (source=<value optimized out>, callback=<value optimized out>, user_data=<value optimized out>) - at gdkevents-x11.c:2372 -#57 0x0000003faa43923e in g_main_dispatch (context=0xb2c210) at gmain.c:1960 -#58 IA__g_main_context_dispatch (context=0xb2c210) at gmain.c:2513 -#59 0x0000003faa43cc28 in g_main_context_iterate (context=0xb2c210, block=<value optimized out>, dispatch=<value optimized out>, - self=<value optimized out>) at gmain.c:2591 -#60 0x0000003faa43d075 in IA__g_main_loop_run (loop=0x1036e80) at gmain.c:2799 -#61 0x000000346014beb7 in IA__gtk_main () at gtkmain.c:1218 -#62 0x00000034615e5c58 in wxEventLoop::Run (this=0xd0f5a0) at src/gtk/evtloop.cpp:76 -#63 0x000000346166e9eb in wxAppBase::MainLoop (this=0xb2bee0) at src/common/appcmn.cpp:312 -#64 0x0000003a73097abc in wxEntry (argc=<value optimized out>, argv=<value optimized out>) at src/common/init.cpp:460 -#65 0x000000000055c2d2 in main () - -
-0 - - -3952688 - -1270387353 -
This bug is probably linked to bug #2970765.
- - -3952835 -dionysos-sf -1270406725 -
Probably, and 2970719 too.
- - - - - - -9363579 -IP -Artifact Created: 82.224.136.31 -1270372677 -dionysos-sf - - -9363840 -priority -5 -1270375382 -dionysos-sf - - -9364059 -IP -Comment Added: 86.67.51.130 -1270387353 - - - -9364658 -IP -Comment Added: 82.224.136.31 -1270406725 -dionysos-sf - - -9367678 -status_id -1 -1270496092 -charras - - -9367679 -resolution_id -100 -1270496092 -charras - - -9367680 -allow_comments -1 -1270496092 -charras - - -9367681 -close_date -0 -1270496092 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2981759 -2981759 -2 -761682 -755196 -1 -dionysos-sf -nobody -charras -1270373635 -1270496091 -5 -PCBnew crash when trying to add a net name to a pad in ModEd -
PCBnew crash when trying to add a net name to a pad in ModEdit. -Perhaps this is something we are not allowed to do. -I wanted to add a net name (GND) to some pads of a module in ModEdit. -When I clicked OK, a popup opened saying "Unknown netname, no change". -I clicked OK on this popup, then PCBnew crashes. - -Here is the baktrace from gdb: -Program received signal SIGSEGV, Segmentation fault. -0x0000003461758128 in typeinfo name for wxWindowBase () from /usr/lib64/libwx_gtk2u_core-2.8.so.0 -(gdb) bt -#0 0x0000003461758128 in typeinfo name for wxWindowBase () from /usr/lib64/libwx_gtk2u_core-2.8.so.0 -#1 0x00000034615faeec in gtk_window_realized_callback (m_widget=0x7fffffffc850, win=0x11c4b60) at src/gtk/window.cpp:2150 -#2 0x00000034616ee365 in wxGetTopLevelParent (win=0x7fffffffc850) at src/common/wincmn.cpp:2808 -#3 0x00000034616f254c in wxWindowBase::~wxWindowBase (this=0x11c4b60, __in_chrg=<value optimized out>) at src/common/wincmn.cpp:324 -#4 0x00000032a4e9676a in ~WinEDA_MessageDialog (this=0x11c4b60, __in_chrg=<value optimized out>) - at /usr/src/debug/kicad-2010.03.14/common/confirm.cpp:35 -#5 WinEDA_MessageDialog::~WinEDA_MessageDialog (this=0x11c4b60, __in_chrg=<value optimized out>) - at /usr/src/debug/kicad-2010.03.14/common/confirm.cpp:35 -#6 0x000000346166eb22 in wxAppBase::DeletePendingObjects (this=<value optimized out>) at src/common/appcmn.cpp:423 -#7 0x000000346166ebeb in wxAppBase::ProcessIdle (this=0xb1a770) at src/common/appcmn.cpp:454 -#8 0x00000034615ce900 in wxapp_idle_callback () at src/gtk/app.cpp:213 -#9 0x0000003faa43923e in g_main_dispatch (context=0xb1aa00) at gmain.c:1960 -#10 IA__g_main_context_dispatch (context=0xb1aa00) at gmain.c:2513 -#11 0x0000003faa43cc28 in g_main_context_iterate (context=0xb1aa00, block=<value optimized out>, dispatch=<value optimized out>, - self=<value optimized out>) at gmain.c:2591 -#12 0x0000003faa43d075 in IA__g_main_loop_run (loop=0xeb7fb0) at gmain.c:2799 -#13 0x000000346014beb7 in IA__gtk_main () at gtkmain.c:1218 -#14 0x00000034615e5c58 in wxEventLoop::Run (this=0xeb76f0) at src/gtk/evtloop.cpp:76 -#15 0x000000346166e9eb in wxAppBase::MainLoop (this=0xb1a770) at src/common/appcmn.cpp:312 -#16 0x0000003a73097abc in wxEntry (argc=<value optimized out>, argv=<value optimized out>) at src/common/init.cpp:460 -#17 0x000000000055c2d2 in main () - -
-0 - - - - - - -9363681 -IP -Artifact Created: 82.224.136.31 -1270373635 -dionysos-sf - - -9367674 -status_id -1 -1270496091 -charras - - -9367675 -resolution_id -100 -1270496091 -charras - - -9367676 -allow_comments -1 -1270496091 -charras - - -9367677 -close_date -0 -1270496091 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2981769 -2981769 -2 -761682 -755196 -105 -dionysos-sf -nobody -charras -1270375278 -1270489033 -5 -Pad colors aren't the same than the tracks -
I changed the default layer color in PCBnew by switching colors between solder layer and component layer -Now, solder layer tracks are red and component layer tracks are green. -Unfortunately, pad colors are not changed: solder layer pads are still green and component layer pads are still red, which isn't easy to work with.
-0 - - - - - - -9363839 -IP -Artifact Created: 82.224.136.31 -1270375278 -dionysos-sf - - -9367382 -status_id -1 -1270489033 -charras - - -9367383 -resolution_id -100 -1270489033 -charras - - -9367384 -allow_comments -1 -1270489033 -charras - - -9367385 -close_date -0 -1270489033 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2982119 -2982119 -2 -1015285 -100 -105 -thewarpi -nobody -charras -1270480629 -1270489033 -5 -Underscores added when creating new part -
Hi! - -When creating a new part in "Component Library Editor" writing the name under "Component name", it automaticly adds underscores instead of space. It also makes the letters uppercase. I know this is a bug because, you can change the name afterwards in the "Field properties" afterwards, and then it works to use partnames with spaces and lowercase.
-0 - - -3953398 -thewarpi -1270483764 -
This goes for aliases aswell.. Why,,,, WHYY??? :)
- - -3953439 -thewarpi -1270485805 -
Ok, maybe it is not a bug since, it didnt work using partnames with spaces. Some error shows up when trying to load the schematic at a later time. - -Can we move this to a feature request?
- - - - - - -9366835 -IP -Artifact Created: 90.237.202.7 -1270480629 -thewarpi - - -9366971 -IP -Comment Added: 90.237.202.7 -1270483764 -thewarpi - - -9367165 -IP -Comment Added: 90.237.202.7 -1270485805 -thewarpi - - -9367378 -status_id -1 -1270489033 -charras - - -9367379 -resolution_id -100 -1270489033 -charras - - -9367380 -allow_comments -1 -1270489033 -charras - - -9367381 -close_date -0 -1270489033 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2982146 -2982146 -2 -1015285 -100 -105 -thewarpi -nobody -charras -1270484084 -1270489032 -5 -Changing Value field of component creates a new one -
I dont know if this is suppose to be this way, when renaming a components value in the "Fields properties" it automaticly creates a new component with that name. Its a very nice way to copy components but it not a very logic one for people who dosent know about it.
-0 - - - - - - -9366987 -IP -Artifact Created: 90.237.202.7 -1270484084 -thewarpi - - -9366989 -category_id -100 -1270484114 -thewarpi - - -9367374 -status_id -1 -1270489032 -charras - - -9367375 -resolution_id -100 -1270489032 -charras - - -9367376 -allow_comments -1 -1270489032 -charras - - -9367377 -close_date -0 -1270489032 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2982182 -2982182 -2 -761682 -755196 -1 -nobody -nobody -charras -1270489450 -1270545636 -5 -PCBNew File - Revert function don't work. -
Sorry my english is not so good :-) I think the Revert-Funktion don't work. If I use the File -> Revert function from the Menu I get the error message: - -Recovery file /home/myuser/project/myproject.000 not found. - -PCBNew create not a backupfile. If I create the file (e.g. with touch command under Linux) then PCBNew update the backupfile correct. -
-0 - - - - - - -9369894 -status_id -1 -1270545636 -charras - - -9369895 -resolution_id -100 -1270545636 -charras - - -9369896 -allow_comments -1 -1270545636 -charras - - -9369897 -close_date -0 -1270545636 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2982617 -2982617 -1 -100 -100 -100 -nobody -nobody -nobody -1270557838 -0 -5 -List unconnected: center on component -
Rightclicking and selecting a pad in the list no longer centers on the chosen pad/component, as it used to in the previous version.
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2982636 -2982636 -1 -100 -100 -100 -nobody -nobody -nobody -1270560526 -0 -5 -List hotkeys -
The function List Hotkeys doesn't show a correct list. (I have assigned F5-F10 to different layers, which works). E g the F9 key is assigned "Switch to Inner layer 5" in file, but is listed both as "key F9: Switch to Inner layer 1" and "key F9: Switch to Inner layer 5".
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2982787 -2982787 -1 -761682 -755196 -100 -daveplatt -nobody -nobody -1270580048 -0 -5 -XORG crash when zooming -
This bug is actually a duplicate of 293063 - I couldn't figure out how to add a comment/artifact to that bug since it has already been closed. - -I also have run into the "Xorg server crash when zooming" using pcbnew, and as with the above bug it started occurring after my Xorg install was upgraded to version 1.7 (I run Debian's "testing" distribution). - -I dug around for a while on the net, and have confirmed that this is a real problem in the new version of Xorg. It certainly affects the Radeon driver, and may affect others as well. - -The problem seems to be centered in the EXA acceleration code in the X server (which the Radeon driver will use on request). There appears to be a situation in which the acceleration code can try to use an internal resource (an offscreen pixmap if I recall correctly) without activating it properly prior to use... smash, bang, segfault. Apparently, pcbnew's drawing of arcs seems to tickle this bug, which is otherwise somewhat difficult to trigger. - -The Xorg people seem to be looking into the cause, but the fix isn't straightforward, so it may take a while to correct the problem. - -Fortunately, there is an effective workaround. Go into your /etc/X11/xorg.conf file, find your Device section, and add (or change) the AccelMethod parameter. Set it to - - AccelMethod "xaa" - -This disables the new EXA accelerator, and switches back to the older XAA acceleration. - -There may be some reduction in screen rendering performance on some systems... this appears to be very dependent on the specific X card you use, and your graphics settings and what programs you're running. - -I didn't notice any degradation on my laptop's Radeon setup last night, when I confirmed that this workaround does actually correct the problem.
-0 - - - - - - -9371406 -IP -Artifact Created: 204.176.49.46 -1270580048 -daveplatt - - - - -http://sourceforge.net/support/tracker.php?aid=2982989 -2982989 -1 -761682 -755196 -100 -nobody -nobody -nobody -1270611363 -0 -5 -error adding board -
If I have the card "A" command and add to plate "B" when I send save it saves as a board "B" append the path of plate "B" being the right thing is to save card as "A" simply because I sent save and at worst should save as a board "A" to append the file is not the primary and secondary
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2983282 -2983282 -1 -1015287 -100 -100 -cfdev -nobody -nobody -1270652596 -0 -1 -Gerbview show/hide all layers -
show/hide all layers works only on 16 first layers (1 to 16)
-0 - - - - - - -9374927 -IP -Artifact Created: 92.153.22.228 -1270652597 -cfdev - - -9374928 -priority -5 -1270652628 -cfdev - - - - -http://sourceforge.net/support/tracker.php?aid=2983287 -2983287 -1 -1015287 -100 -100 -cfdev -nobody -nobody -1270653156 -0 -5 -Gerbview to pcbnew Layer problem -
when I import 2 layers, top and bottom in gerbview, it's ok, -I export to pcnew with select the layer ( *.brd ) - -When I open the *.brd in pcbnew, the board is correct, But I don't work with 2 layers, -so, I go to "design rules" -> impossible to check the layer uncheched, select an different number of layer and reselect 2 layers, -and It"s Ok I can check the layer. - -ps: sorry if I explained poorly
-0 - - - - - - -9374955 -IP -Artifact Created: 92.153.22.228 -1270653156 -cfdev - - - - -http://sourceforge.net/support/tracker.php?aid=2983318 -2983318 -1 -761682 -516020 -100 -nobody -nobody -nobody -1270656622 -0 -5 -Oval Pads Fail DRC Incorrectly -
Although DRC for oval pads works better with the new final release (20100314), it seems that pads placed at corners are treated like rectangular pads, which (depending on rotation) generates an incorrect error. Rotation 0 and 90 generates an error, rotation 0 and -90 does not. - -This issue was mentioned in 2945885 and is supposed to have been corrected, which is not the case (for the final release, at least).
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2983903 -2983903 -1 -761682 -100 -100 -nobody -nobody -nobody -1270734959 -0 -5 -Pad in Zone error -
I have a problem with "Add zones" function. Problem is: When i add zone GND all track and vias on the tracks have a good antipad size and thermal relife. But i have zones GND on the top and on the bottom side and i want to compensate potentianl on the bord. I do it throught vias. I trace the GND track to the vias ( see include file) I dont have thrmal relief. Exclude pads in this case also don`t work. -I highlight the GND net. and display Zones option. Mayby i have bad/incorect settings
-0 - - -3956972 -sebc26 -1270736823 -
Hi ... - -I have a problem that looks like the same : - -http://sourceforge.net/tracker/?func=detail&aid=2980541&group_id=145591&atid=762477 - -I hope this will be solved soon.
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=369871&aid= -369871 -Fill Zones Option and little bord.JPG - -139819 -image/jpeg -1270734959 -nobody - - - - -9381580 -IP -Comment Added: 82.244.110.178 -1270736823 -sebc26 - - - - -http://sourceforge.net/support/tracker.php?aid=2983906 -2983906 -1 -100 -100 -100 -pisulski -nobody -nobody -1270735441 -0 -5 -Show action layer selection -error -
Show action layer selection button don`t change colour when i change layer.
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762476&file_id=369872&aid= -369872 -Show action layer.JPG - -19071 -image/jpeg -1270735441 -pisulski - - - - -9381512 -IP -Artifact Created: 178.36.47.210 -1270735441 -pisulski - - -9381513 -File Added -369872: Show action layer.JPG -1270735441 -pisulski - - - - -http://sourceforge.net/support/tracker.php?aid=2984216 -2984216 -1 -761682 -755196 -100 -nobody -nobody -nobody -1270772601 -0 -5 -erro move zones in blocks -
failed to move the block that contains areas(zones) ,moves after they stay in place that were, only the fill.
-0 - - - - - - - - - - -http://sourceforge.net/?group_id=145591&atid=762477 -762477 -Support Requests -Tech Support Tracking System -All site users -Yes -No -1296000 - - -1209600 -0 -0 -0 - - - - -516021 -v1.0 (example) - - - - -761683 -Install Problem (example) -nobody - - - - - - -1 -Open - - -2 -Closed - - -3 -Deleted - - -4 -Pending - - - - -http://sourceforge.net/support/tracker.php?aid=1528910 -1528910 -3 -100 -100 -plyatov -nobody -dickelbeck -1153911779 -1187885389 -9 -site admin can\'t change file ownersheep -
I'm cannot make command -"chown manneveru -/home/groupsk/ki/kicad/htdocs/pl/index.shtml" - at shell.sourceforge.net . -Error is "Operation not permitted". -"manneveru" is member of my project. -Please help!
-0 - - - - - - -4958170 -status_id -1 -1187885389 -dickelbeck - - -4958171 -summary -site admin can't change file ownersheep -1187885389 -dickelbeck - - -4958172 -close_date -0 -1187885389 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=1943039 -1943039 -1 -100 -100 -nobody -nobody -nobody -1208268198 -0 -5 -KiCAD on PenDrive? -
Is it possible to create KiCAD's directory structure on PenDrive to have "mobile" version of KiCAD?
-0 - - -2897061 -manneveru -1219910997 -
Logged In: YES -user_id=639576 -Originator: NO - -Probably yes. KiCad can be built static with most libraries included. But I don't think anyone tried this before. If you have success, please publish it on wiki.
- - -3580022 -nobody -1237303746 -
It works fine under windows. Make the install on the pendrive and run kicad's exe.
- - - - - - -5902178 -IP -Artifact Created: 134.134.136.33 -1208268198 -nobody - - -6434266 -IP -Comment Added: 217.147.104.41 -1219910997 -manneveru - - -7933342 -IP -Comment Added: 212.99.4.114 -1237303746 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1956745 -1956745 -3 -761683 -516021 -durgadas -nobody -jerryjacobs -1209825873 -1257534813 -5 -looks for libraries and directories that don't exist -
When I start a new schematic I get a long long trail of dialog boxes complaining about libraries that don't exist. I can find no code or config file that names these libraries so can't tell where it gets the idea these should exist. I can edit the schematic file and eliminate the complaints, but every new schematic has them. Seems like either something is missing from the distro or someones private list of libraries has crept into the code (but I can't find them in any code!). - -Also, I get a complaint when kicad opens a browse dialog box about some applinks directory in kde3 not having search permissions. I also cannot find any code that is trying to use that directory. - -Does anyone know where these paths/filenames might be coming from?
-0 - - -3799528 -jerryjacobs -1257534813 -
There should be no problems with new releases.
- - - - - - -5972200 -IP -Artifact Created: 209.180.51.97 -1209825874 -durgadas - - -8855069 -IP -Comment Added: 84.25.204.235 -1257534813 -jerryjacobs - - -8855070 -status_id -1 -1257534813 -jerryjacobs - - -8855071 -close_date -0 -1257534813 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2075168 -2075168 -1 -100 -100 -and10 -nobody -nobody -1219732824 -0 -5 -Schematic print multiple pages -
I have tried to print my A3 sized schematic on an A4 printer HP1200 (and on PDF printer as well) spanning multiple pages, but the "Layout\spread 1 page on 2 pages" doesn't do the trick. -I also wondered if it is correct that all print options resets when I press "preview", which means that it is not possible to preview with specific settings and then immediately print with the same settings. -Running ubuntu linux. - -
-0 - - - - - - -6421914 -IP -Artifact Created: 85.82.142.172 -1219732825 -and10 - - - - -http://sourceforge.net/support/tracker.php?aid=2980541 -2980541 -1 -100 -100 -sebc26 -nobody -nobody -1270127146 -0 -5 -Vias / Zone filling problem -
Hi world, - -From some times, there is a problem I cannot solve ... - -The goal is to set heat sink for SOT_23_5. -= vias under SOT23 will act as heat pipe and GND plane will be the heat sink. - -Please take a look at the picture, there are 4 STEPs on it : - -STEP 1 = I've put 3 vias under my SOT23, and connect them to the GND pin (net 8 on picture). - -STEP 2 = I use the equipotential tool to ensure that there are really connected to GND (net 8). - -STEP 3 = I fill the zone, and them, the zone "take" the vias at center, but avoid the upper and lowers ones ?! - -STEP 4 = What I want ( drawn in paint.net ) - -So ... Do I something wrong ? ... Is there a trick I haven't found ??? - -Maybe some of you have found the same problem ... and maybe some of them have solve it ??!! - -Thanks for reading. - -Sébastien (FR)
-0 - - -3950047 -sebc26 -1270127456 -
Note : to add vias, I need to disable DRC check, looks like it doesn't like this kind of "useless" tracks ... - -Sebastien. -
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762477&file_id=369090&aid= -369090 -Problem_Kicad.png -Pictures -121858 -image/png -1270127147 -sebc26 - - - - -9353250 -IP -Artifact Created: 82.244.110.178 -1270127147 -sebc26 - - -9353251 -File Added -369090: Problem_Kicad.png -1270127147 -sebc26 - - -9353278 -IP -Comment Added: 82.244.110.178 -1270127456 -sebc26 - - - - - - -http://sourceforge.net/?group_id=145591&atid=762478 -762478 -Patches -Patch Tracking System -All site users -Yes -No -1296000 - - -1209600 -0 -0 -0 - - - - -516022 -Unstable (example) - - - - -761684 -Widget (example) -nobody - - -1084471 -eeschema -nobody - - -1084472 -pcbnew -nobody - - - - -1 -Fixed - - -2 -Invalid - - -3 -Wont Fix - - -4 -Later - - -5 -Remind - - -6 -Works For Me - - -100 -None - - -101 -Duplicate - - -102 -Accepted - - -103 -Out of Date - - -104 -Postponed - - -105 -Rejected - - - - -1 -Open - - -2 -Closed - - -3 -Deleted - - -4 -Pending - - - - -http://sourceforge.net/support/tracker.php?aid=1781977 -1781977 -2 -100 -100 -102 -llamatronique -nobody -kintel -1188125222 -1213545924 -5 -Path & execution fixes for Mac OS -
This patch fixes a number of issues regarding the the MacOS handling of execution, arguments and search paths, and is a bit closer to having the kicad applications behave like a typical mac app. - -The convention is for Application Bundles to be executable from the root of an application folder with all support paths relative to the bundle path. - -- Changed SetBinDir() to return application directory rather than executable location. -- Changed executable paths to be relative to application directory. -- Split file dialog paths to path & filename (workaround for file dialogs which substitute path delimiter with "-") -- Added a (temporary) fix to assume that the help/data paths will be the application directory. - -Build changes : - -- Added __UNIX__ compiler flag. -- Added Debug targets. -- Changed path to wxWidgets source to a single variable. -- Better handling for bundle creation (links no longer required, & app bundlers included in clean and install targets)
-0 - - -2807912 -kintel -1213545924 -
Logged In: YES -user_id=145718 -Originator: NO - -Old patch, was accepted last year sometime.
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=242857&aid= -242857 -mac_fixes_20070826_201.patch -Path & execution fixes for Mac OS -16124 -application/octet-stream -1188125222 -llamatronique - - - - -4967277 -IP -Artifact Created: 121.44.11.126 -1188125222 -llamatronique - - -4967278 -File Added -242857: mac_fixes_20070826_201.patch -1188125223 -llamatronique - - -6137451 -IP -Comment Added: 85.127.109.16 -1213545924 -kintel - - -6137452 -status_id -1 -1213545924 -kintel - - -6137453 -resolution_id -100 -1213545924 -kintel - - -6137454 -close_date -0 -1213545924 -kintel - - - - -http://sourceforge.net/support/tracker.php?aid=1905661 -1905661 -2 -100 -100 -102 -diemer -diemer -plyatov -1204460769 -1204577685 -5 -3d-viewer rotation/panning fix -
Hi, - -the attached patch fixes panning in 3d-viewer. The problem was that after the view had been rotated (by left-mouse dragging), panning didn't work intitively anymore. - -The fix was to simply change the order of how rotation and translation get applied in Pcb3D_GLCanvas::Redraw(). - -Best reagards.
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=268807&aid= -268807 -fix_drawing.patch -Patch against latest svn -1265 -text/x-patch -1204460769 -diemer - - - - -5707161 -IP -Artifact Created: 82.83.204.160 -1204460769 -diemer - - -5707162 -File Added -268807: fix_drawing.patch -1204460770 -diemer - - -5713508 -status_id -1 -1204577684 -plyatov - - -5713509 -close_date -0 -1204577685 -plyatov - - -5778213 -resolution_id -100 -1205875552 -diemer - - -5778214 -assigned_to -100 -1205875552 -diemer - - - - -http://sourceforge.net/support/tracker.php?aid=1919368 -1919368 -2 -1084471 -100 -100 -diemer -diemer -jerryjacobs -1205916506 -1257524383 -5 -XOR Artifacts -
To be done: - - - Implement the remaining GetBoundingBox() functions (or use ifs to fall back to the old xor-Method for missing parts). - - - Replace call(s) to EDA_BaseStruct::GetBoundingBox() by returning a simple empty rect. - -
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=271001&aid= -271001 -eeschema_redraw-3.patch - -5992 -text/x-patch -1205916506 -diemer - - - - -5780267 -IP -Artifact Created: 134.169.117.46 -1205916506 -diemer - - -5780268 -File Added -271001: eeschema_redraw-3.patch -1205916506 -diemer - - -8854543 -status_id -1 -1257524383 -jerryjacobs - - -8854544 -close_date -0 -1257524383 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2526177 -2526177 -1 -100 -100 -100 -cfdev -nobody -nobody -1232543764 -0 -5 -WinEDA_PositionCtrl -
hi, -To filter the numeric char : - -In /kicad/common/wxwineda.cpp - -+ #include <wx/valtext.h> - -//in WinEDA_PositionCtrl::WinEDA_PositionCtrl(...) - - * m_FramePosX = new wxTextCtrl( parent, -1, wxEmptyString, wxDefaultPosition, wxDefaultSize, 0, wxTextValidator(wxFILTER_NUMERIC)); - - *m_FramePosY = new wxTextCtrl( parent, -1, wxEmptyString, wxDefaultPosition, wxDefaultSize, 0, wxTextValidator(wxFILTER_NUMERIC)); - - -For me the char '.' is not valide for the value, maybe make an custom list "wxTextValidator". - -++
-0 - - - - - - -7499128 -IP -Artifact Created: 90.52.22.12 -1232543764 -cfdev - - - - -http://sourceforge.net/support/tracker.php?aid=2805197 -2805197 -1 -100 -100 -100 -hauptmech -nobody -nobody -1244773398 -0 -5 -using wxMSW zlib src fails silently -
Altered CMake so that if it can't find the wxMSW /src/zlib/*.h it fails with a hint of what's wrong. CMakeCache.txt can be subsequently modified if necessary
-0 - - -3675855 -hauptmech -1244839701 -
One of the path changes I incorrectly made while trying to compile snuck into the original patch. Updated patch is correct
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=330787&aid= -330787 -improved_cmake.patch - -1562 -text/x-diff -1244841510 -hauptmech - - - - -8367691 -IP -Artifact Created: 118.90.106.51 -1244773398 -hauptmech - - -8367692 -File Added -330674: kicad_compile.patch -1244773399 -hauptmech - - -8369989 -File Deleted -330674: -1244839602 -hauptmech - - -8369991 -IP -Comment Added: 118.90.106.51 -1244839701 -hauptmech - - -8370048 -File Added -330787: improved_cmake.patch -1244841510 -hauptmech - - - - -http://sourceforge.net/support/tracker.php?aid=2805206 -2805206 -1 -1084472 -100 -100 -hauptmech -nobody -nobody -1244776444 -0 -5 -Configurable epoxy thickness for 3D view -
The config variable "LayerThickness" is used to set the distance between layers in the 3D view. The *.brd file must be edited directly, there is no user interface for this.
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=330676&aid= -330676 -brd_thk.diff -Adds LayerThickness variable for 3D viewer -3258 -application/octet-stream -1244776444 -hauptmech - - - - -8367731 -IP -Artifact Created: 118.90.106.51 -1244776444 -hauptmech - - -8367732 -File Added -330676: brd_thk.diff -1244776445 -hauptmech - - - - -http://sourceforge.net/support/tracker.php?aid=2805221 -2805221 -2 -100 -100 -100 -hauptmech -nobody -jerryjacobs -1244779322 -1257524112 -5 -default name for hotkey files incorrect -
Default name was: "prog..key" (such as "pcbnew..key")
-0 - - -3675410 -hauptmech -1244800521 -
Previous patch file did not cover all cases. Working on a new one.
- - - - - - -8367776 -IP -Artifact Created: 118.90.106.51 -1244779322 -hauptmech - - -8367777 -File Added -330679: hotkey_file.diff -1244779322 -hauptmech - - -8368297 -File Deleted -330679: -1244800495 -hauptmech - - -8368299 -IP -Comment Added: 118.90.106.51 -1244800521 -hauptmech - - -8854532 -status_id -1 -1257524112 -jerryjacobs - - -8854533 -allow_comments -1 -1257524112 -jerryjacobs - - -8854534 -close_date -0 -1257524112 -jerryjacobs - - -8854535 -allow_comments -0 -1257524118 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2805860 -2805860 -2 -100 -516022 -100 -hauptmech -nobody -sf-robot -1244889019 -1258770019 -5 -Last tool used toggle -
Patch creating a command to toggle between the present tool and the last used tool in pcbnew. Adds hotkey hooks for pcbnew add_module and add_tracks.
-0 - - -3799394 -jerryjacobs -1257524052 -
Tried to get it in SVN trunk after hand editing it did not work, could you create a new patch?
- - -3812838 -sf-robot -1258770019 -
This Tracker item was closed automatically by the system. It was -previously set to a Pending status, and the original submitter -did not respond within 14 days (the time period specified by -the administrator of this Tracker).
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=330835&aid= -330835 -ToggleCommand.patch - -17294 -text/x-diff -1244889019 -hauptmech - - - - -8371098 -IP -Artifact Created: 118.90.106.51 -1244889019 -hauptmech - - -8371099 -File Added -330835: ToggleCommand.patch -1244889019 -hauptmech - - -8854319 -status_id -1 -1257520699 -jerryjacobs - - -8854320 -close_date -0 -1257520699 -jerryjacobs - - -8854524 -IP -Comment Added: 84.25.204.235 -1257524052 -jerryjacobs - - -8901593 -IP -Comment Added: -1258770019 -sf-robot - - -8901594 -status_id -4 -1258770019 -sf-robot - - -8901595 -allow_comments -1 -1258770019 -sf-robot - - -8901596 -close_date -1257520699 -1258770019 -sf-robot - - - - -http://sourceforge.net/support/tracker.php?aid=2806042 -2806042 -1 -1084472 -100 -100 -hauptmech -nobody -nobody -1244938036 -0 -5 -Move/drag hotkey grabs nodes/tracks -
When the track tool is active, using the 'move footprint' hotkey will move the selected node; using the 'drag footprint' hotkey will move the selected track.
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=330898&aid= -330898 -move_track_hotkey.patch - -6984 -text/x-diff -1244938960 -hauptmech - - - - -8372250 -IP -Artifact Created: 118.90.106.51 -1244938036 -hauptmech - - -8372251 -File Added -330897: move_track_hotkey.patch -1244938036 -hauptmech - - -8372271 -File Deleted -330897: -1244938920 -hauptmech - - -8372272 -File Added -330898: move_track_hotkey.patch -1244938960 -hauptmech - - - - -http://sourceforge.net/support/tracker.php?aid=2806129 -2806129 -2 -1084472 -516022 -100 -hauptmech -nobody -jerryjacobs -1244972676 -1257520170 -5 -Track clearance dropdown menu -
Adds a history and drop down menu for clearance width next to track width. -Adds a toggle button to show/hide "invisible" text.
-0 - - -3676981 -hauptmech -1245020964 -
Last patch was generated by git because I've accumulated too many changes to sort the changes out by hand. You can either strip the git specific stuff or grab the full patch attached and sort through it by hand. - -The combined patch is against svn 1816. It compiles/runs but I don't know the codebase well enough to guarantee stability.
- - -3799346 -jerryjacobs -1257520162 -
Added revision 1828
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=330921&aid= -330921 -clr_dropdown.diff - -25996 -application/octet-stream -1244972676 -hauptmech - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=330982&aid= -330982 -hauptmech.patch -Patch of all changes against svn 1816 -80439 -text/x-diff -1245020803 -hauptmech - - - - -8372724 -IP -Artifact Created: 118.90.106.51 -1244972676 -hauptmech - - -8372725 -File Added -330921: clr_dropdown.diff -1244972676 -hauptmech - - -8374015 -File Added -330982: hauptmech.patch -1245020803 -hauptmech - - -8374017 -IP -Comment Added: 118.90.106.51 -1245020964 -hauptmech - - -8374018 -category_id -100 -1245020964 -hauptmech - - -8374019 -artifact_group_id -100 -1245020964 -hauptmech - - -8854272 -IP -Comment Added: 84.25.204.235 -1257520162 -jerryjacobs - - -8854273 -status_id -1 -1257520170 -jerryjacobs - - -8854274 -allow_comments -1 -1257520170 -jerryjacobs - - -8854275 -close_date -0 -1257520170 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2807379 -2807379 -2 -1084472 -100 -100 -hauptmech -nobody -jerryjacobs -1245187092 -1257519776 -5 -Netnames on other layers not shown in high-contrast mode -
Netnames on other layers not shown in high-contrast mode. Only netnames from the current layer are shown. Helps readability in dense circuits.
-0 - - -3679192 -jerryjacobs -1245262176 -
Patch approved SVN 1820
- - -3799343 -jerryjacobs -1257519768 -
Patched added
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=331227&aid= -331227 -contrast_netnames.patch -Patch against SVN1819 -1522 -text/x-diff -1245187092 -hauptmech - - - - -8381425 -IP -Artifact Created: 118.90.106.51 -1245187092 -hauptmech - - -8381426 -File Added -331227: contrast_netnames.patch -1245187092 -hauptmech - - -8384410 -IP -Comment Added: 84.25.137.47 -1245262176 -jerryjacobs - - -8854261 -IP -Comment Added: 84.25.204.235 -1257519768 -jerryjacobs - - -8854264 -status_id -1 -1257519776 -jerryjacobs - - -8854265 -allow_comments -1 -1257519776 -jerryjacobs - - -8854266 -close_date -0 -1257519776 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2809677 -2809677 -1 -1084472 -100 -100 -hauptmech -nobody -nobody -1245557608 -0 -5 -Hotkey to show/hide clearance -
Hotkey switches between showing all clearances, and the previous state (ie show with new track/via, etc)
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=331758&aid= -331758 -clearance_display.patch - -2142 -text/x-diff -1245557608 -hauptmech - - - - -8393997 -IP -Artifact Created: 118.90.106.51 -1245557608 -hauptmech - - -8393998 -File Added -331758: clearance_display.patch -1245557608 -hauptmech - - - - -http://sourceforge.net/support/tracker.php?aid=2809678 -2809678 -1 -1084472 -100 -100 -hauptmech -nobody -nobody -1245557721 -0 -5 -Read saved track clearances from config file -
A bit of code to read track clearance history that was saved in the config file. (should have been included in a previous patch)
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=331759&aid= -331759 -clearance_width_save.patch - -585 -text/x-diff -1245557721 -hauptmech - - - - -8394000 -IP -Artifact Created: 118.90.106.51 -1245557721 -hauptmech - - -8394001 -File Added -331759: clearance_width_save.patch -1245557721 -hauptmech - - - - -http://sourceforge.net/support/tracker.php?aid=2851908 -2851908 -1 -1084472 -100 -100 -bjerre -nobody -nobody -1252102580 -0 -5 -Copper zone option to inhibit combines with other zones -
Patch to let the user explicitly allow or disallow combining of the current zone with other zones, in the fill zone options menu. The need came from a ground plane requiring two different clearances, one for a microprocessor part and one for a rf frontend part. (Other users might like the same feature for hosting high and low voltage circuits on the same plane ?). In both cases it is akward that the zones gets combined. -Please notice that the attached patch is only a proof of concept, there is no guarantee that it doesn't bite. -
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=341816&aid= -341816 -ZoneMergeOption.patch -Made against svn rev 1949 -15666 -application/octet-stream -1252102580 -bjerre - - - - -8638205 -IP -Artifact Created: 62.107.125.243 -1252102580 -bjerre - - -8638206 -File Added -341816: ZoneMergeOption.patch -1252102581 -bjerre - - - - -http://sourceforge.net/support/tracker.php?aid=2976667 -2976667 -1 -1084471 -100 -100 -nobody -nobody -nobody -1269547292 -0 -5 -Patch to fix PostScript plotting of user-specified sheet siz -
This patch generates the correct %%DocumentMedia tag when generating PostScript plots of user specified sheet sizes. Works against SVN R2347.
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762478&file_id=368217&aid= -368217 -common_plotPS_functions.patch -This patch applies to common/common_plotPS_functions.cpp -707 -text/x-patch -1269547293 -nobody - - - - - - - - -http://sourceforge.net/?group_id=145591&atid=762479 -762479 -Feature Requests -Feature Request Tracking System -All site users -Yes -No -3888000 - - -1209600 -0 -0 -0 - - - - -516023 -Next Release (example) - - - - -761685 -Interface Improvements (example) -nobody - - -1026579 -PCBNEW -nobody - - -1026580 -EESCHEMA -nobody - - -1026581 -PROJECT MGR -nobody - - -1026582 -CVPCB -nobody - - -1026583 -GERBVIEW -nobody - - - - - - -1 -Open - - -2 -Closed - - -3 -Deleted - - -4 -Pending - - - - -http://sourceforge.net/support/tracker.php?aid=1782201 -1782201 -1 -761685 -516023 -tonymux -nobody -nobody -1188175260 -0 -5 -Components registered in database -
-Just wanted to suggest an implementation of a solution whereby each component (reference) would be uniquely associated to information stored on a database (link postgres) including: - - Geometry - - Tolerance - - Other generic info that could be edited (manufacturer, distributer, ref. price, etc) - - Possibility to embed data sheet information into the component info as well as note files - - Possibility to associate with each sheet a text information that could be processed by DoxyGen
-0 - - -2492058 -dickelbeck -1189608309 -
Logged In: YES -user_id=1222857 -Originator: NO - -This posting leaves me asking more questions than it answers. - -Which program, eescema or pcbnew? - -Why is the database desireable? This sounds like a solution without a problem. Please describe the problem first. Databases are not easily moved from one machine to another, so it comes with a bag of disadvantages too. - -Unless you want a globally accessible database, one that every kicad user shares over the internet. - - -
- - - - - - -4968638 -IP -Artifact Created: 85.139.172.13 -1188175260 -tonymux - - -5035371 -IP -Comment Added: 67.64.64.34 -1189608309 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=1783527 -1783527 -1 -761685 -100 -nwimpney -nobody -nobody -1188320339 -0 -5 -Keeping dragged parts connected. -
When re-arranging parts on a crowded layout, it would be useful to have an option to have the connections remain. Even if it's not perfect, it would often be preferable to having to delete and re-connect all of the traces individually. The schematic and board editor could both benefit from this behaviour.
-0 - - -2490077 -nobody -1189452680 -
Logged In: NO - -Or (for now) add an option to automaticaly delete tracks (in PCBnew) and wires (in EEschema) that was connected to the dragged part.
- - -2641671 -alanjshea -1200940917 -
Logged In: YES -user_id=803932 -Originator: NO - -Automatically deleting tracks for a moved part is a bad idea, as you have to recreate the connections and that could be more time-consuming than doing it yourself. At least if they are still hanging there you can more readily re-connect the tracks.
- - -2641673 -alanjshea -1200941039 -
Logged In: YES -user_id=803932 -Originator: NO - -This feature is one of the most important for my application. I can't contribute code, but what else could I do to encourage this?
- - - - - - -4976644 -IP -Artifact Created: 204.174.223.110 -1188320339 -nwimpney - - -5027345 -IP -Comment Added: 89.102.22.118 -1189452680 -nobody - - -5539068 -IP -Comment Added: 207.32.229.26 -1200940918 -alanjshea - - -5539074 -IP -Comment Added: 207.32.229.26 -1200941039 -alanjshea - - - - -http://sourceforge.net/support/tracker.php?aid=1785173 -1785173 -2 -100 -100 -theamigo -nobody -stambaughw -1188503787 -1270750482 -5 -Option to plot without border -
I'd like a checkbox in EESchema's Plot dialog (specifically SVG) that would prevent it from plotting the page border and block that has Title, Size, Rev, etc. - -I use KiCAD for drawing schematics for my electronics class. I plot to SVG and import into OpenOffice. But at the moment, I have to manually remove all of that every time I import a drawing. Adding this feature would help make real-time note taking easier.
-0 - - -3957168 -stambaughw -1270750482 -
Check box to disable plotting reference frame in SVG, PS, and DXF plot dialogs as of release 20100314.
- - - - - - -4986395 -IP -Artifact Created: 129.188.69.145 -1188503787 -theamigo - - -9382243 -IP -Comment Added: 162.83.115.135 -1270750482 -stambaughw - - -9382244 -status_id -1 -1270750482 -stambaughw - - -9382245 -allow_comments -1 -1270750482 -stambaughw - - -9382246 -close_date -0 -1270750482 -stambaughw - - - - -http://sourceforge.net/support/tracker.php?aid=1789042 -1789042 -1 -761685 -516023 -nobody -nobody -nobody -1189035834 -0 -5 -Associate eeschema parts with pcbnew footprints -
Currently, to design a PCB, the user has to design the schematic, then run cv2pcb and tell which footprint to use for every single component, and then run pcbnew and use all the footprints. Changing the footprint of a device after starting on the PCB layout means going back to cv2pcb and editing that entry, then re-importing the cv2pcb output in pcbnew. - -Cv2pcb should simply be eliminated altogether, and eeschema and pcbnew should work more closely together. - -Each component in eeschema's library should have the ability to have one or more footprints, from pcbnew, associated with it. This way, if the user has a particular diode, he can just place it on his schematic, and when he exports to pcbnew, the DO-31 (for example) footprint will automatically show up; he should not have to choose that footprint, except for when he first creates the part in his library. Parts in the main library (included with Kicad) would already have default associations set up. - -It's also useful to allow more than one possible footprint. For instance, some components have thru-hole and SMT versions. Others have multiple orientations (horizontal vs. vertical). After importing a design from eeschema, the user, while laying out the PCB, should be able to right-click on a component, choose Properties or similar, and select any alternate footprint that might be available. The new footprint should immediately replace the old one on the screen. - -Professional CAD programs like PADS generally work like this. -
-0 - - -2485832 -plyatov -1189061775 -
Logged In: YES -user_id=1325376 -Originator: NO - -Possibility to change or select alternate footprint, must be implemented in schematic editor - not in PCB editor! -Because, when user create bill of materials, it is wery important to have the information about footprint in BOM. -In Altium "Protel", user can change the properties of component by double click on it in schematic editor.
- - - - - - -5009935 -IP -Artifact Created: 192.88.158.212 -1189035834 -nobody - - -5010712 -IP -Comment Added: 81.176.8.172 -1189061775 -plyatov - - - - -http://sourceforge.net/support/tracker.php?aid=1789164 -1789164 -1 -100 -100 -plyatov -nobody -nobody -1189061309 -0 -5 -internal planes connection -
"pcbnew" has a problem connecting to internal planes. -I selected the proper layers for the via's and then selected the proper working layer and created/filled a zone. -It looks like there are connections, but it still shows a ratsnest to the ground and power connections and I have unconnected nets.
-0 - - -2492067 -dickelbeck -1189609010 -
Logged In: YES -user_id=1222857 -Originator: NO - -From all the discussion on the mailing lists, I believe now that zones are not "electrically aware" as far as DRC is concerned. What I understand is that you have to put tracks down for all connections, then fill over them as the last step using one or more zones. So maybe you want zones to be electrically aware? What are they doing in geda regarding zones? Maybe we can borrow some ideas and code from them.
- - - - - - -5010698 -IP -Artifact Created: 81.176.8.172 -1189061309 -plyatov - - -5035392 -IP -Comment Added: 67.64.64.34 -1189609010 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=1790488 -1790488 -1 -761685 -516023 -nobody -nobody -nobody -1189210271 -0 -5 -Pins-swap and Gate-swap -
Please add pins-swap and gate-swap functions. For instance, on a 7400 quad NAND gate chip, there are 4 separate gates, all identical. It may ease routing to use gate C instead of gate A, but that's not how the schematic is drawn. pcbnew already has the concept of separate gates, but doesn't have a simple way of swapping them; you have to change the schematic and re-import it to pcbnew. This should be a one-click operation. -
-0 - - - - - - -5018640 -IP -Artifact Created: 192.88.158.212 -1189210271 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1794774 -1794774 -1 -761685 -100 -nobody -nobody -nobody -1189781352 -0 -5 -Netlist editor enhancement -
In addition to assigning the footprint, it -would be nice to edit the module name and -maybe even the ref designator.
-0 - - - - - - -5044158 -IP -Artifact Created: 199.3.246.231 -1189781352 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1794790 -1794790 -1 -761685 -100 -bennett78 -nobody -nobody -1189782392 -0 -5 -contrib: PCB123 to Kicad netlist translator -
Included is a utility I call pcb2kicad, a -PCB123 netlist to kicad translator. I -could not find a good home for this code -and perhaps this might inspire other -translators. - -I like the KiCad netlist format in that -for a ref designator includes: -footprint, ref, module name, value? and schematic symbol. - timestamp SM1208 C1 capacitor 10uf {Lib=C} - -KiCad is "si bon" to rival the >$5000US packages -out there.
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=245679&aid= -245679 -pcb2kicad.tgz -source - pcb123 2 kicad netlist converter -4694 -application/x-gzip -1189782392 -bennett78 - - - - -5044208 -IP -Artifact Created: 199.3.246.231 -1189782392 -bennett78 - - -5044209 -File Added -245679: pcb2kicad.tgz -1189782392 -bennett78 - - - - -http://sourceforge.net/support/tracker.php?aid=1798404 -1798404 -1 -761685 -100 -bennett78 -nobody -nobody -1190236031 -0 -5 -EDIF (Orcad) to KiCad Netlist -
edif.y - Revision x - Frank Bennett - Wed Sep 19 14:19:42 MDT 2 - Modified to output a KiCad Netlist - 1) find/store InstanceNameDef. ViewRef - i.e. CMP31.cap - 2) find/store Nets: NetNameDef, InstRef, PortRef - 3) sort Nets by InstRef - - Files: - makefile - Unix style makefile, runs Bison & runs gcc - edif.y - edif BNF Grammer, yylex, & main.c - PS10 - OrCad schematic in EDIF format - PS10.EDF - Original Ps10 - PS10.pdf - PS10 schematic - PS10.net - KiCad netlist output see below - batest.1 - edif test file - batest.2 - edif test file - hptest - edif test file - hptest.net - KiCad netlist output see below - bugin.net - KiCad bug, pin name truncated - bugout.net - KiCad bug, pin name truncated - - Tested under Linux and cygwin - - Install: - make - edif < PS10.EDF > PS10.net - or edif < hptest >hptest.net - - Edif Notes: - o hptest is more readable for parser debugging. This begs for - EdifBeautifier for the OrCad file - o EDIF schematic file contain - - symbol ports names, Direction, Designator - - symbol graphics, justification, orientation, origin - - sheet ports, instances, instance location, symbol reference - - sheet Netlist, wire paths - Doesn't seem to include footprint references - - TODO: - o find/output schematic drawing, symbol graphics -
-0 - - -2502331 -dickelbeck -1190517318 -
Logged In: YES -user_id=1222857 -Originator: NO - -Very promising so far.
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=246367&aid= -246367 -edif.zip -edif.y and examples -124408 -application/x-zip-compressed -1190236031 -bennett78 - - - - -5064005 -IP -Artifact Created: 199.3.246.231 -1190236031 -bennett78 - - -5064006 -File Added -246367: edif.zip -1190236033 -bennett78 - - -5077398 -IP -Comment Added: 67.64.64.34 -1190517318 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=1800554 -1800554 -1 -761685 -100 -nobody -nobody -nobody -1190546231 -0 -5 -Sugested Project Managment Enhancements -
Project window to have ability to edit the project definitions to modify directories and file names etc. This would be realy useful to allow the project launch window to be updated if the underlying files/directorires etc had been moved/modified/renamed. - -andy@kirbyand.co.uk
-0 - - - - - - -5078120 -IP -Artifact Created: 78.32.7.177 -1190546231 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1800556 -1800556 -1 -761685 -100 -nobody -nobody -nobody -1190546545 -0 -5 -Sugested Project Managment Enhancements 2 -
Project window to have the ability to delete a project either as a reference to the project directories and files or both ie delete the whole thing files as well or delete the project from the list. (pref from right clisk on project name in tree) - -andy@kirbyand.co.uk
-0 - - - - - - -5078130 -IP -Artifact Created: 78.32.7.177 -1190546545 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1800557 -1800557 -1 -761685 -100 -nobody -nobody -nobody -1190546615 -0 -5 -Sugested Project Managment Enhancements 3 -
Project window to have the ability to restore an archived project creating if not already exisiting the relevant files and directories. - -andy@kirbyand.co.uk -
-0 - - - - - - -5078133 -IP -Artifact Created: 78.32.7.177 -1190546615 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1800560 -1800560 -1 -761685 -100 -nobody -nobody -nobody -1190546850 -0 -5 -Schematic capture Symbol Managment. -
Wouldn't it be cool to have a set of capabilities/menus as part of the symbol management that linked to an online cvs/svn etc like repository to allow symbol retrieval, use, modification and submission. - -Libraries could optionally be downloaded then for standalone or the shared online library used to ensure it was always up to date and everybody's contributions to the symbols libraries would be available to all and version controlled. - -andy@kirbyand.co.uk
-0 - - -2507579 -bennett78 -1190927718 -
Logged In: YES -user_id=464167 -Originator: NO - -OR just add cvpcb footprint viewer/assignment per Ref designator and -to the symbol cache to eeSchema. Multiple instances seldon use a -different footprint per board design. - -How well does backannotate from PCBnew -> eeSchema work? for gate swap, -package part swap, netlist compare, etc. - -cvpcb would be only needed for either review or if a netlist exists -without a schematic. - -But then a standalone sym/footprint graphical Library manager would also be -useful. It's cool the KiCad design allows for symbol aliases and multiple -footprints for the same symbol. This improved design productivity.
- - - - - - -5078142 -IP -Artifact Created: 78.32.7.177 -1190546850 -nobody - - -5097894 -IP -Comment Added: 199.3.246.231 -1190927718 -bennett78 - - - - -http://sourceforge.net/support/tracker.php?aid=1803862 -1803862 -1 -761685 -100 -bennett78 -nobody -nobody -1190928158 -0 -5 -PCBnew - Rats nest enhancement -
While manually routing traces, it would be nice -to include the new partial trace endpoint to the -rats nest display. This would help the user -visually to navigate toward the next target pad. - -This is a nice feature currently in PCB123. - -Thanks for the new, improved "selection" user interface.
-0 - - - - - - -5097924 -IP -Artifact Created: 199.3.246.231 -1190928158 -bennett78 - - - - -http://sourceforge.net/support/tracker.php?aid=1808261 -1808261 -1 -1026579 -100 -dickelbeck -nobody -nobody -1191609042 -0 -5 -Change layer of existing track -
Edit the layer that a track resides on, without having to re-create the track
-0 - - - - - - -5126180 -IP -Artifact Created: 67.64.64.34 -1191609042 -dickelbeck - - - - -http://sourceforge.net/support/tracker.php?aid=1815423 -1815423 -2 -1026580 -100 -nobody -nobody -bennett78 -1192662340 -1210343389 -5 -More efficient footprint entry -
We need a quicker way to go over a schematic and set the footprints. Right click -> Edit Component -> Edit -> Fields tab -> Footprint radiobutton is too much work. - -It would be a major step forward for EEscheema to remove this limitation. While footprints can be entered in the library editor and via cvpcb, the schematic editor is often the place where component decisions are made during the design process. - -We often use Eeschema for netlist generation without Kicad PCB and enter custom footprint names not available in Kicad libraries.
-0 - - -2541649 -ckgrier2 -1193848149 -
Logged In: YES -user_id=1921682 -Originator: NO - -This could be added to the existing hot-key list in hotkeys.cpp. Check out the forum message here: -http://tech.groups.yahoo.com/group/kicad-devel/message/480 - -Would that suffice for what you need? I usually pick a footprint for a part and then copy it wherever it is needed in the schematic. All the Fields get copied too. This makes sense if you change footprints depending on the board.
- - -2757185 -bennett78 -1209510191 -
Logged In: YES -user_id=464167 -Originator: NO - -To close the design loop in EEschema add a BackAnnotate button: -that reads the cvpcb "stuff file" and updates the components by reference designator -with the footprint info. A placeholder(F2) already exists to hold the footprint in -the schematics file (database). - -The process for keeping the schematic up to date would be: -eeschema: -o enter starting schematic -o output initial netlist -cvpcb: -o read initial netlist -o add footprint info -o output modified netlist & stuff list (with footprint info) -pcbnew: -o the modified netlist could be used to start initial placement -o save working pcb -eeschema: -o backannotate footprint info from stuff list -o modify schematic if desired, maybe add a few footprints -o output updated netlist (containing footprints) -pcbnew: -o import updated netlist with new components, optionally removed unused parts no longer in netlist -o place new components -
- - -2767442 -bennett78 -1210343389 -
Logged In: YES -user_id=464167 -Originator: NO - -Feature added to EEschema - svn version r1064
- - - - - - -5171579 -IP -Artifact Created: 202.63.59.69 -1192662340 -nobody - - -5220996 -IP -Comment Added: 65.83.202.55 -1193848149 -ckgrier2 - - -5960743 -IP -Comment Added: 208.69.212.143 -1209510191 -bennett78 - - -5992192 -IP -Comment Added: 208.69.212.143 -1210343389 -bennett78 - - -5992193 -status_id -1 -1210343389 -bennett78 - - -5992194 -close_date -0 -1210343389 -bennett78 - - - - -http://sourceforge.net/support/tracker.php?aid=1818392 -1818392 -1 -761685 -100 -brummig -nobody -nobody -1193129157 -0 -5 -Metric Grid Options -
If one switches pcbnew or eeschema to metric, the grid size options are equivalent in size to user-friendly imperial options (such as 25 thousandths of an inch). The result is the list of grid sizes in metric is user-unfriendly (25 thousandths of an inch becomes 0.635mm, for example). This is particularly problematic in pcbnew, as this works with real engineering components. It should be possible to have user-friendly metric grid options, such as 1mm, 0.5mm, 0.1mm. Metric is the measurement system of choice for engineers in all but one advanced country, so kicad needs to make proper use of it. - -If one makes this step, clearly a simple imperial/metric switch is inadequate, as sometimes one might want to switch between user-friendly imperial, and user-friendly metric, and sometimes one will want to keep the grid size but just have pcbnew/eeschema display it in alternative units. There are many ways to solve that, but perhaps the simplest is to replace the current two buttons with four - one pair for switching units ('metric units/imperial units'), and one for switching grids ('metric grids/imperial grids'). Alternatively one of the two existing buttons could be 'metric units/imperial units', and the other could be 'metric grids/imperial grids'.
-0 - - -2610312 -nobody -1198406202 -
Logged In: NO - -There is more and more components with "metric" dimensions, like connectors with 2,5 mm pitch and some SMT IC. It's very useful to have a metric grid. -And in the schematic there is simply no reason to keep that stone-age units.
- - - - - - -5189038 -IP -Artifact Created: 83.216.148.11 -1193129157 -brummig - - -5430242 -IP -Comment Added: 151.47.56.117 -1198406203 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1832573 -1832573 -1 -761685 -100 -nobody -nobody -nobody -1195143381 -0 -5 -Browsing through the files like Eagle -
It would be really good that kicad would change its main interface more like eagle, where you can browse though the projects and libraries and edit them at will. -And another feature that should be added and that is being compatible with eagle files especially to eagle's libary files, or at least being able to convert them.
-0 - - - - - - -5278511 -IP -Artifact Created: 84.151.52.48 -1195143381 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1841163 -1841163 -1 -1026579 -100 -demarchidaniele -nobody -nobody -1196361202 -0 -5 -Import/export of DXF drawings -
Import DXF: -It will be nice to import the DXF drawings of the chassis that will contain the PCB. - -Export DXF: -Some holes of PCB supports/potentiometers/etc may be exported to the mechanical CAD system.
-0 - - -3714238 -nobody -1249034432 -
Yes, I would be a great, great feature I never found in linux (and perhaps windows ?) EDA projects ... I often would use it if it would be implemented and make me save a lot of time ... - -Phil
- - - - - - -5331238 -IP -Artifact Created: 87.2.23.137 -1196361202 -demarchidaniele - - -8526025 -IP -Comment Added: 82.251.254.159 -1249034432 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1845336 -1845336 -1 -1026580 -100 -nobody -nobody -nobody -1196925778 -0 -5 -switch to compounents -
Make possible swith to properties of other component from properties of current component. Combo list. For make easily edit properties a lot of components. Checkbox for change focus in viewly area to editing component.
-0 - - - - - - -5356110 -IP -Artifact Created: 217.150.32.243 -1196925778 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1845337 -1845337 -1 -1026580 -100 -nobody -nobody -nobody -1196925844 -0 -5 -Exec external programm/scripts -
Exec any external programm/script for other works with exported BOM list. - -This need for more simple make BOM list in HTML, XML, PDF format, for automatic calculation of budget, automatic make order in the online store and other.
-0 - - - - - - -5356113 -IP -Artifact Created: 217.150.32.243 -1196925844 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1857566 -1857566 -1 -100 -100 -scls19fr -nobody -nobody -1198508439 -0 -5 -Simulation in Kicad -
Hello, - -first thanks for Kicad. -I'm (or I was) a PSpice 9.2 user (rather old !!). -I like Kicad but unfortunately there is no easy graphical user interface for simulation. -I think you should support spice [ng-spice] or gnucap simulation with a user friendly interface (like PSpice/OrCad). - -Moreover, about simulation, one feature is very usefull for teaching digital electronic (gate, flip-flop, ...) ; this is pseudo-real time simulation... some software support this like Proteus. I really think that Kicad should also add this killer-feature. I know that it's a hard work to do... - -About simulation... maybe Kicad should also support "applications" like in DigSim -http://patrick.furon.free.fr/_elecnumerique/indexDigSim.html -so it could be possible so see both the electronic and the system that is connect to the electronic board -So it will be like the interaction between grafcet and the system with IRAI Automgen and IRIS 2D or IRIS 3D objects - - -Thanks again. - -Regards
-0 - - -2613264 -lab_tdp -1198785125 -
Logged In: YES -user_id=1965738 -Originator: NO - -Kicad is a great work but it would be complete with simulation. The best could be mixed-signal, analog AND digital in the same circuit.
- - -2615277 -scls19fr -1198946251 -
Logged In: YES -user_id=996465 -Originator: YES - -I see on LinuxFR ( http://linuxfr.org/2007/12/24/23498.html see comments ) that Qucs will be integrated with Kicad (or Kicad will be integrated into Qucs). This is a very good idea. - -I would like to add that simulating microcontrollers (like in Proteus VSM or VMLAB for ATMEL AVR) will be very usefull. You can send the .hex file (that you get after compiling a C source code or an ASM code) to the simulated microcontroller and you start the real-time simulation. You can see blinking leds around your microcontroller, you can also use the RS232 terminal of your computer to send data to the uC, etc... - -see -about Proteus VSM http://www.labcenter.co.uk/products/vsm_overview.htm -about VMLAB http://www.amctools.com/vmlab.htm
- - -2615282 -scls19fr -1198946781 -
Logged In: YES -user_id=996465 -Originator: YES - -See also about Qucs -http://sourceforge.net/tracker/index.php?func=detail&aid=1860457&group_id=90337&atid=593245 -
- - -2879703 -licho1983 -1218837252 -
Logged In: YES -user_id=2063229 -Originator: NO - -Estamos con muchos deseos de ver integrado un simulador en kicad para agilizar la depuracion de circuitos. Desde ya, gracias por el excelente programa que nos brindan.
- - - - - - -5433833 -IP -Artifact Created: 86.210.181.100 -1198508439 -scls19fr - - -5442404 -IP -Comment Added: 151.47.56.117 -1198785125 -lab_tdp - - -5450403 -IP -Comment Added: 90.50.27.237 -1198946251 -scls19fr - - -5450423 -IP -Comment Added: 90.50.27.237 -1198946782 -scls19fr - - -6371744 -IP -Comment Added: 200.16.16.13 -1218837252 -licho1983 - - - - -http://sourceforge.net/support/tracker.php?aid=1873088 -1873088 -1 -1026579 -100 -nobody -nobody -nobody -1200506218 -0 -5 -Metric coordinates inaccuracy. -
When using very little dimensions using metric units, there are inaccuracies in the value stored in pcbnew. - -For example, 0.5 mm is stored as 0.5004mm which is slightly wrong. I guess this problem comes from the fact that kicad stores the measurement values using 1/10000th of inch, but I think this measurement mechanism is obsolete and should be improved. - -Regards,
-0 - - -2635122 -linuxcart -1200506486 -
Logged In: YES -user_id=1667631 -Originator: NO - -Sorry, I'm the author of this, I think this is more a bug than a feature request. - -Would anyone be so kind to state so and point me as the author? - -Thanks.
- - -2699123 -nobody -1204849497 -
Logged In: NO - -Who cares? It's out by 4um, which is about the wavelength of IR light. This is a non-issue and should be deleted.
- - - - - - -5519596 -IP -Artifact Created: 87.218.11.210 -1200506218 -nobody - - -5519610 -IP -Comment Added: 87.218.11.210 -1200506486 -linuxcart - - -5728933 -IP -Comment Added: 84.92.181.41 -1204849497 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1873094 -1873094 -1 -1026579 -100 -linuxcart -nobody -nobody -1200506794 -0 -5 -ratsnets coloring/visibility. -
I would like to see some important ratsnest in a different colour or even being able to not showing them when you have ratsnest drawing enabled. - -I guess the Miscellaneous->nets list.. would be useful for it. You could add a new column that specify the visibility and/or colour and draw them in the pcb view accordingly. - -Thanks.
-0 - - -2645109 -nobody -1201193530 -
Logged In: NO - -Yes, for me it's a big enhancement, too!!! -
- - - - - - -5519641 -IP -Artifact Created: 87.218.11.210 -1200506795 -linuxcart - - -5551435 -IP -Comment Added: 151.57.43.144 -1201193530 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1874673 -1874673 -1 -100 -100 -linuxcart -nobody -nobody -1200665157 -0 -5 -Automatic opening of gerber when invoking gerbview -
Once you open a project you can press the "schematic tool" or the "pcb editor" and the design you are working on is automatically opened. - -I would like gerber viewer worked same way. Currently if you press the gerbview button you will have no gerber shown. It would be great that rather than this, and if the gerbers are already generated, gerbview opened all of the upon invocation. - -Thanks.
-0 - - - - - - -5528606 -IP -Artifact Created: 87.218.11.210 -1200665157 -linuxcart - - - - -http://sourceforge.net/support/tracker.php?aid=1875717 -1875717 -1 -100 -100 -nobody -nobody -nobody -1200827238 -0 -5 -3D view export for case construction -
It would be nice to have an option to export the 3D view to dxf, 3ds, vrml or somthing different. This is for having a dataset for case construction. - -Br, -Oliver
-0 - - -2682051 -nobody -1203506407 -
Logged In: NO - -I second that notion. For desktop prototyping, having access to a 3D model cuts out the round-about conversions needed to get board data into a quickly millable format.
- - -3608066 -nobody -1239281614 -
I also vote for this feature. A simple export would work for most tasks. An import of case-models for dimensional constraints would even be better :)
- - - - - - -5533896 -IP -Artifact Created: 77.186.12.144 -1200827238 -nobody - - -5661347 -IP -Comment Added: 195.173.118.233 -1203506408 -nobody - - -8119210 -IP -Comment Added: 195.13.40.237 -1239281614 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1875718 -1875718 -1 -100 -100 -nobody -nobody -nobody -1200827508 -0 -5 -preview windows in part selection -
I am missing preview windows for symbol and module selection. - -Br, -Oliver
-0 - - - - - - -5533900 -IP -Artifact Created: 77.186.12.144 -1200827508 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1875722 -1875722 -1 -100 -100 -nobody -nobody -nobody -1200828039 -0 -5 -Instant global labels -
For large schematics with parts with many pins (controllers, etc.) it is not easy to work with global labels. Defining and connecting all of them on the root sheet results in a huge ratsnest on it. - -I think it was under PADS where i worked with a different type. There a global label was instantly global and usable on other sheets. - -Br, -Oliver
-0 - - - - - - -5533910 -IP -Artifact Created: 77.186.12.144 -1200828039 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1875723 -1875723 -1 -100 -100 -nobody -nobody -nobody -1200828208 -0 -5 -Block rotation -
I think block rotation under eeschema and pcbnew will be useful. - -Br, -Oliver
-0 - - - - - - -5533913 -IP -Artifact Created: 77.186.12.144 -1200828208 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1875724 -1875724 -1 -1026582 -100 -nobody -nobody -nobody -1200828458 -0 -5 -simple board wizard -
I think it is useful to have some help for simple boards like euro cards to have a fast setup. To create the outlines only by editing width and heights of the board. - -Br, -Oliver
-0 - - - - - - -5533915 -IP -Artifact Created: 77.186.12.144 -1200828458 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1877170 -1877170 -1 -1026579 -100 -nobody -nobody -nobody -1200999509 -0 -5 -Undo/Redo -
undo/redo method using save/load commands. Simple boards are 100Kb, complex are 2Mb*. Prerequisition is Ctrl-Z/Y hotkeys mapping to undoredo_save(), undoredoload() functions. (PLEASE add them!). - -Advantages: simplicity, infinite history, history AFTER save command** -Disadvantage: soiling hdd space* - -*50 Level undo buffer will be 10-100Mb w/o compression (compression results in 1:8-1:100 ratio for structured files like this, 1:100 for solid/tar) - -** = you could save and close a project (turn off a computer). Next week open a project and press Ctrl-Z to undo last week actions. -
-0 - - - - - - -5541390 -IP -Artifact Created: 217.26.177.9 -1200999509 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1877281 -1877281 -3 -1026579 -100 -nobody -nobody -plyatov -1201009549 -1201011059 -5 -Undo/Redo -
undo/redo method using save/load commands. Simple boards are 100Kb, complex are 2Mb*. Prerequisition is Ctrl-Z/Y hotkeys mapping to undoredo_save(), undoredoload() functions. (PLEASE add them!). - -Advantages: simplicity, infinite history, history AFTER save command** -Disadvantage: soiling hdd space* - -*50 Level undo buffer will be 10-100Mb w/o compression (compression results in 1:8-1:100 ratio for structured files like this, 1:100 for solid/tar) - -** = you could save and close a project (turn off a computer). Next week open a project and press Ctrl-Z to undo last week actions. -
-0 - - -2642465 -linuxcart -1201010718 -
Logged In: YES -user_id=1667631 -Originator: NO - -You already reported this, please report requests just once. - -Thanks.
- - - - - - -5541847 -IP -Artifact Created: 217.26.177.9 -1201009549 -nobody - - -5541915 -IP -Comment Added: 87.218.11.210 -1201010718 -linuxcart - - -5541927 -status_id -1 -1201011059 -plyatov - - -5541928 -close_date -0 -1201011059 -plyatov - - - - -http://sourceforge.net/support/tracker.php?aid=1880640 -1880640 -1 -1026580 -100 -damunix -nobody -nobody -1201432791 -0 -5 -Text Editor -
Minor request : -I think it would be interesting to have the choise to change the text color in EEschema, and to have a style like a notepad (with a background color). I think that because I put lots of notes on my schematics, and I would like to put some "Warnings".
-0 - - - - - - -5559600 -IP -Artifact Created: 82.245.194.55 -1201432791 -damunix - - - - -http://sourceforge.net/support/tracker.php?aid=1880645 -1880645 -1 -1026579 -100 -damunix -nobody -nobody -1201433270 -0 -5 -Teardrop -
It could be interesting to have a Teardrop functionnality when connecting track to pads in pcbnew, because of the personnal soldering.
-0 - - -2912501 -m_beischer -1220810192 -
Logged In: YES -user_id=2207628 -Originator: NO - -Just adding a picture of what tear drops look like in another application. Look at the second picture at: -http://beischer.com/opencad/fillzone.htm
- - - - - - -5559628 -IP -Artifact Created: 82.245.194.55 -1201433270 -damunix - - -6483947 -IP -Comment Added: 83.227.224.244 -1220810192 -m_beischer - - - - -http://sourceforge.net/support/tracker.php?aid=1884643 -1884643 -1 -100 -100 -terrybarnaby -nobody -nobody -1201883351 -0 -5 -Object selections -
Ability to select one or more items in a standard way -(CTRL + Button1 + mouse click and drag etc) and then -be able to perform general operations on the whole selection such as move and rotate. -Currently there is a special block move on an area -only.
-0 - - - - - - -5581568 -IP -Artifact Created: 82.152.34.172 -1201883352 -terrybarnaby - - - - -http://sourceforge.net/support/tracker.php?aid=1884644 -1884644 -1 -100 -100 -terrybarnaby -nobody -nobody -1201883399 -0 -5 -Zoom/Pan -
Zoom/Pan in smaller steps especially with mouse wheel in -eeschema and pcbnew.
-0 - - - - - - -5581578 -IP -Artifact Created: 82.152.34.172 -1201883400 -terrybarnaby - - - - -http://sourceforge.net/support/tracker.php?aid=1884649 -1884649 -1 -100 -100 -terrybarnaby -nobody -nobody -1201883584 -0 -5 -More organised placement of main function buttons -
It would be better to have a more organised placement of main function buttons in order of work -For example in eeschema group the following buttons in order "annotate, Check, Netlist, Cvpcb, Pcbnew". -This would make it more obvious for new users as to the stages required.
-0 - - - - - - -5581594 -IP -Artifact Created: 82.152.34.172 -1201883584 -terrybarnaby - - - - -http://sourceforge.net/support/tracker.php?aid=1884651 -1884651 -1 -1026580 -100 -terrybarnaby -nobody -nobody -1201883666 -0 -5 -Rubberband wires when components are moved. -
It would be good to rubber band or redraw the wires when a component or block of components is moved. Gschem does this.
-0 - - -2757798 -gouskov -1209579846 -
Logged In: YES -user_id=2076224 -Originator: NO - -I think that, more common, the integrity of conections must be preserved when a component or -block of components is moved. -
- - -2934699 -ckgrier2 -1222224653 -
Already in EEschema and PCBnew. Use the Control key when dragging symbols or the G key to drag modules.
- - - - - - -5581598 -IP -Artifact Created: 82.152.34.172 -1201883666 -terrybarnaby - - -5962741 -IP -Comment Added: 79.98.8.3 -1209579846 -gouskov - - -6557335 -IP -Comment Added: 68.158.4.54 -1222224653 -ckgrier2 - - - - -http://sourceforge.net/support/tracker.php?aid=1884654 -1884654 -1 -1026580 -100 -terrybarnaby -nobody -nobody -1201883738 -0 -5 -Auto shorten of wires. -
When modifying wires and joining to a wire that already exists but is to long, it would be good if the wire was automatically shortened.
-0 - - - - - - -5581605 -IP -Artifact Created: 82.152.34.172 -1201883739 -terrybarnaby - - - - -http://sourceforge.net/support/tracker.php?aid=1884658 -1884658 -1 -1026580 -100 -terrybarnaby -nobody -nobody -1201883802 -0 -5 -Better editing of wires in eeschema -
It would be good to have better editing of wires in eeschema, more like in pcbnew for tracks. For example: move/add/delete nodes and segments.
-0 - - - - - - -5581611 -IP -Artifact Created: 82.152.34.172 -1201883802 -terrybarnaby - - - - -http://sourceforge.net/support/tracker.php?aid=1884661 -1884661 -1 -100 -100 -terrybarnaby -nobody -nobody -1201883842 -0 -5 -Some more standerdised hot keys -
It would be good to have some more standerdised hot keys like CRTL-S for save in eeschema.
-0 - - -2934700 -ckgrier2 -1222224702 -
Done. They are fully customizable now.
- - - - - - -5581614 -IP -Artifact Created: 82.152.34.172 -1201883842 -terrybarnaby - - -6557336 -IP -Comment Added: 68.158.4.54 -1222224702 -ckgrier2 - - - - -http://sourceforge.net/support/tracker.php?aid=1884663 -1884663 -1 -1026580 -100 -terrybarnaby -nobody -nobody -1201884029 -0 -5 -Better component browser -
The component browser in eeschema is poor especially when you have extensive libraries this could be improved perhaps with some hierarchy ability based on the libraries. Perhaps it would be good to have a component "type" field to group components by type (capacitors, logic, Microprocessors etc).
-0 - - - - - - -5581626 -IP -Artifact Created: 82.152.34.172 -1201884029 -terrybarnaby - - - - -http://sourceforge.net/support/tracker.php?aid=1884665 -1884665 -2 -1026579 -100 -terrybarnaby -nobody -jerryjacobs -1201884089 -1256496629 -5 -Ability to turn off layers -
It would be good to be able to select the layers viewable in pcbnew. Ideally with an on-screen list of toggle buttons that can be left on the screen.
-0 - - -2841696 -maxgaukler -1216406985 -
Logged In: YES -user_id=937039 -Originator: NO - -Please specify what exactly you want: Do you want to -- hide layers temporarily -or -- "delete" layers so that they aren't available for use (e.g. if you have a PCB with no layers inside, delete all inner layers that KiCad offers) - -Max Gaukler
- - -3789005 - -1256402271 -
I think that Terry tell us the possibility of only view one layer at the same time, when you are working with multiple layer. Because sometimes is really difficult view your work clear with all layers available. -Thanks.
- - -3789753 -jerryjacobs -1256496628 -
For next release Dr. Isaac wrote already patches for layer selection and since SVN 2029 added. -See http://kicad.svn.sourceforge.net/viewvc/kicad?view=rev&revision=2029 -Try latest SVN build (see main wiki) or compile yourself.
- - - - - - -5581629 -IP -Artifact Created: 82.152.34.172 -1201884089 -terrybarnaby - - -6255219 -IP -Comment Added: 88.65.53.228 -1216406985 -maxgaukler - - -8812542 -IP -Comment Added: 84.126.155.8 -1256402271 - - - -8815661 -IP -Comment Added: 84.25.204.235 -1256496628 -jerryjacobs - - -8815662 -status_id -1 -1256496629 -jerryjacobs - - -8815663 -allow_comments -1 -1256496629 -jerryjacobs - - -8815664 -close_date -0 -1256496629 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=1884835 -1884835 -1 -1026579 -100 -terrybarnaby -nobody -nobody -1201898082 -0 -5 -Cooamnd line window -
Ability to use command line entry window to place components/tracks accurately. Ideally with some scripting language.
-0 - - - - - - -5582667 -IP -Artifact Created: 82.152.34.172 -1201898082 -terrybarnaby - - - - -http://sourceforge.net/support/tracker.php?aid=1884836 -1884836 -1 -1026579 -100 -terrybarnaby -nobody -nobody -1201898120 -0 -5 -More default track widths for first time users -
More default track widths for first time users. -Such as (8, 17, 50, 75, 100).
-0 - - -2934694 -ckgrier2 -1222224095 -
This will only clutter up the track width selection. I don't see any reason someone can't add their own width options. It takes two clicks.
- - - - - - -5582724 -IP -Artifact Created: 82.152.34.172 -1201898120 -terrybarnaby - - -6557324 -IP -Comment Added: 68.158.4.54 -1222224095 -ckgrier2 - - - - -http://sourceforge.net/support/tracker.php?aid=1884838 -1884838 -1 -1026579 -100 -terrybarnaby -nobody -nobody -1201898177 -0 -5 -Ability to turn off "non visable" labels. -
Module labels that have been set to "no show" are still shown when viwing the PCB. This clutters the display.
-0 - - - - - - -5582794 -IP -Artifact Created: 82.152.34.172 -1201898177 -terrybarnaby - - - - -http://sourceforge.net/support/tracker.php?aid=1884839 -1884839 -1 -1026579 -100 -terrybarnaby -nobody -nobody -1201898340 -0 -5 -Better component browser -
The Module browser is very poor in pcbnew, worse than eeschema. It could be improved perhaps with a hierarchy of modules. There could be a type field in the modules to -allow selection of types such as Capacitors, Resistors, Logic, Microprocessors etc. -
-0 - - -3654895 -nobody -1242384236 -
Yes, KiCAD need better component browser i think, too !!! - -Yob. -
- - - - - - -5582891 -IP -Artifact Created: 82.152.34.172 -1201898340 -terrybarnaby - - -8284802 -IP -Comment Added: 134.109.65.160 -1242384236 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1884841 -1884841 -1 -100 -100 -terrybarnaby -nobody -nobody -1201898401 -0 -5 -Different track joins at nodes (curved join etc) -
It would be good to have the ability to have different styles of track joins at nodes (curved join etc). -Useful when tracking differential pairs.
-0 - - - - - - -5582901 -IP -Artifact Created: 82.152.34.172 -1201898402 -terrybarnaby - - - - -http://sourceforge.net/support/tracker.php?aid=1884842 -1884842 -1 -1026579 -100 -terrybarnaby -nobody -nobody -1201898466 -0 -5 -Differential pair track layout tool. -
It would be good to have a differential pair tracking tool that would allow two tracks to be tracked simultaneously with a set gap and track width.
-0 - - -2671997 -nobody -1202843469 -
Logged In: NO - -Yes, please. -Even the upcoming v5 of Eagle will not support differential pairs :-///
- - -2737418 -nobody -1207916797 -
Logged In: NO - -Differential pairs routing? - -Is this feature coming up?
- - -2936400 -johnpuke -1222329211 -
Hello, - -are there any plans to support differential pairs? - -Thanks, John Puke
- - - - - - -5582902 -IP -Artifact Created: 82.152.34.172 -1201898466 -terrybarnaby - - -5627183 -IP -Comment Added: 84.169.21.177 -1202843469 -nobody - - -5887304 -IP -Comment Added: 84.169.19.135 -1207916797 -nobody - - -6563508 -IP -Comment Added: 84.169.14.120 -1222329211 -johnpuke - - - - -http://sourceforge.net/support/tracker.php?aid=1892491 -1892491 -1 -100 -100 -nobody -nobody -nobody -1202890788 -0 -5 -Dot in library name fails! -
Library files with dots in filename (example "my.library.mod" or ".lib") is added to .pro file with right name "my.library". - -Problem: open_library() function fails because it uses a ".library" as extension. -Possible corrections: - a) write full name with "my.library.mod" to .pro file - or - b) remove "." check from open_library() function - -P.S. open_library() is a "pseudo-name".
-0 - - -2695350 -nobody -1204578742 -
Logged In: NO - -I think I have nailed it down to MakeFileName() in common/gestfich.cpp, which is being called by LoadLibraries() in eeschema/eelibs_read_libraryfiles.cpp (and probably elsewhere). - -It looks like MakeFileName() is designed to not add an extension (e.g. ".lib") if there is already an extension (i.e. any "." after the last "/"). - -I am not sure why it is like this and whether it is safe to remove it. In my first tests, it looks like all files (at least in eeschema) have no extensions, so it might be OK to remove that code.
- - -2872350 -nobody -1218446730 -
Logged In: NO - -b) remove "." check from open_library() function - -I suggest correct parsing of file name . The file "extension" , whatever meaning that can have in cross-platform software , is that part after the last "." and not after the first. - -This is not even correct parsing in the limitted context of win32. - -This is a bug not a feature request. Please file as bug. - -
- - - - - - -5629257 -IP -Artifact Created: 217.26.177.9 -1202890788 -nobody - - -5713555 -IP -Comment Added: 82.83.204.133 -1204578743 -nobody - - -6348225 -IP -Comment Added: 79.94.128.197 -1218446730 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1892493 -1892493 -1 -100 -100 -klui_ -nobody -nobody -1202891143 -0 -5 -Net highlight tool in eeSchema. -
Net highlight is very useful with buses and aliases in schema when wire is splitted into parts.
-0 - - - - - - -5629272 -IP -Artifact Created: 217.26.177.9 -1202891143 -klui_ - - - - -http://sourceforge.net/support/tracker.php?aid=1892773 -1892773 -2 -761685 -100 -klui_ -nobody -plyatov -1202913775 -1204570139 -5 -3D Display: Pan when mouse wheel pressed. -
It's very useful to ``pan'' scene in '3D Display' mode using pressed mouse wheel instead of separate panel arrows.
-0 - - -2693798 -diemer -1204460456 -
Logged In: YES -user_id=154672 -Originator: NO - -I have implemented that, see attached patch
- - -2693799 -diemer -1204460477 -
Logged In: YES -user_id=154672 -Originator: NO - -Here goes the patch: - -Index: 3d-viewer/3d_canvas.cpp -=================================================================== ---- 3d-viewer/3d_canvas.cpp (Revision 821) -+++ 3d-viewer/3d_canvas.cpp (Arbeitskopie) -@@ -283,14 +283,22 @@ - - if( event.Dragging() ) - { -- /* drag in progress, simulate trackball */ -- trackball( spin_quat, -+ if (event.LeftIsDown()){ -+ /* drag in progress, simulate trackball */ -+ trackball( spin_quat, - (2.0 * g_Parm_3D_Visu.m_Beginx - size.x) / size.x, - (size.y - 2.0 * g_Parm_3D_Visu.m_Beginy) / size.y, - ( 2.0 * event.GetX() - size.x) / size.x, - ( size.y - 2.0 * event.GetY() ) / size.y ); - -- add_quats( spin_quat, g_Parm_3D_Visu.m_Quat, g_Parm_3D_Visu.m_Quat ); -+ add_quats( spin_quat, g_Parm_3D_Visu.m_Quat, g_Parm_3D_Visu.m_Quat ); -+ } else if (event.MiddleIsDown()){ -+ /* middle button drag -> pan */ -+ /* Current zoom and an additional factor are taken into account for the amount of panning. */ -+ const float PAN_FACTOR = 8.0 * g_Parm_3D_Visu.m_Zoom; -+ g_Draw3d_dx -= PAN_FACTOR * (g_Parm_3D_Visu.m_Beginx - event.GetX()) / size.x; -+ g_Draw3d_dy -= PAN_FACTOR * (event.GetY() - g_Parm_3D_Visu.m_Beginy) / size.y; -+ } - - /* orientation has changed, redraw mesh */ - DisplayStatus(); -
- - - - - - -5630738 -IP -Artifact Created: 217.26.177.9 -1202913775 -klui_ - - -5707155 -IP -Comment Added: 82.83.204.160 -1204460457 -diemer - - -5707156 -IP -Comment Added: 82.83.204.160 -1204460477 -diemer - - -5712301 -status_id -1 -1204570138 -plyatov - - -5712302 -close_date -0 -1204570139 -plyatov - - - - -http://sourceforge.net/support/tracker.php?aid=1900617 -1900617 -1 -100 -100 -klui_ -nobody -nobody -1203808711 -0 -5 -Grids offsets. Metric VS English. -
Modern frames uses both metric dimensions (body+mounts) and inches (pins). Please add "grid offset" in "User Grid size" to greatly simplify footprint designing process.
-0 - - - - - - -5677233 -IP -Artifact Created: 89.178.163.70 -1203808712 -klui_ - - - - -http://sourceforge.net/support/tracker.php?aid=1900688 -1900688 -3 -100 -100 -klui_ -nobody -stambaughw -1203829219 -1270750121 -5 -Grids offsets. Metric VS English. -
Modern frames uses both metric dimensions (body+mounts) and inches (pins). Please add "grid offset" in "User Grid size" to greatly simplify footprint designing process.
-0 - - -3957160 -stambaughw -1270750023 -
Duplicates feature request 1900617.
- - -3957162 -stambaughw -1270750120 -
Duplicate
- - - - - - -5677869 -IP -Artifact Created: 89.178.163.70 -1203829220 -klui_ - - -9382217 -IP -Comment Added: 162.83.115.135 -1270750023 -stambaughw - - -9382218 -status_id -1 -1270750023 -stambaughw - - -9382219 -allow_comments -1 -1270750023 -stambaughw - - -9382220 -close_date -0 -1270750023 -stambaughw - - -9382227 -IP -Comment Added: 162.83.115.135 -1270750120 -stambaughw - - -9382228 -status_id -2 -1270750121 -stambaughw - - -9382229 -close_date -1270750023 -1270750121 -stambaughw - - - - -http://sourceforge.net/support/tracker.php?aid=1902057 -1902057 -1 -761685 -100 -klui_ -nobody -nobody -1204022721 -0 -5 -Block selection in eeSchema selects also in PCBnew. -
It's very useful when manually placing a logical group!
-0 - - - - - - -5687356 -IP -Artifact Created: 217.26.177.9 -1204022721 -klui_ - - - - -http://sourceforge.net/support/tracker.php?aid=1902854 -1902854 -1 -761685 -100 -klui_ -nobody -nobody -1204104233 -0 -5 -Block selection in eeSchema selects also in PCBnew. -
It's very useful when manually placing a logical group!
-0 - - -2783226 -cfdev -1211467994 -
Logged In: YES -user_id=1876469 -Originator: NO - -I agree with this. - -In PCBNEW, -It's will be good to show the content's block when we moving it ! - -Thanks ++
- - - - - - -5691853 -IP -Artifact Created: 217.26.177.9 -1204104234 -klui_ - - -6039888 -IP -Comment Added: 90.52.51.69 -1211467994 -cfdev - - - - -http://sourceforge.net/support/tracker.php?aid=1905019 -1905019 -1 -1026581 -100 -elbuit -nobody -nobody -1204325440 -0 -5 -Store configuration files in .config directory under linux -
Store configuration files in .config directory under linux like the freedesktop standard: -http://standards.freedesktop.org/basedir-spec/basedir-spec-0.6.html
-0 - - - - - - -5703427 -IP -Artifact Created: 84.123.141.48 -1204325440 -elbuit - - - - -http://sourceforge.net/support/tracker.php?aid=1906962 -1906962 -1 -761685 -100 -klui_ -nobody -nobody -1204633868 -0 -5 -Selection improvement. -
Please add the following: -1. selection marquee from-left-to-right selects only 100%inside selection objects (as it now does) -2. from-right-to-left selects all overlapping objects inside selection marquee
-0 - - -2767096 -nobody -1210311009 -
Logged In: NO - -I would like to have a selection like in the Windows Explorer or Eagle, where you can add single items to the selection or remove it while holding down the the Ctrl-Key and clicking on it.
- - - - - - -5715643 -IP -Artifact Created: 217.26.177.9 -1204633869 -klui_ - - -5990970 -IP -Comment Added: 138.246.7.133 -1210311009 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1909202 -1909202 -1 -100 -100 -nobody -nobody -nobody -1204851097 -0 -5 -Show contents of block selection while dragging -
What is says in the title really. It's a bit tricky having to guess where things are going to end up without being able to see them
-0 - - -2784055 -cfdev -1211528171 -
Logged In: YES -user_id=1876469 -Originator: NO - -I agree with this. - -In PCBNEW, -It's will be good to show the content's block when we moving it ! -
- - - - - - -5729034 -IP -Artifact Created: 84.92.181.41 -1204851098 -nobody - - -6042084 -IP -Comment Added: 90.52.51.69 -1211528172 -cfdev - - - - -http://sourceforge.net/support/tracker.php?aid=1920376 -1920376 -1 -100 -100 -nobody -nobody -nobody -1205970758 -0 -5 -Command line utilities -
Add command line utilities for everything where it makes sense: - -Plotting, Printing, netlist generation, autorouting, conversion to pdf, ps, .... -
-0 - - -3580557 -nobody -1237330833 -
That would be really nice
- - -3580558 -nobody -1237330916 -
That would be really nice
- - -3580561 -nobody -1237331137 -
That would be really nice
- - - - - - -5784957 -IP -Artifact Created: 85.178.27.18 -1205970758 -nobody - - -7935241 -IP -Comment Added: 91.150.229.252 -1237330833 -nobody - - -7935251 -IP -Comment Added: 91.150.229.252 -1237330916 -nobody - - -7935266 -IP -Comment Added: 91.150.229.252 -1237331137 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1925393 -1925393 -1 -100 -100 -nobody -nobody -nobody -1206467264 -0 -5 -hole matrix board-function in KiCad and another function. -
install a funtion that we can create a virtual hole matrix board. - -make the Programm easier for non-professionel -electronician! For example, when I would create a new electronic component it is too unclear for new user. -Please organize the function new, that new user find the function better. - -Create a function that people can simulate a board with all his function, in the PC. - -Please create a function that we can checking a complete board. - -create a function that we can simulate a IC on the board and we can programm it, too. - -Sincerely yours...
-0 - - - - - - -5812308 -IP -Artifact Created: 84.163.88.231 -1206467264 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1938219 -1938219 -1 -1026579 -100 -nobody -nobody -nobody -1207697939 -0 -5 -Export to G-Code -
Greetings, -In fact I'm very intusiast on this program, but there some issues that you need to re-think, one of them is usability, because there are some functionalities that could increase usability of this program, one is the zoom that we do with the wheel of the mouse, the steps are very big. The change should be smoother. -But what I believe it hould be a huge improvement was the export to G-code the board.
-0 - - -2821551 -lomarcan -1214820415 -
Logged In: YES -user_id=115128 -Originator: NO - -There are already some programs (even free) which generates G-code for milling PCB (and anyhow photomechanical processing is better :P) - -You can look, for example, to kcam or deskcam. - -The zoom issue is already on file :D -
- - - - - - -5877353 -IP -Artifact Created: 87.196.203.110 -1207697939 -nobody - - -6187372 -IP -Comment Added: 88.149.185.186 -1214820415 -lomarcan - - - - -http://sourceforge.net/support/tracker.php?aid=1943010 -1943010 -1 -100 -100 -nobody -nobody -nobody -1208267315 -0 -5 -KiCAD as PortableApps application. -
Is it possible to made KiCAD "installation" compatible with PortableApps.com applications? -
-0 - - - - - - -5902096 -IP -Artifact Created: 143.183.121.4 -1208267316 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1947959 -1947959 -1 -1026579 -100 -diemer -nobody -nobody -1208788810 -0 -5 -Optical/Accoustic feedback on DRC violation -
Basically, there should be a beep/blink when a track cannot be created due to DRC violations. - - -From Users-ML: -"> > - when DRC is ON and something is not allowed it should at least sound -> > a beep or something to let user know about the problem. -> -> You mean a beep when trying to place a track that violates DRC rules (e.g. -> spacing) ? - -Exactly, for a beginner, I could not figure out why I could not lay a trace sometimes. -Later I noticed the status on a status line, but it is not obvious right away. -A beep or a highlighting of the error area would be nice (feature request)." -
-0 - - - - - - -5928737 -IP -Artifact Created: 134.169.117.46 -1208788810 -diemer - - - - -http://sourceforge.net/support/tracker.php?aid=1959203 -1959203 -1 -1026582 -100 -nobody -nobody -nobody -1210132197 -0 -5 -Pre-link between schematic symbol and footprint -
One of the wishe is "Support for including part #'s(Digikey, Mouser,etc) and price in BOM" -I agree with this approach, wouldn't put it into the package files but as a downloadable list to add to the libraries. -One condition for this is to have a default footprint for each component. KiCad does not go this way yet so I would like to suggest to have a pre-fixed footprint which is still changeable in CVPCB. - -[I am a HW and PCB designer myself and just looking for a capable but not too expensive CAD package as I just started with a small company. The work you guys did is incredible and I really hope the enthusiasm will continue - -heiko.lange@baycity-technologies.com]
-0 - - -2821547 -lomarcan -1214820146 -
Logged In: YES -user_id=115128 -Originator: NO - -I use one of the fields for saving the RS/Distrelec/whatever part number, and it comes out in the BOM if you ask for it. - -The default footprint can be done with equiv files in cvpcb or footprint filters in the library (never tried that, anyhow). - -Latest (developement only) version also support backannotating using a stuff file.
- - - - - - -5982895 -IP -Artifact Created: 222.153.213.254 -1210132197 -nobody - - -6187354 -IP -Comment Added: 88.149.185.186 -1214820146 -lomarcan - - - - -http://sourceforge.net/support/tracker.php?aid=1962617 -1962617 -1 -1026579 -100 -blixhavn -nobody -nobody -1210623822 -0 -5 -Improved DRC -
The DRC should be able to detect annular ring width violations in vias and pads. -It would also be nice to have a check of overlapping drill holes. I have sometimes managed to place vias on pads.
-0 - - - - - - -6002382 -IP -Artifact Created: 88.90.95.148 -1210623822 -blixhavn - - - - -http://sourceforge.net/support/tracker.php?aid=1975439 -1975439 -1 -1026582 -100 -ddeeds -nobody -nobody -1211920276 -0 -5 -No-connect should color entire pad -
A no-connect pin currently indicates the no-connect with a slash (/) through the pin number. It would be preferable to color the entire pin with the no-connect color. It would also be preferable to allow the user to select the no-connect color.
-0 - - - - - - -6059820 -IP -Artifact Created: 96.226.65.105 -1211920277 -ddeeds - - - - -http://sourceforge.net/support/tracker.php?aid=1989008 -1989008 -1 -1026579 -100 -nobody -nobody -nobody -1213028271 -0 -5 -Add Assembly Drawing Layers -
When creating a new PCB footprint, there should be an assembly drawing layer available to put the actual part outline on. -Often (especially with SMT components) it is not practical to place the outline on the silk screen layer, and it would be helpful to have some component documentation to print for reference during PCB assembly.
-0 - - - - - - -6114540 -IP -Artifact Created: 63.241.173.64 -1213028272 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=1993312 -1993312 -1 -1026580 -100 -jerryjacobs -nobody -nobody -1213386742 -0 -5 -Copy multiple selected components -
It could be handy if we could select multiple components at ones and copy them. - -Greets -Jerry
-0 - - - - - - -6132790 -IP -Artifact Created: 84.25.41.149 -1213386742 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2003295 -2003295 -1 -761685 -516023 -josteinaj -nobody -nobody -1214500344 -0 -5 -Online library -
This one goes for libraries in general, whether it's a schematic, a footprint or a 3D model; - -An effective (and simple) way to build a big library of components would be to allow users to submit their creations to an online database, search the db for components, and download them. Why keep the library offline when you can have it online? (Well, of course you'll need an offline version as well, but still...)
-0 - - -2827160 -over2there -1215326570 -
Logged In: YES -user_id=1664921 -Originator: NO - -Grate idea!
- - -3158034 -nobody -1225992054 -
Really neat :P
- - -3953299 -thewarpi -1270473533 -
Very nice! Reduce all the double work everywhere. - -Working online is far more common and therefore I believe that the libraries should be there aswell. Maybe you could download an offline version just temporary if you need it.
- - -3956598 -seaton -1270708114 -
I would like to see a central repository with the client build into kicad, that would allow the user to select what components they want, these would then get synced locally. - -By using existing technology, such as GIT or HG rather than SVN it would 1) allow revision management of the library, but also 2) allow different versions of existing components to be created and placed under revision control, i.e. same footprints but with pad or solder mask variations etc. - -I would also like to see integrated into the local client would be a comment or voting system so users could comment on how well the component worked, or why it didn't work for them. - -By using a centralised approach then any faulty footprints would be quickly rectified and distributed to all users.
- - - - - - -6176642 -IP -Artifact Created: 193.71.117.211 -1214500344 -josteinaj - - -6207504 -IP -Comment Added: 217.233.235.34 -1215326570 -over2there - - -6882212 -IP -Comment Added: 91.150.229.252 -1225992054 -nobody - - -9366594 -IP -Comment Added: 90.237.202.7 -1270473534 -thewarpi - - -9380166 -IP -Comment Added: 58.6.1.177 -1270708114 -seaton - - - - -http://sourceforge.net/support/tracker.php?aid=2006617 -2006617 -1 -1026580 -100 -lomarcan -nobody -nobody -1214821629 -0 -5 -Grid reference in BOM -
It would be VERY useful in the BOM to add as a field the grid locator reference (like sheet 2, square B4). Otherwise the sheet cartouche isn't very useful as is...
-0 - - - - - - -6187439 -IP -Artifact Created: 88.149.185.186 -1214821629 -lomarcan - - - - -http://sourceforge.net/support/tracker.php?aid=2008118 -2008118 -1 -100 -100 -nobody -nobody -nobody -1214937648 -0 -5 -Need simple cluster-of-vias method -
For some surface mount power components, the manufacturer requires the designer to tie a single component pin (actually a very large pad) through a dozen or more vias to an inner layer or opposite side of the board for heat dissipation. PCBNEW 2007-11-29a makes this frustratingly difficult by deleting vias already tied in parallel to the same layers. - My interim solution for now is to define new module footprints for these power components with a multitude of pins tied to small pads, then wire each pad through a via in the pad to another layer, and finally to create zones on the component layer and inner layer that merge the pads into rectangular filled areas. This is a LOT of work, and my schematic looks weird with a huge number of pins on these components.
-0 - - - - - - -6193383 -IP -Artifact Created: 192.18.128.5 -1214937649 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2011581 -2011581 -1 -100 -100 -over2there -nobody -nobody -1215326524 -0 -5 -Funktion to add smd resistors as a bridge -
It would be great to have a function (e.g. you press b) and you are asked which type of smd resistor you want to use as a bridge. That would ease designing single layer smd layouts very much! Hope you can realize that!
-0 - - -3763939 -korp -1254234857 -
Please also consider implementing an extra option to exclude these resistor bridges from being removed on netlist re-import, when "Remove Extra Footprints" is selected.
- - - - - - -6207503 -IP -Artifact Created: 217.233.235.34 -1215326525 -over2there - - -8718869 -IP -Comment Added: 194.71.159.2 -1254234858 -korp - - - - -http://sourceforge.net/support/tracker.php?aid=2013694 -2013694 -1 -1026579 -100 -nobody -nobody -nobody -1215539349 -0 -5 -wish list IPC-2581 compliance -
-I would like to see KiCAD conform to IPC-2581. It would be the first package to support this standard as far as I know. If picked up by the industry this standard would eliminate the need for us to enter pads. - -http://webstds.ipc.org/2581/documents/IPC-2581witham1pub.pdf
-0 - - - - - - -6217343 -IP -Artifact Created: 207.254.33.78 -1215539349 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2024791 -2024791 -1 -1026579 -516023 -nobody -nobody -nobody -1216740618 -0 -5 -3D images export, POVRay -
I think it would be nice to use POVRay instead of wings3d, just like matwei.de has done it with Eagle PCB. By the reading from the links, it seems fairly easy to do this. - -The reasons of doing this is mainly, because that an nice library already exist and that it looks very nice. Besides I think that it will make Kicad even more popular. - -Links: -http://www.matwei.de/doku.php?id=en:eagle3d:eagle3d -http://www.matwei.de/doku.php?id=en:eagle3d:documentation -http://www.matwei.de/doku.php?id=en:eagle3d:library -http://www.matwei.de/doku.php?id=en:eagle3d:gallery - -BTW: Kicad rocks!
-0 - - -2904025 -nobody -1220340200 -
Logged In: NO - -I think it could be integrated into kicad, there needs to be somebody with POVray knowledge and how to integrate it into KiCad
- - -2904026 -nobody -1220340255 -
Logged In: NO - -I think it could be integrated into kicad, there needs to be somebody with POVray knowledge and how to integrate it into KiCad
- - -2904027 -nobody -1220340293 -
Logged In: NO - -I think it could be integrated into kicad, there needs to be somebody with POVray knowledge and how to integrate it into KiCad
- - -3160729 -nobody -1226137931 -
Yes, I believe so too, therefore this request. But unfortunately I am not the one for the job yet.
- - -3508980 -nobody -1234131197 -
In addition, I think Blender would be an excellent source of models.
- - -3508987 -nobody -1234131219 -
In addition, I think Blender would be an excellent source of models.
- - -3508992 -nobody -1234131240 -
In addition, I think Blender would be an excellent source of models.
- - -3509081 -nobody -1234131844 -
In addition, I think Blender would be an excellent source of models.
- - -3509100 -nobody -1234132043 -
In addition, I think Blender would be an excellent source of models.
- - -3509122 -nobody -1234132192 -
In addition, I think Blender would be an excellent source of models.
- - - - - - -6268701 -IP -Artifact Created: 91.150.229.252 -1216740618 -nobody - - -6457363 -IP -Comment Added: 212.178.132.86 -1220340200 -nobody - - -6457366 -IP -Comment Added: 212.178.132.86 -1220340255 -nobody - - -6457367 -IP -Comment Added: 212.178.132.86 -1220340293 -nobody - - -6897603 -IP -Comment Added: 91.150.229.252 -1226137931 -nobody - - -7656210 -IP -Comment Added: 155.246.252.94 -1234131197 -nobody - - -7656214 -IP -Comment Added: 155.246.252.94 -1234131219 -nobody - - -7656222 -IP -Comment Added: 155.246.252.94 -1234131240 -nobody - - -7656257 -IP -Comment Added: 155.246.252.94 -1234131844 -nobody - - -7656292 -IP -Comment Added: 155.246.252.94 -1234132043 -nobody - - -7656321 -IP -Comment Added: 155.246.252.94 -1234132192 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2031726 -2031726 -1 -1026583 -516023 -nobody -nobody -nobody -1217355776 -0 -5 -CAM capabilities (PCB milling) -
The possibility to generate toolpaths for PCB milling machines (e.g. LPKF) or CNC routers (e.g. ISEL, Roland) would be desirable. - -At the moment, the only electronic CAD package that integrates this functionality is Cadsoft Eagle. Major PCB milling machine manufacturers have their own CAM packages, that take as input Gerber and Excellon files, and output the toolpaths. Eagle is limited to milling out track contours and drilling holes. Proprietary packages can also mill out (rub out) the unnecessary copper from selected areas. - -If a rubout function, as above, is provided, for usability it must be possible to select the areas where to apply it. This because rubouts are extremely demanding on machine time and tool wear, and should therefore be applied where strictly necessary only. - -The output format should be either HPGL or simple G-Code (lines only, with no arcs, and possibility to select metric or imperial G-Code, for highest compatibility) or, possibly, both, as PCB millers normally require HPGL and milling machines G-Code. - -Possibly the best tools for such integration would be Gerbview or EeSchema, with a preference for Gerbtool, as the generation of toolpath code effectively follows the generation of geometrical production data (Gerber, Excellon). - - -E-mail: giardini@btinternet.com
-0 - - - - - - -6297536 -IP -Artifact Created: 138.251.105.6 -1217355776 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2035487 -2035487 -1 -100 -100 -jerryjacobs -nobody -nobody -1217638501 -0 -5 -Auto-Refresh after draw -
Sometimes i hate it to refresh many times when drawing, maybe somewone could add a auto-refresh function ( with toggle button )
-0 - - -2899278 -nobody -1220026933 -
Logged In: NO - -Isen't that fixed in new version?
- - - - - - -6311924 -IP -Artifact Created: 84.25.41.149 -1217638501 -jerryjacobs - - -6442722 -IP -Comment Added: 91.150.229.252 -1220026933 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2098301 -2098301 -1 -1026579 -516023 -nobody -nobody -nobody -1220777988 -0 -5 -[Enhancement] Fillzone Smoothness -
I found this on the internet: - -http://beischer.com/opencad/fillzone.htm
-0 - - -3185405 -nobody -1227563071 -
Currently implemented in svn (r1426) as polygon fill mode.
- - - - - - -6482311 -IP -Artifact Created: 84.25.41.149 -1220777988 -nobody - - -7047337 -IP -Comment Added: 91.153.138.49 -1227563071 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2098313 -2098313 -1 -761685 -100 -nobody -nobody -nobody -1220778556 -0 -5 -Line and Cross grid -
It would be nice if there is a option to choose from different grids, dot, line, crosses. - -In PCBNEW and EESCHEMA
-0 - - - - - - -6482326 -IP -Artifact Created: 84.25.41.149 -1220778556 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2098983 -2098983 -1 -1026579 -100 -m_beischer -nobody -nobody -1220811131 -0 -5 -File driven post processing -
It would be very nice if there was a function that could read a file (unique to every board) that controls the generation of production files. - -The reason for having such function is: -- This is a very important step and it should not be done manually (more than once). -- When changing an old design it is desireble to be able to regenerate the manufacturing data with the same settings. - -The file could contain: -#Gerber settings, PCB manufacturing data -- Layers to generate -- Gerber format and other settings that can be done manually -- Settings for drill file - -#Printing and circuit board manufacturing data -- Layers to generate for printing -- Format and other stuff - -#Other settings -- Output directory -- Naming conventions etc. - -
-0 - - - - - - -6483986 -IP -Artifact Created: 83.227.224.244 -1220811131 -m_beischer - - - - -http://sourceforge.net/support/tracker.php?aid=2099036 -2099036 -1 -100 -100 -m_beischer -nobody -nobody -1220813476 -0 -5 -Unplated holes in separate drill file -
It would be very nice to have 2 drill files instead of one. The second file would contain the unplated holes. Today I don't think that KiCAD supports unplated holes at all... (please correct me if I'm wrong). Unplated holes are drilled in the last manufaturing process step, so a seperate file is desireble. - -The way around this for me is to just put unplated holes as circles in the board outline layer in the sympols that require unplated holes, but this method puts extra responsibility and manuall work on the PCB manufacturer. There is also no way to change the diameter of such a hole in the module editor (you have to create a new circle in the edge layer and delete the old one and place it on the exact same coorinate).
-0 - - - - - - -6484069 -IP -Artifact Created: 83.227.224.244 -1220813476 -m_beischer - - - - -http://sourceforge.net/support/tracker.php?aid=2130008 -2130008 -1 -1026580 -100 -brendansimon -nobody -nobody -1222428095 -0 -5 -[FEATURE-REQUEST] OS X build -
Could we please have OS X support for kicad. - -I'd like to be able to download OS X binaries, with timely releases inline with UNIX and MSW releases. - -Thanks, Brendan. -
-0 - - -3185012 -nobody -1227549009 -
2nd that.
- - - - - - -6569353 -IP -Artifact Created: 124.168.26.242 -1222428095 -brendansimon - - -7045982 -IP -Comment Added: 76.235.68.246 -1227549009 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2211764 -2211764 -1 -1026579 -100 -lomarcan -nobody -nobody -1225457031 -0 -5 -Nonplated holes -
They could be implemented with and additional flag in the pad, together with the drill size... - -So in the excellon/drill report they would be assigned different tools and the NPTH label. - -Once declared a tool as non-plated it's trivial for the manufacturer to separate it in two. -
-0 - - - - - - -6846424 -IP -Artifact Created: 88.149.185.186 -1225457031 -lomarcan - - - - -http://sourceforge.net/support/tracker.php?aid=2211768 -2211768 -1 -1026579 -100 -lomarcan -nobody -nobody -1225457223 -0 -5 -Zone grid filling -
Sometimes a solid fill is not the right thing (tm) to do. It would be useful a cross hatched filling, specifying the hatch pitch/density. - -Something like seen in -http://www.labcenter.co.uk/products/zones.gif
-0 - - -3581559 -damunix -1237395762 -
Yeah I think that this should be in Kicad PCBNEW software. It gives a better look'n feel to the board. - -another example : http://www.adamthole.com/ee/wp-content/uploads/2007/02/tiltboard.jpg
- - -3913172 - -1267154167 -
This feature is critical for a successful PCB layout program.
- - - - - - -6846428 -IP -Artifact Created: 88.149.185.186 -1225457223 -lomarcan - - -7947327 -IP -Comment Added: 91.121.195.179 -1237395762 -damunix - - -9215661 -IP -Comment Added: 24.59.31.155 -1267154167 - - - - - -http://sourceforge.net/support/tracker.php?aid=2220944 -2220944 -2 -100 -100 -damunix -nobody -raburton -1225805671 -1226322713 -5 -kicad deb file -
Hi all, - -I made a deb file of the last kicad stable version for Ubuntu 64 bits desktop. - -You can download it at http://dtc.brainfault.net/kicad_20081104-1_amd64.deb - -Tell me if you have any problems with it (I think about dependencies that are not shure ) - - -damunix
-0 - - -3158031 -nobody -1225991968 -
:-) Why are you posting this under "Feature request"? Why don't you visit #kicad on freenode?
- - -3162605 -xtronics -1226280630 -
?? the last stable release was 2008-08-25 ? - -Was there a release that missed the mailing list on yahoo?
- - -3163049 -raburton -1226322034 -
There is no stable release 20081104. The last stable release is 20080825c. - -The latest stable release is availble from the official debian repository (inc. for amd64), which should work on Ubuntu as well. The Debian packages are pulled into Ubuntu's universe repository. - -If you want to build your own packages of svn builds I recommend you use the offical Debian build files from here: -https://svn.flexserv.de/kicad/trunk/debian/ -This has the additional benefit of finding problems in the official Debian packages in advance of a release, and in advance of them being pulled into Ubuntu. - -Richard.
- - - - - - -6865622 -IP -Artifact Created: 195.221.233.56 -1225805671 -damunix - - -6882186 -IP -Comment Added: 91.150.229.252 -1225991968 -nobody - - -6912219 -IP -Comment Added: 63.245.153.165 -1226280630 -xtronics - - -6916328 -IP -Comment Added: 128.243.82.246 -1226322034 -raburton - - -6916396 -status_id -1 -1226322713 -raburton - - -6916397 -close_date -0 -1226322713 -raburton - - - - -http://sourceforge.net/support/tracker.php?aid=2339553 -2339553 -1 -1026579 -100 -nobody -nobody -nobody -1227549178 -0 -5 -Layer Viewing Isolation Mode -
(Searched, but unable to see if this is possible in current version). - -I would be outstanding to be able to isolate layers for viewing. This is a standard feature in Altium, and it makes routing certain areas of the board easier. - -Basically, an option to "View Selected Layer Only" in the right-click menu with a corollary "View All Layers" to return to the normal high contrast mode. - -I really wish I had this right now as I struggle with silkscreens and such. - -Thanks!!! --Red
-0 - - -3198361 -nobody -1228293245 -
Yes, I'd even wish to have user definable layer sets, where the layouter can activate his layer sets for e.g. all layers associated with top side, or tracks & pads only, etc. - -Rob
- - -3651058 -nobody -1241964156 -
I agree. The ability to turn off selected layers would be very nice. I started a board yesterday, and the first thing I did was create the outline. So now I have a drawing layer with dimensions that are always visible. I'd love to turn them off for a while.
- - - - - - -7045999 -IP -Artifact Created: 76.235.68.246 -1227549178 -nobody - - -7114926 -IP -Comment Added: 83.189.111.196 -1228293245 -nobody - - -8268931 -IP -Comment Added: 72.74.211.34 -1241964156 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2394764 -2394764 -1 -100 -100 -djsbriscoe -nobody -nobody -1228556661 -0 -5 -Highlight selected nets in EEschema -
Please implement the highlighting of a selected net or multiple nets in EEschema. This will help a user to understand how a net is connected. It would be ideal if nets could be highlighted throughout the hierarchical structure of a design. -Thanks
-0 - - - - - - -7139688 -IP -Artifact Created: 213.160.109.227 -1228556662 -djsbriscoe - - - - -http://sourceforge.net/support/tracker.php?aid=2407747 -2407747 -1 -1026579 -100 -gembler -nobody -nobody -1228775412 -0 -5 -Autoscroll Zone Boundary Drawing -
Add autoscrolling to the drawing of zone boundary lines. -
-0 - - - - - - -7159465 -IP -Artifact Created: 216.239.45.4 -1228775412 -gembler - - - - -http://sourceforge.net/support/tracker.php?aid=2410898 -2410898 -1 -1026581 -100 -fransschreuder -nobody -nobody -1228818921 -0 -5 -Global library locations -
Could it be possible to have the option to have a global library location? I mean that when you add a library in schematic, that it is also there in the converter and in pcbnew? (it is all saved in the same project file, so it wouldn't be too much effort)
-0 - - - - - - -7164003 -IP -Artifact Created: 129.125.37.39 -1228818921 -fransschreuder - - - - -http://sourceforge.net/support/tracker.php?aid=2414195 -2414195 -2 -1026580 -100 -cfdev -nobody -stambaughw -1228927402 -1270749499 -5 -Improve the search fonction -
hi, - -is It possible to improve the search fonction in EESCHEMA, by peace of word, not by exact word ? - -sample: -I search in library 'PIC', result : don't found... :( -but PIC16F627 is in the library. - - -For example: - -the fonction search, will search with : -if ( m_lib->componentName.Find(wxT("PIC")) != wxNOT_FOUND ) -{ -...// OK -} -And the result of search fonction will writing in an listbox. - - - -thanks - -Cyril Frausti
-0 - - -3307198 -nobody -1231487304 -
This is already done -And you can use jokers (?, *) in names
- - -3307273 -nobody -1231487912 -
Ok thanks, I don't know the jokers. -But the result of search is in wxMessagebox so, -if there are many components in result, the visibility is not very good.
- - -3957150 -stambaughw -1270749499 -
New find dialog in SVN r2464 fixes this problem.
- - - - - - -7170856 -IP -Artifact Created: 90.52.207.22 -1228927402 -cfdev - - -7399452 -IP -Comment Added: 86.219.149.61 -1231487304 -nobody - - -7399521 -IP -Comment Added: 90.52.146.141 -1231487912 -nobody - - -9382172 -IP -Comment Added: 162.83.115.135 -1270749499 -stambaughw - - -9382173 -status_id -1 -1270749499 -stambaughw - - -9382174 -allow_comments -1 -1270749499 -stambaughw - - -9382175 -close_date -0 -1270749499 -stambaughw - - - - -http://sourceforge.net/support/tracker.php?aid=2489807 -2489807 -1 -1026579 -516023 -fransschreuder -nobody -nobody -1231235842 -0 -5 -Add arcs / circles on copper layers -
Hi, - -Would it be possible to draw arcs on copper layers? - -Thanks for the nice software! - -Frans
-0 - - - - - - -7371637 -IP -Artifact Created: 129.125.37.39 -1231235842 -fransschreuder - - - - -http://sourceforge.net/support/tracker.php?aid=2493392 -2493392 -1 -1026579 -100 -dandumit -nobody -nobody -1231399444 -0 -5 -Push Aside and Springback on Routing -
a very handy and usefull functionality while routing would be "push aside" other tracks and (eventually) "spring back" . -The movie from link it's self explanatory : - -http://www.cadstarworld.com/avis/CMovie/routing.html seconds 0.59 and 03.05
-0 - - - - - - -7386765 -IP -Artifact Created: 81.12.134.7 -1231399444 -dandumit - - - - -http://sourceforge.net/support/tracker.php?aid=2494013 -2494013 -1 -1026579 -516023 -cfdev -nobody -nobody -1231427875 -0 -5 -Fill Zones Why ? -
Hello, - -why in the newest stable version of pcbnew, it's not possible to create an zone to an other Layer than copper and component ? - -Why there must attach an NET to the Zone ? - - -I use Kicad in professional midle, and I uses this very often this 2 fonctions what I said. - -It's possible to change this in the next release? - - - -Thanks -cfdev
-0 - - - - - - -7390859 -IP -Artifact Created: 90.27.240.57 -1231427875 -cfdev - - - - -http://sourceforge.net/support/tracker.php?aid=2495741 -2495741 -2 -1026580 -516023 -cfdev -bennett78 -bennett78 -1231508184 -1267319591 -5 -bill of material -
Hi, - -is it possible with an checkbox on the Bill of material windows, to choice if the value of component are on the same line with the number like orcad ? - -Example: -Quantity Reference Value FootPrint -4 C1,C2,C25,C29 100nF C0805 - -Actually: -C1 100nF C0805 -C2 100nF C0805 -C25 100nF C0805 -C29 100nF C0805 - - -it's quicker to equip pcb. - - -Thanks - -
-0 - - -3329763 -cfdev -1231746500 -
<< -Actually: -C1 100nF C0805 -C2 100nF C0805 -C25 100nF C0805 -C29 100nF C0805 ->> - -correction -<< -Currently: -C1 100nF C0805 -C2 100nF C0805 -C25 100nF C0805 -C29 100nF C0805 ->> - -Sorry
- - -3634532 -drannou -1240681833 -
done ! -See in PCBnew in svn version
- - -3674521 -cfdev -1244709006 -
PCBnew ? no no this fonctionality is in Eeschema, -but it is not implemented yet ?? isn't it
- - -3915053 -bennett78 -1267319591 -
I just added an option to the BOM output format & updated the documentaion -(EEschema->Help->Contents) in SVN Revision: 2399....all parts with the same -Value are combined into a "Single Part per line" - -The only problem is figuring out what release will contain Rev 2399 if you can't -svn and build the latest code. -
- - - - - - -7402021 -IP -Artifact Created: 90.52.146.141 -1231508184 -cfdev - - -7426314 -IP -Comment Added: 90.52.205.11 -1231746500 -cfdev - - -8212713 -IP -Comment Added: 92.135.120.54 -1240681833 -drannou - - -8364838 -IP -Comment Added: 90.52.202.205 -1244709006 -cfdev - - -9221503 -IP -Comment Added: 76.76.79.173 -1267319591 -bennett78 - - -9221504 -status_id -1 -1267319591 -bennett78 - - -9221505 -assigned_to -100 -1267319591 -bennett78 - - -9221506 -allow_comments -1 -1267319591 -bennett78 - - -9221507 -close_date -0 -1267319591 -bennett78 - - - - -http://sourceforge.net/support/tracker.php?aid=2503160 -2503160 -1 -100 -100 -nobody -nobody -nobody -1231808934 -0 -5 -Renove title block & frame -
It would be good if title block and frame could be removed, better yet fully customized (not just its lines). Often schematics are drawn to be included in a paper and then it gets in the way. Also, often custom title blocks are needed that look a bit more professional. - -Just a suggestion. - -Regards, -Joerg -joergsch@analogconsultants.com
-0 - - - - - - -7432197 -IP -Artifact Created: 75.26.171.247 -1231808934 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2505497 -2505497 -1 -1026579 -100 -spedgenius -nobody -nobody -1231884104 -0 -5 -per module layer isolation -
I would like to see the ability to isolate a layer for routing in each module. currently the only way to do that is to edit the footprint library, which means all modules with the same footprint get changed.
-0 - - - - - - -7440798 -IP -Artifact Created: 65.184.25.198 -1231884104 -spedgenius - - - - -http://sourceforge.net/support/tracker.php?aid=2508886 -2508886 -1 -1026581 -100 -randy_u -nobody -nobody -1231995547 -0 -5 -project cost -
I have recently been designing a couple of devices and using Kicad to design them; I have to say it’s been a quite enjoyable experience. This program is top quality especially considering its price. - -The most tedious part of the engineering process has been the importing of data on each part into a database or into Kicad to document the bill of materials and calculate units costs. I have probably spent more time doing that than actually designing circuits and pcbs. - -I had an idea that would make the process significantly easier and much faster but would require effort on both the developers of Kicad and parts suppliers. - -My idea is fairly simple. On each supplier part page have a link to a file, probably XML, that contains all of the data the supplier has (or wants to publish) on that part. This would require the creation of some documented, hopefully open source developed, XML structure that can be easily generated from manufacturer data or suppliers existing databases and can be imported into Kicad. The user would be able to select the part in EESchema or CVpcb (and back annotate into EESchema) to allow PCBnew to put the correct package footprint on the pcb when the netlist is read. This would allow the Bill of Materials to be more robust and the addition of a project cost sub-module in EESchema (based on user selection of quantity). - -Off the top of my head the XML structure would look something like this: - -<Manufacturer> -<Manufacturer Part Number> -<Part Group> -<Part Type> -<Part Subtype> -<Part Value> -<Mount Type> -<Package> -+<Suppliers> - <Supplier Name> - <Supplier Part Number> - +<Price> - <Qty_Start> - <Qty_End> - <Price> -<Datasheet Link> -+<Additional Specifications> - <Spec Name> - <Spec Value> - -I’m sure there’s plenty more to add to that structure and I’m pretty sure that there's plenty of people that have experience that would be beneficial to the creation of the standard structure. - -Even if the suppliers don't initially subscribe to this idea us users could create and share these XML files and hopefully this concept (open standard) would be adopted by not just Kicad but all major EDA software applications - then eventually the suppliers would come on board. -
-0 - - -3349932 -nobody -1232035877 -
To go one step further, integrate with one or more of the open source ERP/CRM systems such as Compiere.
- - -3409728 -nobody -1232848173 -
What it is really needed is the company_part_number because this can be the index to the data base where all the other data are stored. -One of the field of the component properties should be Pno. and may be one fieeld can be Manufacturer P No. -No part should be used if does not have a company part number. For one time circuit you can use the project number followed by a sequential number. -Gianni -
- - -3422425 -randy_u -1233074093 -
ADDITION: -I talked to Mouser and they said they would be interested in pursuing this concept.
- - -3574845 -nobody -1237004477 -
SUre !!
- - -3915078 -bennett78 -1267321183 -
Check out octpart.com & http://octopart.com/api/documentation. - -This solves the supplier, procurement side by specifiying the exact part of interest -but not the symbol or footprint selection for each part !
- - - - - - -7451518 -IP -Artifact Created: 69.2.166.18 -1231995547 -randy_u - - -7457212 -IP -Comment Added: 66.162.122.39 -1232035877 -nobody - - -7533817 -IP -Comment Added: 70.20.101.22 -1232848173 -nobody - - -7557478 -IP -Comment Added: 69.2.166.18 -1233074097 -randy_u - - -7914831 -IP -Comment Added: 206.167.181.19 -1237004477 -nobody - - -9221531 -IP -Comment Added: 76.76.79.173 -1267321183 -bennett78 - - - - -http://sourceforge.net/support/tracker.php?aid=2536238 -2536238 -1 -761685 -100 -nobody -nobody -nobody -1232922935 -0 -5 -rotate key in libedit -
It would be nice if the rotate key (r) would also work in libedit. Now you need to press 'e' and choose the direction. Simply pressing 'r', just like in eeschema, works a lot quicker. - -Another suggestion: to place a pin, you first have to pick a location, then the properties dialog comes up, after pressing ok, the pin is still not placed, you have to pick the location *again*! -Why not placing the pin at the first picked location?
-0 - - -3957148 -stambaughw -1270749235 -
R key rotates drawing objects in library editor in release 20100313. The pin placement suggestion actually makes this two feature requests. If the second part is moved to a separate request, this request can be closed.
- - - - - - -7538965 -IP -Artifact Created: 80.101.23.250 -1232922935 -nobody - - -9382162 -IP -Comment Added: 162.83.115.135 -1270749235 -stambaughw - - - - -http://sourceforge.net/support/tracker.php?aid=2540776 -2540776 -1 -1026580 -100 -randy_u -nobody -nobody -1233074687 -0 -5 -Auto ERC and Netlist Generation -
I would like an option (set via preferences; options dialog box) for EESchema automatically to perform an ERC (hidden if successful) and Netlist generation upon the exiting of EESchema - I wouldn't mind if it gives me a dialog box asking me if I am sure I want to do it - where if I select NO it will just exit. If the option is not set in then the program exits normally. - -I know ERC will fail if a component is not annotated - no need to add anything new there. If the ERC does fail the user should have the option of ignoring the failure and exiting (without updating the netlist) or aborting the exit and fixing the problem. - -I think this should be done before the save dialog.
-0 - - - - - - -7557546 -IP -Artifact Created: 69.2.166.18 -1233074687 -randy_u - - - - -http://sourceforge.net/support/tracker.php?aid=2542994 -2542994 -1 -1026580 -100 -tobias-weber -nobody -nobody -1233148072 -0 -5 -Ability to drag wires -
I like to drag existing wires in a way that connected wires drag with it. For example, I can drag parts by pressing "G" and the connected wires follow the moving part. But I cannot move/drag singe wires. I would like dragging the wires on a rectangular basis. - -That means: horizontal wires can only be dragged vertically and vertical wires can only be dragged horizontal. - -It makes the Rearrangement of parts and wires much easier. Usually when moving whole areas only a bit within EESCHEMA, wire connections break when moving and must be reconnected lateron. I'd rather drag the part and then rearrange some wire if nessecary by dragging instead of reconnecting them all. - -It also helps to move away wires when an additional wire should be added on a place where it's aleady packed. - -BTW: KICAD is an excellent project! -
-0 - - - - - - -7563142 -IP -Artifact Created: 217.5.214.130 -1233148072 -tobias-weber - - - - -http://sourceforge.net/support/tracker.php?aid=2545362 -2545362 -2 -1026581 -100 -nobody -nobody -jerryjacobs -1233232281 -1246881078 -5 -Version Management -
Guys, seriously, this thing needs some version management. I don't know how others are using KiCad but if you have multiple projects and several models/versions of projects, that in some cases depend certain versions of other projects, it's very painful to manage. -Maybe it's as simple as adding a project version number and incrementing it whenever you archive - regardless of how it's done I need some versioning support.
-0 - - -3691816 -jerryjacobs -1246881078 -
Look at GIT,Subversion,CVS
- - - - - - -7571460 -IP -Artifact Created: 69.2.166.18 -1233232281 -nobody - - -8440173 -IP -Comment Added: 212.178.132.86 -1246881078 -jerryjacobs - - -8440174 -status_id -1 -1246881078 -jerryjacobs - - -8440175 -allow_comments -1 -1246881078 -jerryjacobs - - -8440176 -close_date -0 -1246881078 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2557155 -2557155 -1 -761685 -100 -matong -nobody -nobody -1233585544 -0 -5 -Module Editor, ruler -
Module Editor. -Please add the ruler or the information about length of graphic line, polygon etc.
-0 - - - - - - -7601961 -IP -Artifact Created: 85.128.50.246 -1233585545 -matong - - - - -http://sourceforge.net/support/tracker.php?aid=2580257 -2580257 -1 -1026579 -100 -brumbarchris -nobody -nobody -1234124716 -0 -5 -Change Layer names -
Following a discussion on the KiCAD Yahoo groups, I reached the conclusion that the sequence of layers, from top to bottom, would be as follows: - -Top Layer: Component -Next Layer: Inner_L14 -Next Layer: Inner_L13 -... -... -... -Next Layer: Inner_L1 -Bottom Layer: Copper - -This is very un-natural, as one would count the inner layers incrementally from top to bottom. Ideally, KiCAD would allow customizing layer names for a given project, but if this necessitates too much effort, then a more natural fixed layer naming scheme should be adopted, something like: - -Top Layer: Top_Copper -Next Layer: Inner1 -Next Layer: Inner2 -... -... -... -Next Layer: Inner14 -Bottom Layer: Bottom_Copper - -This should also be reflected in repositioning the layer order in the color window (attached, for reference). - -Regards, -Cristian
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=312611&aid= -312611 -layer_stack-up.PNG -layer stack-up -32477 -image/png -1234124717 -brumbarchris - - - - -7655726 -IP -Artifact Created: 212.2.180.1 -1234124717 -brumbarchris - - -7655727 -File Added -312611: layer_stack-up.PNG -1234124717 -brumbarchris - - - - -http://sourceforge.net/support/tracker.php?aid=2584336 -2584336 -1 -1026579 -516023 -cfdev -nobody -nobody -1234256302 -0 -5 -Unroute component -
Hi all, - -it's would be nice to have on right click menu (on component) "unroute component".Currently, to do this, I use the deletion of the block but it's not good for that. -(sample: popupmenu -> U10 -> Move,Drag....Unroute) - -thanks if you can do this. - -Cfdev
-0 - - - - - - -7675677 -IP -Artifact Created: 90.52.62.14 -1234256313 -cfdev - - - - -http://sourceforge.net/support/tracker.php?aid=2609766 -2609766 -1 -1026579 -100 -sebastianjardi -nobody -nobody -1234894292 -0 -5 -Not Scaled Printing in Linux, UBUNTU -
Hi: - -Second: I have found a bug in the Scale adjustment for printing in Linux, Ubuntu 8.04. - -When I try to print a PCB, it isn't print to scale 1:1, using Acurate Scale option. - -Then I use X Scale Adjust and Y Scale Adjust option to adjust the scale.After that, the Y Scale prints correct, but the X Scale don't have adjusted to X Scale Adjust value. Its seem to be adjusted to the Y Scale Adjust value. - -Thanks and Regards. - -Sebastián. -
-0 - - - - - - -7731278 -IP -Artifact Created: 79.153.201.43 -1234894292 -sebastianjardi - - - - -http://sourceforge.net/support/tracker.php?aid=2687297 -2687297 -1 -100 -100 -arius-marius -nobody -nobody -1237080965 -0 -5 -Dialog to create SVG file -
Would be nice having a file chooser being able to quickly navigate to a different folder other than the current project folder. -Also, if the file extension (*.svg) was not specified it could be appended automatically to the given file name. - -This goes for eeschema and pcbnew. - --arius-
-0 - - - - - - -7918214 -IP -Artifact Created: 78.49.15.52 -1237080965 -arius-marius - - - - -http://sourceforge.net/support/tracker.php?aid=2689643 -2689643 -1 -100 -100 -yneko -nobody -nobody -1237270846 -0 -5 -Separate power pins -
As for logic ICs, connecting power pin onto the symbol is not suitable. Please make possible to separate power pins from their symbols, like EAGLE.
-0 - - -3665205 -daveplatt -1243643920 -
This is actually possible in kicad, although I don't think the way it's implemented is necessarily the same -as is true in Eagle. - -What you need to do, is create a component module which has two or more units... units that are *not* locked together as being identical. Draw one module unit with the logic, analog, etc. pins. Draw another unit which has just the power and ground pins, with a small rectangle symbol (e.g.) to anchor them. - -Now, to get a complete copy of the component on the board, place *two* of them. Use the "Edit component / unit" popup menu to change one of the two to "Unit B" (e.g. the one with the power pins). Now, use "Edit component / reference" on both of them, to manually annotate them with the same component name (e.g. U10). - -You can now drag U10B (e.g.), with the power pins, down to a corner of one of your sheets, placing it out of the way of your main schematic, and tie it (and other such components) to power busses. - -As an example: download the "MAXIM" library (which was converted from Eagle) and take a look at the MAX238 component. The A and B units are very different - the former has all of the data pins, and the latter has just power and ground.
- - - - - - -7930892 -IP -Artifact Created: 203.141.143.22 -1237270846 -yneko - - -8327537 -IP -Comment Added: 204.176.49.46 -1243643921 -daveplatt - - - - -http://sourceforge.net/support/tracker.php?aid=2691772 -2691772 -1 -1026580 -100 -wolverine222 -nobody -nobody -1237382340 -0 -5 -Library refresh -
Hello, - -The kicad suite has been improving at a serious pace, and in the latest release candidate there was already a feature that is VERY handy - the "Reset to library defaults" in the component properties, despite not working correctly in the 20090216-RC6 yet. - -However, there is another feature that is related and would also be VERY helpfull. Since most of the times i edit the libraries directly in the .lib files (it's just easier to copy/paste the resistors, capacitors, etc), however i allways need to restart eeschema to reload the libraries. I believe that could be a button that would just re-read the library files. - -Thanks for the good work anyway.
-0 - - -3625046 -nobody -1240242119 -
And also the ability to reload ALL components to the library defaults would be a nice feature.
- - - - - - -7945996 -IP -Artifact Created: 213.63.0.163 -1237382340 -wolverine222 - - -8185815 -IP -Comment Added: 213.63.0.163 -1240242119 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2728236 -2728236 -1 -100 -100 -nobody -nobody -nobody -1238763882 -0 -5 -embedded scriping -
Why not embed scripting engine (Python, Lua, Guile) ? -I think for such project is a must - develop API for all functions (common for all tools (sch,pcb,lib) - GUI, drawing primitives, etc) with binding to script engine, rewrite most functionality in higher-level language, made possibility to users to create scripts (creating sch/pcb elements, placing, routing). -Only basic primitives (line, ellipse, arc, polyline, polygon, text, group) enough for creation of any abject, complex objects can be created as group of primitives. Objects can have any number of attributes, available for user editing (coordinates, colors, layer, refdes).
-0 - - - - - - -8075067 -IP -Artifact Created: 194.187.230.100 -1238763882 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2731447 -2731447 -1 -1026579 -100 -nobody -nobody -nobody -1238860573 -0 -5 -Different clearance by trace -
Right now you can select a 'global' clearance value for track, and that is used during routing and ERC of the board. On power design there are different rules for different track, i.e. a 240 VAC track must have at least 4.8mm of clearance, which are of course too much for anything that's surface mounted (well, some inductor maybe :P) - -I'd like to see a user interface exactly like that of the track width to set the clearance for segment/track/net/everything
-0 - - - - - - -8086733 -IP -Artifact Created: 87.6.47.114 -1238860573 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2741292 -2741292 -1 -100 -100 -nobody -nobody -nobody -1239125484 -0 -5 -usability improvements to common standards -
- panning : - - 'c' key moves view center to cursor position; - - moving mouse with pressed right key does panning; -- mouse wheel : - - without pressed buttons shifts up-down; - - with 'Shift' - left-right; - - with 'Ctrl' - changes view scale; -- rotation : - - 'r' key rotates selected element/block clockwise by 45 degrees; - - 'Shift-r' rotates counterclockwise; -- scaling : - - '-'/'_' scales down; - - '='/'+' scales up; -
-0 - - -3641947 -nobody -1241103741 -
that would be very cool!
- - -3650478 -nobody -1241843735 -
Common Standards? - -I think the mouse wheel priority without pressed key is wrong! -It should remain as it is: without pressed buttons zooms in and out of cursor position! -This is already implemented very well and is enough as it allows to get to any point very quickly! - -But lets add the following to the list: Ctrl-c, Ctrl-v, Ctrl-x for copy, paste and cut. -These of course require a standard based _Object Selection System_ where: - -The user is able to select items (in Schematic, PCB or Library editors) that then are being highlighted differently for the time they are selected! - -Ideally before selection dynamic highlighting of elements having the mouse pointer above them indicates a selectable item and it shows its selectability by some form of highlight! - -If shift or control is pressed: further refining of the selection should be possible! -If a right click is performed: access to methods of the selected objects should be given, and applied to the whole selection as applicable! - -A drag gesture should directly drag the element it is executed on -If items are selected and the drag initiates on one of the selected items these should be dragged all together. - -A right click on selected objects asks the Objects which methods can be applied all of them. - -The marque 'lasso' as it turns up currently should _only happen_ when the drag is initiated above clean deskspace (above nothing selectable)! It should not by default result in a question to move, but if a drag follows on one of the selected components the drag should be performed on all selected components! -
- - - - - - -8105514 -IP -Artifact Created: 194.187.230.100 -1239125484 -nobody - - -8232701 -IP -Comment Added: 128.113.122.124 -1241103741 -nobody - - -8266604 -IP -Comment Added: 201.143.195.217 -1241843735 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2743328 -2743328 -1 -1026581 -100 -cfdev -nobody -nobody -1239176866 -0 -5 -Save the project as -
hi, - -it's possible to have in Kicad "Save the project and files as". - -this fonction will create an copy of the actual project and files, to an other name. - -sample: -my_project.pro -my_project.sh -my_project.bdr - -to - -my_New_project.pro -my_New_project.sh -my_New_project.bdr - -Thanks -
-0 - - - - - - -8111363 -IP -Artifact Created: 90.27.113.11 -1239176879 -cfdev - - - - -http://sourceforge.net/support/tracker.php?aid=2776401 -2776401 -2 -1026580 -100 -wolverine222 -bennett78 -bennett78 -1240242733 -1267318930 -5 -Annotation options -
It would be interesting to have an option to annotate the components in a diferent manner. -For example, include padding (R001, R002, R003), including the sheet number (R101, R201, etc) - -Currently, the only option to do this is to find the components that are annotated first and then letting them increment the numbers.
-0 - - -3655490 -nobody -1242476177 -
It is a good idea, many times I develop circuits with more than 1 sheets and its feature could help a lot. -
- - -3915042 -bennett78 -1267318930 -
Sheets in EESchema are hierarchical, so the sugession doesn't make sense, there is no sheet 1,2,etc. -I would recommend using the find feature. - -I better request would be - next to each signal, provide a hot link to the next reference of this signal.
- - - - - - -8185866 -IP -Artifact Created: 213.63.0.163 -1240242734 -wolverine222 - - -8289038 -IP -Comment Added: 187.10.92.142 -1242476177 -nobody - - -9221486 -IP -Comment Added: 76.76.79.173 -1267318930 -bennett78 - - -9221487 -status_id -1 -1267318930 -bennett78 - - -9221488 -assigned_to -100 -1267318930 -bennett78 - - -9221489 -allow_comments -1 -1267318930 -bennett78 - - -9221490 -close_date -0 -1267318930 -bennett78 - - - - -http://sourceforge.net/support/tracker.php?aid=2787280 -2787280 -1 -100 -100 -phili -nobody -nobody -1241533273 -0 -5 -Import/Export "dxf" for contours & drawings -
Is it possible to implement dxf import & export, particulary for contour boards and drawings ... It could be fine to have these stuff . Actually, the "plot" menu only purpose plotting to popscript, Gerber or HPGL they are very usefull format, but dxf could largely be too, particulary to develop mechanicals with 2D (or 3D ) DAO ( like Qcad for example ...) with compatibillity with electronics ... And I didn't find anything to import mechanical drawings ...
-0 - - -3667144 -nobody -1243892046 -
I second that, but while doing DXF, I'd also add an option to import raster format background (.bmp, .png, pnm, even JPEG). -I will be willing to contribute with coding if that can be done with reasonable effort. I have not looked at the code yet, so, I don't have an idea how that may fit into the existing desgn. -vleolml@gmail.com
- - - - - - -8249366 -IP -Artifact Created: 82.250.108.40 -1241533273 -phili - - -8335322 -IP -Comment Added: 195.98.166.154 -1243892046 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2794887 -2794887 -1 -1026580 -100 -nobody -nobody -nobody -1242921753 -0 -5 -rubberband wires keeping othogonality when dragging devices -
It would be nice if when dragging a device or a wire segment in any direction , all the attached wires would extend only horizontaly and verticaly if orthogonality button is set.
-0 - - - - - - -8302677 -IP -Artifact Created: 90.4.144.48 -1242921753 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2794902 -2794902 -1 -1026579 -100 -nobody -nobody -nobody -1242922783 -0 -5 -add option "keep drill holes open" -
For hobbist that use to home made pcb with an hand drilling process, add an option to have fixed size uncoppered areas in all the drilled the pads center, (simulating drill holes on the film) - - As the copper would be etched in this unprotected area, it would help to center the drill for the manual operation - -AFAIK, this option is called "keep drill holes open" in ORCAD and is done by an external script in EAGLE
-0 - - -3704725 -nobody -1248185646 -
I agree with this - it's really difficult to drill manually a board created with Kicad, when the pads are the same size with the traces or less, or when they are embedded in a copper zone. -In CADSTAR I can solve this by selecting annulus pads (ring-shaped) instead of circle pads. This can be another option.
- - - - - - -8302733 -IP -Artifact Created: 90.4.144.48 -1242922783 -nobody - - -8493240 -IP -Comment Added: 194.102.139.216 -1248185646 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2798092 -2798092 -1 -761685 -516023 -jerryjacobs -nobody -nobody -1243542428 -0 -5 -Zooming and Selecting Objects -
I created some movies to compare kicad vs eagle/pcb zooming. (View best with VideoLan Player) -http://www.bassmasters-heaven.nl/kicad/ - -Bad about kicad zooming: - + If cursor placed to a point and then zoom it "jumps" to the place and centers the cursor on drawing area. - + Big zonefills flash if zooming. ( Try coldfire demo ) - -Also to select a object that it will highlight like in eagle (and/or select multiple other objects (footprints,nets,etc). And then you can move it indepented from the other objects instead of irritating about move blocks.
-0 - - - - - - -8323760 -IP -Artifact Created: 84.25.219.10 -1243542428 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2802441 -2802441 -2 -1026582 -100 -over2there -nobody -jerryjacobs -1244362531 -1246878069 -5 -No single error messages any more - instead: summery -
Hi, as I use a lot of modules for my project and they have mdc-File I get an error message, that the mdc file is not found. But this forces me - when I open cvpcb - to click one million times "okay". This costs a lot of time. I would wish to have a text area where all error messages are displayed and I only need to click one time okay. -Shouldn't be a to big thing, or? - -By the way: I'm using the svn revision 1806.
-0 - - -3691333 -jerryjacobs -1246816783 -
Closed bug SVN 1871 by me
- - - - - - -8350730 -IP -Artifact Created: 217.233.218.215 -1244362531 -over2there - - -8437683 -IP -Comment Added: 84.25.137.47 -1246816783 -jerryjacobs - - -8439971 -status_id -1 -1246878069 -jerryjacobs - - -8439972 -close_date -0 -1246878069 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2804192 -2804192 -1 -1026580 -516023 -cfdev -nobody -nobody -1244644327 -0 -5 -Copy Label -
Hi all, - -is it possible to have in the fonction of click right "copy the label" - -it's very good to avoid to make a mistakes about differents labels. - -Thanks -good day - -Cyril
-0 - - - - - - -8362261 -IP -Artifact Created: 90.52.202.205 -1244644328 -cfdev - - - - -http://sourceforge.net/support/tracker.php?aid=2804199 -2804199 -1 -1026580 -516023 -cfdev -nobody -nobody -1244644731 -0 -5 -Gaphic line discontinuous -
is it possible to have the choice between "line" "Discontinuous" "Dot" for graphical line ? -(wxSOLID , wxDOT_DASH ...) - - -thx -Cyril
-0 - - - - - - -8362283 -IP -Artifact Created: 90.52.202.205 -1244644731 -cfdev - - - - -http://sourceforge.net/support/tracker.php?aid=2804696 -2804696 -1 -1026579 -516023 -cfdev -nobody -nobody -1244710365 -0 -6 -Line To Arc -
hi, - -is it possible to transforme an Line(2pts) in Arc(3pts), Like ORCAD software. -it's an very good feature when we don't know the center of arc. -see attach file. - -thanks a lot -Cyril - -++
-0 - - -3675327 -cfdev -1244791763 -
ho, I saw this fonction in libedit !!!!!! good but, -why it's different in pcbnew ????
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=330592&aid= -330592 -arc.png - -15104 -image/png -1244710375 -cfdev - - - - -8364883 -IP -Artifact Created: 90.52.202.205 -1244710371 -cfdev - - -8364885 -File Added -330592: arc.png -1244710383 -cfdev - - -8367960 -IP -Comment Added: 90.52.202.205 -1244791763 -cfdev - - -8367991 -priority -5 -1244792347 -cfdev - - - - -http://sourceforge.net/support/tracker.php?aid=2807226 -2807226 -3 -1026580 -100 -briansidebotham -nobody -briansidebotham -1245166159 -1245166249 -5 -Relative Library path is ignored -
If when editing the Preferences->Library dialog, a relative path is used for the Default library file path, KiCad successfully navigates to the correct directory when the Add button is used to add a library. However, instead of adding the selected library name, it adds the complete file path instead. - -If the .pro preferences file is edited by hand the relative library path works fine.
-0 - - -3678261 -briansidebotham -1245166249 -
Added this to the feature tracker - was meant for the bug tracker!! -
- - - - - - -8380470 -IP -Artifact Created: 87.74.132.43 -1245166160 -briansidebotham - - -8380477 -IP -Comment Added: 87.74.132.43 -1245166249 -briansidebotham - - -8380478 -status_id -1 -1245166249 -briansidebotham - - -8380479 -allow_comments -1 -1245166249 -briansidebotham - - -8380480 -close_date -0 -1245166249 -briansidebotham - - - - -http://sourceforge.net/support/tracker.php?aid=2810163 -2810163 -1 -1026579 -100 -reshpe63 -nobody -nobody -1245664383 -0 -5 -Clearance track-to-track, track-to-via, via-to-via -
Kicad (version 20090216) in the "Dimensions->Tracks and Vias" menu, has only one Clearance type for the ERC; is it possible to have the following clearance types: track-to-track, track-to-via, track-to-pad, via-to-via, via-to-pad, pad-to-pad?
-0 - - - - - - -8396740 -IP -Artifact Created: 87.25.117.224 -1245664383 -reshpe63 - - - - -http://sourceforge.net/support/tracker.php?aid=2810796 -2810796 -1 -1026580 -100 -hauptmech -nobody -nobody -1245749265 -0 -5 -Netlist creation uniques heirarchial annotation labels -
Trying to use two existing schematics as heirarchial sub-schematics of another design does not work. The sub-schematics already have annotation labels and PCB layouts that depend on them. - -One solution is to have the netlist generating logic add a unique letter for each subschematic.
-0 - - - - - - -8399627 -IP -Artifact Created: 118.90.106.51 -1245749265 -hauptmech - - - - -http://sourceforge.net/support/tracker.php?aid=2823288 -2823288 -1 -1026579 -100 -nobody -nobody -nobody -1247861927 -0 -5 -no hebrew -
i cant seem to write hebrew labels in the linux version
-0 - - - - - - -8482603 -IP -Artifact Created: 79.183.112.193 -1247861927 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2825238 -2825238 -1 -1026579 -516023 -cfdev -nobody -nobody -1248252878 -0 -5 -Show Layer -
Hi all, -to choice the colors to display a layer is not fast enough ! - -It's possible to have an menu with hotkey to show or not an Layer. -for example ctrl+1 show only the layer component. - -this feature is good when there is 4 or more layers...(see attach file) - -
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=336042&aid= -336042 -4layers.png - -57397 -image/png -1248252878 -cfdev - - - - -8496152 -IP -Artifact Created: 90.52.57.77 -1248252878 -cfdev - - -8496153 -File Added -336042: 4layers.png -1248252879 -cfdev - - - - -http://sourceforge.net/support/tracker.php?aid=2826465 -2826465 -1 -1026580 -100 -evbuilder -nobody -nobody -1248425788 -0 -5 -cmos4000 lib error -
4072 is listed as a dual 4-input NAND. Shoudn't this be a dual 4-input OR? -I think the 4012 is the dual 4-input NAND.
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=336371&aid= -336371 -cmos4000.lib -updated file -32803 -application/octet-stream -1248425788 -evbuilder - - - - -8503063 -IP -Artifact Created: 118.92.207.91 -1248425788 -evbuilder - - -8503064 -File Added -336371: cmos4000.lib -1248425788 -evbuilder - - - - -http://sourceforge.net/support/tracker.php?aid=2831480 -2831480 -1 -100 -100 -frohro -nobody -nobody -1249306303 -0 -5 -Graphic Text (Comment) Formatting -
Hi, - -I can't seem to make anything but a one line graphic text comment. I don't want multiple comments because They will eventually be deleted when all the issues are addressed. (I use them like sticky notes to note issues I need to address later.) Could this be added, or is there a better way to do this? - -Thanks, - -Rob
-0 - - - - - - -8534091 -IP -Artifact Created: 66.62.174.7 -1249306303 -frohro - - - - -http://sourceforge.net/support/tracker.php?aid=2832296 -2832296 -1 -1026580 -100 -nobody -nobody -nobody -1249422428 -0 -5 -Preferences Form Update -
I'd like to update the current Preferences menu into a tabbed (wxListbook) form to live in Edit->Preferences as is the norm for the majority of Linux applications I've come across. I'm willing to take this on myself and would welcome any suggestions. I've used Kicad extensively for school (schematic capture as well as PCB design and production) and want to help give back, but don't feel confident touching the more critical parts.
-0 - - -3718117 -superlou -1249423011 -
Sorry, thought I had logged in. Apparently hadn't. Does anyone know how to associate me with the above post?
- - - - - - -8539061 -IP -Artifact Created: 67.87.133.3 -1249422428 -nobody - - -8539080 -IP -Comment Added: 67.87.133.3 -1249423011 -superlou - - - - -http://sourceforge.net/support/tracker.php?aid=2835205 -2835205 -1 -1026579 -100 -superlou -nobody -nobody -1249943856 -0 -5 -Show netnames on PCB traces -
Sorry to add to the pile of requests and it's something I'm hoping to work on in the future (but don't want to forget about it now). - -An option to show netnames on top of traces in PCBNew can help when you are routing and trying to avoid cross-talk between critical nets. Would be good to filter between user named nets and auto named nets to keep from cluttering the screen too much.
-0 - - - - - - -8555396 -IP -Artifact Created: 67.87.133.3 -1249943856 -superlou - - - - -http://sourceforge.net/support/tracker.php?aid=2836769 -2836769 -1 -761685 -100 -gregoryhicks -nobody -nobody -1250150798 -0 -5 -Front Panel Layer -
Add two front panel layers to enable silk screen and hole centers in a user defined panel. - -This could extend to sides and backs of various boxes and enclosures.
-0 - - - - - - -8564316 -IP -Artifact Created: 124.171.196.23 -1250150798 -gregoryhicks - - - - -http://sourceforge.net/support/tracker.php?aid=2839745 -2839745 -1 -1026582 -100 -nobody -nobody -nobody -1250617328 -0 -5 -Kicad Tutorial -
Much appreciated, however towards the end of the tutorial key images are missing making progress to the end difficult. Thanx
-0 - - - - - - -8583054 -IP -Artifact Created: 70.49.190.209 -1250617328 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2840152 -2840152 -2 -100 -100 -jerryjacobs -nobody -jerryjacobs -1250673424 -1257527868 -5 -Signal grouping -
Hi Jerry, - -I would have a feature request, but I don't think it's that easy. At the moment you can chose your pcb size and via size, etc. in the drop-down menu. How about grouping this pcb sizes and vias to groups, so you only have to change groups. Eg. one group "small signal" or "power signal". It would be great if I (as a user) could set, edit and delete such connection groups. For drawing pcbs i just select the group and here we go. Could this be possible? What do you think about this idea? - -Thanks -Michael
-0 - - -3799453 -jerryjacobs -1257527868 -
Work in progress -> Net classes.(design rules)
- - - - - - -8585933 -IP -Artifact Created: 84.25.137.47 -1250673424 -jerryjacobs - - -8854788 -IP -Comment Added: 84.25.204.235 -1257527868 -jerryjacobs - - -8854789 -status_id -1 -1257527868 -jerryjacobs - - -8854790 -allow_comments -1 -1257527868 -jerryjacobs - - -8854791 -close_date -0 -1257527868 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2843726 -2843726 -1 -1026580 -100 -nobody -nobody -nobody -1251136992 -0 -5 -Highlight Nets -
It would be absolutely wonderful if there would be some highlight of nets (wires and/or busses). Viewing nets will gladly keep the program in great condition. Keep in mind this is a feature, a great feature that most programs of its kind currently have and certainly adds another professional look. Attached is an example of the project I am working on with KiCAD. - -When a user right clicks on a wire or bus shape, add one display member to the drop down box that says "View Net". -After the user clicks "View Net", all surrounding cables are highlighted with the shown picture color. - -Regards, -Juan Miguez -
-0 - - -3855931 -mrluzeiro -1263299782 -
Add highlight to PCBeditor too...
- - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=340378&aid= -340378 -Highlight Nets.jpg -Example of Viewing Nets, highlighting wires in EESchema -64990 -image/jpeg -1251136994 -nobody - - - - -8601275 -IP -Artifact Created: 66.246.152.4 -1251136993 -nobody - - -8601276 -File Added -340378: Highlight Nets.jpg -1251136994 -nobody - - -9062435 -IP -Comment Added: 83.240.238.169 -1263299787 -mrluzeiro - - - - -http://sourceforge.net/support/tracker.php?aid=2856247 -2856247 -1 -1026579 -100 -spflanze -nobody -nobody -1252605360 -0 -5 -IPC-7351B Footprints -
I would like Pcbnew to interface directly to the database of footprints that come with the "IPC-7351B LP Viewer" available at: -http://pcbmatrix.com/Products/LPSoftware/LPViewer/ -http://landpatterns.ipc.org/default.asp -This library is vast and free. The ability to use it directly in Kicad would save a lot of labor.
-0 - - -3762903 -maxgaukler -1254121059 -
Sorry, but the library you mentioned is not compatible with kicad's license: -"This software, any upgrades, or license information cannot be distributed or re-sold. PCBM is the sole entity authorized to assign licenses to use this software."
- - - - - - -8656285 -IP -Artifact Created: 66.92.40.104 -1252605360 -spflanze - - -8714423 -IP -Comment Added: 88.65.61.105 -1254121059 -maxgaukler - - - - -http://sourceforge.net/support/tracker.php?aid=2859048 -2859048 -2 -1026580 -100 -nobody -nobody -jerryjacobs -1252984232 -1257527600 -5 -Default reference numbering -
First, thank you for such a great project! - -I found that manually setting the reference numbers on a large number of resistors is very time consuming (in eeSchema). It would be so nice to have the -reference number of each component of an already existing type increase by one as one more component is placed in the schematic. I think most people anyway choose R1, R2, R3... by default, so why not have this simply done by default. The same can be done with transistors, Q1, Q2, ..., or capacitors, C1, C2, ... -it would save a lot of time, and I'm sure it would be a simple feature to add. - -Thank you again!
-0 - - -3799446 -jerryjacobs -1257527600 -
This is added, see the icon next to the Netlist generaton button/icon. The function is called schematic annotation (or automatic annotate)
- - - - - - -8670292 -IP -Artifact Created: 216.99.58.108 -1252984232 -nobody - - -8854767 -IP -Comment Added: 84.25.204.235 -1257527600 -jerryjacobs - - -8854768 -status_id -1 -1257527600 -jerryjacobs - - -8854769 -allow_comments -1 -1257527600 -jerryjacobs - - -8854770 -close_date -0 -1257527600 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2865752 -2865752 -2 -1026579 -100 -nobody -nobody -jerryjacobs -1253801719 -1257527418 -5 -Undo and redo command -
It is very unsual that in win version of Kicad are no UNDO and REDO command, Please make this veru usefull function, Thanks
-0 - - -3799442 -jerryjacobs -1257527418 -
Already added. -See snapshots for testing, will be in next release.
- - - - - - -8702814 -IP -Artifact Created: 213.155.231.66 -1253801719 -nobody - - -8854751 -IP -Comment Added: 84.25.204.235 -1257527418 -jerryjacobs - - -8854752 -status_id -1 -1257527418 -jerryjacobs - - -8854753 -allow_comments -1 -1257527418 -jerryjacobs - - -8854754 -close_date -0 -1257527418 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2865755 -2865755 -2 -1026579 -100 -nobody -nobody -jerryjacobs -1253802255 -1257527734 -5 -Group movement command -
If I use group movement command, there is inconveniently view. I see only a border of this area but I dont see devices inner this area. So I cant precioslly locate all group of parts. In EEschema is this command allright, so I dont know why is this "bug" in PCBnew
-0 - - -3799448 -jerryjacobs -1257527729 -
Added bug in TODO.txt
- - - - - - -8702839 -IP -Artifact Created: 213.155.231.66 -1253802255 -nobody - - -8854773 -IP -Comment Added: 84.25.204.235 -1257527729 -jerryjacobs - - -8854775 -status_id -1 -1257527734 -jerryjacobs - - -8854776 -allow_comments -1 -1257527734 -jerryjacobs - - -8854777 -close_date -0 -1257527734 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2869825 -2869825 -1 -1026579 -100 -negative2404 -nobody -nobody -1254235765 -0 -5 -Internal nets in footprints -
I would be extremely useful feature to allow internal connection of pins in PCB footprint. -This would help in designing boards with devices that have internal pads connected (e.g. pusbuttons). -This would automatically solve feature request #2011581 as bridge would be a 0805/1205 footprint with internally connected pads. -Other solution would be to make the internal nets available in EESCHEMA components. -I don't know which is better or easier to implement but each have both advantages and disadvantages. -For example: -- PCB footptints shall be independent on chip type (e.g. DIP) so it would be better to have this in EESCHEMA -- EECHEMA components builds a schematic so pusbutton just connects 2 pins, but the PCB footprint consists usually of 2 pairs of connected pins so routing woule be easier if PCBNEW knows that these pins are connected. -- interconnection of pins in PCB footprints would be extremely nice because for adding a bridge, one could add a '1206 bridge' footprint and connect pins to a single net and PCB verification tool would report no error. - -If both of the ideas are implemente, there would be automatically new feature: macro circuits. One could make a set of commonly used circuits and its footprints which would speedup board design. - -It would be very kind of you if you consider the feature I have described. - -Kind regards.
-0 - - -3764535 -nobody -1254303703 -
Quick potential solution for internal nets in PCB layout could be assigning a kind of 'local net names' in each pin. e.g. assign pin1 and pin2 net name like $local_interconn would affect a connection of pin1 and 2. -I do not know whether the same solution is possible in EESCHEMA, but I think it is.
- - - - - - -8718900 -IP -Artifact Created: 78.133.245.162 -1254235765 -negative2404 - - -8722799 -IP -Comment Added: 78.133.245.162 -1254303703 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2869830 -2869830 -1 -1026579 -100 -korp -nobody -nobody -1254235971 -0 -5 -Option for other origin than the fixed page origin -
It would be nice with an option in PCBNEW to relate to the origin set by "Offset adjust for drill and place files." or the latest relative coordinates reset instead of only the fixed page origin. It is useful especially when moving components by right clicking it, Footprint (Component), Edit. And also when editing the position, or start and end of graphical elements like lines, arcs etc.
-0 - - - - - - -8718909 -IP -Artifact Created: 194.71.159.2 -1254235972 -korp - - - - -http://sourceforge.net/support/tracker.php?aid=2875556 -2875556 -2 -1026580 -100 -nobody -nobody -jerryjacobs -1255077632 -1257527038 -5 -DragnDrop between windows -
There should be the ability to choose parts or the whole drawing and transfer it via Drag&Drop to another EESchema-Window. That would make re-using of former drawings more easy.
-0 - - -3799437 -jerryjacobs -1257527038 -
Added in TODO.txt
- - - - - - -8753536 -IP -Artifact Created: 193.174.73.57 -1255077632 -nobody - - -8854728 -IP -Comment Added: 84.25.204.235 -1257527038 -jerryjacobs - - -8854729 -status_id -1 -1257527038 -jerryjacobs - - -8854730 -allow_comments -1 -1257527038 -jerryjacobs - - -8854731 -close_date -0 -1257527038 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2885937 -2885937 -2 -100 -100 -nobody -nobody -jerryjacobs -1256480473 -1257526931 -5 -Areas of improvements -
I am new to KiCAD, and maybe some of the futures were not discovered yet, but in my opinion it would be nice if the following areas are improved: - -EESchema: -- When in “Place a component†mode, there is not auto scrolling (up, down) with the mouse -- Interface for selecting components, ports etc. It is a bit inconvenient; every time a component is needed a menu appears and requires searching for a component. -- Some of the commands like Netlist generation are not showed on the menu - -CVpcb: -- Preview of the assigned to a component package - -PCBnew: -- Edit: Undo/Redo -- There seems to be some issues with the mouse-autoscroll in different modes. -- Selection on component just by clicking on it -- Move a component just by grabbing it with the mouse -- Mode for showing all netlist connections -- Cursor shape, just arrow is fine sometimes -- When selecting area might be useful not the menu move block to appear, what if it is intended to delete the selection -
-0 - - -3799435 -jerryjacobs -1257526931 -
Added in TODO.txt -Thank you for your request!
- - - - - - -8815249 -IP -Artifact Created: 212.25.47.124 -1256480474 -nobody - - -8854713 -IP -Comment Added: 84.25.204.235 -1257526931 -jerryjacobs - - -8854714 -status_id -1 -1257526931 -jerryjacobs - - -8854715 -allow_comments -1 -1257526931 -jerryjacobs - - -8854716 -close_date -0 -1257526931 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2886974 -2886974 -2 -1026579 -516023 -nobody -nobody -jerryjacobs -1256632108 -1257526480 -5 -Undo -
At least a one-level undo function is needed. Could be implemented using autosave (backup) for the time being.
-0 - - -3799429 -jerryjacobs -1257526480 -
Done for next release, in SVN !
- - - - - - -8820037 -IP -Artifact Created: 213.64.86.172 -1256632108 -nobody - - -8854687 -IP -Comment Added: 84.25.204.235 -1257526480 -jerryjacobs - - -8854688 -status_id -1 -1257526480 -jerryjacobs - - -8854689 -artifact_group_id -100 -1257526480 -jerryjacobs - - -8854690 -allow_comments -1 -1257526480 -jerryjacobs - - -8854691 -close_date -0 -1257526480 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2886977 -2886977 -2 -1026580 -100 -nobody -nobody -jerryjacobs -1256632365 -1257526319 -5 -Search in libraries -
While editing symbols, a search function that shows in what lib a symbol exists, would be desirable. - -Also, the text "OK" in the EESCHEMA add component dialog should rather say "search/ok" since it's used for searching.
-0 - - -3799423 -jerryjacobs -1257526319 -
Added in TODO list
- - - - - - -8820046 -IP -Artifact Created: 213.64.86.172 -1256632365 -nobody - - -8854669 -IP -Comment Added: 84.25.204.235 -1257526319 -jerryjacobs - - -8854670 -status_id -1 -1257526319 -jerryjacobs - - -8854671 -allow_comments -1 -1257526319 -jerryjacobs - - -8854672 -close_date -0 -1257526319 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2890612 -2890612 -2 -1026579 -100 - -nobody -jerryjacobs -1257157587 -1257527268 -5 -footprint in automatic placement file -
We are an electronics company and are trying to switch from our CAD program to kicad. We strongly miss the footprint name for each components in the automatic placement files, as our pick & place needs it to work properly.
-0 - - -3799441 -jerryjacobs -1257527268 -
Added in TODO.txt
- - - - - - -8839463 -IP -Artifact Created: 80.33.161.202 -1257157587 - - - -8854741 -IP -Comment Added: 84.25.204.235 -1257527268 -jerryjacobs - - -8854742 -status_id -1 -1257527268 -jerryjacobs - - -8854743 -allow_comments -1 -1257527268 -jerryjacobs - - -8854744 -close_date -0 -1257527268 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2909570 -2909570 -1 -1026580 -100 -stefanl38 -nobody -nobody -1260102963 -0 -5 -much more efficient way to add new devices on a schematic -
I would like to have the following feature in the schematic symbol placing - -ONE click on add device opens the library-browser where ALL symbols are listed as small pictures. (Don't tell me this would use to much memory). -The I can do drag and drop symbols directly in the schematic window. - -Or second best solution to have e second button "add n devices" opens the library browser and the software behaves like this: - -a double-click on the name OR the picture closes automatically close the browser window I can place the device on the schematic and -the browser-window opens automatically again. -Doubleclick for choose - leftclick for placing -Doubleclick for choose - leftclick for placing -Doubleclick for choose - leftclick for placing -etc. etc. -now I'm forced to do the following -1) click on schematic: window choose opens -2) Click on librarybrowser -3) Click on device name -4) Click on add to schematic -5) place device on schematic - -1) click on schematic: window choose opens -2) Click on librarybrowser -3) Click on device name -4) Click on add to schematic -5) place device on schematic - -1) click on schematic: window choose opens -2) Click on librarybrowser -3) Click on device name -4) Click on add to schematic -5) place device on schematic -etc. etc. - -hey that's uncomfortable like hell !! I'm wondering that nobody complaint about that ?!! - -OK guys I estimate changing this takes 1-2 hours. When do you have time to insert that ? - -best regards - -Stefan
-0 - - -3830779 -vovanium -1260373839 -
I would better like to use "palette" side panel like one in QCAD. :)
- - - - - - -8948960 -IP -Artifact Created: 88.202.126.34 -1260102963 -stefanl38 - - -8959005 -IP -Comment Added: 195.208.204.245 -1260373839 -vovanium - - - - -http://sourceforge.net/support/tracker.php?aid=2910567 -2910567 -1 -1026580 -100 -nobody -nobody -nobody -1260266240 -0 -5 -Copy blocks from one file to another -
I can't find an easy way to copy/paste blocks from one schematic.sch to another-schematic.sch. - -could be cool to CTRL+C/CTRL+V between .sch files or to can import a schematic - -Maybe this is already possible, but it is not clear in the documentation - -regards, - -Marc BERLIOUX
-0 - - -3926095 -ultim -1268277825 -
+1 vote to copy blocks between sheets and schematics
- - - - - - -8954372 -IP -Artifact Created: 81.56.216.19 -1260266240 -nobody - - -9269875 -IP -Comment Added: 193.170.138.226 -1268277826 -ultim - - - - -http://sourceforge.net/support/tracker.php?aid=2918627 -2918627 -1 -100 -100 -nobody -nobody -nobody -1261396160 -0 -5 -Block operations on one side only -
Unless I've missed something, block operations work on all layers at the same time. That makes the block operations useless. Wouldn't it be better if the only layers affected, were the ones that are currently visible?
-0 - - - - - - -8991238 -IP -Artifact Created: 213.64.86.172 -1261396160 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2918944 -2918944 -1 -1026579 -100 -nobody -nobody -nobody -1261432223 -0 -5 -Edit solder paste shape/size in module editor -
One major feature that kicad lacking is the capability to edit Solder Paste layer. - -As parts size shrinks, simply making solder paste equal to pad size in general is not sufficient for manufacturing. -Different part manufacturer may put different recommendation on relationship of pad size and solder paste size. This is especially true for the QFN package where the center heat sink in general needs a low percentage of solder paste coverage to prevent the chip from floating to one side during re-flow process. Also consider the poor flowing characteristic of no-lead solder paste, simply globally shrink the solder paste using other tools won't always work either. - -A feature to edit the shape of solder paste of each module in Module editor is needed. It may implemented by using polygon, circle or etc to define the area for solder paste.
-0 - - - - - - -8993056 -IP -Artifact Created: 63.240.163.139 -1261432223 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2922241 -2922241 -1 -1026579 -100 -opendous -nobody -nobody -1262004234 -0 -5 -Matched Length Traces -
Add the ability to modify the length of a trace segment when traces need to be length matched. - -How I see development proceeding: - -1) alter the microwave fixed length tool to support arbitrary dimensions (no size ratio restriction) -2) alter the microwave fixed length tool to output traces instead of pads -3a) move the above functionality to the track right-click menu so that any track segment can have its length altered -3b) add a secondary "trace clearance" option so that the designer can allow for trace length matching. Normal trace clearance uses a solid line so the secondary trace clearance could use a dashed line. -
-0 - - - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=357403&aid= -357403 -MLT_Test.tar.bz2 -An example design created with kicad-2009-02-16-final. Uses the microwave line tool to match trace lengths. -3100 -application/octet-stream -1262419981 -opendous - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=357404&aid= -357404 -MatchedLengthTraces-Example.jpg -Picture of the design in MLT_Test.tar.bz2 -27870 -image/jpeg -1262420029 -opendous - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=357405&aid= -357405 -MatchedLengthTraces-MLT-Clearance.jpg -A secondary "trace clearance" option would make room for trace length matching. -53051 -image/jpeg -1262420079 -opendous - - -http://sourceforge.net/tracker/download.php?group_id=145591&atid=762479&file_id=357406&aid= -357406 -MatchedLengthTraces-SegmentExtensionExample.jpg -Any trace segment can be "extended" to match length with other traces. -15778 -image/jpeg -1262420146 -opendous - - - - -9008141 -IP -Artifact Created: 216.221.38.241 -1262004235 -opendous - - -9032961 -File Added -357403: MLT_Test.tar.bz2 -1262419981 -opendous - - -9032963 -File Added -357404: MatchedLengthTraces-Example.jpg -1262420029 -opendous - - -9032964 -File Added -357405: MatchedLengthTraces-MLT-Clearance.jpg -1262420079 -opendous - - -9032965 -File Added -357406: MatchedLengthTraces-SegmentExtensionExample.jpg -1262420146 -opendous - - - - -http://sourceforge.net/support/tracker.php?aid=2922245 -2922245 -1 -1026579 -100 -opendous -nobody -nobody -1262004551 -0 -5 -Component Style Vias -
Add the ability to create vias that behave like components. - -When routing by hand it helps to plan via placement. This is much easier when your vias behave like normal 1-pin components. - -An option could exist to then delete all non-connected vias once layout is complete.
-0 - - - - - - -9008149 -IP -Artifact Created: 216.221.38.241 -1262004551 -opendous - - - - -http://sourceforge.net/support/tracker.php?aid=2929409 -2929409 -1 -1026580 -100 -peteb6 -nobody -nobody -1263150553 -0 -5 -PAN function -
There doesn't seem to be any PAN function in editing schematics? -All CAD programs I've ever used have zoom and pan. -These two are the most frequent things I use. -PAN functionality would be a major improvement over having to use scroll bars. -Thanks -
-0 - - - - - - -9056492 -IP -Artifact Created: 71.164.23.220 -1263150554 -peteb6 - - - - -http://sourceforge.net/support/tracker.php?aid=2932891 -2932891 -1 -1026579 -100 -nobody -nobody -nobody -1263565470 -0 -5 -Plot several copies of board in single PostScript sheet -
I'm making my pcb's with toner tranfser method and I'd like to have an ability to print several copies of board onto single sheet of paper.
-0 - - - - - - -9074317 -IP -Artifact Created: 95.56.69.159 -1263565471 -nobody - - - - -http://sourceforge.net/support/tracker.php?aid=2938296 -2938296 -1 -1026580 -100 -radioguy00 -nobody -nobody -1264301278 -0 -5 -Wider Pane in dialog boxes to display Library path -
The pame where library are listed (for example when browsing library) is too narrow and cannot be widened to see the full library path. This is especially a problem when there is a mix of libraries in different directory. Suggestion is to be enable to drag the separator bewteen fiedl to see the full path and save the new width for a later opening of the same dialog box.
-0 - - - - - - -9102038 -IP -Artifact Created: 216.246.120.157 -1264301278 -radioguy00 - - - - -http://sourceforge.net/support/tracker.php?aid=2952118 -2952118 -1 -1026579 -100 -brummig -nobody -nobody -1266246004 -0 -5 -Arcs in Gerbers -
Arcs are plotted in Gerbers as straight lines, but the number of lines is too small, resulting in visibly notchy board edges. Could the number of lines be increased, please? Ideally the number of straight lines should be user-configurable, of course, but just a significant increase in the hard-coded number would be very welcome.
-0 - - - - - - -9180319 -IP -Artifact Created: 83.216.148.11 -1266246004 -brummig - - - - -http://sourceforge.net/support/tracker.php?aid=2952227 -2952227 -1 -1026579 -100 -mrluzeiro -nobody -nobody -1266256580 -0 -5 -Add custom track and vias -
The custom track and vias dialog must be improved... also the possibilite to set a custom value while editing.. -
-0 - - - - - - -9180896 -IP -Artifact Created: 85.241.153.82 -1266256581 -mrluzeiro - - - - -http://sourceforge.net/support/tracker.php?aid=2957135 -2957135 -1 -1026579 -100 -nobody -nobody -nobody -1266921739 -0 -5 -3D export -
3D export for other CAD tools
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2957383 -2957383 -1 -1026580 -516023 -nobody -nobody -nobody -1266952959 -0 -5 -Remember last choicen sheet size in schematic editor -
Dear Mr. Jacobs, - -on the website http://iut-tice.ujf-grenoble.fr/cao/AUTHORS.txt I found your name and I was wondering if you could help me. -Either yourself of direct me to some one who may be able to answer my questions. - -Our company recently started using KiCad as an EDA tool. -If I start Eeschema application I find an A4 template in which I can enter my schematic. - -Is it possible to change this A4 template to an A3 size page ? - -Thanks in advance for your support. - - -kind regards - - -Dominicus Erens -Quantified Quality within reach - - -Chief EMC Engineer -Electronic Expertise \ EMC
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2959522 -2959522 -1 -1026579 -100 -nobody -nobody -nobody -1267175889 -0 -5 -Errors of translation -
In Russian PCBnew -1) Grammatics error in button ==To execute verification of planning rules===. -2) If select English language, but text of the buttons is in Russian language
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2959531 -2959531 -1 -100 -100 -nobody -nobody -nobody -1267176090 -0 -5 -New function KiCad (delete project) -
In main menu of KiCad to add a new function ===File - to Delete a project=== (delete file *.pro)
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2959619 -2959619 -1 -1026579 -100 -alidoig -nobody -nobody -1267188934 -0 -5 -Place multiple pads, based on their pitch -
Rather than placing new module pads individually, could there be an option to have the module editor place multiple pads, offset from each other by the same pitch (in X an Y), with the pin number auto incremented for each? - -This would make it a lot easier to create large parts, and should be much less prone to mistakes. I have had the pleasure of using this feature in another layout tool, and was seriously impressed by it. - -Thanks - -
-0 - - - - - - -9216817 -IP -Artifact Created: 92.24.45.200 -1267188935 -alidoig - - - - -http://sourceforge.net/support/tracker.php?aid=2959967 -2959967 -1 -1026582 -100 -paulgittings -nobody -nobody -1267242491 -0 -5 -Add splitter bar. -
It should be possible to resize the footprint listing pane in the main frame of CVPCB - splitter bar/sashwindows.
-0 - - - - - - -9218929 -IP -Artifact Created: 211.30.110.233 -1267242492 -paulgittings - - - - -http://sourceforge.net/support/tracker.php?aid=2959968 -2959968 -1 -1026582 -100 -paulgittings -nobody -nobody -1267242638 -0 -5 -CVPCB context menu -
It would be useful to have a context menu in CVPCB, with an option to view footprint (personal thing I dislike toolbars for common actions much prefer right click context menus).
-0 - - - - - - -9218936 -IP -Artifact Created: 211.30.110.233 -1267242638 -paulgittings - - - - -http://sourceforge.net/support/tracker.php?aid=2959969 -2959969 -1 -1026581 -100 -paulgittings -nobody -nobody -1267242792 -0 -5 -Library and footprint manager -
It would be useful if a library manager and a footprint manager could be accessed from kicad without the need to run one of the sub programs. The managers should allow for the editing, browsing of the relevant content.
-0 - - - - - - -9218937 -IP -Artifact Created: 211.30.110.233 -1267242792 -paulgittings - - - - -http://sourceforge.net/support/tracker.php?aid=2959970 -2959970 -1 -100 -100 -paulgittings -nobody -nobody -1267243156 -0 -5 -Re-order library buttons -
In both EEschema and PCBnew when setting library preferences the user is warned that the order of active libraries is important. However, there is no obvious way for the user to change the order. There should be "up", "down" buttons which activate when the user selects an active library in the list, clicking on the button will move the library in the list. - -Also, it would be useful if the dialog was expanded to show a listing of what was in the selected library. -
-0 - - - - - - -9218949 -IP -Artifact Created: 211.30.110.233 -1267243156 -paulgittings - - - - -http://sourceforge.net/support/tracker.php?aid=2961557 -2961557 -1 -1026579 -100 -nobody -nobody -nobody -1267482671 -0 -5 -Portuguese Translation errors -
1) Portuguese translaton errors on the Layers Box. -2) Changing language to English and still displays in Portuguese some of the layers
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2962280 -2962280 -1 -1026579 -100 -nobody -nobody -nobody -1267575909 -0 -5 -PCBnew Assign Ratsnest Colors to Net Classes. -
1. -Possiblity to assign a Ratsnest Colour to a Net Class. -Multiple colors allow a much better view of different (critical) Net Classes during module placement and during adding tracks. - -2. -Possibility (check-box?) for each Net Class, to DISABLE displaying the ratsnest for that Net Class. -This allows to unclutter the ratsnest on dense pcb design. - -3. -Possibility (click-button?) to uncheck ALL, so the ratsnest is displayed for all Net Classes.
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2963755 -2963755 -1 -1026580 -100 -nobody -nobody -nobody -1267741823 -0 -5 -Wizard for make Component -
Something similar (or better!) than this: -http://kicad.rohrbacher.net/quicklib.php
-0 - - -3953292 -thewarpi -1270473058 -
I would be nice to have a similar feature as Altium Designer with their IPC footprint wizard: http://wiki.altium.com/download/attachments/3080430/image028.jpg -1. Select package type: BGA, DPAK, SOIC, SOP... -2. Enter dimensions which is unique for that package (shown in the picture above) -3. Voila, you have the component with the exact dimensions.
- - - - - - -9366578 -IP -Comment Added: 90.237.202.7 -1270473058 -thewarpi - - - - -http://sourceforge.net/support/tracker.php?aid=2964095 -2964095 -1 -1026580 -100 -mrluzeiro -nobody -nobody -1267783197 -0 -5 -Select multiple libs in Library editor to be removed -
If I load a lot of libs then if i need to remove,it can only be done one by one. -There should be a way of selected multiple libs to remove.
-0 - - - - - - -9240477 -IP -Artifact Created: 82.154.249.123 -1267783198 -mrluzeiro - - - - -http://sourceforge.net/support/tracker.php?aid=2971149 -2971149 -1 -100 -100 -nobody -nobody -nobody -1268730673 -0 -5 -Copy and placement multiple pcb/gerber in 1 pcb/gerber -
I would like to have a means to build ready-made cards to order one file. - -This situation arises when the project consists of several small boards. -For each file, manufacturers are taking the money. It pays off when a large number of boards, and if necessary a prototype or one or two products, it becomes very expensive. - -Perhaps for this function is better to add a fifth button KiCad "GERBER EDIT". - -The order of being able to be as follows: - -1. Developing its own or taken from the internet printed circuit boards, which should make. - -2. Then set the size of the workpiece. Consistently open the files with the boards and placed in the right quantity to the workpiece. The boards can move, delete, add to obtain the desired location. It will automatically be stored, the specified minimum distance between the boards. - -3. The boards can be represented conventionally in the form of rectangles. To mark the differences between their colors and / or numbers. Ie problem when linking would be to put the rectangles in the workpiece contour with minimal voids between them. Need the ability to move, resize the workpiece. - -4. Then the contours of each board avtomatichski erased and replaced with rectangular cutouts drawn given the minimum width for subsequent milling. - -5. A final automatic control clearances, etc. - -6. Forming files for the order in production. - -7. After manufacturing the workpiece is mechanically separated into individual boards.
-0 - - - - - - -9289278 -summary -COPY AND PLACEMENT MULTIPLE PCB/GERBER IN 1 PCB/GERBER -1268733578 -jerryjacobs - - - - -http://sourceforge.net/support/tracker.php?aid=2976031 -2976031 -1 -1026579 -100 -nobody -nobody -nobody -1269451741 -0 -5 -transformation track of several segments in one -
Very convenient to shift the track to the conservation angle. But if the track consists of several segments, this function does not work. - -I wish that some segments are automatically converted into one. - -Thank you.
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2980517 -2980517 -1 -1026579 -100 -nobody -nobody -nobody -1270124582 -0 -5 -Export HD bitmaps from 3Di -
Hi guys, - -it's could be cool to allow user to export bigger bitmap of 3D view. - -Actually, the bitmap is "just" a screen snap-shot, so the resolution is quite poor in many cases and not printable at all. - -Another solution is to allow user to save the 3D scene as a free 3D tools file (ie : Blender, POV ...ect...). - -In any case : thanks for this fantastic piece of code !
-0 - - -3950015 -jerryjacobs -1270125390 -
To enable such option to export to POV, Blender or other 3D format takes some time and effort. Maybe some other people will volunteer us and make something nice :-). - -Good luck, -Jerry
- - -3950053 -sebc26 -1270127917 -
And about a bitmap file with bigger resolution ? - -It could be great to have a printable bitmap of 3D view ! - -Thanks.
- - - - - - -9353135 -IP -Comment Added: 212.178.132.86 -1270125391 -jerryjacobs - - -9353294 -IP -Comment Added: 82.244.110.178 -1270127917 -sebc26 - - - - -http://sourceforge.net/support/tracker.php?aid=2981608 -2981608 -1 -761685 -100 -jerryjacobs -nobody -nobody -1270320252 -0 -5 -Library dialog alphabetical list -
The enhancement of the library dialog is much better, it would even better if it lists the libraries in alphabetical order.
-0 - - -3954008 -charras -1270545917 -
Libraries are shown in decreasing priority order, that is important fo select duplicate components. -In library dialog, alphabetic order is therefore a non sense.
- - - - - - -9362095 -IP -Artifact Created: 84.25.204.235 -1270320253 -jerryjacobs - - -9369903 -assigned_to -1293228 -1270545767 -charras - - -9369907 -IP -Comment Added: 152.77.63.2 -1270545917 -charras - - - - -http://sourceforge.net/support/tracker.php?aid=2982081 -2982081 -1 -761685 -100 -thewarpi -nobody -nobody -1270473401 -0 -5 -Add all icon shortcuts to menu -
Please add all shortcuts which you find under the icons aswell in the menu. Examples -Library editor (found EESchema) could maybe be under a menu called Tools etc... - -Thanks!
-0 - - - - - - -9366589 -IP -Artifact Created: 90.237.202.7 -1270473401 -thewarpi - - - - -http://sourceforge.net/support/tracker.php?aid=2982117 -2982117 -1 -1026580 -100 -nobody -nobody -nobody -1270479736 -0 -5 -Show and sort by description in Library browser -
Would be nice with the posebility to show all descriptions of all components in the library browser and then even be able to sort by "part name" or sort by "description". - -Thanks!
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2982613 -2982613 -1 -1026579 -100 -nobody -nobody -nobody -1270557149 -0 -5 -List unconnects: net name -
Display of corresponding net along with unconnected pad would be nice (in dialog List unconnected).
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2982614 -2982614 -1 -1026579 -100 -nobody -nobody -nobody -1270557290 -0 -5 -List unconnects: ignore/filter -
Ability to ignore/filter certain components or even nets.
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2983714 -2983714 -1 -1026579 -100 -nobody -nobody -nobody -1270715726 -0 -5 -Remember active layers -
The layer setup (hide paste, silk, invisible text etc) should be saved in the project file.
-0 - - - - - - - - -http://sourceforge.net/support/tracker.php?aid=2983870 -2983870 -1 -1026579 -100 -nobody -nobody -nobody -1270732057 -0 -5 -Default board settings -
It would be very useful feature if PCBnew (and probably EEschema) would be able to load default values from file when creating new board (circuit in case of EESchema). -As example: Custom track widths, Custom VIA sizes, Net classes; -I believe most users use some default values for all boards theu develop (use common calsses GND, VCC, VDD etc and use the same values for these nets). -The same comes with custom net sizes. -Currently on new design all these values must be added manually while these could be loaded from template board (like default project settings are loaded from kicad.pro file). -
-0 - - - - - - - - - - - - - - -kintel -Marius Kintel -145718 -kintel@users.sourceforge.net - - -diemer -Jonas Diemer -154672 -diemer@users.sourceforge.net - - -bennett78 -Frank Bennett -464167 -bennett78@users.sourceforge.net - - -manneveru -Michał Fita -639576 -manneveru@users.sourceforge.net - - -strangeril -Milan Horák -1196510 -strangeril@users.sourceforge.net - - -vesa_solonen -Vesa Solonen -1207241 -vesa_solonen@users.sourceforge.net - - -raburton -rab -1213654 -raburton@users.sourceforge.net - - -dickelbeck -Dick Hollenbeck -1222857 -dickelbeck@users.sourceforge.net - - -goutnet -Florian Delizy -1283799 -goutnet@users.sourceforge.net - - -charras -jp-charras -1293228 -charras@users.sourceforge.net - - -plyatov -Igor Plyatov -1325376 -plyatov@users.sourceforge.net - - -f3nix -Mateusz Skowroński -1459455 -f3nix@users.sourceforge.net - - -aircraft -aircraft -1777188 -aircraft@users.sourceforge.net - - -faa -faa -1805271 -faa@users.sourceforge.net - - -messo -Messo -1810278 -messo@users.sourceforge.net - - -lifekidyeaa -Tim Hanson -1811176 -lifekidyeaa@users.sourceforge.net - - -g_harland -Geoff Harland -1848371 -g_harland@users.sourceforge.net - - -reniemarquet -Renie S. Marquet -1894170 -reniemarquet@users.sourceforge.net - - -a-lunev -Alexander Lunev -1930733 -a-lunev@users.sourceforge.net - - -kajtek1 -Kajtek1 -1935577 -kajtek1@users.sourceforge.net - - -stambaughw -Wayne Stambaugh -1994912 -stambaughw@users.sourceforge.net - - -klui_ -Vladimir Kalyaev -2007962 -klui_@users.sourceforge.net - - -george_han -George Han -2010903 -george_han@users.sourceforge.net - - -peud -Per Uddén -2031753 -peud@users.sourceforge.net - - -jerryjacobs -Jerry Jacobs -2066563 -jerryjacobs@users.sourceforge.net - - -drannou -Damien RANNOU -2488236 -drannou@users.sourceforge.net - - -vovanium -Vladimir Uryvaev -2728450 -vovanium@users.sourceforge.net - - -viknn -Yuri Vikulov -2800567 -viknn@users.sourceforge.net - - -emmedics4 -Marco Serantoni -2808437 -emmedics4@users.sourceforge.net - - -broran -bror eriksson -2489811 -broran@users.sourceforge.net - - -beerslayer -The Beerslayer -595890 -beerslayer@users.sourceforge.net - - -xcskier -skier -1371184 -xcskier@users.sourceforge.net - - -stefanl38 -Stefan L38 -2727268 -stefanl38@users.sourceforge.net - - -jenningsthecat -jenningsthecat -2566598 -jenningsthecat@users.sourceforge.net - - -jgmejiah -juan -1898891 -jgmejiah@users.sourceforge.net - - -cablik -Jan Cablik -2171930 -cablik@users.sourceforge.net - - -di2 -di2 -1949317 -di2@users.sourceforge.net - - -cyrilbuttay -buttay -895957 -cyrilbuttay@users.sourceforge.net - - -sfabris -Simone Fabris -751509 -sfabris@users.sourceforge.net - - -djsbriscoe -David Briscoe -1047261 -djsbriscoe@users.sourceforge.net - - -ckgrier2 -CGrier -1921682 -ckgrier2@users.sourceforge.net - - -lainal -Dom -606626 -lainal@users.sourceforge.net - - -sunnysan -SunnySan -1517698 -sunnysan@users.sourceforge.net - - -whitis -Mark Whitis -131590 -whitis@users.sourceforge.net - - -wolverine222 -wolverine222 -1976880 -wolverine222@users.sourceforge.net - - -mungewell -simon wood -39509 -mungewell@users.sourceforge.net - - -linuxcart -Raúl -1667631 -linuxcart@users.sourceforge.net - - -sb-sf -Sergey A. Borshch -1653090 -sb-sf@users.sourceforge.net - - -fhsplitt -Fred -2036552 -fhsplitt@users.sourceforge.net - - -durgadas -Douglas Miller -183226 -durgadas@users.sourceforge.net - - -rokmarko -rok -1126317 -rokmarko@users.sourceforge.net - - -ddeeds -Doug Deeds -2099685 -ddeeds@users.sourceforge.net - - -oecherexpat -Oecher Expat -2100265 -oecherexpat@users.sourceforge.net - - -landyacht79 -Ron G -2119379 -landyacht79@users.sourceforge.net - - -alpheb -Yoann CONGAL -1890423 -alpheb@users.sourceforge.net - - -queueram -Marq Schneider -1563510 -queueram@users.sourceforge.net - - -gembler -Gary Embler -1880516 -gembler@users.sourceforge.net - - -ok1rrmartin -OK1RR -1917693 -ok1rrmartin@users.sourceforge.net - - -werner2101 -Werner Hoch -223984 -werner2101@users.sourceforge.net - - -galzsolt -Gál Zsolt -1960122 -galzsolt@users.sourceforge.net - - -josh_eeg -Joshua Wojnas -1311806 -josh_eeg@users.sourceforge.net - - -lomarcan -Lorenzo Marcantonio -115128 -lomarcan@users.sourceforge.net - - -jdoire -Joc -1158418 -jdoire@users.sourceforge.net - - -cfdev -cfdev -1876469 -cfdev@users.sourceforge.net - - -bachkhois -Nguyễn Hồng Quân -2330012 -bachkhois@users.sourceforge.net - - -dandumit -Daniel DUMITRU -665455 -dandumit@users.sourceforge.net - - -arius-marius -arius -2253890 -arius-marius@users.sourceforge.net - - -imrehg -Gergely Imreh -705860 -imrehg@users.sourceforge.net - - -rom4ik -vortex -1965104 -rom4ik@users.sourceforge.net - - -jacobeluz -Jacob Eluz -2424831 -jacobeluz@users.sourceforge.net - - -yneko -YAMANEKO -2099471 -yneko@users.sourceforge.net - - -henryvt -Henry von Tresckow -1628960 -henryvt@users.sourceforge.net - - -briansidebotham -BrianSidebotham -1221593 -briansidebotham@users.sourceforge.net - - -lodentoni -lodentoni -2541341 -lodentoni@users.sourceforge.net - - -sergeiste -Sergei -1270005 -sergeiste@users.sourceforge.net - - -mnurolcay -Mehmet Nur Olcay -2482977 -mnurolcay@users.sourceforge.net - - -brummig -Brummig -1919588 -brummig@users.sourceforge.net - - -frohro -Rob Frohne -606101 -frohro@users.sourceforge.net - - -bioname -Anatoly Burdeiny -2597904 -bioname@users.sourceforge.net - - -crasic -crasic -2713022 -crasic@users.sourceforge.net - - -tregare -GeoffR -2723699 -tregare@users.sourceforge.net - - -hyperflexed -HyperFlexed -1085956 -hyperflexed@users.sourceforge.net - - -elw_2 -ELW_2 -2237083 -elw_2@users.sourceforge.net - - -mrluzeiro -Mario Rui Luzeiro -2597274 -mrluzeiro@users.sourceforge.net - - -alidoig -Ali Doig -2822537 -alidoig@users.sourceforge.net - - -yageek -HEINRICH Yannick -2635482 -yageek@users.sourceforge.net - - -pisulski -pisulski -2824644 -pisulski@users.sourceforge.net - - -khame -Mehdi Khairy -2863739 -khame@users.sourceforge.net - - -herg -Harold Toler -583470 -herg@users.sourceforge.net - - -dionysos-sf -Alain PORTAL -787731 -dionysos-sf@users.sourceforge.net - - -thewarpi -Bengt Vänerhall -2765863 -thewarpi@users.sourceforge.net - - -daveplatt -Dave Platt -984178 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