From 2652068933564d8a2caa8cb1748c01f973ad2242 Mon Sep 17 00:00:00 2001
From: Seth Hillbrand <seth@kipro-pcb.com>
Date: Mon, 24 Jul 2023 15:18:18 -0700
Subject: [PATCH] When routing, check for board-level clearances

If the board-level clearance exceeds the max pad/track clearance, we end
up missing collisions in the router.

Fixes https://gitlab.com/kicad/code/kicad/-/issues/15162

(cherry picked from commit 000998ccae9da7aa4f0d5f0d56cf5399dae9f3cd)
---
 pcbnew/board_design_settings.cpp | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/pcbnew/board_design_settings.cpp b/pcbnew/board_design_settings.cpp
index 3df1de5376..2d36bcff7a 100644
--- a/pcbnew/board_design_settings.cpp
+++ b/pcbnew/board_design_settings.cpp
@@ -1028,9 +1028,12 @@ bool BOARD_DESIGN_SETTINGS::Ignore( int aDRCErrorCode )
 
 int BOARD_DESIGN_SETTINGS::GetBiggestClearanceValue() const
 {
-    int            biggest = 0;
+    int            biggest = std::max( m_MinClearance, m_HoleClearance );
     DRC_CONSTRAINT constraint;
 
+    biggest = std::max( biggest, m_HoleToHoleMin );
+    biggest = std::max( biggest, m_CopperEdgeClearance );
+
     if( m_DRCEngine )
     {
         m_DRCEngine->QueryWorstConstraint( CLEARANCE_CONSTRAINT, constraint );