diff --git a/pcbnew/edit_track_width.cpp b/pcbnew/edit_track_width.cpp
index 0a6560e8ed..91e3caf9b7 100644
--- a/pcbnew/edit_track_width.cpp
+++ b/pcbnew/edit_track_width.cpp
@@ -73,6 +73,12 @@ bool PCB_EDIT_FRAME::SetTrackSegmentWidth( TRACK*             aTrackItem,
     {
         const VIA *via = static_cast<const VIA *>( aTrackItem );
 
+        // Micro vias have a size only defined in their netclass
+        // (no specific values defined by a table of specific value)
+        // Ensure the netcall is accessible:
+        if( via->GetViaType() == VIA_MICROVIA && net == NULL )
+            net = aTrackItem->GetNet();
+
         // Get the draill value, regardless it is default or specific
         initial_drill = via->GetDrillValue();
 
@@ -96,14 +102,16 @@ bool PCB_EDIT_FRAME::SetTrackSegmentWidth( TRACK*             aTrackItem,
                 new_drill = net->GetMicroViaDrillSize();
             }
             else
-                new_width = GetDesignSettings().GetCurrentMicroViaSize();
+            {
+                // Should not occur
+            }
         }
 
         // Old versions set a drill value <= 0, when the default netclass it used
         // but it could be better to set the drill value to the actual value
         // to avoid issues for existing vias, if the default drill value is modified
         // in the netclass, and not in current vias.
-        if( via->GetDrill() <= 0 )    // means default netclass drill value used
+        if( via->GetDrill() <= 0 )      // means default netclass drill value used
         {
             initial_drill  = -1;        // Force drill vias re-initialization
         }
diff --git a/pcbnew/exporters/gen_modules_placefile.cpp b/pcbnew/exporters/gen_modules_placefile.cpp
index 4976796455..56864087ee 100644
--- a/pcbnew/exporters/gen_modules_placefile.cpp
+++ b/pcbnew/exporters/gen_modules_placefile.cpp
@@ -99,6 +99,7 @@ public:
         m_parent( aParent ),
         m_plotOpts( aParent->GetPlotSettings() )
     {
+        m_reporter = &m_messagesPanel->Reporter();
         initDialog();
 
         GetSizer()->SetSizeHints(this);
diff --git a/pcbnew/pcb_draw_panel_gal.cpp b/pcbnew/pcb_draw_panel_gal.cpp
index 213bb02da1..bcb661c546 100644
--- a/pcbnew/pcb_draw_panel_gal.cpp
+++ b/pcbnew/pcb_draw_panel_gal.cpp
@@ -219,12 +219,13 @@ void PCB_DRAW_PANEL_GAL::DisplayBoard( const BOARD* aBoard )
     UseColorScheme( aBoard->GetColorsSettings() );
 
     PCB_BASE_FRAME* frame = dynamic_cast<PCB_BASE_FRAME*>( GetParent() );
-    SetTopLayer( frame->GetActiveLayer() );
 
     if( frame )
     {
+        SetTopLayer( frame->GetActiveLayer() );
         DISPLAY_OPTIONS* displ_opts = (DISPLAY_OPTIONS*) frame->GetDisplayOptions();
-        static_cast<KIGFX::PCB_RENDER_SETTINGS*>( m_view->GetPainter()->GetSettings() )->LoadDisplayOptions( displ_opts );
+        static_cast<KIGFX::PCB_RENDER_SETTINGS*>(
+            m_view->GetPainter()->GetSettings() )->LoadDisplayOptions( displ_opts );
     }
 
     m_view->RecacheAllItems( true );
diff --git a/pcbnew/router/pns_meander_placer_base.cpp b/pcbnew/router/pns_meander_placer_base.cpp
index a8b04b285b..0a655e44fe 100644
--- a/pcbnew/router/pns_meander_placer_base.cpp
+++ b/pcbnew/router/pns_meander_placer_base.cpp
@@ -25,6 +25,7 @@
 PNS_MEANDER_PLACER_BASE::PNS_MEANDER_PLACER_BASE( PNS_ROUTER* aRouter ) :
         PNS_PLACEMENT_ALGO( aRouter )
 {
+    m_currentWidth = 0;
 }
 
 
@@ -69,7 +70,7 @@ void PNS_MEANDER_PLACER_BASE::cutTunedLine( const SHAPE_LINE_CHAIN& aOrigin,
     if ( cp == aTuneStart ) // we don't like tuning segments with 0 length
     {
         int idx = aOrigin.FindSegment( cp );
-        if( idx >= 0 ) 
+        if( idx >= 0 )
         {
             const SEG& s = aOrigin.CSegment( idx );
             cp += (s.B - s.A).Resize(2);