From 3e3ae8925a9a8c29b50e3dcfc7a85e6ed3b87c96 Mon Sep 17 00:00:00 2001
From: dickelbeck <Unknown>
Date: Sat, 22 Sep 2007 04:33:44 +0000
Subject: [PATCH] see 2007-Sep-22 change_log.txt

---
 change_log.txt        |  8 ++++++++
 pcbnew/collectors.cpp | 11 ++++++++++-
 pcbnew/hotkeys.cpp    |  9 ++++++---
 pcbnew/surbrill.cpp   |  2 ++
 4 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/change_log.txt b/change_log.txt
index cf3d262358..68ba56b94a 100644
--- a/change_log.txt
+++ b/change_log.txt
@@ -4,6 +4,14 @@ Started 2007-June-11
 Please add newer entries at the top, list the date and your name with 
 email address.
 
+2007-Sep-22 UPDATE   Dick Hollenbeck <dick@softplc.com>
+================================================================================
++ pcbnew
+    GENERAL_COLLECTOR::Collect() was skipping thru hole pads even though they
+    were visible.
+    Highlight tool now sends message to eeschema when a pad is selected.
+    
+
 2007-Sep-20 UPDATE   Dick Hollenbeck <dick@softplc.com>
 ================================================================================
 + eeschema
diff --git a/pcbnew/collectors.cpp b/pcbnew/collectors.cpp
index a859fc2d6e..16715f433a 100644
--- a/pcbnew/collectors.cpp
+++ b/pcbnew/collectors.cpp
@@ -152,7 +152,15 @@ SEARCH_RESULT GENERAL_COLLECTOR::Inspect( EDA_BaseStruct* testItem, const void*
     switch( item->Type() )
     {
     case TYPEPAD:
-        module = (MODULE*) item->GetParent();
+        // if pad is a thru hole, then it can be visible when its parent module is not.
+        if( ((D_PAD*)item)->m_Attribut != SMD )    // a hole is present, so multiple layers
+        {
+            // there are no pad specific visibility controls at this time.
+            // proceed to the common tests below, but without the parent module test, 
+            // by leaving module==NULL
+        }
+        else    // smd, so use common test below
+            module = (MODULE*) item->GetParent();
         break;
         
     case TYPEVIA:
@@ -198,6 +206,7 @@ SEARCH_RESULT GENERAL_COLLECTOR::Inspect( EDA_BaseStruct* testItem, const void*
     {
         if( m_Guide->IgnoreModulesOnCu() && module->GetLayer()==LAYER_CUIVRE_N )
             goto exit;
+        
         if( m_Guide->IgnoreModulesOnCmp() && module->GetLayer()==LAYER_CMP_N )
             goto exit;
     }
diff --git a/pcbnew/hotkeys.cpp b/pcbnew/hotkeys.cpp
index 6a1d80e3ff..6404bc8adb 100644
--- a/pcbnew/hotkeys.cpp
+++ b/pcbnew/hotkeys.cpp
@@ -181,6 +181,7 @@ void WinEDA_PcbFrame::OnHotKey( wxDC* DC, int hotkey,
     // Remap the control key Ctrl A (0x01) to GR_KB_CTRL + 'A' (just easier to handle...)
     if( (hotkey & GR_KB_CTRL) != 0 )
         hotkey += 'A' - 1;
+    
     /* Convert lower to upper case (the usual toupper function has problem with non ascii codes like function keys */
     if( (hotkey >= 'a') && (hotkey <= 'z') )
         hotkey += 'A' - 'a';
@@ -325,8 +326,9 @@ void WinEDA_PcbFrame::OnHotKey( wxDC* DC, int hotkey,
         break;
 
     case HK_END_TRACK:
-		if ( ! ItemFree && (GetCurItem()->Type() == TYPETRACK) && ((GetCurItem()->m_Flags & IS_NEW) != 0) )
-		{	// A new track is in progress: call to End_Route()
+		if( ! ItemFree && (GetCurItem()->Type() == TYPETRACK) && ((GetCurItem()->m_Flags & IS_NEW) != 0) )
+		{	
+            // A new track is in progress: call to End_Route()
 			DrawPanel->MouseToCursorSchema();
 			End_Route( (TRACK*) ( GetCurItem() ), DC );
 		}
@@ -417,9 +419,10 @@ void WinEDA_PcbFrame::OnHotKey( wxDC* DC, int hotkey,
                                              | MATCH_LAYER
     #endif
                                              );
+            
             if( module == NULL )          // no footprint found
             {
-                module = Locate_Prefered_Module( m_Pcb, CURSEUR_OFF_GRILLE );
+                module = Locate_Prefered_Module( m_Pcb, CURSEUR_OFF_GRILLE | VISIBLE_ONLY );
                 if( module )
                 {
                     // a footprint is found, but locked or on an other layer
diff --git a/pcbnew/surbrill.cpp b/pcbnew/surbrill.cpp
index 4b5301480f..ef3ad02570 100644
--- a/pcbnew/surbrill.cpp
+++ b/pcbnew/surbrill.cpp
@@ -95,6 +95,7 @@ int WinEDA_PcbFrame::Select_High_Light( wxDC* DC )
 
     if( g_HightLigt_Status )
         Hight_Light( DC );
+    
     pt_piste = Locate_Pistes( m_Pcb->m_Track, masquelayer, CURSEUR_OFF_GRILLE );
     if( pt_piste )
     {
@@ -108,6 +109,7 @@ int WinEDA_PcbFrame::Select_High_Light( wxDC* DC )
         {
             code = g_HightLigth_NetCode = pt_pad->m_NetCode;
             Hight_Light( DC );
+            SendMessageToEESCHEMA( pt_pad );
         }
     }