diff --git a/3d-viewer/3d_canvas.h b/3d-viewer/3d_canvas.h index 43a1f7ed85..d4ad84cebf 100644 --- a/3d-viewer/3d_canvas.h +++ b/3d-viewer/3d_canvas.h @@ -47,7 +47,7 @@ class BOARD_DESIGN_SETTINGS; class EDA_3D_FRAME; class S3D_VERTEX; -class SEGVIA; +class VIA; class D_PAD; // We are using GL lists to store layers and other items @@ -160,8 +160,8 @@ public: void Draw3DGrid( double aGriSizeMM ); void Draw3DAxis(); - void Draw3DViaHole( SEGVIA * aVia ); - void Draw3DPadHole( D_PAD * aPad ); + void Draw3DViaHole( const VIA * aVia ); + void Draw3DPadHole( const D_PAD * aPad ); DECLARE_EVENT_TABLE() }; diff --git a/3d-viewer/3d_draw.cpp b/3d-viewer/3d_draw.cpp index 1afdfe9c27..3216947b8e 100644 --- a/3d-viewer/3d_draw.cpp +++ b/3d-viewer/3d_draw.cpp @@ -302,18 +302,19 @@ void EDA_3D_CANVAS::BuildBoard3DView() // Add via hole if( track->Type() == PCB_VIA_T ) { - int shape = track->GetShape(); - int holediameter = track->GetDrillValue(); - int thickness = g_Parm_3D_Visu.GetCopperThicknessBIU(); + VIA *via = static_cast( track ); + VIATYPE_T viatype = via->GetViaType(); + int holediameter = via->GetDrillValue(); + int thickness = g_Parm_3D_Visu.GetCopperThicknessBIU(); int hole_outer_radius = (holediameter + thickness) / 2; - if( shape != VIA_THROUGH ) + if( viatype != VIA_THROUGH ) TransformCircleToPolygon( currLayerHoles, - track->GetStart(), hole_outer_radius, + via->GetStart(), hole_outer_radius, segcountLowQuality ); else if( !throughHolesListBuilt ) TransformCircleToPolygon( allLayerHoles, - track->GetStart(), hole_outer_radius, + via->GetStart(), hole_outer_radius, segcountLowQuality ); } } @@ -433,8 +434,10 @@ void EDA_3D_CANVAS::BuildBoard3DView() // Draw vias holes (vertical cylinders) for( TRACK* track = pcb->m_Track; track != NULL; track = track->Next() ) { - if( track->Type() == PCB_VIA_T ) - Draw3DViaHole( (SEGVIA*) track ); + const VIA *via = dynamic_cast(track); + + if( via ) + Draw3DViaHole( via ); } // Draw pads holes (vertical cylinders) @@ -529,13 +532,14 @@ void EDA_3D_CANVAS::BuildTechLayers3DView() // Add via hole if( track->Type() == PCB_VIA_T ) { - int shape = track->GetShape(); - int holediameter = track->GetDrillValue(); + const VIA *via = static_cast( track ); + VIATYPE_T viatype = via->GetViaType(); + int holediameter = via->GetDrillValue(); int hole_outer_radius = (holediameter + thickness) / 2; - if( shape == VIA_THROUGH ) + if( viatype == VIA_THROUGH ) TransformCircleToPolygon( allLayerHoles, - track->GetStart(), hole_outer_radius, + via->GetStart(), hole_outer_radius, segcountLowQuality ); } } @@ -1047,7 +1051,7 @@ void EDA_3D_CANVAS::Draw3DGrid( double aGriSizeMM ) } -void EDA_3D_CANVAS::Draw3DViaHole( SEGVIA* aVia ) +void EDA_3D_CANVAS::Draw3DViaHole( const VIA* aVia ) { LAYER_NUM top_layer, bottom_layer; int inner_radius = aVia->GetDrillValue() / 2; @@ -1060,7 +1064,7 @@ void EDA_3D_CANVAS::Draw3DViaHole( SEGVIA* aVia ) SetGLCopperColor(); else { - EDA_COLOR_T color = g_ColorsSettings.GetItemColor( VIAS_VISIBLE + aVia->GetShape() ); + EDA_COLOR_T color = g_ColorsSettings.GetItemColor( VIAS_VISIBLE + aVia->GetViaType() ); SetGLColor( color ); } @@ -1111,7 +1115,7 @@ void MODULE::ReadAndInsert3DComponentShape( EDA_3D_CANVAS* glcanvas, // Draw 3D pads. -void EDA_3D_CANVAS::Draw3DPadHole( D_PAD* aPad ) +void EDA_3D_CANVAS::Draw3DPadHole( const D_PAD* aPad ) { // Draw the pad hole wxSize drillsize = aPad->GetDrillSize(); diff --git a/include/class_board_design_settings.h b/include/class_board_design_settings.h index 31ebfccfe5..67e0c73a88 100644 --- a/include/class_board_design_settings.h +++ b/include/class_board_design_settings.h @@ -7,6 +7,7 @@ #include // NB_COLORS #include +#include #include @@ -19,7 +20,7 @@ class BOARD_DESIGN_SETTINGS public: bool m_MicroViasAllowed; ///< true to allow micro vias bool m_BlindBuriedViaAllowed; ///< true to allow blind/buried vias - int m_CurrentViaType; ///< via type (VIA_BLIND_BURIED, VIA_THROUGH VIA_MICROVIA) + VIATYPE_T m_CurrentViaType; ///< via type (VIA_BLIND_BURIED, VIA_THROUGH VIA_MICROVIA) /// if true, when creating a new track starting on an existing track, use this track width bool m_UseConnectedTrackWidth; diff --git a/include/view/view_item.h b/include/view/view_item.h index c06538b224..f64bb4f1c7 100644 --- a/include/view/view_item.h +++ b/include/view/view_item.h @@ -57,8 +57,8 @@ enum KICAD_T PCB_TEXT_T, ///< class TEXTE_PCB, text on a layer PCB_MODULE_TEXT_T, ///< class TEXTE_MODULE, text in a footprint PCB_MODULE_EDGE_T, ///< class EDGE_MODULE, a footprint edge - PCB_TRACE_T, ///< class TRACKE, a track segment (segment on a copper layer) - PCB_VIA_T, ///< class SEGVIA, a via (like a track segment on a copper layer) + PCB_TRACE_T, ///< class TRACK, a track segment (segment on a copper layer) + PCB_VIA_T, ///< class VIA, a via (like a track segment on a copper layer) PCB_ZONE_T, ///< class SEGZONE, a segment used to fill a zone area (segment on a ///< copper layer) PCB_MARKER_T, ///< class MARKER_PCB, a marker used to show something diff --git a/include/wxPcbStruct.h b/include/wxPcbStruct.h index 70cefc2a36..9ad56f1016 100644 --- a/include/wxPcbStruct.h +++ b/include/wxPcbStruct.h @@ -44,7 +44,7 @@ class TEXTE_PCB; class MODULE; class TRACK; class SEGZONE; -class SEGVIA; +class VIA; class D_PAD; class TEXTE_MODULE; class PCB_TARGET; diff --git a/pcbnew/autorouter/auto_place_footprints.cpp b/pcbnew/autorouter/auto_place_footprints.cpp index 0351c43bd1..a49ccd1b2c 100644 --- a/pcbnew/autorouter/auto_place_footprints.cpp +++ b/pcbnew/autorouter/auto_place_footprints.cpp @@ -516,12 +516,7 @@ int genPlacementRoutingMatrix( BOARD* aBrd, EDA_MSG_PANEL* messagePanel ) if( DrawSegm->GetLayer() != EDGE_N ) break; - TmpSegm.SetStart( DrawSegm->GetStart() ); - TmpSegm.SetEnd( DrawSegm->GetEnd() ); - TmpSegm.SetShape( DrawSegm->GetShape() ); - TmpSegm.m_Param = DrawSegm->GetAngle(); - - TraceSegmentPcb( &TmpSegm, HOLE | CELL_is_EDGE, + TraceSegmentPcb( DrawSegm, HOLE | CELL_is_EDGE, RoutingMatrix.m_GridRouting, WRITE_CELL ); break; diff --git a/pcbnew/autorouter/autorout.h b/pcbnew/autorouter/autorout.h index 98f5ac0b3a..b284b63ab8 100644 --- a/pcbnew/autorouter/autorout.h +++ b/pcbnew/autorouter/autorout.h @@ -38,6 +38,7 @@ class BOARD; +class DRAWSEGMENT; #define TOP 0 @@ -195,6 +196,7 @@ void PlacePad( D_PAD* pt_pad, int type, int marge, int op_logic ); /* Draws a segment of track on the board. */ void TraceSegmentPcb( TRACK* pt_segm, int type, int marge, int op_logic ); +void TraceSegmentPcb( DRAWSEGMENT* pt_segm, int type, int marge, int op_logic ); /* Uses the color value of all cells included in the board * coord of the rectangle ux0, uy0 (top right corner) diff --git a/pcbnew/autorouter/graphpcb.cpp b/pcbnew/autorouter/graphpcb.cpp index 28dff7ff32..54b94a01f7 100644 --- a/pcbnew/autorouter/graphpcb.cpp +++ b/pcbnew/autorouter/graphpcb.cpp @@ -38,6 +38,7 @@ #include #include #include +#include #include #include @@ -256,29 +257,52 @@ void TraceFilledCircle( int cx, int cy, int radius, } } - -void TraceSegmentPcb( TRACK* pt_segm, int color, int marge, int op_logic ) +void TraceSegmentPcb( DRAWSEGMENT* pt_segm, int color, int marge, int op_logic ) { - int half_width; - int ux0, uy0, ux1, uy1; - - half_width = ( pt_segm->GetWidth() / 2 ) + marge; + int half_width = ( pt_segm->GetWidth() / 2 ) + marge; // Calculate the bounding rectangle of the segment (if H, V or Via) - ux0 = pt_segm->GetStart().x - RoutingMatrix.GetBrdCoordOrigin().x; - uy0 = pt_segm->GetStart().y - RoutingMatrix.GetBrdCoordOrigin().y; - ux1 = pt_segm->GetEnd().x - RoutingMatrix.GetBrdCoordOrigin().x; - uy1 = pt_segm->GetEnd().y - RoutingMatrix.GetBrdCoordOrigin().y; + int ux0 = pt_segm->GetStart().x - RoutingMatrix.GetBrdCoordOrigin().x; + int uy0 = pt_segm->GetStart().y - RoutingMatrix.GetBrdCoordOrigin().y; + int ux1 = pt_segm->GetEnd().x - RoutingMatrix.GetBrdCoordOrigin().x; + int uy1 = pt_segm->GetEnd().y - RoutingMatrix.GetBrdCoordOrigin().y; - // Test if VIA (filled circle was drawn) - if( pt_segm->Type() == PCB_VIA_T ) + LAYER_NUM layer = pt_segm->GetLayer(); + + if( color == VIA_IMPOSSIBLE ) + layer = UNDEFINED_LAYER; + + switch( pt_segm->GetShape() ) + { + // The segment is here a straight line or a circle or an arc.: + case S_CIRCLE: + TraceCircle( ux0, uy0, ux1, uy1, half_width, layer, color, op_logic ); + break; + + case S_ARC: + TraceArc( ux0, uy0, ux1, uy1, pt_segm->GetAngle(), half_width, layer, color, op_logic ); + break; + + // The segment is here a line segment. + default: + DrawSegmentQcq( ux0, uy0, ux1, uy1, half_width, layer, color, op_logic ); + break; + } +} + +void TraceSegmentPcb( TRACK* aTrack, int color, int marge, int op_logic ) +{ + int half_width = ( aTrack->GetWidth() / 2 ) + marge; + + // Test if VIA (filled circle need to be drawn) + if( aTrack->Type() == PCB_VIA_T ) { LAYER_MSK layer_mask = NO_LAYERS; - if( pt_segm->IsOnLayer( g_Route_Layer_BOTTOM ) ) + if( aTrack->IsOnLayer( g_Route_Layer_BOTTOM ) ) layer_mask = GetLayerMask( g_Route_Layer_BOTTOM ); - if( pt_segm->IsOnLayer( g_Route_Layer_TOP ) ) + if( aTrack->IsOnLayer( g_Route_Layer_TOP ) ) { if( layer_mask == 0 ) layer_mask = GetLayerMask( g_Route_Layer_TOP ); @@ -290,39 +314,25 @@ void TraceSegmentPcb( TRACK* pt_segm, int color, int marge, int op_logic ) layer_mask = FULL_LAYERS; if( layer_mask ) - TraceFilledCircle( pt_segm->GetStart().x, pt_segm->GetStart().y, + TraceFilledCircle( aTrack->GetStart().x, aTrack->GetStart().y, half_width, layer_mask, color, op_logic ); - return; } - - LAYER_NUM layer = pt_segm->GetLayer(); - - if( color == VIA_IMPOSSIBLE ) - layer = UNDEFINED_LAYER; - - // The segment is here a straight line or a circle or an arc.: - if( pt_segm->GetShape() == S_CIRCLE ) + else { - TraceCircle( ux0, uy0, ux1, uy1, half_width, layer, color, op_logic ); - return; - } + // Calculate the bounding rectangle of the segment + int ux0 = aTrack->GetStart().x - RoutingMatrix.GetBrdCoordOrigin().x; + int uy0 = aTrack->GetStart().y - RoutingMatrix.GetBrdCoordOrigin().y; + int ux1 = aTrack->GetEnd().x - RoutingMatrix.GetBrdCoordOrigin().x; + int uy1 = aTrack->GetEnd().y - RoutingMatrix.GetBrdCoordOrigin().y; - if( pt_segm->GetShape() == S_ARC ) - { - TraceArc( ux0, uy0, ux1, uy1, pt_segm->m_Param, half_width, layer, color, op_logic ); - return; - } + // Ordinary track + LAYER_NUM layer = aTrack->GetLayer(); + + if( color == VIA_IMPOSSIBLE ) + layer = UNDEFINED_LAYER; - // The segment is here a line segment. - if( ( ux0 != ux1 ) && ( uy0 != uy1 ) ) // Segment tilts. - { DrawSegmentQcq( ux0, uy0, ux1, uy1, half_width, layer, color, op_logic ); - return; } - - // The segment is horizontal or vertical. - // F4EXB 051018-01 - DrawSegmentQcq( ux0, uy0, ux1, uy1, half_width, layer, color, op_logic ); } diff --git a/pcbnew/autorouter/routing_matrix.cpp b/pcbnew/autorouter/routing_matrix.cpp index b5d02e926a..8449c90bc1 100644 --- a/pcbnew/autorouter/routing_matrix.cpp +++ b/pcbnew/autorouter/routing_matrix.cpp @@ -225,7 +225,6 @@ void PlaceCells( BOARD* aPcb, int net_code, int flag ) // Place outlines of modules on matrix routing, if they are on a copper layer // or on the edge layer - TRACK tmpSegm( NULL ); // A dummy track used to create segments. for( MODULE* module = aPcb->m_Modules; module; module = module->Next() ) { @@ -236,21 +235,13 @@ void PlaceCells( BOARD* aPcb, int net_code, int flag ) case PCB_MODULE_EDGE_T: { EDGE_MODULE* edge = (EDGE_MODULE*) item; + EDGE_MODULE tmpEdge( *edge ); - tmpSegm.SetLayer( edge->GetLayer() ); + if( tmpEdge.GetLayer() == EDGE_N ) + tmpEdge.SetLayer( UNDEFINED_LAYER ); - if( tmpSegm.GetLayer() == EDGE_N ) - tmpSegm.SetLayer( UNDEFINED_LAYER ); - - tmpSegm.SetStart( edge->GetStart() ); - tmpSegm.SetEnd( edge->GetEnd() ); - tmpSegm.SetShape( edge->GetShape() ); - tmpSegm.SetWidth( edge->GetWidth() ); - tmpSegm.m_Param = edge->GetAngle(); - tmpSegm.SetNetCode( -1 ); - - TraceSegmentPcb( &tmpSegm, HOLE, marge, WRITE_CELL ); - TraceSegmentPcb( &tmpSegm, VIA_IMPOSSIBLE, via_marge, WRITE_OR_CELL ); + TraceSegmentPcb( &tmpEdge, HOLE, marge, WRITE_CELL ); + TraceSegmentPcb( &tmpEdge, VIA_IMPOSSIBLE, via_marge, WRITE_OR_CELL ); } break; @@ -271,7 +262,7 @@ void PlaceCells( BOARD* aPcb, int net_code, int flag ) int type_cell = HOLE; DrawSegm = (DRAWSEGMENT*) item; - tmpSegm.SetLayer( DrawSegm->GetLayer() ); + DRAWSEGMENT tmpSegm( DrawSegm ); if( DrawSegm->GetLayer() == EDGE_N ) { @@ -279,13 +270,6 @@ void PlaceCells( BOARD* aPcb, int net_code, int flag ) type_cell |= CELL_is_EDGE; } - tmpSegm.SetStart( DrawSegm->GetStart() ); - tmpSegm.SetEnd( DrawSegm->GetEnd() ); - tmpSegm.SetShape( DrawSegm->GetShape() ); - tmpSegm.SetWidth( DrawSegm->GetWidth() ); - tmpSegm.m_Param = DrawSegm->GetAngle(); - tmpSegm.SetNetCode( -1 ); - TraceSegmentPcb( &tmpSegm, type_cell, marge, WRITE_CELL ); } break; diff --git a/pcbnew/autorouter/solve.cpp b/pcbnew/autorouter/solve.cpp index 86e937073a..5e94db6b09 100644 --- a/pcbnew/autorouter/solve.cpp +++ b/pcbnew/autorouter/solve.cpp @@ -1159,14 +1159,11 @@ static int Retrace( PCB_EDIT_FRAME* pcbframe, wxDC* DC, static void OrCell_Trace( BOARD* pcb, int col, int row, int side, int orient, int current_net_code ) { - int dx0, dy0, dx1, dy1; - TRACK* newTrack; - if( orient == HOLE ) // placement of a via { - newTrack = new SEGVIA( pcb ); + VIA *newVia = new VIA( pcb ); - g_CurrentTrackList.PushBack( newTrack ); + g_CurrentTrackList.PushBack( newVia ); g_CurrentTrackSegment->SetState( TRACK_AR, true ); g_CurrentTrackSegment->SetLayer( 0x0F ); @@ -1178,13 +1175,15 @@ static void OrCell_Trace( BOARD* pcb, int col, int row, g_CurrentTrackSegment->SetEnd( g_CurrentTrackSegment->GetStart() ); g_CurrentTrackSegment->SetWidth( pcb->GetCurrentViaSize() ); - g_CurrentTrackSegment->SetShape( pcb->GetDesignSettings().m_CurrentViaType ); + newVia->SetViaType( pcb->GetDesignSettings().m_CurrentViaType ); g_CurrentTrackSegment->SetNetCode( current_net_code ); } else // placement of a standard segment { - newTrack = new TRACK( pcb ); + TRACK *newTrack = new TRACK( pcb ); + int dx0, dy0, dx1, dy1; + g_CurrentTrackList.PushBack( newTrack ); diff --git a/pcbnew/board_undo_redo.cpp b/pcbnew/board_undo_redo.cpp index a5a3ad314e..96d4c844da 100644 --- a/pcbnew/board_undo_redo.cpp +++ b/pcbnew/board_undo_redo.cpp @@ -232,31 +232,38 @@ void BOARD_ITEM::SwapData( BOARD_ITEM* aImage ) int atmp = track->GetWidth(); track->SetWidth( image->GetWidth() ); image->SetWidth( atmp ); - atmp = track->GetShape(); - track->SetShape( image->GetShape() ); - image->SetShape( atmp ); - atmp = track->GetDrillValue(); + if( Type() == PCB_VIA_T ) + { + VIA *via = static_cast( this ); + VIA *viaimage = static_cast( aImage ); - if( track->IsDrillDefault() ) - atmp = -1; + VIATYPE_T viatmp = via->GetViaType(); + via->SetViaType( viaimage->GetViaType() ); + viaimage->SetViaType( viatmp ); - int itmp = image->GetDrillValue(); + int drilltmp = via->GetDrillValue(); - if( image->IsDrillDefault() ) - itmp = -1; + if( via->IsDrillDefault() ) + drilltmp = -1; - EXCHG(itmp, atmp ); + int itmp = viaimage->GetDrillValue(); - if( atmp > 0 ) - track->SetDrill( atmp ); - else - track->SetDrillDefault(); + if( viaimage->IsDrillDefault() ) + itmp = -1; - if( itmp > 0 ) - image->SetDrill( itmp ); - else - image->SetDrillDefault(); + EXCHG(itmp, drilltmp ); + + if( drilltmp > 0 ) + via->SetDrill( drilltmp ); + else + via->SetDrillDefault(); + + if( itmp > 0 ) + viaimage->SetDrill( itmp ); + else + viaimage->SetDrillDefault(); + } } break; diff --git a/pcbnew/class_board.cpp b/pcbnew/class_board.cpp index 20860474eb..6109e60945 100644 --- a/pcbnew/class_board.cpp +++ b/pcbnew/class_board.cpp @@ -242,7 +242,7 @@ void BOARD::chainMarkedSegments( wxPoint aPosition, LAYER_MSK aLayerMask, TRACK_ segment = m_Track; candidate = NULL; NbSegm = 0; - while( ( segment = ::GetTrace( segment, NULL, aPosition, aLayerMask ) ) != NULL ) + while( ( segment = ::GetTrack( segment, NULL, aPosition, aLayerMask ) ) != NULL ) { if( segment->GetState( BUSY ) ) // already found and selected: skip it { @@ -1172,7 +1172,7 @@ SEARCH_RESULT BOARD::Visit( INSPECTOR* inspector, const void* testData, #if 0 // both these are on same list, so we must scan it twice in order // to get VIA priority, using new #else code below. - // But we are not using separate lists for TRACKs and SEGVIAs, because + // But we are not using separate lists for TRACKs and VIA, because // items are ordered (sorted) in the linked // list by netcode AND by physical distance: // when created, if a track or via is connected to an existing track or @@ -1561,11 +1561,9 @@ int BOARD::SetAreasNetCodesFromNetNames( void ) } -TRACK* BOARD::GetViaByPosition( const wxPoint& aPosition, LAYER_NUM aLayer) +VIA* BOARD::GetViaByPosition( const wxPoint& aPosition, LAYER_NUM aLayer) const { - TRACK* track; - - for( track = m_Track; track; track = track->Next() ) + for( TRACK *track = m_Track; track; track = track->Next() ) { if( track->Type() != PCB_VIA_T ) continue; @@ -1576,14 +1574,11 @@ TRACK* BOARD::GetViaByPosition( const wxPoint& aPosition, LAYER_NUM aLayer) if( track->GetState( BUSY | IS_DELETED ) ) continue; - if( aLayer == UNDEFINED_LAYER ) - break; - - if( track->IsOnLayer( aLayer ) ) - break; + if( (aLayer == UNDEFINED_LAYER) || (track->IsOnLayer( aLayer )) ) + return static_cast( track ); } - return track; + return NULL; } @@ -1777,9 +1772,10 @@ void BOARD::GetSortedPadListByXthenYCoord( std::vector& aVector, int aNe } -TRACK* BOARD::GetTrace( TRACK* aTrace, const wxPoint& aPosition, LAYER_MSK aLayerMask ) +TRACK* BOARD::GetTrack( TRACK* aTrace, const wxPoint& aPosition, + LAYER_MSK aLayerMask ) const { - for( TRACK* track = aTrace; track; track = track->Next() ) + for( TRACK* track = aTrace; track; track = track->Next() ) { LAYER_NUM layer = track->GetLayer(); @@ -1846,16 +1842,16 @@ TRACK* BOARD::MarkTrace( TRACK* aTrace, int* aCount, if( aTrace->Type() == PCB_VIA_T ) { TRACK* Segm1, * Segm2 = NULL, * Segm3 = NULL; - Segm1 = ::GetTrace( m_Track, NULL, aTrace->GetStart(), layerMask ); + Segm1 = ::GetTrack( m_Track, NULL, aTrace->GetStart(), layerMask ); if( Segm1 ) { - Segm2 = ::GetTrace( Segm1->Next(), NULL, aTrace->GetStart(), layerMask ); + Segm2 = ::GetTrack( Segm1->Next(), NULL, aTrace->GetStart(), layerMask ); } if( Segm2 ) { - Segm3 = ::GetTrace( Segm2->Next(), NULL, aTrace->GetStart(), layerMask ); + Segm3 = ::GetTrack( Segm2->Next(), NULL, aTrace->GetStart(), layerMask ); } if( Segm3 ) // More than 2 segments are connected to this via. the track" is only this via @@ -1903,7 +1899,7 @@ TRACK* BOARD::MarkTrace( TRACK* aTrace, int* aCount, layerMask = via->GetLayerMask(); - TRACK* track = ::GetTrace( m_Track, NULL, via->GetStart(), layerMask ); + TRACK* track = ::GetTrack( m_Track, NULL, via->GetStart(), layerMask ); // GetTrace does not consider tracks flagged BUSY. // So if no connected track found, this via is on the current track @@ -1925,7 +1921,7 @@ TRACK* BOARD::MarkTrace( TRACK* aTrace, int* aCount, */ LAYER_NUM layer = track->GetLayer(); - while( ( track = ::GetTrace( track->Next(), NULL, via->GetStart(), layerMask ) ) != NULL ) + while( ( track = ::GetTrack( track->Next(), NULL, via->GetStart(), layerMask ) ) != NULL ) { if( layer != track->GetLayer() ) { @@ -2127,10 +2123,10 @@ BOARD_CONNECTED_ITEM* BOARD::GetLockPoint( const wxPoint& aPosition, LAYER_MSK a } /* No pad has been located so check for a segment of the trace. */ - TRACK* segment = ::GetTrace( m_Track, NULL, aPosition, aLayerMask ); + TRACK* segment = ::GetTrack( m_Track, NULL, aPosition, aLayerMask ); if( segment == NULL ) - segment = GetTrace( m_Track, aPosition, aLayerMask ); + segment = GetTrack( m_Track, aPosition, aLayerMask ); return segment; } diff --git a/pcbnew/class_board.h b/pcbnew/class_board.h index 12150cda90..d899096819 100644 --- a/pcbnew/class_board.h +++ b/pcbnew/class_board.h @@ -286,7 +286,7 @@ public: DLIST m_Drawings; // linked list of lines & texts DLIST m_Modules; // linked list of MODULEs - DLIST m_Track; // linked list of TRACKs and SEGVIAs + DLIST m_Track; // linked list of TRACKs and VIAs DLIST m_Zone; // linked list of SEGZONEs /// Ratsnest list for the BOARD @@ -1370,9 +1370,9 @@ public: *

* @param aPosition The wxPoint to HitTest() against. * @param aLayer The layer to search. Use -1 for a don't care. - * @return TRACK* A point a to the SEGVIA object if found, else NULL. + * @return VIA* A point a to the VIA object if found, else NULL. */ - TRACK* GetViaByPosition( const wxPoint& aPosition, LAYER_NUM aLayer = UNDEFINED_LAYER ); + VIA* GetViaByPosition( const wxPoint& aPosition, LAYER_NUM aLayer = UNDEFINED_LAYER ) const; /** * Function GetPad @@ -1438,7 +1438,7 @@ public: void GetSortedPadListByXthenYCoord( std::vector& aVector, int aNetCode = -1 ); /** - * Function GetTrace + * Function GetTrack * find the segment of \a aTrace at \a aPosition on \a aLayer if \a Layer is visible. * Traces that are flagged as deleted or busy are ignored. * @@ -1448,7 +1448,7 @@ public: * layer mask. * @return A TRACK object pointer if found otherwise NULL. */ - TRACK* GetTrace( TRACK* aTrace, const wxPoint& aPosition, LAYER_MSK aLayerMask ); + TRACK* GetTrack( TRACK* aTrace, const wxPoint& aPosition, LAYER_MSK aLayerMask ) const; /** * Function MarkTrace diff --git a/pcbnew/class_netinfo_item.cpp b/pcbnew/class_netinfo_item.cpp index f61705385f..447cf8a503 100644 --- a/pcbnew/class_netinfo_item.cpp +++ b/pcbnew/class_netinfo_item.cpp @@ -82,7 +82,6 @@ void NETINFO_ITEM::Draw( EDA_DRAW_PANEL* panel, void NETINFO_ITEM::GetMsgPanelInfo( std::vector< MSG_PANEL_ITEM >& aList ) { int count; - EDA_ITEM* Struct; wxString txt; MODULE* module; D_PAD* pad; @@ -113,20 +112,19 @@ void NETINFO_ITEM::GetMsgPanelInfo( std::vector< MSG_PANEL_ITEM >& aList ) aList.push_back( MSG_PANEL_ITEM( _( "Pads" ), txt, DARKGREEN ) ); count = 0; - Struct = m_parent->GetBoard()->m_Track; - for( ; Struct != NULL; Struct = Struct->Next() ) + for( const TRACK *track = m_parent->GetBoard()->m_Track; track != NULL; track = track->Next() ) { - if( Struct->Type() == PCB_VIA_T ) + if( track->Type() == PCB_VIA_T ) { - if( ( (SEGVIA*) Struct )->GetNetCode() == GetNet() ) + if( track->GetNetCode() == GetNet() ) count++; } - if( Struct->Type() == PCB_TRACE_T ) + if( track->Type() == PCB_TRACE_T ) { - if( ( (TRACK*) Struct )->GetNetCode() == GetNet() ) - lengthnet += ( (TRACK*) Struct )->GetLength(); + if( track->GetNetCode() == GetNet() ) + lengthnet += track->GetLength(); } } diff --git a/pcbnew/class_track.cpp b/pcbnew/class_track.cpp index f15033d3e1..48a665927d 100644 --- a/pcbnew/class_track.cpp +++ b/pcbnew/class_track.cpp @@ -88,15 +88,13 @@ inline bool IsNear( wxPoint& p1, wxPoint& p2, int max_dist ) } -TRACK* GetTrace( TRACK* aStartTrace, TRACK* aEndTrace, const wxPoint& aPosition, - LAYER_MSK aLayerMask ) +TRACK* GetTrack( TRACK* aStartTrace, TRACK* aEndTrace, + const wxPoint& aPosition, LAYER_MSK aLayerMask ) { - TRACK* PtSegm; - if( aStartTrace == NULL ) return NULL; - for( PtSegm = aStartTrace; PtSegm != NULL; PtSegm = PtSegm->Next() ) + for( TRACK *PtSegm = aStartTrace; PtSegm != NULL; PtSegm = PtSegm->Next() ) { if( PtSegm->GetState( IS_DELETED | BUSY ) == 0 ) { @@ -125,9 +123,7 @@ TRACK::TRACK( BOARD_ITEM* aParent, KICAD_T idtype ) : BOARD_CONNECTED_ITEM( aParent, idtype ) { m_Width = Millimeter2iu( 0.2 ); - m_Shape = S_SEGMENT; start = end = NULL; - SetDrillDefault(); m_Param = 0; } @@ -179,34 +175,41 @@ wxString SEGZONE::GetSelectMenuText() const } -SEGVIA::SEGVIA( BOARD_ITEM* aParent ) : +VIA::VIA( BOARD_ITEM* aParent ) : TRACK( aParent, PCB_VIA_T ) { - SetShape( VIA_THROUGH ); + SetViaType( VIA_THROUGH ); m_Width = Millimeter2iu( 0.5 ); + SetDrillDefault(); } -EDA_ITEM* SEGVIA::Clone() const +EDA_ITEM* VIA::Clone() const { - return new SEGVIA( *this ); + return new VIA( *this ); } -wxString SEGVIA::GetSelectMenuText() const +wxString VIA::GetSelectMenuText() const { wxString text; wxString format; BOARD* board = GetBoard(); - int shape = GetShape(); - - if( shape == VIA_BLIND_BURIED ) + switch( GetViaType() ) + { + case VIA_BLIND_BURIED: format = _( "Blind/Buried Via %s, net[%s] (%d) on layers %s/%s" ); - else if( shape == VIA_MICROVIA ) + break; + case VIA_MICROVIA: format = _( "Micro Via %s, Net [%s] (%d) on layers %s/%s" ); + break; // else say nothing about normal (through) vias - else format = _( "Via %s net [%s] (%d) on layers %s/%s" ); + default: + format = _( "Via %s net [%s] (%d) on layers %s/%s" ); + break; + } + if( board ) { @@ -224,7 +227,7 @@ wxString SEGVIA::GetSelectMenuText() const } else { - wxFAIL_MSG( wxT( "SEGVIA::GetSelectMenuText: BOARD is NULL" ) ); + wxFAIL_MSG( wxT( "VIA::GetSelectMenuText: BOARD is NULL" ) ); text.Printf( format.GetData(), GetChars( ShowWidth() ), wxT( "???" ), 0, wxT( "??" ), wxT( "??" ) ); @@ -242,18 +245,15 @@ int TRACK::GetClearance( BOARD_CONNECTED_ITEM* aItem ) const } -int TRACK::GetDrillValue() const +int VIA::GetDrillValue() const { - if( Type() != PCB_VIA_T ) - return 0; - if( m_Drill > 0 ) // Use the specific value. return m_Drill; // Use the default value from the Netclass NETCLASS* netclass = GetNetClass(); - if( m_Shape == VIA_MICROVIA ) + if( GetViaType() == VIA_MICROVIA ) return netclass->GetuViaDrill(); return netclass->GetViaDrill(); @@ -391,7 +391,7 @@ SEARCH_RESULT TRACK::Visit( INSPECTOR* inspector, const void* testData, } -bool SEGVIA::IsOnLayer( LAYER_NUM layer_number ) const +bool VIA::IsOnLayer( LAYER_NUM layer_number ) const { LAYER_NUM bottom_layer, top_layer; @@ -403,43 +403,38 @@ bool SEGVIA::IsOnLayer( LAYER_NUM layer_number ) const return false; } +LAYER_MSK VIA::GetLayerMask() const +{ + if( GetViaType() == VIA_THROUGH ) + return ALL_CU_LAYERS; + + // VIA_BLIND_BURIED or VIA_MICRVIA: + + LAYER_NUM bottom_layer, top_layer; + + // LayerPair() knows how layers are stored + LayerPair( &top_layer, &bottom_layer ); + + LAYER_MSK layermask = NO_LAYERS; + + while( bottom_layer <= top_layer ) + { + layermask |= ::GetLayerMask( bottom_layer ); + ++bottom_layer; + } + + return layermask; +} LAYER_MSK TRACK::GetLayerMask() const { - if( Type() == PCB_VIA_T ) - { - int via_type = GetShape(); - - if( via_type == VIA_THROUGH ) - return ALL_CU_LAYERS; - - // VIA_BLIND_BURIED or VIA_MICRVIA: - - LAYER_NUM bottom_layer, top_layer; - - // LayerPair() knows how layers are stored - ( (SEGVIA*) this )->LayerPair( &top_layer, &bottom_layer ); - - LAYER_MSK layermask = NO_LAYERS; - - while( bottom_layer <= top_layer ) - { - layermask |= ::GetLayerMask( bottom_layer ); - ++bottom_layer; - } - - return layermask; - } - else - { - return ::GetLayerMask( m_Layer ); - } + return ::GetLayerMask( m_Layer ); } -void SEGVIA::SetLayerPair( LAYER_NUM top_layer, LAYER_NUM bottom_layer ) +void VIA::SetLayerPair( LAYER_NUM top_layer, LAYER_NUM bottom_layer ) { - if( GetShape() == VIA_THROUGH ) + if( GetViaType() == VIA_THROUGH ) { top_layer = LAYER_N_FRONT; bottom_layer = LAYER_N_BACK; @@ -453,12 +448,12 @@ void SEGVIA::SetLayerPair( LAYER_NUM top_layer, LAYER_NUM bottom_layer ) } -void SEGVIA::LayerPair( LAYER_NUM* top_layer, LAYER_NUM* bottom_layer ) const +void VIA::LayerPair( LAYER_NUM* top_layer, LAYER_NUM* bottom_layer ) const { LAYER_NUM b_layer = LAYER_N_BACK; LAYER_NUM t_layer = LAYER_N_FRONT; - if( GetShape() != VIA_THROUGH ) + if( GetViaType() != VIA_THROUGH ) { // XXX EVIL usage of LAYER b_layer = (m_Layer >> 4) & 15; @@ -557,116 +552,13 @@ TRACK* TRACK::GetEndNetCode( int NetCode ) return NULL; } - -void TRACK::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, - const wxPoint& aOffset ) +void TRACK::DrawShortNetname( EDA_DRAW_PANEL* panel, + wxDC* aDC, GR_DRAWMODE aDrawMode, EDA_COLOR_T aBgColor ) { - int l_trace; - int radius; - LAYER_NUM curr_layer = ( (PCB_SCREEN*) panel->GetScreen() )->m_Active_Layer; - - if( Type() == PCB_ZONE_T && DisplayOpt.DisplayZonesMode != 0 ) - return; - - BOARD * brd = GetBoard( ); - EDA_COLOR_T color = brd->GetLayerColor(m_Layer); - - if( brd->IsLayerVisible( m_Layer ) == false && !( aDrawMode & GR_HIGHLIGHT ) ) - return; - -#ifdef USE_WX_OVERLAY - // If dragged not draw in OnPaint otherwise remains impressed in wxOverlay - if( (m_Flags && IS_DRAGGED) && aDC->IsKindOf(wxCLASSINFO(wxPaintDC))) - return; -#endif - - if( ( aDrawMode & GR_ALLOW_HIGHCONTRAST ) && DisplayOpt.ContrastModeDisplay ) - { - if( !IsOnLayer( curr_layer ) ) - ColorTurnToDarkDarkGray( &color ); - } - - if( aDrawMode & GR_HIGHLIGHT ) - ColorChangeHighlightFlag( &color, !(aDrawMode & GR_AND) ); - - ColorApplyHighlightFlag( &color ); - - SetAlpha( &color, 150 ); - - GRSetDrawMode( aDC, aDrawMode ); - - - l_trace = m_Width >> 1; - - if( m_Shape == S_CIRCLE ) - { - radius = KiROUND( GetLineLength( m_Start, m_End ) ); - - if( aDC->LogicalToDeviceXRel( l_trace ) <= MIN_DRAW_WIDTH ) - { - GRCircle( panel->GetClipBox(), aDC, m_Start.x + aOffset.x, - m_Start.y + aOffset.y, radius, color ); - } - else - { - - if( aDC->LogicalToDeviceXRel( l_trace ) <= MIN_DRAW_WIDTH ) // Line mode if too small - { - GRCircle( panel->GetClipBox(), aDC, m_Start.x + aOffset.x, - m_Start.y + aOffset.y, radius, color ); - } - else if( ( !DisplayOpt.DisplayPcbTrackFill) || GetState( FORCE_SKETCH ) ) - { - GRCircle( panel->GetClipBox(), aDC, m_Start.x + aOffset.x, - m_Start.y + aOffset.y, radius - l_trace, color ); - GRCircle( panel->GetClipBox(), aDC, m_Start.x + aOffset.x, - m_Start.y + aOffset.y, radius + l_trace, color ); - } - else - { - GRCircle( panel->GetClipBox(), aDC, m_Start.x + aOffset.x, - m_Start.y + aOffset.y, radius, m_Width, color ); - } - } - - return; - } - - if( aDC->LogicalToDeviceXRel( l_trace ) <= MIN_DRAW_WIDTH ) - { - GRLine( panel->GetClipBox(), aDC, m_Start + aOffset, m_End + aOffset, 0, color ); - return; - } - - if( !DisplayOpt.DisplayPcbTrackFill || GetState( FORCE_SKETCH ) ) - { - GRCSegm( panel->GetClipBox(), aDC, m_Start + aOffset, m_End + aOffset, m_Width, color ); - } - else - { - GRFillCSegm( panel->GetClipBox(), aDC, m_Start.x + aOffset.x, - m_Start.y + aOffset.y, - m_End.x + aOffset.x, m_End.y + aOffset.y, m_Width, color ); - } - - if( panel->GetScreen()->m_IsPrinting ) - return; - - // Show clearance for tracks, not for zone segments - if( ShowClearance( this ) ) - { - GRCSegm( panel->GetClipBox(), aDC, m_Start + aOffset, m_End + aOffset, - m_Width + (GetClearance() * 2), color ); - } - - /* Display the short netname for tracks, not for zone segments. - * we must filter tracks, to avoid a lot of texts. + /* we must filter tracks, to avoid a lot of texts. * - only tracks with a length > 10 * thickness are eligible * and, of course, if we are not printing the board */ - if( Type() == PCB_ZONE_T ) - return; - if( DisplayOpt.DisplayNetNamesMode == 0 || DisplayOpt.DisplayNetNamesMode == 1 ) return; @@ -703,7 +595,7 @@ void TRACK::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, // Calculate angle: if the track segment is vertical, angle = 90 degrees // If horizontal 0 degrees, otherwise compute it - double angle; // angle is in 0.1 degree + double angle; // angle is in 0.1 degree if( dy == 0 ) // Horizontal segment { @@ -723,6 +615,7 @@ void TRACK::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, } } + LAYER_NUM curr_layer = ( (PCB_SCREEN*) panel->GetScreen() )->m_Active_Layer; if( ( aDC->LogicalToDeviceXRel( tsize ) >= MIN_TEXT_SIZE ) && ( !(!IsOnLayer( curr_layer )&& DisplayOpt.ContrastModeDisplay) ) ) { @@ -732,15 +625,136 @@ void TRACK::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, tsize = (tsize * 7) / 10; // small reduction to give a better look EDA_RECT* clipbox = panel? panel->GetClipBox() : NULL; DrawGraphicHaloText( clipbox, aDC, tpos, - color, BLACK, WHITE, net->GetShortNetname(), angle, - wxSize( tsize, tsize ), - GR_TEXT_HJUSTIFY_CENTER, GR_TEXT_VJUSTIFY_CENTER, - tsize / 7, - false, false ); + aBgColor, BLACK, WHITE, net->GetShortNetname(), angle, + wxSize( tsize, tsize ), + GR_TEXT_HJUSTIFY_CENTER, GR_TEXT_VJUSTIFY_CENTER, + tsize / 7, + false, false ); } } } +void TRACK::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, + const wxPoint& aOffset ) +{ + BOARD * brd = GetBoard( ); + EDA_COLOR_T color = brd->GetLayerColor(m_Layer); + + if( brd->IsLayerVisible( m_Layer ) == false && !( aDrawMode & GR_HIGHLIGHT ) ) + return; + +#ifdef USE_WX_OVERLAY + // If dragged not draw in OnPaint otherwise remains impressed in wxOverlay + if( (m_Flags && IS_DRAGGED) && aDC->IsKindOf(wxCLASSINFO(wxPaintDC))) + return; +#endif + + if( ( aDrawMode & GR_ALLOW_HIGHCONTRAST ) && DisplayOpt.ContrastModeDisplay ) + { + LAYER_NUM curr_layer = ( (PCB_SCREEN*) panel->GetScreen() )->m_Active_Layer; + + if( !IsOnLayer( curr_layer ) ) + ColorTurnToDarkDarkGray( &color ); + } + + if( aDrawMode & GR_HIGHLIGHT ) + ColorChangeHighlightFlag( &color, !(aDrawMode & GR_AND) ); + + ColorApplyHighlightFlag( &color ); + + SetAlpha( &color, 150 ); + + GRSetDrawMode( aDC, aDrawMode ); + + int l_trace = m_Width / 2; + + if( aDC->LogicalToDeviceXRel( l_trace ) <= MIN_DRAW_WIDTH ) + { + GRLine( panel->GetClipBox(), aDC, m_Start + aOffset, m_End + aOffset, 0, color ); + return; + } + + if( !DisplayOpt.DisplayPcbTrackFill || GetState( FORCE_SKETCH ) ) + { + GRCSegm( panel->GetClipBox(), aDC, m_Start + aOffset, m_End + aOffset, m_Width, color ); + } + else + { + GRFillCSegm( panel->GetClipBox(), aDC, m_Start.x + aOffset.x, + m_Start.y + aOffset.y, + m_End.x + aOffset.x, m_End.y + aOffset.y, m_Width, color ); + } + + if( panel->GetScreen()->m_IsPrinting ) + return; + + // Show clearance for tracks, not for zone segments + if( ShowClearance( this ) ) + { + GRCSegm( panel->GetClipBox(), aDC, m_Start + aOffset, m_End + aOffset, + m_Width + (GetClearance() * 2), color ); + } + + DrawShortNetname( panel, aDC, aDrawMode, color ); +} + +void SEGZONE::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, + const wxPoint& aOffset ) +{ + if( DisplayOpt.DisplayZonesMode != 0 ) + return; + + BOARD * brd = GetBoard( ); + EDA_COLOR_T color = brd->GetLayerColor(m_Layer); + + if( brd->IsLayerVisible( m_Layer ) == false && !( aDrawMode & GR_HIGHLIGHT ) ) + return; + +#ifdef USE_WX_OVERLAY + // If dragged not draw in OnPaint otherwise remains impressed in wxOverlay + if( (m_Flags && IS_DRAGGED) && aDC->IsKindOf(wxCLASSINFO(wxPaintDC))) + return; +#endif + + if( ( aDrawMode & GR_ALLOW_HIGHCONTRAST ) && DisplayOpt.ContrastModeDisplay ) + { + LAYER_NUM curr_layer = ( (PCB_SCREEN*) panel->GetScreen() )->m_Active_Layer; + + if( !IsOnLayer( curr_layer ) ) + ColorTurnToDarkDarkGray( &color ); + } + + if( aDrawMode & GR_HIGHLIGHT ) + ColorChangeHighlightFlag( &color, !(aDrawMode & GR_AND) ); + + ColorApplyHighlightFlag( &color ); + + SetAlpha( &color, 150 ); + + GRSetDrawMode( aDC, aDrawMode ); + + int l_trace = m_Width / 2; + + if( aDC->LogicalToDeviceXRel( l_trace ) <= MIN_DRAW_WIDTH ) + { + GRLine( panel->GetClipBox(), aDC, m_Start + aOffset, m_End + aOffset, 0, color ); + return; + } + + if( !DisplayOpt.DisplayPcbTrackFill || GetState( FORCE_SKETCH ) ) + { + GRCSegm( panel->GetClipBox(), aDC, m_Start + aOffset, m_End + aOffset, m_Width, color ); + } + else + { + GRFillCSegm( panel->GetClipBox(), aDC, m_Start.x + aOffset.x, + m_Start.y + aOffset.y, + m_End.x + aOffset.x, m_End.y + aOffset.y, m_Width, color ); + } + + // No clearance or netnames for zones +} + void TRACK::ViewGetLayers( int aLayers[], int& aCount ) const { @@ -764,7 +778,7 @@ unsigned int TRACK::ViewGetLOD( int aLayer ) const } -void SEGVIA::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, +void VIA::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, const wxPoint& aOffset ) { int radius; @@ -780,9 +794,9 @@ void SEGVIA::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, GRSetDrawMode( aDC, aDrawMode ); BOARD * brd = GetBoard( ); - EDA_COLOR_T color = brd->GetVisibleElementColor(VIAS_VISIBLE + m_Shape); + EDA_COLOR_T color = brd->GetVisibleElementColor(VIAS_VISIBLE + GetViaType()); - if( brd->IsElementVisible( PCB_VISIBLE(VIAS_VISIBLE + m_Shape) ) == false + if( brd->IsElementVisible( PCB_VISIBLE(VIAS_VISIBLE + GetViaType()) ) == false && ( color & HIGHLIGHT_FLAG ) != HIGHLIGHT_FLAG ) return; @@ -879,7 +893,7 @@ void SEGVIA::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, // for Micro Vias, draw a partial cross : X on component layer, or + on copper layer // (so we can see 2 superimposed microvias ): - if( GetShape() == VIA_MICROVIA ) + if( GetViaType() == VIA_MICROVIA ) { int ax, ay, bx, by; @@ -917,12 +931,12 @@ void SEGVIA::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, // for Buried Vias, draw a partial line : orient depending on layer pair // (so we can see superimposed buried vias ): - if( GetShape() == VIA_BLIND_BURIED ) + if( GetViaType() == VIA_BLIND_BURIED ) { int ax = 0, ay = radius, bx = 0, by = drill_radius; LAYER_NUM layer_top, layer_bottom; - ( (SEGVIA*) this )->LayerPair( &layer_top, &layer_bottom ); + ( (VIA*) this )->LayerPair( &layer_top, &layer_bottom ); // lines for the top layer RotatePoint( &ax, &ay, layer_top * 3600.0 / brd->GetCopperLayerCount( ) ); @@ -978,7 +992,7 @@ void SEGVIA::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, } -void SEGVIA::ViewGetLayers( int aLayers[], int& aCount ) const +void VIA::ViewGetLayers( int aLayers[], int& aCount ) const { // Just show it on common via & via holes layers aLayers[0] = ITEM_GAL_LAYER( VIAS_VISIBLE ); @@ -1035,56 +1049,12 @@ void TRACK::GetMsgPanelInfo( std::vector< MSG_PANEL_ITEM >& aList ) } } - -void TRACK::GetMsgPanelInfoBase( std::vector< MSG_PANEL_ITEM >& aList ) +void TRACK::GetMsgPanelInfoBase_Common( std::vector< MSG_PANEL_ITEM >& aList ) { wxString msg; - BOARD* board = GetBoard(); - switch( Type() ) - { - case PCB_VIA_T: - switch( GetShape() ) - { - default: - case 0: - msg = wxT( "???" ); // Not used yet, does not exist currently - break; - - case 1: - msg = _( "Micro Via" ); // from external layer (TOP or BOTTOM) from - // the near neighbor inner layer only - break; - - case 2: - msg = _( "Blind/Buried Via" ); // from inner or external to inner - // or external layer (no restriction) - break; - - case 3: - msg = _( "Through Via" ); // Usual via (from TOP to BOTTOM layer only ) - break; - } - - break; - - case PCB_TRACE_T: - msg = _( "Track" ); - break; - - case PCB_ZONE_T: - msg = _( "Zone" ); - break; - - default: - msg = wxT( "???" ); - break; - } - - aList.push_back( MSG_PANEL_ITEM( _( "Type" ), msg, DARKCYAN ) ); - - // Display Net Name (in Pcbnew) - if( board ) + // Display Net Name + if( GetBoard() ) { NETINFO_ITEM* net = GetNet(); @@ -1095,7 +1065,7 @@ void TRACK::GetMsgPanelInfoBase( std::vector< MSG_PANEL_ITEM >& aList ) aList.push_back( MSG_PANEL_ITEM( _( "NetName" ), msg, RED ) ); - /* Display net code : (useful in test or debug) */ + // Display net code : (useful in test or debug) msg.Printf( wxT( "%d.%d" ), GetNetCode(), GetSubNet() ); aList.push_back( MSG_PANEL_ITEM( _( "NetCode" ), msg, RED ) ); } @@ -1127,7 +1097,7 @@ void TRACK::GetMsgPanelInfoBase( std::vector< MSG_PANEL_ITEM >& aList ) #endif // defined(DEBUG) - /* Display the State member */ + // Display the State member msg = wxT( ". . " ); if( GetState( TRACK_LOCKED ) ) @@ -1137,64 +1107,126 @@ void TRACK::GetMsgPanelInfoBase( std::vector< MSG_PANEL_ITEM >& aList ) msg[2] = 'A'; aList.push_back( MSG_PANEL_ITEM( _( "Status" ), msg, MAGENTA ) ); +} - /* Display layer or layer pair) */ - if( Type() == PCB_VIA_T ) - { - SEGVIA* Via = (SEGVIA*) this; - LAYER_NUM top_layer, bottom_layer; +void TRACK::GetMsgPanelInfoBase( std::vector< MSG_PANEL_ITEM >& aList ) +{ + wxString msg; + BOARD* board = GetBoard(); - Via->LayerPair( &top_layer, &bottom_layer ); - if( board ) - msg = board->GetLayerName( top_layer ) + wxT( "/" ) - + board->GetLayerName( bottom_layer ); - else - msg.Printf(wxT("%d/%d"), top_layer, bottom_layer ); - } + aList.push_back( MSG_PANEL_ITEM( _( "Type" ), _( "Track" ), DARKCYAN ) ); + + GetMsgPanelInfoBase_Common( aList ); + + // Display layer + if( board ) + msg = board->GetLayerName( m_Layer ); else - { - if( board ) - msg = board->GetLayerName( m_Layer ); - else - msg.Printf(wxT("%d"), m_Layer ); - } + msg.Printf(wxT("%d"), m_Layer ); aList.push_back( MSG_PANEL_ITEM( _( "Layer" ), msg, BROWN ) ); // Display width msg = ::CoordinateToString( (unsigned) m_Width ); - if( Type() == PCB_VIA_T ) // Display Diam and Drill values - { - // Display diameter value: - aList.push_back( MSG_PANEL_ITEM( _( "Diam" ), msg, DARKCYAN ) ); - - // Display drill value - int drill_value = GetDrillValue(); - - msg = ::CoordinateToString( drill_value ); - - wxString title = _( "Drill" ); - title += wxT( " " ); - - if( m_Drill >= 0 ) - title += _( "(Specific)" ); - else - title += _( "(Default)" ); - - aList.push_back( MSG_PANEL_ITEM( title, msg, RED ) ); - } - else - { - aList.push_back( MSG_PANEL_ITEM( _( "Width" ), msg, DARKCYAN ) ); - } + aList.push_back( MSG_PANEL_ITEM( _( "Width" ), msg, DARKCYAN ) ); // Display segment length - if( Type() != PCB_VIA_T ) // Display Diam and Drill values + msg = ::LengthDoubleToString( GetLength() ); + aList.push_back( MSG_PANEL_ITEM( _( "Segment Length" ), msg, DARKCYAN ) ); +} + +void SEGZONE::GetMsgPanelInfoBase( std::vector< MSG_PANEL_ITEM >& aList ) +{ + wxString msg; + BOARD* board = GetBoard(); + + aList.push_back( MSG_PANEL_ITEM( _( "Type" ), _( "Zone " ), DARKCYAN ) ); + + GetMsgPanelInfoBase_Common( aList ); + + // Display layer + if( board ) + msg = board->GetLayerName( m_Layer ); + else + msg.Printf(wxT("%d"), m_Layer ); + + aList.push_back( MSG_PANEL_ITEM( _( "Layer" ), msg, BROWN ) ); + + // Display width + msg = ::CoordinateToString( (unsigned) m_Width ); + + aList.push_back( MSG_PANEL_ITEM( _( "Width" ), msg, DARKCYAN ) ); + + // Display segment length + msg = ::LengthDoubleToString( GetLength() ); + aList.push_back( MSG_PANEL_ITEM( _( "Segment Length" ), msg, DARKCYAN ) ); +} + +void VIA::GetMsgPanelInfoBase( std::vector< MSG_PANEL_ITEM >& aList ) +{ + wxString msg; + BOARD* board = GetBoard(); + + switch( GetViaType() ) { - msg = ::LengthDoubleToString( GetLength() ); - aList.push_back( MSG_PANEL_ITEM( _( "Segment Length" ), msg, DARKCYAN ) ); + default: + case VIA_NOT_DEFINED: + msg = wxT( "???" ); // Not used yet, does not exist currently + break; + + case VIA_MICROVIA: + msg = _( "Micro Via" ); // from external layer (TOP or BOTTOM) from + // the near neighbor inner layer only + break; + + case VIA_BLIND_BURIED: + msg = _( "Blind/Buried Via" ); // from inner or external to inner + // or external layer (no restriction) + break; + + case VIA_THROUGH: + msg = _( "Through Via" ); // Usual via (from TOP to BOTTOM layer only ) + break; } + + aList.push_back( MSG_PANEL_ITEM( _( "Type" ), msg, DARKCYAN ) ); + + GetMsgPanelInfoBase_Common( aList ); + + + // Display layer pair + LAYER_NUM top_layer, bottom_layer; + + LayerPair( &top_layer, &bottom_layer ); + if( board ) + msg = board->GetLayerName( top_layer ) + wxT( "/" ) + + board->GetLayerName( bottom_layer ); + else + msg.Printf(wxT("%d/%d"), top_layer, bottom_layer ); + + aList.push_back( MSG_PANEL_ITEM( _( "Layers" ), msg, BROWN ) ); + + // Display width + msg = ::CoordinateToString( (unsigned) m_Width ); + + // Display diameter value: + aList.push_back( MSG_PANEL_ITEM( _( "Diam" ), msg, DARKCYAN ) ); + + // Display drill value + int drill_value = GetDrillValue(); + + msg = ::CoordinateToString( drill_value ); + + wxString title = _( "Drill" ); + title += wxT( " " ); + + if( m_Drill >= 0 ) + title += _( "(Specific)" ); + else + title += _( "(Default)" ); + + aList.push_back( MSG_PANEL_ITEM( title, msg, RED ) ); } @@ -1243,11 +1275,9 @@ bool TRACK::HitTest( const EDA_RECT& aRect, bool aContained, int aAccuracy ) con } -TRACK* TRACK::GetVia( const wxPoint& aPosition, LAYER_NUM aLayer) +VIA* TRACK::GetVia( const wxPoint& aPosition, LAYER_NUM aLayer) { - TRACK* track; - - for( track = this; track; track = track->Next() ) + for( TRACK *track = this; track; track = track->Next() ) { if( track->Type() != PCB_VIA_T ) continue; @@ -1258,22 +1288,17 @@ TRACK* TRACK::GetVia( const wxPoint& aPosition, LAYER_NUM aLayer) if( track->GetState( BUSY | IS_DELETED ) ) continue; - if( aLayer == UNDEFINED_LAYER ) - break; - - if( track->IsOnLayer( aLayer ) ) - break; + if( (aLayer == UNDEFINED_LAYER) || (track->IsOnLayer( aLayer )) ) + return static_cast( track ); } - return track; + return NULL; } -TRACK* TRACK::GetVia( TRACK* aEndTrace, const wxPoint& aPosition, LAYER_MSK aLayerMask ) +VIA* TRACK::GetVia( TRACK* aEndTrace, const wxPoint& aPosition, LAYER_MSK aLayerMask ) { - TRACK* trace; - - for( trace = this; trace != NULL; trace = trace->Next() ) + for( TRACK *trace = this; trace; trace = trace->Next() ) { if( trace->Type() == PCB_VIA_T ) { @@ -1282,7 +1307,7 @@ TRACK* TRACK::GetVia( TRACK* aEndTrace, const wxPoint& aPosition, LAYER_MSK aLay if( trace->GetState( BUSY | IS_DELETED ) == 0 ) { if( aLayerMask & trace->GetLayerMask() ) - return trace; + return static_cast( trace ); } } } @@ -1295,7 +1320,7 @@ TRACK* TRACK::GetVia( TRACK* aEndTrace, const wxPoint& aPosition, LAYER_MSK aLay } -TRACK* TRACK::GetTrace( TRACK* aStartTrace, TRACK* aEndTrace, int aEndPoint ) +TRACK* TRACK::GetTrack( TRACK* aStartTrace, TRACK* aEndTrace, int aEndPoint ) { const int NEIGHTBOUR_COUNT_MAX = 50; @@ -1466,7 +1491,7 @@ int TRACK::GetEndSegments( int aCount, TRACK** aStartTrace, TRACK** aEndTrace ) } Track->SetState( BUSY, true ); - segm = ::GetTrace( this, TrackListEnd, Track->m_Start, layerMask ); + segm = ::GetTrack( this, TrackListEnd, Track->m_Start, layerMask ); Track->SetState( BUSY, false ); if( via ) @@ -1513,7 +1538,7 @@ int TRACK::GetEndSegments( int aCount, TRACK** aStartTrace, TRACK** aEndTrace ) } Track->SetState( BUSY, true ); - segm = ::GetTrace( this, TrackListEnd, Track->m_End, layerMask ); + segm = ::GetTrack( this, TrackListEnd, Track->m_End, layerMask ); Track->SetState( BUSY, false ); if( via ) diff --git a/pcbnew/class_track.h b/pcbnew/class_track.h index 56ac970102..8b727dde17 100644 --- a/pcbnew/class_track.h +++ b/pcbnew/class_track.h @@ -38,23 +38,27 @@ class TRACK; +class VIA; class D_PAD; class MSG_PANEL_ITEM; -// Via attributes (m_Shape parameter) -#define VIA_THROUGH 3 /* Always a through hole via */ -#define VIA_BLIND_BURIED 2 /* this via can be on internal layers */ -#define VIA_MICROVIA 1 /* this via which connect from an external layer - * to the near neighbor internal layer */ -#define VIA_NOT_DEFINED 0 /* not yet used */ +// Via types +enum VIATYPE_T +{ + VIA_THROUGH = 3, /* Always a through hole via */ + VIA_BLIND_BURIED = 2, /* this via can be on internal layers */ + VIA_MICROVIA = 1, /* this via which connect from an external layer + * to the near neighbor internal layer */ + VIA_NOT_DEFINED = 0 /* not yet used */ +}; #define UNDEFINED_DRILL_DIAMETER -1 //< Undefined via drill diameter. #define MIN_VIA_DRAW_SIZE 4 /// Minimum size in pixel for full drawing /** - * Function GetTrace + * Function GetTrack * is a helper function to locate a trace segment having an end point at \a aPosition * on \a aLayerMask starting at \a aStartTrace and end at \a aEndTrace. *

@@ -69,9 +73,8 @@ class MSG_PANEL_ITEM; * layer mask. * @return A TRACK object pointer if found otherwise NULL. */ -extern TRACK* GetTrace( TRACK* aStartTrace, TRACK* aEndTrace, const wxPoint& aPosition, - LAYER_MSK aLayerMask ); - +extern TRACK* GetTrack( TRACK* aStartTrace, TRACK* aEndTrace, + const wxPoint& aPosition, LAYER_MSK aLayerMask ); class TRACK : public BOARD_CONNECTED_ITEM { @@ -85,9 +88,6 @@ protected: int m_Width; // Thickness of track, or via diameter wxPoint m_Start; // Line start point wxPoint m_End; // Line end point - int m_Shape; // vias: shape and type, Track = shape.. - - int m_Drill; // for vias: via drill (- 1 for default value) public: BOARD_CONNECTED_ITEM* start; // pointers to a connected item (pad or track) @@ -124,9 +124,6 @@ public: void SetStart( const wxPoint& aStart ) { m_Start = aStart; } const wxPoint& GetStart() const { return m_Start; } - int GetShape() const { return m_Shape; } - void SetShape( int aShape ) { m_Shape = aShape; } - // Virtual function const EDA_RECT GetBoundingBox() const; @@ -180,47 +177,13 @@ public: int aClearanceValue, int aCircleToSegmentsCount, double aCorrectionFactor ) const; - /** - * Function SetDrill - * sets the drill value for vias. - * @param aDrill is the new drill diameter - */ - void SetDrill( int aDrill ) { m_Drill = aDrill; } - - /** - * Function GetDrill - * returns the local drill setting for this VIA. If you want the calculated value, - * use GetDrillValue() instead. - */ - int GetDrill() const { return m_Drill; } - - /** - * Function GetDrillValue - * "calculates" the drill value for vias (m-Drill if > 0, or default - * drill value for the board. - * @return real drill_value - */ - int GetDrillValue() const; - - /** - * Function SetDrillDefault - * sets the drill value for vias to the default value #UNDEFINED_DRILL_DIAMETER. - */ - void SetDrillDefault() { m_Drill = UNDEFINED_DRILL_DIAMETER; } - - /** - * Function IsDrillDefault - * @return true if the drill value is default value (-1) - */ - bool IsDrillDefault() { return m_Drill <= 0; } - /** * Function GetLayerMask * returns a "layer mask", which is a bitmap of all layers on which the - * TRACK segment or SEGVIA physically resides. + * TRACK segment or VIA physically resides. * @return int - a layer mask, see pcbstruct.h's LAYER_BACK, etc. */ - LAYER_MSK GetLayerMask() const; + virtual LAYER_MSK GetLayerMask() const; /** * Function IsPointOnEnds @@ -239,13 +202,6 @@ public: void GetMsgPanelInfo( std::vector< MSG_PANEL_ITEM >& aList ); - /** - * Function GetMsgPanelInfoBase - * Display info about the track segment only, and does not calculate the full track length - * @param aList A list of #MSG_PANEL_ITEM objects to add status information. - */ - void GetMsgPanelInfoBase( std::vector< MSG_PANEL_ITEM >& aList ); - /** * Function ShowWidth * returns the width of the track in displayable user units. @@ -265,28 +221,28 @@ public: /** * Function GetVia - * finds the first SEGVIA object at \a aPosition on \a aLayer starting at the trace. + * finds the first VIA object at \a aPosition on \a aLayer starting at the trace. * * @param aPosition The wxPoint to HitTest() against. * @param aLayer The layer to match, pass -1 for a don't care. - * @return A pointer to a SEGVIA object if found, else NULL. + * @return A pointer to a VIA object if found, else NULL. */ - TRACK* GetVia( const wxPoint& aPosition, LAYER_NUM aLayer = UNDEFINED_LAYER ); + VIA* GetVia( const wxPoint& aPosition, LAYER_NUM aLayer = UNDEFINED_LAYER ); /** * Function GetVia - * finds the first SEGVIA object at \a aPosition on \a aLayer starting at the trace + * finds the first VIA object at \a aPosition on \a aLayer starting at the trace * and ending at \a aEndTrace. * * @param aEndTrace Pointer to the last TRACK object to end search. * @param aPosition The wxPoint to HitTest() against. * @param aLayerMask The layers to match, pass -1 for a don't care. - * @return A pointer to a SEGVIA object if found, else NULL. + * @return A pointer to a VIA object if found, else NULL. */ - TRACK* GetVia( TRACK* aEndTrace, const wxPoint& aPosition, LAYER_MSK aLayerMask ); + VIA* GetVia( TRACK* aEndTrace, const wxPoint& aPosition, LAYER_MSK aLayerMask ); /** - * Function GetTrace + * Function GetTrack * return the trace segment connected to the segment at \a aEndPoint from \a * aStartTrace to \a aEndTrace. * @@ -296,7 +252,7 @@ public: * @param aEndPoint The start or end point of the segment to test against. * @return A TRACK object pointer if found otherwise NULL. */ - TRACK* GetTrace( TRACK* aStartTrace, TRACK* aEndTrace, int aEndPoint ); + TRACK* GetTrack( TRACK* aStartTrace, TRACK* aEndTrace, int aEndPoint ); /** * Function GetEndSegments @@ -349,6 +305,24 @@ public: static wxString ShowState( int stateBits ); #endif + +protected: + /** + * Function GetMsgPanelInfoBase + * Display info about the track segment only, and does not calculate the full track length + * @param aList A list of #MSG_PANEL_ITEM objects to add status information. + */ + virtual void GetMsgPanelInfoBase( std::vector< MSG_PANEL_ITEM >& aList ); + + + /** + * Helper function for the common panel info */ + void GetMsgPanelInfoBase_Common( std::vector< MSG_PANEL_ITEM >& aList ); + + /** + * Helper for drawing the short netname in tracks */ + void DrawShortNetname( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, + EDA_COLOR_T aBgColor ); }; @@ -369,16 +343,22 @@ public: wxString GetSelectMenuText() const; + void Draw( EDA_DRAW_PANEL* panel, wxDC* DC, + GR_DRAWMODE aDrawMode, const wxPoint& aOffset = ZeroOffset ); + BITMAP_DEF GetMenuImage() const { return add_zone_xpm; } EDA_ITEM* Clone() const; + +protected: + virtual void GetMsgPanelInfoBase( std::vector< MSG_PANEL_ITEM >& aList ); }; -class SEGVIA : public TRACK +class VIA : public TRACK { public: - SEGVIA( BOARD_ITEM* aParent ); + VIA( BOARD_ITEM* aParent ); // Do not create a copy constructor. The one generated by the compiler is adequate. @@ -387,6 +367,8 @@ public: bool IsOnLayer( LAYER_NUM aLayer ) const; + virtual LAYER_MSK GetLayerMask() const; + /** * Function SetLayerPair * set the .m_Layer member param: @@ -428,6 +410,52 @@ public: #if defined (DEBUG) virtual void Show( int nestLevel, std::ostream& os ) const { ShowDummy( os ); } // override #endif + + VIATYPE_T GetViaType() const { return m_ViaType; } + void SetViaType( VIATYPE_T aViaType ) { m_ViaType = aViaType; } + + /** + * Function SetDrill + * sets the drill value for vias. + * @param aDrill is the new drill diameter + */ + void SetDrill( int aDrill ) { m_Drill = aDrill; } + + /** + * Function GetDrill + * returns the local drill setting for this VIA. If you want the calculated value, + * use GetDrillValue() instead. + */ + int GetDrill() const { return m_Drill; } + + /** + * Function GetDrillValue + * "calculates" the drill value for vias (m-Drill if > 0, or default + * drill value for the board. + * @return real drill_value + */ + int GetDrillValue() const; + + /** + * Function SetDrillDefault + * sets the drill value for vias to the default value #UNDEFINED_DRILL_DIAMETER. + */ + void SetDrillDefault() { m_Drill = UNDEFINED_DRILL_DIAMETER; } + + /** + * Function IsDrillDefault + * @return true if the drill value is default value (-1) + */ + bool IsDrillDefault() const { return m_Drill <= 0; } + + +protected: + virtual void GetMsgPanelInfoBase( std::vector< MSG_PANEL_ITEM >& aList ); + +private: + VIATYPE_T m_ViaType; // Type of via + + int m_Drill; // for vias: via drill (- 1 for default value) }; diff --git a/pcbnew/clean.cpp b/pcbnew/clean.cpp index 63d72de226..443394157d 100644 --- a/pcbnew/clean.cpp +++ b/pcbnew/clean.cpp @@ -111,7 +111,7 @@ void PCB_EDIT_FRAME::Clean_Pcb() * Delete * - Redundant points on tracks (merge aligned segments) * - vias on pad - * - null lenght segments + * - null length segments * Create segments when track ends are incorrectly connected: * i.e. when a track end covers a pad or a via but is not exactly on the pad or the via center */ @@ -201,10 +201,13 @@ bool TRACKS_CLEANER::clean_vias() { if( track->GetStart() != track->GetEnd() ) track->SetEnd( track->GetStart() ); - } - if( track->GetShape() != VIA_THROUGH ) - continue; + VIA *via = static_cast( track ); + /* Important: this cleanup only does thru hole vias, it doesn't + * (yet) handle high density interconnects */ + if( via->GetViaType() != VIA_THROUGH ) + continue; + } // Search and delete others vias at same location TRACK* alt_track = track->Next(); @@ -213,17 +216,21 @@ bool TRACKS_CLEANER::clean_vias() for( ; alt_track != NULL; alt_track = next_track ) { next_track = alt_track->Next(); + VIA *alt_via = dynamic_cast( alt_track ); + if( alt_via ) + { - if( alt_track->GetShape() != VIA_THROUGH ) - continue; + if( alt_via->GetViaType() != VIA_THROUGH ) + continue; - if( alt_track->GetStart() != track->GetStart() ) - continue; + if( alt_via->GetStart() != track->GetStart() ) + continue; - // delete via - alt_track->UnLink(); - delete alt_track; - modified = true; + // delete via + alt_track->UnLink(); + delete alt_track; + modified = true; + } } } @@ -233,7 +240,8 @@ bool TRACKS_CLEANER::clean_vias() { next_track = track->Next(); - if( track->GetShape() != VIA_THROUGH ) + VIA *via = dynamic_cast( track ); + if( !via || (via->GetViaType() != VIA_THROUGH )) continue; // Examine the list of connected pads: @@ -296,7 +304,7 @@ bool TRACKS_CLEANER::deleteUnconnectedTracks() if( (type_end & START_ON_PAD ) == 0 ) { - TRACK* other = track->GetTrace( m_Brd->m_Track, NULL, FLG_START ); + TRACK* other = track->GetTrack( m_Brd->m_Track, NULL, FLG_START ); if( other == NULL ) // Test a connection to zones { @@ -309,7 +317,7 @@ bool TRACKS_CLEANER::deleteUnconnectedTracks() } else { - ((SEGVIA*)track)->LayerPair( &top_layer, &bottom_layer ); + ((VIA*)track)->LayerPair( &top_layer, &bottom_layer ); zone = m_Brd->HitTestForAnyFilledArea( track->GetStart(), top_layer, bottom_layer, track->GetNetCode() ); @@ -332,8 +340,8 @@ bool TRACKS_CLEANER::deleteUnconnectedTracks() // search for another segment following the via track->SetState( BUSY, true ); - SEGVIA* via = (SEGVIA*) other; - other = via->GetTrace( m_Brd->m_Track, NULL, FLG_START ); + VIA* via = (VIA*) other; + other = via->GetTrack( m_Brd->m_Track, NULL, FLG_START ); if( other == NULL ) { @@ -356,7 +364,7 @@ bool TRACKS_CLEANER::deleteUnconnectedTracks() // test if this track end point is connected to an other track if( (type_end & END_ON_PAD ) == 0 ) { - TRACK* other = track->GetTrace( m_Brd->m_Track, NULL, FLG_END ); + TRACK* other = track->GetTrack( m_Brd->m_Track, NULL, FLG_END ); if( other == NULL ) // Test a connection to zones { @@ -369,7 +377,7 @@ bool TRACKS_CLEANER::deleteUnconnectedTracks() } else { - ((SEGVIA*)track)->LayerPair( &top_layer, &bottom_layer ); + ((VIA*)track)->LayerPair( &top_layer, &bottom_layer ); zone = m_Brd->HitTestForAnyFilledArea( track->GetEnd(), top_layer, bottom_layer, track->GetNetCode() ); @@ -393,8 +401,8 @@ bool TRACKS_CLEANER::deleteUnconnectedTracks() track->SetState( BUSY, true ); - SEGVIA* via = (SEGVIA*) other; - other = via->GetTrace( m_Brd->m_Track, NULL, FLG_END ); + VIA* via = (VIA*) other; + other = via->GetTrack( m_Brd->m_Track, NULL, FLG_END ); if( other == NULL ) { @@ -500,7 +508,7 @@ bool TRACKS_CLEANER::clean_segments() // search for a possible point connected to the START point of the current segment for( segStart = segment->Next(); ; ) { - segStart = segment->GetTrace( segStart, NULL, FLG_START ); + segStart = segment->GetTrack( segStart, NULL, FLG_START ); if( segStart ) { @@ -514,7 +522,7 @@ bool TRACKS_CLEANER::clean_segments() // We must have only one segment connected segStart->SetState( BUSY, true ); - other = segment->GetTrace( m_Brd->m_Track, NULL, FLG_START ); + other = segment->GetTrack( m_Brd->m_Track, NULL, FLG_START ); segStart->SetState( BUSY, false ); if( other == NULL ) @@ -540,7 +548,7 @@ bool TRACKS_CLEANER::clean_segments() // search for a possible point connected to the END point of the current segment: for( segEnd = segment->Next(); ; ) { - segEnd = segment->GetTrace( segEnd, NULL, FLG_END ); + segEnd = segment->GetTrack( segEnd, NULL, FLG_END ); if( segEnd ) { @@ -552,7 +560,7 @@ bool TRACKS_CLEANER::clean_segments() // We must have only one segment connected segEnd->SetState( BUSY, true ); - other = segment->GetTrace( m_Brd->m_Track, NULL, FLG_END ); + other = segment->GetTrack( m_Brd->m_Track, NULL, FLG_END ); segEnd->SetState( BUSY, false ); if( other == NULL ) @@ -736,7 +744,7 @@ bool PCB_EDIT_FRAME::RemoveMisConnectedTracks() } else { - other = segment->GetTrace( GetBoard()->m_Track, NULL, FLG_START ); + other = segment->GetTrack( GetBoard()->m_Track, NULL, FLG_START ); if( other ) net_code_s = other->GetNetCode(); @@ -754,7 +762,7 @@ bool PCB_EDIT_FRAME::RemoveMisConnectedTracks() } else { - other = segment->GetTrace( GetBoard()->m_Track, NULL, FLG_END ); + other = segment->GetTrack( GetBoard()->m_Track, NULL, FLG_END ); if( other ) net_code_e = other->GetNetCode(); diff --git a/pcbnew/collectors.cpp b/pcbnew/collectors.cpp index 4aee57a556..2470684c6d 100644 --- a/pcbnew/collectors.cpp +++ b/pcbnew/collectors.cpp @@ -149,7 +149,7 @@ SEARCH_RESULT GENERAL_COLLECTOR::Inspect( EDA_ITEM* testItem, const void* testDa MODULE* module = NULL; D_PAD* pad = NULL; bool pad_through = false; - SEGVIA* via = NULL; + VIA* via = NULL; MARKER_PCB* marker = NULL; #if 0 // debugging @@ -252,7 +252,7 @@ SEARCH_RESULT GENERAL_COLLECTOR::Inspect( EDA_ITEM* testItem, const void* testDa break; case PCB_VIA_T: // vias are on many layers, so layer test is specific - via = (SEGVIA*) item; + via = (VIA*) item; break; case PCB_TRACE_T: diff --git a/pcbnew/dialogs/dialog_gendrill.cpp b/pcbnew/dialogs/dialog_gendrill.cpp index dc03481fca..6daa73471e 100644 --- a/pcbnew/dialogs/dialog_gendrill.cpp +++ b/pcbnew/dialogs/dialog_gendrill.cpp @@ -140,15 +140,27 @@ void DIALOG_GENDRILL::InitDisplayParams() for( TRACK* track = m_parent->GetBoard()->m_Track; track != NULL; track = track->Next() ) { - if( track->Type() != PCB_VIA_T ) - continue; + const VIA *via = dynamic_cast( track ); + if( via ) + { + switch( via->GetViaType() ) + { + case VIA_THROUGH: + m_throughViasCount++; + break; - if( track->GetShape() == VIA_THROUGH ) - m_throughViasCount++; - else if( track->GetShape() == VIA_MICROVIA ) - m_microViasCount++; - else if( track->GetShape() == VIA_BLIND_BURIED ) - m_blindOrBuriedViasCount++; + case VIA_MICROVIA: + m_microViasCount++; + break; + + case VIA_BLIND_BURIED: + m_blindOrBuriedViasCount++; + break; + + default: + break; + } + } } m_MicroViaDrillValue->Enable( m_microViasCount ); diff --git a/pcbnew/drc.cpp b/pcbnew/drc.cpp index c53df84be0..07b8ebf0f9 100644 --- a/pcbnew/drc.cpp +++ b/pcbnew/drc.cpp @@ -597,7 +597,7 @@ void DRC::testKeepoutAreas() if( ! area->GetDoNotAllowVias() ) continue; - if( ! ((SEGVIA*)segm)->IsOnLayer( area->GetLayer() ) ) + if( ! ((VIA*)segm)->IsOnLayer( area->GetLayer() ) ) continue; if( area->Outline()->Distance( segm->GetPosition() ) < segm->GetWidth()/2 ) @@ -645,7 +645,7 @@ bool DRC::doTrackKeepoutDrc( TRACK* aRefSeg ) if( ! area->GetDoNotAllowVias() ) continue; - if( ! ((SEGVIA*)aRefSeg)->IsOnLayer( area->GetLayer() ) ) + if( ! ((VIA*)aRefSeg)->IsOnLayer( area->GetLayer() ) ) continue; if( area->Outline()->Distance( aRefSeg->GetPosition() ) < aRefSeg->GetWidth()/2 ) diff --git a/pcbnew/drc_clearance_test_functions.cpp b/pcbnew/drc_clearance_test_functions.cpp index 0550f6cfa2..04394d2d08 100644 --- a/pcbnew/drc_clearance_test_functions.cpp +++ b/pcbnew/drc_clearance_test_functions.cpp @@ -169,21 +169,22 @@ bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads ) // Phase 0 : Test vias if( aRefSeg->Type() == PCB_VIA_T ) { + const VIA *refvia = static_cast( aRefSeg ); // test if the via size is smaller than minimum - if( aRefSeg->GetShape() == VIA_MICROVIA ) + if( refvia->GetViaType() == VIA_MICROVIA ) { - if( aRefSeg->GetWidth() < netclass->GetuViaMinDiameter() ) + if( refvia->GetWidth() < netclass->GetuViaMinDiameter() ) { - m_currentMarker = fillMarker( aRefSeg, NULL, + m_currentMarker = fillMarker( refvia, NULL, DRCE_TOO_SMALL_MICROVIA, m_currentMarker ); return false; } } else { - if( aRefSeg->GetWidth() < netclass->GetViaMinDiameter() ) + if( refvia->GetWidth() < netclass->GetViaMinDiameter() ) { - m_currentMarker = fillMarker( aRefSeg, NULL, + m_currentMarker = fillMarker( refvia, NULL, DRCE_TOO_SMALL_VIA, m_currentMarker ); return false; } @@ -192,9 +193,9 @@ bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads ) // test if via's hole is bigger than its diameter // This test is necessary since the via hole size and width can be modified // and a default via hole can be bigger than some vias sizes - if( aRefSeg->GetDrillValue() > aRefSeg->GetWidth() ) + if( refvia->GetDrillValue() > refvia->GetWidth() ) { - m_currentMarker = fillMarker( aRefSeg, NULL, + m_currentMarker = fillMarker( refvia, NULL, DRCE_VIA_HOLE_BIGGER, m_currentMarker ); return false; } @@ -202,12 +203,12 @@ bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads ) // For microvias: test if they are blind vias and only between 2 layers // because they are used for very small drill size and are drill by laser // and **only one layer** can be drilled - if( aRefSeg->GetShape() == VIA_MICROVIA ) + if( refvia->GetViaType() == VIA_MICROVIA ) { LAYER_NUM layer1, layer2; bool err = true; - ( (SEGVIA*) aRefSeg )->LayerPair( &layer1, &layer2 ); + refvia->LayerPair( &layer1, &layer2 ); if( layer1 > layer2 ) EXCHG( layer1, layer2 ); @@ -222,7 +223,7 @@ bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads ) if( err ) { - m_currentMarker = fillMarker( aRefSeg, NULL, + m_currentMarker = fillMarker( refvia, NULL, DRCE_MICRO_VIA_INCORRECT_LAYER_PAIR, m_currentMarker ); return false; } diff --git a/pcbnew/drc_marker_functions.cpp b/pcbnew/drc_marker_functions.cpp index 817d7e17d9..9a5002521d 100644 --- a/pcbnew/drc_marker_functions.cpp +++ b/pcbnew/drc_marker_functions.cpp @@ -44,7 +44,8 @@ #include -MARKER_PCB* DRC::fillMarker( TRACK* aTrack, BOARD_ITEM* aItem, int aErrorCode, MARKER_PCB* fillMe ) +MARKER_PCB* DRC::fillMarker( const TRACK* aTrack, BOARD_ITEM* aItem, int aErrorCode, + MARKER_PCB* fillMe ) { wxString textA = aTrack->GetSelectMenuText(); wxString textB; @@ -62,7 +63,7 @@ MARKER_PCB* DRC::fillMarker( TRACK* aTrack, BOARD_ITEM* aItem, int aErrorCode, M } else if( aItem->Type() == PCB_VIA_T ) { - posB = position = ((SEGVIA*)aItem)->GetPosition(); + posB = position = ((VIA*)aItem)->GetPosition(); } else if( aItem->Type() == PCB_TRACE_T ) { diff --git a/pcbnew/drc_stuff.h b/pcbnew/drc_stuff.h index f2daee5b95..927e94936a 100644 --- a/pcbnew/drc_stuff.h +++ b/pcbnew/drc_stuff.h @@ -212,14 +212,14 @@ private: * DRC problem, or unconnected pad problem. * * @param aTrack The reference track. - * @param aItem Another item on the BOARD, such as a SEGVIA, SEGZONE, + * @param aItem Another item on the BOARD, such as a VIA, SEGZONE, * or TRACK. * @param aErrorCode A categorizing identifier for the particular type * of error that is being reported. * @param fillMe A MARKER_PCB* which is to be filled in, or NULL if one is to * first be allocated, then filled. */ - MARKER_PCB* fillMarker( TRACK* aTrack, BOARD_ITEM* aItem, int aErrorCode, MARKER_PCB* fillMe ); + MARKER_PCB* fillMarker( const TRACK* aTrack, BOARD_ITEM* aItem, int aErrorCode, MARKER_PCB* fillMe ); MARKER_PCB* fillMarker( D_PAD* aPad, D_PAD* bPad, int aErrorCode, MARKER_PCB* fillMe ); diff --git a/pcbnew/eagle_plugin.cpp b/pcbnew/eagle_plugin.cpp index f8e31fddec..a78007761b 100644 --- a/pcbnew/eagle_plugin.cpp +++ b/pcbnew/eagle_plugin.cpp @@ -2410,9 +2410,9 @@ void EAGLE_PLUGIN::loadSignals( CPTREE& aSignals ) if( IsCopperLayer( layer_front_most ) && IsCopperLayer( layer_back_most ) ) { - int kidiam; - int drillz = kicad( v.drill ); - SEGVIA* via = new SEGVIA( m_board ); + int kidiam; + int drillz = kicad( v.drill ); + VIA* via = new VIA( m_board ); m_board->m_Track.Insert( via, NULL ); via->SetLayerPair( layer_front_most, layer_back_most ); @@ -2439,11 +2439,11 @@ void EAGLE_PLUGIN::loadSignals( CPTREE& aSignals ) m_min_via_hole = drillz; if( layer_front_most == LAYER_N_FRONT && layer_back_most == LAYER_N_BACK ) - via->SetShape( VIA_THROUGH ); + via->SetViaType( VIA_THROUGH ); else if( layer_front_most == LAYER_N_FRONT || layer_back_most == LAYER_N_BACK ) - via->SetShape( VIA_MICROVIA ); + via->SetViaType( VIA_MICROVIA ); else - via->SetShape( VIA_BLIND_BURIED ); + via->SetViaType( VIA_BLIND_BURIED ); via->SetTimeStamp( timeStamp( it->second ) ); @@ -2453,8 +2453,6 @@ void EAGLE_PLUGIN::loadSignals( CPTREE& aSignals ) via->SetEnd( pos ); via->SetNetCode( netCode ); - - via->SetShape( S_CIRCLE ); // @todo should be in SEGVIA constructor } m_xpath->pop(); } diff --git a/pcbnew/edit.cpp b/pcbnew/edit.cpp index 92b267c856..98a3ec4fee 100644 --- a/pcbnew/edit.cpp +++ b/pcbnew/edit.cpp @@ -394,14 +394,23 @@ void PCB_EDIT_FRAME::Process_Special_Functions( wxCommandEvent& event ) } else { - int v_type = GetDesignSettings().m_CurrentViaType; - if( id == ID_POPUP_PCB_PLACE_BLIND_BURIED_VIA || - id == ID_POPUP_PCB_SELECT_CU_LAYER_AND_PLACE_BLIND_BURIED_VIA ) - GetDesignSettings().m_CurrentViaType = VIA_BLIND_BURIED; - else if( id == ID_POPUP_PCB_PLACE_MICROVIA ) - GetDesignSettings().m_CurrentViaType = VIA_MICROVIA; - else - GetDesignSettings().m_CurrentViaType = VIA_THROUGH; + BOARD_DESIGN_SETTINGS &settings = GetDesignSettings(); + VIATYPE_T v_type = settings.m_CurrentViaType; + switch( id ) + { + case ID_POPUP_PCB_PLACE_BLIND_BURIED_VIA: + case ID_POPUP_PCB_SELECT_CU_LAYER_AND_PLACE_BLIND_BURIED_VIA: + settings.m_CurrentViaType = VIA_BLIND_BURIED; + break; + + case ID_POPUP_PCB_PLACE_MICROVIA: + settings.m_CurrentViaType = VIA_MICROVIA; + break; + + default: + settings.m_CurrentViaType = VIA_THROUGH; + break; + } // place via and switch layer. if( id == ID_POPUP_PCB_SELECT_CU_LAYER_AND_PLACE_THROUGH_VIA || @@ -426,7 +435,7 @@ void PCB_EDIT_FRAME::Process_Special_Functions( wxCommandEvent& event ) else Other_Layer_Route( (TRACK*) GetCurItem(), &dc ); - GetDesignSettings().m_CurrentViaType = v_type; + settings.m_CurrentViaType = v_type; if( DisplayOpt.ContrastModeDisplay ) m_canvas->Refresh(); diff --git a/pcbnew/edit_track_width.cpp b/pcbnew/edit_track_width.cpp index 4c2d5e8327..c371ee0978 100644 --- a/pcbnew/edit_track_width.cpp +++ b/pcbnew/edit_track_width.cpp @@ -47,8 +47,10 @@ bool PCB_EDIT_FRAME::SetTrackSegmentWidth( TRACK* aTrackItem, if( aTrackItem->Type() == PCB_VIA_T ) { - if( !aTrackItem->IsDrillDefault() ) - initial_drill = aTrackItem->GetDrillValue(); + const VIA *via = static_cast( aTrackItem ); + + if( !via->IsDrillDefault() ) + initial_drill = via->GetDrillValue(); if( net ) { @@ -60,7 +62,7 @@ bool PCB_EDIT_FRAME::SetTrackSegmentWidth( TRACK* aTrackItem, new_drill = GetBoard()->GetCurrentViaDrill(); } - if( aTrackItem->GetShape() == VIA_MICROVIA ) + if( via->GetViaType() == VIA_MICROVIA ) { if( net ) new_width = net->GetMicroViaSize(); @@ -107,10 +109,11 @@ bool PCB_EDIT_FRAME::SetTrackSegmentWidth( TRACK* aTrackItem, if( aTrackItem->Type() == PCB_VIA_T ) { // Set new drill value. Note: currently microvias have only a default drill value + VIA *via = static_cast( aTrackItem ); if( new_drill > 0 ) - aTrackItem->SetDrill( new_drill ); + via->SetDrill( new_drill ); else - aTrackItem->SetDrillDefault(); + via->SetDrillDefault(); } } } diff --git a/pcbnew/editrack-part2.cpp b/pcbnew/editrack-part2.cpp index e394ad1ca3..bedbcac572 100644 --- a/pcbnew/editrack-part2.cpp +++ b/pcbnew/editrack-part2.cpp @@ -95,9 +95,9 @@ bool PCB_EDIT_FRAME::Other_Layer_Route( TRACK* aTrack, wxDC* DC ) m_canvas->CallMouseCapture( DC, wxDefaultPosition, false ); // create the via - SEGVIA* via = new SEGVIA( GetBoard() ); + VIA* via = new VIA( GetBoard() ); via->SetFlags( IS_NEW ); - via->SetShape( GetDesignSettings().m_CurrentViaType ); + via->SetViaType( GetDesignSettings().m_CurrentViaType ); via->SetWidth( GetBoard()->GetCurrentViaSize()); via->SetNetCode( GetBoard()->GetHighLightNetCode() ); via->SetEnd( g_CurrentTrackSegment->GetEnd() ); @@ -118,7 +118,7 @@ bool PCB_EDIT_FRAME::Other_Layer_Route( TRACK* aTrack, wxDC* DC ) last_layer = GetScreen()->m_Route_Layer_BOTTOM; // Adjust the actual via layer pair - switch ( via->GetShape() ) + switch ( via->GetViaType() ) { case VIA_BLIND_BURIED: via->SetLayerPair( first_layer, last_layer ); diff --git a/pcbnew/exporters/export_d356.cpp b/pcbnew/exporters/export_d356.cpp index 865986acc9..f75dfbdeba 100644 --- a/pcbnew/exporters/export_d356.cpp +++ b/pcbnew/exporters/export_d356.cpp @@ -198,23 +198,23 @@ static void build_via_testpoints( BOARD *aPcb, { if( track->Type() == PCB_VIA_T ) { - SEGVIA *via = (SEGVIA*) track; - NETINFO_ITEM *net = track->GetNet(); + VIA *via = (VIA*) track; + NETINFO_ITEM *net = track->GetNet(); D356_RECORD rk; - rk.smd = false; + rk.smd = false; rk.hole = true; - if( net ) - rk.netname = net->GetNetname(); - else - rk.netname = wxEmptyString; + if( net ) + rk.netname = net->GetNetname(); + else + rk.netname = wxEmptyString; rk.refdes = wxT("VIA"); rk.pin = wxT(""); rk.midpoint = true; // Vias are always midpoints rk.drill = via->GetDrillValue(); rk.mechanical = false; LAYER_NUM top_layer, bottom_layer; - via->LayerPair( &top_layer, &bottom_layer ); + via->LayerPair( &top_layer, &bottom_layer ); rk.access = via_access_code( aPcb, top_layer, bottom_layer ); rk.x_location = via->GetPosition().x - origin.x; rk.y_location = origin.y - via->GetPosition().y; diff --git a/pcbnew/exporters/export_gencad.cpp b/pcbnew/exporters/export_gencad.cpp index 8ef7e19214..601c91ae6d 100644 --- a/pcbnew/exporters/export_gencad.cpp +++ b/pcbnew/exporters/export_gencad.cpp @@ -222,8 +222,8 @@ static int PadListSortByShape( const void* aRefptr, const void* aObjptr ) // Sort vias for uniqueness static int ViaSort( const void* aRefptr, const void* aObjptr ) { - TRACK* padref = *(TRACK**) aRefptr; - TRACK* padcmp = *(TRACK**) aObjptr; + VIA* padref = *(VIA**) aRefptr; + VIA* padcmp = *(VIA**) aObjptr; if( padref->GetWidth() != padcmp->GetWidth() ) return padref->GetWidth() - padcmp->GetWidth(); @@ -253,8 +253,8 @@ static void CreatePadsShapesSection( FILE* aFile, BOARD* aPcb ) { std::vector pads; std::vector padstacks; - std::vector vias; - std::vector viastacks; + std::vector vias; + std::vector viastacks; padstacks.resize( 1 ); // We count pads from 1 // The master layermask (i.e. the enabled layers) for padstack generation @@ -275,17 +275,17 @@ static void CreatePadsShapesSection( FILE* aFile, BOARD* aPcb ) { if( track->Type() == PCB_VIA_T ) { - vias.push_back( track ); + vias.push_back( static_cast(track) ); } } - qsort( &vias[0], vias.size(), sizeof(TRACK*), ViaSort ); + qsort( &vias[0], vias.size(), sizeof(VIA*), ViaSort ); // Emit vias pads TRACK* old_via = 0; for( unsigned i = 0; i < vias.size(); i++ ) { - TRACK* via = vias[i]; + VIA* via = vias[i]; if( old_via && 0 == ViaSort( &old_via, &via ) ) continue; @@ -433,7 +433,7 @@ static void CreatePadsShapesSection( FILE* aFile, BOARD* aPcb ) // Via padstacks for( unsigned i = 0; i < viastacks.size(); i++ ) { - TRACK* via = viastacks[i]; + VIA* via = viastacks[i]; LAYER_MSK mask = via->GetLayerMask() & master_layermask; fprintf( aFile, "PADSTACK VIA%d.%d.%X %g\n", via->GetWidth(), via->GetDrillValue(), mask, @@ -832,11 +832,12 @@ static void CreateRoutesSection( FILE* aFile, BOARD* aPcb ) } if( track->Type() == PCB_VIA_T ) { + const VIA *via = static_cast(track); fprintf( aFile, "VIA VIA%d.%d.%X %g %g ALL %g via%d\n", - track->GetWidth(), track->GetDrillValue(), - track->GetLayerMask() & master_layermask, - MapXTo( track->GetStart().x ), MapYTo( track->GetStart().y ), - track->GetDrillValue() / SCALE_FACTOR, vianum++ ); + via->GetWidth(), via->GetDrillValue(), + via->GetLayerMask() & master_layermask, + MapXTo( via->GetStart().x ), MapYTo( via->GetStart().y ), + via->GetDrillValue() / SCALE_FACTOR, vianum++ ); } } diff --git a/pcbnew/exporters/export_vrml.cpp b/pcbnew/exporters/export_vrml.cpp index 5962ba276b..2522e813e2 100644 --- a/pcbnew/exporters/export_vrml.cpp +++ b/pcbnew/exporters/export_vrml.cpp @@ -801,7 +801,7 @@ static void export_round_padstack( MODEL_VRML& aModel, BOARD* pcb, } -static void export_vrml_via( MODEL_VRML& aModel, BOARD* pcb, SEGVIA* via ) +static void export_vrml_via( MODEL_VRML& aModel, BOARD* pcb, const VIA* via ) { double x, y, r, hole; LAYER_NUM top_layer, bottom_layer; @@ -827,7 +827,7 @@ static void export_vrml_tracks( MODEL_VRML& aModel, BOARD* pcb ) { if( track->Type() == PCB_VIA_T ) { - export_vrml_via( aModel, pcb, (SEGVIA*) track ); + export_vrml_via( aModel, pcb, (const VIA*) track ); } else if( track->GetLayer() == FIRST_COPPER_LAYER || track->GetLayer() == LAST_COPPER_LAYER ) diff --git a/pcbnew/exporters/gendrill_Excellon_writer.cpp b/pcbnew/exporters/gendrill_Excellon_writer.cpp index 8a3413db1f..a8a086187a 100644 --- a/pcbnew/exporters/gendrill_Excellon_writer.cpp +++ b/pcbnew/exporters/gendrill_Excellon_writer.cpp @@ -458,7 +458,7 @@ void EXCELLON_WRITER::BuildHolesList( int aFirstLayer, if( track->Type() != PCB_VIA_T ) continue; - SEGVIA* via = (SEGVIA*) track; + const VIA* via = (const VIA*) track; hole_value = via->GetDrillValue(); if( hole_value == 0 ) diff --git a/pcbnew/kicad_plugin.cpp b/pcbnew/kicad_plugin.cpp index a675d8fcfd..fd7059399a 100644 --- a/pcbnew/kicad_plugin.cpp +++ b/pcbnew/kicad_plugin.cpp @@ -1342,7 +1342,7 @@ void PCB_IO::format( TRACK* aTrack, int aNestLevel ) const { LAYER_NUM layer1, layer2; - SEGVIA* via = (SEGVIA*) aTrack; + const VIA* via = static_cast(aTrack); BOARD* board = (BOARD*) via->GetParent(); wxCHECK_RET( board != 0, wxT( "Via " ) + via->GetSelectMenuText() + @@ -1352,7 +1352,7 @@ void PCB_IO::format( TRACK* aTrack, int aNestLevel ) const via->LayerPair( &layer1, &layer2 ); - switch( aTrack->GetShape() ) + switch( via->GetViaType() ) { case VIA_THROUGH: // Default shape not saved. break; @@ -1366,15 +1366,15 @@ void PCB_IO::format( TRACK* aTrack, int aNestLevel ) const break; default: - THROW_IO_ERROR( wxString::Format( _( "unknown via type %d" ), aTrack->GetShape() ) ); + THROW_IO_ERROR( wxString::Format( _( "unknown via type %d" ), via->GetViaType() ) ); } m_out->Print( 0, " (at %s) (size %s)", FMT_IU( aTrack->GetStart() ).c_str(), FMT_IU( aTrack->GetWidth() ).c_str() ); - if( aTrack->GetDrill() != UNDEFINED_DRILL_DIAMETER ) - m_out->Print( 0, " (drill %s)", FMT_IU( aTrack->GetDrill() ).c_str() ); + if( via->GetDrill() != UNDEFINED_DRILL_DIAMETER ) + m_out->Print( 0, " (drill %s)", FMT_IU( via->GetDrill() ).c_str() ); m_out->Print( 0, " (layers %s %s)", m_out->Quotew( m_board->GetLayerName( layer1 ) ).c_str(), diff --git a/pcbnew/legacy_plugin.cpp b/pcbnew/legacy_plugin.cpp index f548c2b997..12e500b023 100644 --- a/pcbnew/legacy_plugin.cpp +++ b/pcbnew/legacy_plugin.cpp @@ -1998,7 +1998,7 @@ void LEGACY_PLUGIN::loadTrackList( int aStructType ) assert( TESTLINE( "Po" ) ); - int shape = intParse( line + SZ( "Po" ), &data ); + VIATYPE_T viatype = static_cast( intParse( line + SZ( "Po" ), &data )); BIU start_x = biuParse( data, &data ); BIU start_y = biuParse( data, &data ); BIU end_x = biuParse( data, &data ); @@ -2059,7 +2059,7 @@ void LEGACY_PLUGIN::loadTrackList( int aStructType ) break; case PCB_VIA_T: - newTrack = new SEGVIA( m_board ); + newTrack = new VIA( m_board ); m_board->m_Track.Append( newTrack ); break; @@ -2075,19 +2075,20 @@ void LEGACY_PLUGIN::loadTrackList( int aStructType ) newTrack->SetEnd( wxPoint( end_x, end_y ) ); newTrack->SetWidth( width ); - newTrack->SetShape( shape ); - - if( drill < 0 ) - newTrack->SetDrillDefault(); - else - newTrack->SetDrill( drill ); - newTrack->SetLayer( layer ); if( makeType == PCB_VIA_T ) // Ensure layers are OK when possible: { - if( newTrack->GetShape() == VIA_THROUGH ) - ( (SEGVIA*) newTrack )->SetLayerPair( LAYER_N_FRONT, LAYER_N_BACK ); + VIA *via = static_cast( newTrack ); + via->SetViaType( viatype ); + + if( drill < 0 ) + via->SetDrillDefault(); + else + via->SetDrill( drill ); + + if( via->GetViaType() == VIA_THROUGH ) + via->SetLayerPair( LAYER_N_FRONT, LAYER_N_BACK ); } newTrack->SetNetCode( net_code ); @@ -3620,17 +3621,24 @@ void LEGACY_PLUGIN::savePCB_LINE( const DRAWSEGMENT* me ) const void LEGACY_PLUGIN::saveTRACK( const TRACK* me ) const { int type = 0; + VIATYPE_T viatype = VIA_NOT_DEFINED; + int drill = UNDEFINED_DRILL_DIAMETER; if( me->Type() == PCB_VIA_T ) + { + const VIA *via = static_cast(me); type = 1; + viatype = via->GetViaType(); + drill = via->GetDrill(); + } fprintf(m_fp, "Po %d %s %s %s %s\n", - me->GetShape(), + viatype, fmtBIUPoint( me->GetStart() ).c_str(), fmtBIUPoint( me->GetEnd() ).c_str(), fmtBIU( me->GetWidth() ).c_str(), - me->GetDrill() == UNDEFINED_DRILL_DIAMETER ? - "-1" : fmtBIU( me->GetDrill() ).c_str() ); + drill == UNDEFINED_DRILL_DIAMETER ? + "-1" : fmtBIU( drill ).c_str() ); fprintf(m_fp, "De %d %d %d %lX %X\n", me->GetLayer(), type, me->GetNetCode(), diff --git a/pcbnew/magnetic_tracks_functions.cpp b/pcbnew/magnetic_tracks_functions.cpp index 5c84d0d6d8..1c901cf760 100644 --- a/pcbnew/magnetic_tracks_functions.cpp +++ b/pcbnew/magnetic_tracks_functions.cpp @@ -193,7 +193,7 @@ bool Magnetize( PCB_EDIT_FRAME* frame, int aCurrentTool, wxSize aGridSize, { LAYER_MSK layer_mask = GetLayerMask( layer ); - TRACK* track = m_Pcb->GetTrace( m_Pcb->m_Track, pos, layer_mask ); + TRACK* track = m_Pcb->GetTrack( m_Pcb->m_Track, pos, layer_mask ); if( !track || track->Type() != PCB_TRACE_T ) { diff --git a/pcbnew/move_or_drag_track.cpp b/pcbnew/move_or_drag_track.cpp index 6525d7abd7..7d108eea4b 100644 --- a/pcbnew/move_or_drag_track.cpp +++ b/pcbnew/move_or_drag_track.cpp @@ -709,7 +709,7 @@ void PCB_EDIT_FRAME::Start_DragTrackSegmentAndKeepSlope( TRACK* track, wxDC* DC s_StartSegmentPresent = s_EndSegmentPresent = true; if( ( track->start == NULL ) || ( track->start->Type() == PCB_TRACE_T ) ) - TrackToStartPoint = track->GetTrace( GetBoard()->m_Track, NULL, FLG_START ); + TrackToStartPoint = track->GetTrack( GetBoard()->m_Track, NULL, FLG_START ); // Test if more than one segment is connected to this point if( TrackToStartPoint ) @@ -717,14 +717,14 @@ void PCB_EDIT_FRAME::Start_DragTrackSegmentAndKeepSlope( TRACK* track, wxDC* DC TrackToStartPoint->SetState( BUSY, true ); if( ( TrackToStartPoint->Type() == PCB_VIA_T ) - || track->GetTrace( GetBoard()->m_Track, NULL, FLG_START ) ) + || track->GetTrack( GetBoard()->m_Track, NULL, FLG_START ) ) error = true; TrackToStartPoint->SetState( BUSY, false ); } if( ( track->end == NULL ) || ( track->end->Type() == PCB_TRACE_T ) ) - TrackToEndPoint = track->GetTrace( GetBoard()->m_Track, NULL, FLG_END ); + TrackToEndPoint = track->GetTrack( GetBoard()->m_Track, NULL, FLG_END ); // Test if more than one segment is connected to this point if( TrackToEndPoint ) @@ -732,7 +732,7 @@ void PCB_EDIT_FRAME::Start_DragTrackSegmentAndKeepSlope( TRACK* track, wxDC* DC TrackToEndPoint->SetState( BUSY, true ); if( (TrackToEndPoint->Type() == PCB_VIA_T) - || track->GetTrace( GetBoard()->m_Track, NULL, FLG_END ) ) + || track->GetTrack( GetBoard()->m_Track, NULL, FLG_END ) ) error = true; TrackToEndPoint->SetState( BUSY, false ); diff --git a/pcbnew/pcad2kicadpcb_plugin/pcb_pad.cpp b/pcbnew/pcad2kicadpcb_plugin/pcb_pad.cpp index 4985958fc9..c1e7c416b2 100644 --- a/pcbnew/pcad2kicadpcb_plugin/pcb_pad.cpp +++ b/pcbnew/pcad2kicadpcb_plugin/pcb_pad.cpp @@ -329,7 +329,7 @@ void PCB_PAD::AddToBoard() if( IsCopperLayer( m_KiCadLayer ) ) { - SEGVIA* via = new SEGVIA( m_board ); + VIA* via = new VIA( m_board ); m_board->m_Track.Append( via ); via->SetTimeStamp( 0 ); @@ -338,8 +338,8 @@ void PCB_PAD::AddToBoard() via->SetEnd( wxPoint( m_positionX, m_positionY ) ); via->SetWidth( height ); - via->SetShape( VIA_THROUGH ); - ( (SEGVIA*) via )->SetLayerPair( LAYER_N_FRONT, LAYER_N_BACK ); + via->SetViaType( VIA_THROUGH ); + via->SetLayerPair( LAYER_N_FRONT, LAYER_N_BACK ); via->SetDrill( m_hole ); via->SetLayer( m_KiCadLayer ); diff --git a/pcbnew/pcb_painter.cpp b/pcbnew/pcb_painter.cpp index ff5d085939..c2d98603ed 100644 --- a/pcbnew/pcb_painter.cpp +++ b/pcbnew/pcb_painter.cpp @@ -210,15 +210,15 @@ bool PCB_PAINTER::Draw( const VIEW_ITEM* aItem, int aLayer ) { case PCB_ZONE_T: case PCB_TRACE_T: - draw( (TRACK*) aItem, aLayer ); + draw( (const TRACK*) aItem, aLayer ); break; case PCB_VIA_T: - draw( (SEGVIA*) aItem, aLayer ); + draw( (const VIA*) aItem, aLayer ); break; case PCB_PAD_T: - draw( (D_PAD*) aItem, aLayer ); + draw( (const D_PAD*) aItem, aLayer ); break; case PCB_LINE_T: @@ -329,7 +329,7 @@ void PCB_PAINTER::draw( const TRACK* aTrack, int aLayer ) } -void PCB_PAINTER::draw( const SEGVIA* aVia, int aLayer ) +void PCB_PAINTER::draw( const VIA* aVia, int aLayer ) { VECTOR2D center( aVia->GetStart() ); double radius; diff --git a/pcbnew/pcb_painter.h b/pcbnew/pcb_painter.h index cf9f242b8c..85b1192936 100644 --- a/pcbnew/pcb_painter.h +++ b/pcbnew/pcb_painter.h @@ -37,7 +37,7 @@ class DISPLAY_OPTIONS; class BOARD_ITEM; class BOARD; -class SEGVIA; +class VIA; class TRACK; class D_PAD; class DRAWSEGMENT; @@ -161,7 +161,7 @@ protected: // Drawing functions for various types of PCB-specific items void draw( const TRACK* aTrack, int aLayer ); - void draw( const SEGVIA* aVia, int aLayer ); + void draw( const VIA* aVia, int aLayer ); void draw( const D_PAD* aPad, int aLayer ); void draw( const DRAWSEGMENT* aSegment ); void draw( const TEXTE_PCB* aText, int aLayer ); diff --git a/pcbnew/pcb_parser.cpp b/pcbnew/pcb_parser.cpp index 11b4035090..97e073d1d5 100644 --- a/pcbnew/pcb_parser.cpp +++ b/pcbnew/pcb_parser.cpp @@ -432,7 +432,7 @@ BOARD* PCB_PARSER::parseBOARD() throw( IO_ERROR, PARSE_ERROR ) break; case T_via: - m_board->Add( parseSEGVIA(), ADD_APPEND ); + m_board->Add( parseVIA(), ADD_APPEND ); break; case T_zone: @@ -2310,15 +2310,15 @@ TRACK* PCB_PARSER::parseTRACK() throw( IO_ERROR, PARSE_ERROR ) } -SEGVIA* PCB_PARSER::parseSEGVIA() throw( IO_ERROR, PARSE_ERROR ) +VIA* PCB_PARSER::parseVIA() throw( IO_ERROR, PARSE_ERROR ) { wxCHECK_MSG( CurTok() == T_via, NULL, - wxT( "Cannot parse " ) + GetTokenString( CurTok() ) + wxT( " as SEGVIA." ) ); + wxT( "Cannot parse " ) + GetTokenString( CurTok() ) + wxT( " as VIA." ) ); wxPoint pt; T token; - std::auto_ptr< SEGVIA > via( new SEGVIA( m_board ) ); + std::auto_ptr< VIA > via( new VIA( m_board ) ); for( token = NextTok(); token != T_RIGHT; token = NextTok() ) { @@ -2328,11 +2328,11 @@ SEGVIA* PCB_PARSER::parseSEGVIA() throw( IO_ERROR, PARSE_ERROR ) switch( token ) { case T_blind: - via->SetShape( VIA_BLIND_BURIED ); + via->SetViaType( VIA_BLIND_BURIED ); break; case T_micro: - via->SetShape( VIA_MICROVIA ); + via->SetViaType( VIA_MICROVIA ); break; case T_at: diff --git a/pcbnew/pcb_parser.h b/pcbnew/pcb_parser.h index 0dfb0bbdc5..eeb4faf9d6 100644 --- a/pcbnew/pcb_parser.h +++ b/pcbnew/pcb_parser.h @@ -49,7 +49,7 @@ class TEXTE_PCB; class TRACK; class MODULE; class PCB_TARGET; -class SEGVIA; +class VIA; class S3D_MASTER; class ZONE_CONTAINER; @@ -101,7 +101,7 @@ class PCB_PARSER : public PCB_LEXER EDGE_MODULE* parseEDGE_MODULE() throw( IO_ERROR, PARSE_ERROR ); D_PAD* parseD_PAD( MODULE* aParent = NULL ) throw( IO_ERROR, PARSE_ERROR ); TRACK* parseTRACK() throw( IO_ERROR, PARSE_ERROR ); - SEGVIA* parseSEGVIA() throw( IO_ERROR, PARSE_ERROR ); + VIA* parseVIA() throw( IO_ERROR, PARSE_ERROR ); ZONE_CONTAINER* parseZONE_CONTAINER() throw( IO_ERROR, PARSE_ERROR ); PCB_TARGET* parsePCB_TARGET() throw( IO_ERROR, PARSE_ERROR ); BOARD* parseBOARD() throw( IO_ERROR, PARSE_ERROR ); diff --git a/pcbnew/plot_board_layers.cpp b/pcbnew/plot_board_layers.cpp index 34d708195b..f299787716 100644 --- a/pcbnew/plot_board_layers.cpp +++ b/pcbnew/plot_board_layers.cpp @@ -357,10 +357,10 @@ void PlotStandardLayer( BOARD *aBoard, PLOTTER* aPlotter, // plot them on solder mask for( TRACK* track = aBoard->m_Track; track; track = track->Next() ) { - if( track->Type() != PCB_VIA_T ) - continue; + const VIA* Via = dynamic_cast( track ); - SEGVIA* Via = (SEGVIA*) track; + if( !Via ) + continue; // vias are not plotted if not on selected layer, but if layer // is SOLDERMASK_LAYER_BACK or SOLDERMASK_LAYER_FRONT,vias are drawn, @@ -396,7 +396,7 @@ void PlotStandardLayer( BOARD *aBoard, PLOTTER* aPlotter, if( diameter <= 0 ) continue; - EDA_COLOR_T color = aBoard->GetVisibleElementColor(VIAS_VISIBLE + Via->GetShape()); + EDA_COLOR_T color = aBoard->GetVisibleElementColor(VIAS_VISIBLE + Via->GetViaType()); // Set plot color (change WHITE to LIGHTGRAY because // the white items are not seen on a white paper or screen aPlotter->SetColor( color != WHITE ? color : LIGHTGRAY); @@ -534,10 +534,10 @@ void PlotSolderMaskLayer( BOARD *aBoard, PLOTTER* aPlotter, int via_margin = via_clearance + inflate; for( TRACK* track = aBoard->m_Track; track; track = track->Next() ) { - if( track->Type() != PCB_VIA_T ) - continue; + const VIA* via = dynamic_cast( track ); - SEGVIA* via = (SEGVIA*) track; + if( !via ) + continue; // vias are plotted only if they are on the corresponding // external copper layer @@ -553,11 +553,11 @@ void PlotSolderMaskLayer( BOARD *aBoard, PLOTTER* aPlotter, continue; via->TransformShapeWithClearanceToPolygon( bufferPolys, via_margin, - circleToSegmentsCount, - correction ); + circleToSegmentsCount, + correction ); via->TransformShapeWithClearanceToPolygon( initialPolys, via_clearance, - circleToSegmentsCount, - correction ); + circleToSegmentsCount, + correction ); } } diff --git a/pcbnew/plot_brditems_plotter.cpp b/pcbnew/plot_brditems_plotter.cpp index aa4dfc3860..1535b3593f 100644 --- a/pcbnew/plot_brditems_plotter.cpp +++ b/pcbnew/plot_brditems_plotter.cpp @@ -685,11 +685,12 @@ void BRDITEMS_PLOTTER::PlotDrillMarks() for( TRACK *pts = m_board->m_Track; pts != NULL; pts = pts->Next() ) { - if( pts->Type() != PCB_VIA_T ) - continue; + const VIA *via = dynamic_cast( pts ); - plotOneDrillMark( PAD_DRILL_CIRCLE, pts->GetStart(), wxSize( pts->GetDrillValue(), 0 ), - wxSize( pts->GetWidth(), 0 ), 0, small_drill ); + if( via ) + plotOneDrillMark( PAD_DRILL_CIRCLE, via->GetStart(), + wxSize( via->GetDrillValue(), 0 ), + wxSize( via->GetWidth(), 0 ), 0, small_drill ); } for( MODULE *Module = m_board->m_Modules; Module != NULL; Module = Module->Next() ) diff --git a/pcbnew/print_board_functions.cpp b/pcbnew/print_board_functions.cpp index f663521417..2683e268b5 100644 --- a/pcbnew/print_board_functions.cpp +++ b/pcbnew/print_board_functions.cpp @@ -249,12 +249,14 @@ void PCB_EDIT_FRAME::PrintPage( wxDC* aDC, if( track->Type() == PCB_VIA_T ) // VIA encountered. { - int radius = track->GetWidth() >> 1; - EDA_COLOR_T color = g_ColorsSettings.GetItemColor( VIAS_VISIBLE + track->GetShape() ); + int radius = track->GetWidth() / 2; + const VIA *via = static_cast( track ); + + EDA_COLOR_T color = g_ColorsSettings.GetItemColor( VIAS_VISIBLE + via->GetViaType() ); GRSetDrawMode( aDC, drawmode ); GRFilledCircle( m_canvas->GetClipBox(), aDC, - track->GetStart().x, - track->GetStart().y, + via->GetStart().x, + via->GetStart().y, radius, 0, color, color ); } @@ -313,11 +315,12 @@ void PCB_EDIT_FRAME::PrintPage( wxDC* aDC, if( track->Type() == PCB_VIA_T ) // VIA encountered. { int diameter; + const VIA *via = static_cast( track ); if( drillShapeOpt == PRINT_PARAMETERS::SMALL_DRILL_SHAPE ) - diameter = std::min( SMALL_DRILL, track->GetDrillValue() ); + diameter = std::min( SMALL_DRILL, via->GetDrillValue() ); else - diameter = track->GetDrillValue(); + diameter = via->GetDrillValue(); GRFilledCircle( m_canvas->GetClipBox(), aDC, track->GetStart().x, track->GetStart().y, diff --git a/pcbnew/ratsnest_data.cpp b/pcbnew/ratsnest_data.cpp index 97f04e29b0..26a0d34bf2 100644 --- a/pcbnew/ratsnest_data.cpp +++ b/pcbnew/ratsnest_data.cpp @@ -393,7 +393,7 @@ void RN_NET::AddItem( const D_PAD* aPad ) } -void RN_NET::AddItem( const SEGVIA* aVia ) +void RN_NET::AddItem( const VIA* aVia ) { m_vias[aVia] = m_links.AddNode( aVia->GetPosition().x, aVia->GetPosition().y ); @@ -482,7 +482,7 @@ void RN_NET::RemoveItem( const D_PAD* aPad ) } -void RN_NET::RemoveItem( const SEGVIA* aVia ) +void RN_NET::RemoveItem( const VIA* aVia ) { try { @@ -686,7 +686,7 @@ std::list RN_NET::GetNodes( const BOARD_CONNECTED_ITEM* aItem ) con case PCB_VIA_T: { - const SEGVIA* via = static_cast( aItem ); + const VIA* via = static_cast( aItem ); nodes.push_back( m_vias.at( via ) ); } break; @@ -877,7 +877,7 @@ void RN_DATA::Add( const BOARD_ITEM* aItem ) break; case PCB_VIA_T: - m_nets[net].AddItem( static_cast( aItem ) ); + m_nets[net].AddItem( static_cast( aItem ) ); break; case PCB_ZONE_AREA_T: @@ -928,7 +928,7 @@ void RN_DATA::Remove( const BOARD_ITEM* aItem ) break; case PCB_VIA_T: - m_nets[net].RemoveItem( static_cast( aItem ) ); + m_nets[net].RemoveItem( static_cast( aItem ) ); break; case PCB_ZONE_AREA_T: @@ -973,7 +973,7 @@ void RN_DATA::ProcessBoard() if( netCode > 0 ) { if( track->Type() == PCB_VIA_T ) - m_nets[netCode].AddItem( static_cast( track ) ); + m_nets[netCode].AddItem( static_cast( track ) ); else if( track->Type() == PCB_TRACE_T ) m_nets[netCode].AddItem( track ); } diff --git a/pcbnew/ratsnest_data.h b/pcbnew/ratsnest_data.h index 712909f2fa..59f3f0e356 100644 --- a/pcbnew/ratsnest_data.h +++ b/pcbnew/ratsnest_data.h @@ -44,7 +44,7 @@ class BOARD_ITEM; class BOARD_CONNECTED_ITEM; class MODULE; class D_PAD; -class SEGVIA; +class VIA; class TRACK; class ZONE_CONTAINER; class CPolyPt; @@ -332,7 +332,7 @@ public: * taken into account during ratsnest computations. * @param aVia is a via for which node is added. */ - void AddItem( const SEGVIA* aVia ); + void AddItem( const VIA* aVia ); /** * Function AddItem() @@ -364,7 +364,7 @@ public: * taken into account during ratsnest computations anymore. * @param aVia is a via for which nodes and edges are removed. */ - void RemoveItem( const SEGVIA* aVia ); + void RemoveItem( const VIA* aVia ); /** * Function RemoveItem() @@ -522,7 +522,7 @@ protected: boost::unordered_map m_pads; ///> Map that associates nodes in the ratsnest model to respective vias. - boost::unordered_map m_vias; + boost::unordered_map m_vias; ///> Map that associates edges in the ratsnest model to respective tracks. boost::unordered_map m_tracks; diff --git a/pcbnew/router/pns_router.cpp b/pcbnew/router/pns_router.cpp index e3cf287596..5f63911751 100644 --- a/pcbnew/router/pns_router.cpp +++ b/pcbnew/router/pns_router.cpp @@ -189,7 +189,7 @@ PNS_ITEM* PNS_ROUTER::syncTrack( TRACK* aTrack ) } -PNS_ITEM* PNS_ROUTER::syncVia( SEGVIA* aVia ) +PNS_ITEM* PNS_ROUTER::syncVia( VIA* aVia ) { PNS_VIA* v = new PNS_VIA( aVia->GetPosition(), @@ -268,7 +268,7 @@ void PNS_ROUTER::SyncWorld() if( type == PCB_TRACE_T ) item = syncTrack( t ); else if( type == PCB_VIA_T ) - item = syncVia( static_cast( t ) ); + item = syncVia( static_cast( t ) ); if( item ) m_world->Add( item ); @@ -618,7 +618,7 @@ void PNS_ROUTER::commitRouting( PNS_NODE* aNode ) case PNS_ITEM::VIA: { - SEGVIA* via_board = new SEGVIA( m_board ); + VIA* via_board = new VIA( m_board ); PNS_VIA* via = static_cast( item ); via_board->SetPosition( wxPoint( via->GetPos().x, via->GetPos().y ) ); via_board->SetWidth( via->GetDiameter() ); diff --git a/pcbnew/router/pns_router.h b/pcbnew/router/pns_router.h index 430f950a37..e5fabbeec2 100644 --- a/pcbnew/router/pns_router.h +++ b/pcbnew/router/pns_router.h @@ -37,7 +37,7 @@ class BOARD; class BOARD_ITEM; class D_PAD; class TRACK; -class SEGVIA; +class VIA; class PNS_NODE; class PNS_LINE_PLACER; class PNS_ITEM; @@ -169,7 +169,7 @@ private: PNS_ITEM* syncPad( D_PAD* aPad ); PNS_ITEM* syncTrack( TRACK* aTrack ); - PNS_ITEM* syncVia( SEGVIA* aVia ); + PNS_ITEM* syncVia( VIA* aVia ); void commitPad( PNS_SOLID* aPad ); void commitSegment( PNS_SEGMENT* aTrack ); diff --git a/pcbnew/specctra.h b/pcbnew/specctra.h index 35572563fa..d2a5104d95 100644 --- a/pcbnew/specctra.h +++ b/pcbnew/specctra.h @@ -40,7 +40,7 @@ class TYPE_COLLECTOR; // outside the DSN namespace class BOARD; class TRACK; -class SEGVIA; +class VIA; class NETCLASS; class MODULE; @@ -3790,12 +3790,12 @@ class SPECCTRA_DB : public SPECCTRA_LEXER /** * Function makeVia - * makes any kind of PADSTACK using the given KiCad SEGVIA. - * @param aVia The SEGVIA to build the padstack from. + * makes any kind of PADSTACK using the given KiCad VIA. + * @param aVia The VIA to build the padstack from. * @return PADSTACK* - The padstack, which is on the heap only, user must save * or delete it. */ - PADSTACK* makeVia( const SEGVIA* aVia ); + PADSTACK* makeVia( const ::VIA* aVia ); /** * Function deleteNETs @@ -3827,10 +3827,10 @@ class SPECCTRA_DB : public SPECCTRA_LEXER /** * Function makeVIA - * instantiates a KiCad SEGVIA on the heap and initializes it with internal + * instantiates a KiCad VIA on the heap and initializes it with internal * values consistent with the given PADSTACK, POINT, and netcode. */ - SEGVIA* makeVIA( PADSTACK* aPadstack, const POINT& aPoint, int aNetCode ) throw( IO_ERROR ); + ::VIA* makeVIA( PADSTACK* aPadstack, const POINT& aPoint, int aNetCode ) throw( IO_ERROR ); //--------------------------------------------------------- diff --git a/pcbnew/specctra_export.cpp b/pcbnew/specctra_export.cpp index 40aa2eeb97..ef452ce66d 100644 --- a/pcbnew/specctra_export.cpp +++ b/pcbnew/specctra_export.cpp @@ -834,7 +834,7 @@ PADSTACK* SPECCTRA_DB::makeVia( int aCopperDiameter, int aDrillDiameter, } -PADSTACK* SPECCTRA_DB::makeVia( const SEGVIA* aVia ) +PADSTACK* SPECCTRA_DB::makeVia( const ::VIA* aVia ) { LAYER_NUM topLayerNum; LAYER_NUM botLayerNum; @@ -1985,7 +1985,7 @@ void SPECCTRA_DB::FromBOARD( BOARD* aBoard ) throw( IO_ERROR ) for( int i = 0; iType() == PCB_VIA_T ); int netcode = via->GetNetCode(); diff --git a/pcbnew/specctra_import.cpp b/pcbnew/specctra_import.cpp index 417d433bb3..dbe998375c 100644 --- a/pcbnew/specctra_import.cpp +++ b/pcbnew/specctra_import.cpp @@ -214,9 +214,9 @@ TRACK* SPECCTRA_DB::makeTRACK( PATH* aPath, int aPointIndex, int aNetcode ) thro } -SEGVIA* SPECCTRA_DB::makeVIA( PADSTACK* aPadstack, const POINT& aPoint, int aNetCode ) throw( IO_ERROR ) +::VIA* SPECCTRA_DB::makeVIA( PADSTACK* aPadstack, const POINT& aPoint, int aNetCode ) throw( IO_ERROR ) { - SEGVIA* via = 0; + ::VIA* via = 0; SHAPE* shape; int shapeCount = aPadstack->Length(); @@ -261,10 +261,10 @@ SEGVIA* SPECCTRA_DB::makeVIA( PADSTACK* aPadstack, const POINT& aPoint, int aNet CIRCLE* circle = (CIRCLE*) shape->shape; int viaDiam = scale( circle->diameter, routeResolution ); - via = new SEGVIA( sessionBoard ); + via = new ::VIA( sessionBoard ); via->SetPosition( mapPt( aPoint, routeResolution ) ); via->SetDrill( drillDiam ); - via->SetShape( VIA_THROUGH ); + via->SetViaType( VIA_THROUGH ); via->SetWidth( viaDiam ); via->SetLayerPair( LAYER_N_FRONT, LAYER_N_BACK ); } @@ -279,10 +279,10 @@ SEGVIA* SPECCTRA_DB::makeVIA( PADSTACK* aPadstack, const POINT& aPoint, int aNet CIRCLE* circle = (CIRCLE*) shape->shape; int viaDiam = scale( circle->diameter, routeResolution ); - via = new SEGVIA( sessionBoard ); + via = new ::VIA( sessionBoard ); via->SetPosition( mapPt( aPoint, routeResolution ) ); via->SetDrill( drillDiam ); - via->SetShape( VIA_THROUGH ); + via->SetViaType( VIA_THROUGH ); via->SetWidth( viaDiam ); via->SetLayerPair( LAYER_N_FRONT, LAYER_N_BACK ); } @@ -321,15 +321,15 @@ SEGVIA* SPECCTRA_DB::makeVIA( PADSTACK* aPadstack, const POINT& aPoint, int aNet viaDiam = scale( circle->diameter, routeResolution ); } - via = new SEGVIA( sessionBoard ); + via = new ::VIA( sessionBoard ); via->SetPosition( mapPt( aPoint, routeResolution ) ); via->SetDrill( drillDiam ); if( (topLayerNdx==0 && botLayerNdx==1) || (topLayerNdx==copperLayerCount-2 && botLayerNdx==copperLayerCount-1)) - via->SetShape( VIA_MICROVIA ); + via->SetViaType( VIA_MICROVIA ); else - via->SetShape( VIA_BLIND_BURIED ); + via->SetViaType( VIA_BLIND_BURIED ); via->SetWidth( viaDiam ); @@ -546,7 +546,7 @@ void SPECCTRA_DB::FromSESSION( BOARD* aBoard ) throw( IO_ERROR ) for( unsigned v=0; vvertexes.size(); ++v ) { - SEGVIA* via = makeVIA( padstack, wire_via->vertexes[v], netCode ); + ::VIA* via = makeVIA( padstack, wire_via->vertexes[v], netCode ); aBoard->Add( via ); } } diff --git a/pcbnew/swap_layers.cpp b/pcbnew/swap_layers.cpp index 11180b107b..e3bf92bc59 100644 --- a/pcbnew/swap_layers.cpp +++ b/pcbnew/swap_layers.cpp @@ -360,9 +360,9 @@ void PCB_EDIT_FRAME::Swap_Layers( wxCommandEvent& event ) if( pt_segm->Type() == PCB_VIA_T ) { - SEGVIA* Via = (SEGVIA*) pt_segm; + VIA* Via = (VIA*) pt_segm; - if( Via->GetShape() == VIA_THROUGH ) + if( Via->GetViaType() == VIA_THROUGH ) continue; LAYER_NUM top_layer, bottom_layer; diff --git a/pcbnew/tools/selection_tool.cpp b/pcbnew/tools/selection_tool.cpp index fd567a16d1..d5d85b5431 100644 --- a/pcbnew/tools/selection_tool.cpp +++ b/pcbnew/tools/selection_tool.cpp @@ -459,7 +459,7 @@ bool SELECTION_TOOL::selectable( const BOARD_ITEM* aItem ) const { // For vias it is enough if only one of layers is visible LAYER_NUM top, bottom; - static_cast( aItem )->LayerPair( &top, &bottom ); + static_cast( aItem )->LayerPair( &top, &bottom ); return board->IsLayerVisible( top ) || board->IsLayerVisible( bottom ); } diff --git a/pcbnew/tr_modif.cpp b/pcbnew/tr_modif.cpp index 59c0f042fb..2e929fc9a1 100644 --- a/pcbnew/tr_modif.cpp +++ b/pcbnew/tr_modif.cpp @@ -168,7 +168,7 @@ int PCB_EDIT_FRAME::EraseRedundantTrack( wxDC* aDC, /* A segment must be connected to the starting point, otherwise * it is unnecessary to analyze the other point */ - pt_segm = GetTrace( bufStart, bufEnd, start, startmasklayer ); + pt_segm = GetTrack( bufStart, bufEnd, start, startmasklayer ); if( pt_segm == NULL ) // Not connected to the track starting point. { @@ -183,7 +183,7 @@ int PCB_EDIT_FRAME::EraseRedundantTrack( wxDC* aDC, */ for( pt_del = bufStart, nbconnect = 0; ; ) { - pt_segm = GetTrace( pt_del, bufEnd, end, endmasklayer ); + pt_segm = GetTrack( pt_del, bufEnd, end, endmasklayer ); if( pt_segm == NULL ) break; diff --git a/pcbnew/zones_polygons_test_connections.cpp b/pcbnew/zones_polygons_test_connections.cpp index ce9c948c46..b1d69d0455 100644 --- a/pcbnew/zones_polygons_test_connections.cpp +++ b/pcbnew/zones_polygons_test_connections.cpp @@ -175,12 +175,15 @@ void BOARD::Test_Connections_To_Copper_Areas( int aNetcode ) } else if( item->Type() == PCB_VIA_T ) { - pos1 = pos2 = ( (SEGVIA*) item )->GetStart(); + const VIA *via = static_cast( item ); + pos1 = via->GetStart(); + pos2 = pos1; } else if( item->Type() == PCB_TRACE_T ) { - pos1 = ( (TRACK*) item )->GetStart(); - pos2 = ( (TRACK*) item )->GetEnd(); + const TRACK *trk = static_cast( item ); + pos1 = trk->GetStart(); + pos2 = trk->GetEnd(); } else {