diff --git a/translation/pofiles/zh_CN.po b/translation/pofiles/zh_CN.po index c3db391ca7..d1bce6b60e 100644 --- a/translation/pofiles/zh_CN.po +++ b/translation/pofiles/zh_CN.po @@ -10,7 +10,7 @@ msgstr "" "Project-Id-Version: KiCad_zh_CN_Master_v0.0.32\n" "Report-Msgid-Bugs-To: \n" "POT-Creation-Date: 2021-04-12 11:06-0700\n" -"PO-Revision-Date: 2021-04-15 15:01+0000\n" +"PO-Revision-Date: 2021-04-15 16:43+0000\n" "Last-Translator: taotieren \n" "Language-Team: Chinese (Simplified) \n" @@ -175,7 +175,7 @@ msgstr "简化铜层多边形" #: 3d-viewer/3d_canvas/create_layer_items.cpp:829 msgid "Simplify holes contours" -msgstr "简化孔轮廓" +msgstr "简化通孔轮廓" #: 3d-viewer/3d_canvas/create_layer_items.cpp:858 msgid "Build Tech layers" @@ -183,7 +183,7 @@ msgstr "构造工艺层" #: 3d-viewer/3d_canvas/create_layer_items.cpp:1033 msgid "Build BVH for holes and vias" -msgstr "为孔和过孔构造 BVH (盲埋孔)" +msgstr "为通孔和过孔构造 BVH (盲埋孔)" #: 3d-viewer/3d_canvas/eda_3d_canvas.cpp:413 msgid "Your OpenGL version is not supported. Minimum required is 1.5" @@ -249,7 +249,7 @@ msgstr "载入 OpenGL：电路板" #: 3d-viewer/3d_rendering/legacy/create_scene.cpp:481 msgid "Load OpenGL: holes and vias" -msgstr "载入 OpenGL：开孔和过孔" +msgstr "载入 OpenGL：通孔和过孔" #: 3d-viewer/3d_rendering/legacy/create_scene.cpp:547 msgid "Load OpenGL: layers" @@ -582,7 +582,7 @@ msgstr "禁用过孔" #: 3d-viewer/3d_viewer/dialogs/dialog_3D_view_option_base.cpp:219 msgid "Disable holes" -msgstr "禁用孔" +msgstr "禁用通孔" #: 3d-viewer/3d_viewer/dialogs/dialog_3D_view_option_base.cpp:229 msgid "OpenGL" @@ -935,11 +935,11 @@ msgstr "根据材质的漫反射颜色使用 CAD 颜色样式" #: 3d-viewer/3d_viewer/tools/3d_actions.cpp:210 msgid "Toggle Through Hole 3D models" -msgstr "切换直插 3D 模型" +msgstr "切换直插通孔 3D 模型" #: 3d-viewer/3d_viewer/tools/3d_actions.cpp:210 msgid "Toggle 3D models with 'Through hole' attribute" -msgstr "切换直插元件的 3D 模型" +msgstr "切换直插元件的通孔 3D 模型" #: 3d-viewer/3d_viewer/tools/3d_actions.cpp:216 msgid "Toggle SMD 3D models" @@ -19030,7 +19030,7 @@ msgstr "传输线路" #: pcb_calculator/dialogs/pcb_calculator_frame_base.cpp:1152 msgid "Finished hole diameter (D):" -msgstr "成品孔直径 (D)：" +msgstr "成品通孔直径 (D)：" #: pcb_calculator/dialogs/pcb_calculator_frame_base.cpp:1166 msgid "Plating thickness (T):" @@ -19058,7 +19058,7 @@ msgstr "间隙孔直径：" #: pcb_calculator/dialogs/pcb_calculator_frame_base.cpp:1208 msgid "Diameter of clearance hole in ground plane(s)" -msgstr "地平面过孔直径" +msgstr "地平面通孔直径" #: pcb_calculator/dialogs/pcb_calculator_frame_base.cpp:1220 msgid "Z0:" @@ -27536,6 +27536,206 @@ msgid "" " (constraint clearance (min \"1.5mm\"))\n" " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" msgstr "" +"### Top-level Clauses\n" +"\n" +" (version )\n" +"\n" +" (rule ...)\n" +"\n" +"\n" +"

\n" +"\n" +"### Rule Clauses\n" +"\n" +" (constraint ...)\n" +"\n" +" (condition \"\")\n" +"\n" +" (layer \"\")\n" +"\n" +"\n" +"

\n" +"\n" +"### Constraint Types\n" +"\n" +" * annular_width\n" +" * clearance\n" +" * courtyard_clearance\n" +" * diff\\_pair\\_gap\n" +" * diff\\_pair\\_uncoupled\n" +" * disallow\n" +" * edge_clearance\n" +" * length\n" +" * hole\n" +" * hole_clearance\n" +" * silk_clearance\n" +" * skew\n" +" * track_width\n" +" * via_count\n" +"\n" +"\n" +"

\n" +"\n" +"### Item Types\n" +"\n" +" * buried_via\n" +" * graphic\n" +" * hole\n" +" * micro_via\n" +" * pad\n" +" * text\n" +" * track\n" +" * via\n" +" * zone\n" +"\n" +"
\n" +"\n" +"### Examples\n" +"\n" +" (rule HV\n" +" (constraint clearance (min 1.5mm))\n" +" (condition \"A.NetClass == 'HV'\"))\n" +"\n" +"\n" +" (rule HV\n" +" (layer outer)\n" +" (constraint clearance (min 1.5mm))\n" +" (condition \"A.NetClass == 'HV'\"))\n" +"\n" +"\n" +" (rule HV_HV\n" +" # wider clearance between HV tracks\n" +" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +"\n" +"\n" +" (rule HV_unshielded\n" +" (constraint clearance (min 2mm))\n" +" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +"

\n" +"\n" +"### Notes\n" +"\n" +"Version clause must be the first clause.\n" +"\n" +"Rules should be ordered by specificity. Later rules take\n" +"precedence over earlier rules; once a matching rule is found\n" +"no further rules will be checked.\n" +"\n" +"Use Ctrl+/ to comment or uncomment line(s).\n" +"


\n" +"\n" +"### Expression functions\n" +"\n" +"All function parameters support simple wildcards (`*` and `?`).\n" +"

\n" +"\n" +" A.insideCourtyard('')\n" +"True if any part of `A` lies within the given footprint's principal " +"courtyard.\n" +"

\n" +"\n" +" A.insideFrontCourtyard('')\n" +"True if any part of `A` lies within the given footprint's front courtyard.\n" +"

\n" +"\n" +" A.insideBackCourtyard('')\n" +"True if any part of `A` lies within the given footprint's back courtyard.\n" +"

\n" +"\n" +" A.insideArea('')\n" +"True if any part of `A` lies within the given zone's outline.\n" +"

\n" +"\n" +" A.isPlated()\n" +"True if `A` has a hole which is plated.\n" +"

\n" +"\n" +" A.inDiffPair('')\n" +"True if `A` has net that is part of the specified differential pair.\n" +"`` is the base name of the differential pair. For example, " +"`inDiffPair('CLK')`\n" +"matches items in the `CLK_P` and `CLK_N` nets.\n" +"

\n" +"\n" +" AB.isCoupledDiffPair()\n" +"True if `A` and `B` are members of the same diff pair.\n" +"

\n" +"\n" +" A.memberOf('')\n" +"True if `A` is a member of the given group. Includes nested membership.\n" +"

\n" +"\n" +" A.existsOnLayer('')\n" +"True if `A` exists on the given layer. The layer name can be\n" +"either the name assigned in Board Setup > Board Editor Layers or\n" +"the canonical name (ie: `F.Cu`).\n" +"\n" +"NB: this returns true if `A` is on the given layer, independently\n" +"of whether or not the rule is being evaluated for that layer.\n" +"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +"


\n" +"\n" +"### More Examples\n" +"\n" +" (rule \"copper keepout\"\n" +" (constraint disallow track via zone)\n" +" (condition \"A.insideArea('zone3')\"))\n" +"\n" +"\n" +" (rule \"BGA neckdown\"\n" +" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +" (condition \"A.insideCourtyard('U3')\"))\n" +"\n" +"\n" +" # prevent silk over tented vias\n" +" (rule silk_over_via\n" +" (constraint silk_clearance (min 0.2mm))\n" +" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +"\n" +"\n" +" (rule \"Distance between Vias of Different Nets\" \n" +" (constraint hole_to_hole (min 0.254mm))\n" +" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" +"\n" +" (rule \"Clearance between Pads of Different Nets\" \n" +" (constraint clearance (min 3.0mm))\n" +" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" +"\n" +"\n" +" (rule \"Via Hole to Track Clearance\" \n" +" (constraint hole_clearance (min 0.254mm))\n" +" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" +" \n" +" (rule \"Pad to Track Clearance\" \n" +" (constraint clearance (min 0.2mm))\n" +" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +"\n" +"\n" +" (rule \"clearance-to-1mm-cutout\"\n" +" (constraint clearance (min 0.8mm))\n" +" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +"\n" +"\n" +" (rule \"Max Drill Hole Size Mechanical\" \n" +" (constraint hole (max 6.3mm))\n" +" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +" \n" +" (rule \"Max Drill Hole Size PTH\" \n" +" (constraint hole (max 6.35mm))\n" +" (condition \"A.Pad_Type == 'Through-hole'\"))\n" +"\n" +"\n" +" # Specify an optimal gap for a particular diff-pair\n" +" (rule \"dp clock gap\"\n" +" (constraint diff_pair_gap (opt \"0.8mm\"))\n" +" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" +"\n" +" # Specify a larger clearance around any diff-pair\n" +" (rule \"dp clearance\"\n" +" (constraint clearance (min \"1.5mm\"))\n" +" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:74 msgid "Default properties for new dimension objects:"