diff --git a/include/class_board_design_settings.h b/include/class_board_design_settings.h index a22f3c5bb6..8d04fe0922 100644 --- a/include/class_board_design_settings.h +++ b/include/class_board_design_settings.h @@ -102,18 +102,22 @@ public: BOARD_DESIGN_SETTINGS(); /** - * Function SetCurrentNetClassName - * sets the current net class name to \a aName. - * - * @param aName is a reference to a wxString object containing the current net class name. + * Function GetDefault + * @return the default netclass. */ - void SetCurrentNetClassName( const wxString& aName ) { m_currentNetClassName = aName; } + inline NETCLASS* GetDefault() const + { + return m_NetClasses.GetDefault(); + } /** * Function GetCurrentNetClassName * @return the current net class name. */ - const wxString& GetCurrentNetClassName() const { return m_currentNetClassName; } + const wxString& GetCurrentNetClassName() const + { + return m_currentNetClassName; + } /** * Function SetCurrentNetClass @@ -275,8 +279,6 @@ public: return m_customViaSize.m_Drill; } - // TODO microvia methods should go here - /** * Function UseCustomTrackViaSize * Enables/disables custom track/via size settings. If enabled, values set with diff --git a/pcbnew/autorouter/routing_matrix.cpp b/pcbnew/autorouter/routing_matrix.cpp index 9d87b52bda..ee1890bf2a 100644 --- a/pcbnew/autorouter/routing_matrix.cpp +++ b/pcbnew/autorouter/routing_matrix.cpp @@ -201,7 +201,7 @@ void PlaceCells( BOARD* aPcb, int net_code, int flag ) LAYER_MSK layerMask; // use the default NETCLASS? - NETCLASS* nc = aPcb->GetDesignSettings().m_NetClasses.GetDefault(); + NETCLASS* nc = aPcb->GetDesignSettings().GetDefault(); int trackWidth = nc->GetTrackWidth(); int clearance = nc->GetClearance(); diff --git a/pcbnew/autorouter/solve.cpp b/pcbnew/autorouter/solve.cpp index c1f66b5423..0e0120c458 100644 --- a/pcbnew/autorouter/solve.cpp +++ b/pcbnew/autorouter/solve.cpp @@ -280,7 +280,7 @@ int PCB_EDIT_FRAME::Solve( wxDC* DC, int aLayersCount ) m_canvas->SetAbortRequest( false ); - s_Clearance = GetBoard()->GetDesignSettings().m_NetClasses.GetDefault()->GetClearance(); + s_Clearance = GetBoard()->GetDesignSettings().GetDefault()->GetClearance(); // Prepare the undo command info s_ItemsListPicker.ClearListAndDeleteItems(); // Should not be necessary, but... diff --git a/pcbnew/class_board.cpp b/pcbnew/class_board.cpp index c05474d29f..2fc5fa7d3e 100644 --- a/pcbnew/class_board.cpp +++ b/pcbnew/class_board.cpp @@ -91,7 +91,7 @@ BOARD::BOARD() : m_Layer[layer].m_Type = LT_UNDEFINED; } - NETCLASS* defaultClass = m_designSettings.m_NetClasses.GetDefault(); + NETCLASS* defaultClass = m_designSettings.GetDefault(); defaultClass->SetDescription( _( "This is the default net class." ) ); // Initialize default values in default netclass. diff --git a/pcbnew/class_board_connected_item.cpp b/pcbnew/class_board_connected_item.cpp index 9aaa6d14ad..0b91036802 100644 --- a/pcbnew/class_board_connected_item.cpp +++ b/pcbnew/class_board_connected_item.cpp @@ -144,7 +144,7 @@ NETCLASS* BOARD_CONNECTED_ITEM::GetNetClass() const if( netclass ) return netclass; else - return board->GetDesignSettings().m_NetClasses.GetDefault(); + return board->GetDesignSettings().GetDefault(); } @@ -158,7 +158,7 @@ wxString BOARD_CONNECTED_ITEM::GetNetClassName() const else { BOARD* board = GetBoard(); - name = board->GetDesignSettings().m_NetClasses.GetDefault()->GetName(); + name = NETCLASS::Default; } return name; diff --git a/pcbnew/eagle_plugin.cpp b/pcbnew/eagle_plugin.cpp index b1da39fc6f..2e59478403 100644 --- a/pcbnew/eagle_plugin.cpp +++ b/pcbnew/eagle_plugin.cpp @@ -1146,7 +1146,7 @@ BOARD* EAGLE_PLUGIN::Load( const wxString& aFileName, BOARD* aAppendToMe, const if( m_rules->mdWireWire ) { - NETCLASS* defaultNetclass = designSettings.m_NetClasses.GetDefault(); + NETCLASS* defaultNetclass = designSettings.GetDefault(); int clearance = KiROUND( m_rules->mdWireWire ); if( clearance < defaultNetclass->GetClearance() ) diff --git a/pcbnew/files.cpp b/pcbnew/files.cpp index 89671c066b..10eaa4be0a 100644 --- a/pcbnew/files.cpp +++ b/pcbnew/files.cpp @@ -678,7 +678,7 @@ bool PCB_EDIT_FRAME::SavePcbFile( const wxString& aFileName, bool aCreateBackupF // Select default Netclass before writing file. // Useful to save default values in headers - GetDesignSettings().SetCurrentNetClass( GetDesignSettings().m_NetClasses.GetDefault()->GetName() ); + GetDesignSettings().SetCurrentNetClass( NETCLASS::Default ); try { diff --git a/pcbnew/kicad_plugin.cpp b/pcbnew/kicad_plugin.cpp index adf5ce76eb..f77c4dfbb4 100644 --- a/pcbnew/kicad_plugin.cpp +++ b/pcbnew/kicad_plugin.cpp @@ -572,7 +572,7 @@ void PCB_IO::format( BOARD* aBoard, int aNestLevel ) const FMTIU( dsnSettings.m_TrackWidthList[ii] ).c_str() ); m_out->Print( aNestLevel+1, "(trace_clearance %s)\n", - FMTIU( dsnSettings.m_NetClasses.GetDefault()->GetClearance() ).c_str() ); + FMTIU( dsnSettings.GetDefault()->GetClearance() ).c_str() ); // ZONE_SETTINGS m_out->Print( aNestLevel+1, "(zone_clearance %s)\n", @@ -590,9 +590,9 @@ void PCB_IO::format( BOARD* aBoard, int aNestLevel ) const // Save current default via size, for compatibility with older Pcbnew version; m_out->Print( aNestLevel+1, "(via_size %s)\n", - FMTIU( dsnSettings.m_NetClasses.GetDefault()->GetViaDiameter() ).c_str() ); + FMTIU( dsnSettings.GetDefault()->GetViaDiameter() ).c_str() ); m_out->Print( aNestLevel+1, "(via_drill %s)\n", - FMTIU( dsnSettings.m_NetClasses.GetDefault()->GetViaDrill() ).c_str() ); + FMTIU( dsnSettings.GetDefault()->GetViaDrill() ).c_str() ); m_out->Print( aNestLevel+1, "(via_min_size %s)\n", FMTIU( dsnSettings.m_ViasMinSize ).c_str() ); m_out->Print( aNestLevel+1, "(via_min_drill %s)\n", @@ -610,9 +610,9 @@ void PCB_IO::format( BOARD* aBoard, int aNestLevel ) const m_out->Print( aNestLevel+1, "(blind_buried_vias_allowed yes)\n" ); m_out->Print( aNestLevel+1, "(uvia_size %s)\n", - FMTIU( dsnSettings.m_NetClasses.GetDefault()->GetuViaDiameter() ).c_str() ); + FMTIU( dsnSettings.GetDefault()->GetuViaDiameter() ).c_str() ); m_out->Print( aNestLevel+1, "(uvia_drill %s)\n", - FMTIU( dsnSettings.m_NetClasses.GetDefault()->GetuViaDrill() ).c_str() ); + FMTIU( dsnSettings.GetDefault()->GetuViaDrill() ).c_str() ); m_out->Print( aNestLevel+1, "(uvias_allowed %s)\n", ( dsnSettings.m_MicroViasAllowed ) ? "yes" : "no" ); m_out->Print( aNestLevel+1, "(uvia_min_size %s)\n", @@ -683,7 +683,7 @@ void PCB_IO::format( BOARD* aBoard, int aNestLevel ) const m_out->Print( 0, "\n" ); // Save the default net class first. - NETCLASS defaultNC = *dsnSettings.m_NetClasses.GetDefault(); + NETCLASS defaultNC = *dsnSettings.GetDefault(); filterNetClass( *aBoard, defaultNC ); // Remove empty nets (from a copy of a netclass) defaultNC.Format( m_out, aNestLevel, m_ctl ); diff --git a/pcbnew/legacy_plugin.cpp b/pcbnew/legacy_plugin.cpp index 77a4d14a0e..f2f174267b 100644 --- a/pcbnew/legacy_plugin.cpp +++ b/pcbnew/legacy_plugin.cpp @@ -632,7 +632,7 @@ void LEGACY_PLUGIN::loadSHEET() void LEGACY_PLUGIN::loadSETUP() { - NETCLASS* netclass_default = m_board->GetDesignSettings().m_NetClasses.GetDefault(); + NETCLASS* netclass_default = m_board->GetDesignSettings().GetDefault(); // TODO Orson: is it really necessary to first operate on a copy and then apply it? // would not it be better to use reference here and apply all the changes instantly? BOARD_DESIGN_SETTINGS bds = m_board->GetDesignSettings(); @@ -897,7 +897,7 @@ void LEGACY_PLUGIN::loadSETUP() // at all, the global defaults should go into a preferences // file instead so they are there to start new board // projects. - m_board->GetDesignSettings().m_NetClasses.GetDefault()->SetParams( m_board->GetDesignSettings() ); + m_board->GetDesignSettings().GetDefault()->SetParams( m_board->GetDesignSettings() ); return; // preferred exit } @@ -2985,7 +2985,7 @@ void LEGACY_PLUGIN::saveSHEET( const BOARD* aBoard ) const void LEGACY_PLUGIN::saveSETUP( const BOARD* aBoard ) const { const BOARD_DESIGN_SETTINGS& bds = aBoard->GetDesignSettings(); - NETCLASS* netclass_default = bds.m_NetClasses.GetDefault(); + NETCLASS* netclass_default = bds.GetDefault(); fprintf( m_fp, "$SETUP\n" ); diff --git a/pcbnew/pcb_parser.cpp b/pcbnew/pcb_parser.cpp index 77586e843f..547120fa9b 100644 --- a/pcbnew/pcb_parser.cpp +++ b/pcbnew/pcb_parser.cpp @@ -808,7 +808,7 @@ void PCB_PARSER::parseSetup() throw( IO_ERROR, PARSE_ERROR ) wxT( "Cannot parse " ) + GetTokenString( CurTok() ) + wxT( " as setup." ) ); T token; - NETCLASS* defaultNetClass = m_board->GetDesignSettings().m_NetClasses.GetDefault(); + NETCLASS* defaultNetClass = m_board->GetDesignSettings().GetDefault(); // TODO Orson: is it really necessary to first operate on a copy and then apply it? // would not it be better to use reference here and apply all the changes instantly? BOARD_DESIGN_SETTINGS designSettings = m_board->GetDesignSettings(); diff --git a/pcbnew/router/router_tool.cpp b/pcbnew/router/router_tool.cpp index a983fac319..e0f4a2068a 100644 --- a/pcbnew/router/router_tool.cpp +++ b/pcbnew/router/router_tool.cpp @@ -279,7 +279,7 @@ void ROUTER_TOOL::getNetclassDimensions( int aNetCode, int& aWidth, } if( !netClass ) - netClass = bds.m_NetClasses.GetDefault(); + netClass = bds.GetDefault(); aWidth = netClass->GetTrackWidth(); aViaDiameter = netClass->GetViaDiameter();