diff --git a/qa/tests/pcbnewswig/test_001_pcb_load.py b/qa/tests/pcbnewswig/test_001_pcb_load.py
index 8d5facd49d..212a14d7f6 100644
--- a/qa/tests/pcbnewswig/test_001_pcb_load.py
+++ b/qa/tests/pcbnewswig/test_001_pcb_load.py
@@ -6,7 +6,7 @@ import pdb
 class TestPCBLoad(unittest.TestCase):
 
     def setUp(self):
-        self.pcb = pcbnew.LoadBoard("../../data/pcbnew/complex_hierarchy.kicad_pcb")
+        self.pcb = pcbnew.LoadBoard("../data/pcbnew/complex_hierarchy.kicad_pcb")
 
     def test_pcb_load(self):
         self.assertNotEqual(self.pcb,None)
diff --git a/qa/tests/pcbnewswig/test_002_board_class.py b/qa/tests/pcbnewswig/test_002_board_class.py
index 8b554eefb9..a0539f1b92 100644
--- a/qa/tests/pcbnewswig/test_002_board_class.py
+++ b/qa/tests/pcbnewswig/test_002_board_class.py
@@ -17,7 +17,7 @@ NEW_NAME = 'My_Fancy_Layer_Name'
 class TestBoardClass(unittest.TestCase):
 
     def setUp(self):
-        self.pcb = LoadBoard("../../data/pcbnew/complex_hierarchy.kicad_pcb")
+        self.pcb = LoadBoard("../data/pcbnew/complex_hierarchy.kicad_pcb")
         self.TITLE="Test Board"
         self.COMMENT1="For load/save test"
         self.FILENAME=tempfile.mktemp()+".kicad_pcb"
@@ -122,7 +122,7 @@ class TestBoardClass(unittest.TestCase):
         self.assertEqual(pcb.GetLayerID(B_CU), b_cu_id)
 
     def test_footprint_properties(self):
-        pcb = LoadBoard("../../data/pcbnew/custom_fields.kicad_pcb")
+        pcb = LoadBoard("../data/pcbnew/custom_fields.kicad_pcb")
         footprint = pcb.FindFootprintByReference('J1')
         expected_properties = {
             'Sheet file': 'custom_fields.kicad_sch',
diff --git a/qa/tests/pcbnewswig/test_003_pads.py b/qa/tests/pcbnewswig/test_003_pads.py
index 40e2510ff4..37fd61f63d 100644
--- a/qa/tests/pcbnewswig/test_003_pads.py
+++ b/qa/tests/pcbnewswig/test_003_pads.py
@@ -4,7 +4,7 @@ import pcbnew
 class TestPads(unittest.TestCase):
 
     def setUp(self):
-        self.pcb = pcbnew.LoadBoard("../../data/pcbnew/custom_pads.kicad_pcb")
+        self.pcb = pcbnew.LoadBoard("../data/pcbnew/custom_pads.kicad_pcb")
 
     def test_custom_pads_outline(self):
         custom_pad1 = self.pcb.FindFootprintByReference("SB1").Pads()[0]
diff --git a/qa/tests/pcbnewswig/test_004_tracks.py b/qa/tests/pcbnewswig/test_004_tracks.py
index 71c0b27246..d285c4f291 100644
--- a/qa/tests/pcbnewswig/test_004_tracks.py
+++ b/qa/tests/pcbnewswig/test_004_tracks.py
@@ -4,7 +4,7 @@ import pcbnew
 class TestTracks(unittest.TestCase):
 
     def setUp(self):
-        self.pcb = pcbnew.LoadBoard("../../data/pcbnew/tracks_arcs_vias.kicad_pcb")
+        self.pcb = pcbnew.LoadBoard("../data/pcbnew/tracks_arcs_vias.kicad_pcb")
 
     def test_tracks(self):
         tracks = [t for t in self.pcb.Tracks() if t.GetClass() == 'PCB_TRACK']
diff --git a/qa/tests/pcbnewswig/test_005_connectivity_data.py b/qa/tests/pcbnewswig/test_005_connectivity_data.py
index 1b5ba46b67..7adf528e6b 100644
--- a/qa/tests/pcbnewswig/test_005_connectivity_data.py
+++ b/qa/tests/pcbnewswig/test_005_connectivity_data.py
@@ -10,7 +10,7 @@ class TestConnectivity(unittest.TestCase):
 
     def setUp(self):
         """Setup shared attributes."""
-        self.pcb = pcbnew.LoadBoard("../../data/pcbnew/complex_hierarchy.kicad_pcb")
+        self.pcb = pcbnew.LoadBoard("../data/pcbnew/complex_hierarchy.kicad_pcb")
         self.connectivity = self.pcb.GetConnectivity()
         self.nets = self.pcb.GetNetsByName()