diff --git a/pcbnew/python/swig/board.i b/pcbnew/python/swig/board.i
index 91082ca7af..7ef1f70a0f 100644
--- a/pcbnew/python/swig/board.i
+++ b/pcbnew/python/swig/board.i
@@ -194,8 +194,8 @@ HANDLE_EXCEPTIONS(BOARD::TracksInNetBetweenPoints)
 
         # Copy the NETCLASS_MAP so the one in the BOARD isn't modified
         # when we add the Default net class.
-        netclassmap = {k:v for k,v in self.GetNetClasses().NetClasses().items()}
-        netclassmap['Default'] = self.GetNetClasses().GetDefault()
+        netclassmap = {k:v for k,v in self.GetNetClasses().items()}
+        netclassmap['Default'] = self.GetDesignSettings().m_NetSettings.m_DefaultNetClass
         return netclassmap
     %}
 }