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Move layer defaults and diff-pair dimensions to board file.

This commit is contained in:
Jeff Young 2019-07-03 22:19:09 +01:00
parent 09100100c9
commit 562ab0bdea
6 changed files with 236 additions and 67 deletions
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12
common/pcb.keywords
View File

@ -60,7 +60,11 @@ crossbar
custom custom
outline outline
convexhull convexhull
copper_line_width
copper_text_dims
courtyard_line_width
date date
defaults
descr descr
die_length die_length
dimension dimension
@ -69,6 +73,8 @@ diff_pair_gap
drawings drawings
drill drill
edge edge
edge_clearance
edge_cuts_line_width
edge_width edge_width
effects effects
end end
@ -105,6 +111,7 @@ hide
italic italic
justify justify
keepout keepout
keep_upright
kicad_pcb kicad_pcb
last_trace_width last_trace_width
layer layer
@ -133,6 +140,8 @@ not_allowed
np_thru_hole np_thru_hole
offset offset
options options
other_layers_line_width
other_layers_text_dims
oval oval
pad pad
pads pads
@ -167,6 +176,8 @@ scale
segment segment
segment_width segment_width
setup setup
silk_line_width
silk_text_dims
size size
smd smd
smoothing smoothing
@ -199,6 +210,7 @@ thru_hole_only
tstamp tstamp
unlocked unlocked
user user
user_diff_pair
user_trace_width user_trace_width
user_via user_via
uvia_dia uvia_dia

29
pcbnew/files.cpp
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@ -515,11 +515,13 @@ bool PCB_EDIT_FRAME::OpenProjectFiles( const std::vector<wxString>& aFileSet, in
return false; return false;
} }
// 6.0 TODO: some settings didn't make it into the board file in 5.1 so as not to
// change the file format. For 5.1 we must copy them across from the config-initialized
// board.
BOARD_DESIGN_SETTINGS& bds = loadedBoard->m_designSettings; BOARD_DESIGN_SETTINGS& bds = loadedBoard->m_designSettings;
if( bds.m_CopperEdgeClearance == Millimeter2iu( LEGACY_COPPEREDGECLEARANCE ) )
{
// 5.1 boards stored some settings in the config so as not to bump the file version.
// These will have been loaded into the config-initialized board, so we copy them
// from there.
BOARD_DESIGN_SETTINGS& configBds = GetBoard()->GetDesignSettings(); BOARD_DESIGN_SETTINGS& configBds = GetBoard()->GetDesignSettings();
bds.m_RequireCourtyards = configBds.m_RequireCourtyards; bds.m_RequireCourtyards = configBds.m_RequireCourtyards;
@ -533,17 +535,26 @@ bool PCB_EDIT_FRAME::OpenProjectFiles( const std::vector<wxString>& aFileSet, in
bds.m_DiffPairDimensionsList = configBds.m_DiffPairDimensionsList; bds.m_DiffPairDimensionsList = configBds.m_DiffPairDimensionsList;
bds.m_CopperEdgeClearance = configBds.m_CopperEdgeClearance; bds.m_CopperEdgeClearance = configBds.m_CopperEdgeClearance;
// Before we had a copper edge clearance setting, the edge line widths could be used
// as a kludge to control them. So if there's no setting then infer it from the
// edge widths.
if( bds.m_CopperEdgeClearance == Millimeter2iu( LEGACY_COPPEREDGECLEARANCE ) )
bds.SetCopperEdgeClearance( inferLegacyEdgeClearance( loadedBoard ) );
}
// 6.0 TODO: some of the 5.1 settings still haven't moved because they're waiting on
// the new DRC architecture
BOARD_DESIGN_SETTINGS& configBds = GetBoard()->GetDesignSettings();
bds.m_RequireCourtyards = configBds.m_RequireCourtyards;
bds.m_ProhibitOverlappingCourtyards = configBds.m_ProhibitOverlappingCourtyards;
bds.m_HoleToHoleMin = configBds.m_HoleToHoleMin;
SetBoard( loadedBoard ); SetBoard( loadedBoard );
// we should not ask PLUGINs to do these items: // we should not ask PLUGINs to do these items:
loadedBoard->BuildListOfNets(); loadedBoard->BuildListOfNets();
loadedBoard->SynchronizeNetsAndNetClasses(); loadedBoard->SynchronizeNetsAndNetClasses();
// If this is a legacy board then we set the copper edge clearance to 1/2 the edge-cut
// line width (which was a legacy kludge for implementing edge clearances).
if( bds.m_CopperEdgeClearance == Millimeter2iu( LEGACY_COPPEREDGECLEARANCE ) )
bds.SetCopperEdgeClearance( inferLegacyEdgeClearance( loadedBoard ) );
if( loadedBoard->IsModified() ) if( loadedBoard->IsModified() )
OnModify(); OnModify();
else else

83
pcbnew/kicad_plugin.cpp
View File

@ -477,10 +477,12 @@ void PCB_IO::formatSetup( BOARD* aBoard, int aNestLevel ) const
m_out->Print( aNestLevel+1, "(last_trace_width %s)\n", m_out->Print( aNestLevel+1, "(last_trace_width %s)\n",
FormatInternalUnits( dsnSettings.GetCurrentTrackWidth() ).c_str() ); FormatInternalUnits( dsnSettings.GetCurrentTrackWidth() ).c_str() );
// Save custom tracks width list (the first is not saved here: this is the netclass value // Save custom track widths list (the first is not saved here: it's the netclass value)
for( unsigned ii = 1; ii < dsnSettings.m_TrackWidthList.size(); ii++ ) for( unsigned ii = 1; ii < dsnSettings.m_TrackWidthList.size(); ii++ )
{
m_out->Print( aNestLevel+1, "(user_trace_width %s)\n", m_out->Print( aNestLevel+1, "(user_trace_width %s)\n",
FormatInternalUnits( dsnSettings.m_TrackWidthList[ii] ).c_str() ); FormatInternalUnits( dsnSettings.m_TrackWidthList[ii] ).c_str() );
}
m_out->Print( aNestLevel+1, "(trace_clearance %s)\n", m_out->Print( aNestLevel+1, "(trace_clearance %s)\n",
FormatInternalUnits( dsnSettings.GetDefault()->GetClearance() ).c_str() ); FormatInternalUnits( dsnSettings.GetDefault()->GetClearance() ).c_str() );
@ -504,13 +506,21 @@ void PCB_IO::formatSetup( BOARD* aBoard, int aNestLevel ) const
m_out->Print( aNestLevel+1, "(via_min_drill %s)\n", m_out->Print( aNestLevel+1, "(via_min_drill %s)\n",
FormatInternalUnits( dsnSettings.m_ViasMinDrill ).c_str() ); FormatInternalUnits( dsnSettings.m_ViasMinDrill ).c_str() );
// Save custom vias diameters list (the first is not saved here: this is // Save custom via dimensions list (the first is not saved here: it's the netclass value)
// the netclass value
for( unsigned ii = 1; ii < dsnSettings.m_ViasDimensionsList.size(); ii++ ) for( unsigned ii = 1; ii < dsnSettings.m_ViasDimensionsList.size(); ii++ )
m_out->Print( aNestLevel+1, "(user_via %s %s)\n", m_out->Print( aNestLevel+1, "(user_via %s %s)\n",
FormatInternalUnits( dsnSettings.m_ViasDimensionsList[ii].m_Diameter ).c_str(), FormatInternalUnits( dsnSettings.m_ViasDimensionsList[ii].m_Diameter ).c_str(),
FormatInternalUnits( dsnSettings.m_ViasDimensionsList[ii].m_Drill ).c_str() ); FormatInternalUnits( dsnSettings.m_ViasDimensionsList[ii].m_Drill ).c_str() );
// Save custom diff-pair dimensions (the first is not saved here: it's the netclass value)
for( unsigned ii = 1; ii < dsnSettings.m_DiffPairDimensionsList.size(); ii++ )
{
m_out->Print( aNestLevel+1, "(user_diff_pair %s %s %s)\n",
FormatInternalUnits( dsnSettings.m_DiffPairDimensionsList[ii].m_Width ).c_str(),
FormatInternalUnits( dsnSettings.m_DiffPairDimensionsList[ii].m_Gap ).c_str(),
FormatInternalUnits( dsnSettings.m_DiffPairDimensionsList[ii].m_ViaGap ).c_str() );
}
// for old versions compatibility: // for old versions compatibility:
if( dsnSettings.m_BlindBuriedViaAllowed ) if( dsnSettings.m_BlindBuriedViaAllowed )
m_out->Print( aNestLevel+1, "(blind_buried_vias_allowed yes)\n" ); m_out->Print( aNestLevel+1, "(blind_buried_vias_allowed yes)\n" );
@ -533,28 +543,7 @@ void PCB_IO::formatSetup( BOARD* aBoard, int aNestLevel ) const
if( dsnSettings.m_ZoneUseNoOutlineInFill ) if( dsnSettings.m_ZoneUseNoOutlineInFill )
m_out->Print( aNestLevel+1, "(filled_areas_thickness no)\n" ); m_out->Print( aNestLevel+1, "(filled_areas_thickness no)\n" );
// 6.0 TODO: are we going to update the tokens we save these under? formatDefaults( dsnSettings, aNestLevel+1 );
// 6.0 TODO: need to save the LAYER_CLASS_OTHERS stuff
// 6.0 TODO: need to save the TextItalic and TextUpright settings
m_out->Print( aNestLevel+1, "(edge_width %s)\n",
FormatInternalUnits( dsnSettings.m_LineThickness[ LAYER_CLASS_EDGES ] ).c_str() );
m_out->Print( aNestLevel+1, "(segment_width %s)\n",
FormatInternalUnits( dsnSettings.m_LineThickness[ LAYER_CLASS_COPPER ] ).c_str() );
m_out->Print( aNestLevel+1, "(pcb_text_width %s)\n",
FormatInternalUnits( dsnSettings.m_TextThickness[ LAYER_CLASS_COPPER ] ).c_str() );
m_out->Print( aNestLevel+1, "(pcb_text_size %s %s)\n",
FormatInternalUnits( dsnSettings.m_TextSize[ LAYER_CLASS_COPPER ].x ).c_str(),
FormatInternalUnits( dsnSettings.m_TextSize[ LAYER_CLASS_COPPER ].y ).c_str() );
m_out->Print( aNestLevel+1, "(mod_edge_width %s)\n",
FormatInternalUnits( dsnSettings.m_LineThickness[ LAYER_CLASS_SILK ] ).c_str() );
m_out->Print( aNestLevel+1, "(mod_text_size %s %s)\n",
FormatInternalUnits( dsnSettings.m_TextSize[ LAYER_CLASS_SILK ].x ).c_str(),
FormatInternalUnits( dsnSettings.m_TextSize[ LAYER_CLASS_SILK ].y ).c_str() );
m_out->Print( aNestLevel+1, "(mod_text_width %s)\n",
FormatInternalUnits( dsnSettings.m_TextThickness[ LAYER_CLASS_SILK ] ).c_str() );
m_out->Print( aNestLevel+1, "(pad_size %s %s)\n", m_out->Print( aNestLevel+1, "(pad_size %s %s)\n",
FormatInternalUnits( dsnSettings.m_Pad_Master.GetSize().x ).c_str(), FormatInternalUnits( dsnSettings.m_Pad_Master.GetSize().x ).c_str(),
@ -595,6 +584,50 @@ void PCB_IO::formatSetup( BOARD* aBoard, int aNestLevel ) const
} }
void PCB_IO::formatDefaults( const BOARD_DESIGN_SETTINGS& aSettings, int aNestLevel ) const
{
m_out->Print( aNestLevel, "(defaults\n" );
m_out->Print( aNestLevel+1, "(edge_clearance %s)\n",
FormatInternalUnits( aSettings.m_CopperEdgeClearance ).c_str() );
m_out->Print( aNestLevel+1, "(edge_cuts_line_width %s)\n",
FormatInternalUnits( aSettings.m_LineThickness[ LAYER_CLASS_EDGES ] ).c_str() );
m_out->Print( aNestLevel+1, "(courtyard_line_width %s)\n",
FormatInternalUnits( aSettings.m_LineThickness[ LAYER_CLASS_COURTYARD ] ).c_str() );
m_out->Print( aNestLevel+1, "(copper_line_width %s)\n",
FormatInternalUnits( aSettings.m_LineThickness[ LAYER_CLASS_COPPER ] ).c_str() );
m_out->Print( aNestLevel+1, "(copper_text_dims (size %s %s) (thickness %s)%s%s)\n",
FormatInternalUnits( aSettings.m_TextSize[ LAYER_CLASS_COPPER ].x ).c_str(),
FormatInternalUnits( aSettings.m_TextSize[ LAYER_CLASS_COPPER ].y ).c_str(),
FormatInternalUnits( aSettings.m_TextThickness[ LAYER_CLASS_COPPER ] ).c_str(),
aSettings.m_TextItalic[ LAYER_CLASS_COPPER ] ? " italic" : "",
aSettings.m_TextUpright[ LAYER_CLASS_COPPER ] ? " keep_upright" : "" );
m_out->Print( aNestLevel+1, "(silk_line_width %s)\n",
FormatInternalUnits( aSettings.m_LineThickness[ LAYER_CLASS_SILK ] ).c_str() );
m_out->Print( aNestLevel+1, "(silk_text_dims (size %s %s) (thickness %s)%s%s)\n",
FormatInternalUnits( aSettings.m_TextSize[ LAYER_CLASS_SILK ].x ).c_str(),
FormatInternalUnits( aSettings.m_TextSize[ LAYER_CLASS_SILK ].y ).c_str(),
FormatInternalUnits( aSettings.m_TextThickness[ LAYER_CLASS_SILK ] ).c_str(),
aSettings.m_TextItalic[ LAYER_CLASS_SILK ] ? " italic" : "",
aSettings.m_TextUpright[ LAYER_CLASS_SILK ] ? " keep_upright" : "" );
m_out->Print( aNestLevel+1, "(other_layers_line_width %s)\n",
FormatInternalUnits( aSettings.m_LineThickness[ LAYER_CLASS_OTHERS ] ).c_str() );
m_out->Print( aNestLevel+1, "(other_layers_text_dims (size %s %s) (thickness %s)%s%s)\n",
FormatInternalUnits( aSettings.m_TextSize[ LAYER_CLASS_OTHERS ].x ).c_str(),
FormatInternalUnits( aSettings.m_TextSize[ LAYER_CLASS_OTHERS ].y ).c_str(),
FormatInternalUnits( aSettings.m_TextThickness[ LAYER_CLASS_OTHERS ] ).c_str(),
aSettings.m_TextItalic[ LAYER_CLASS_OTHERS ] ? " italic" : "",
aSettings.m_TextUpright[ LAYER_CLASS_OTHERS ] ? " keep_upright" : "" );
m_out->Print( aNestLevel, ")\n" );
}
void PCB_IO::formatGeneral( BOARD* aBoard, int aNestLevel ) const void PCB_IO::formatGeneral( BOARD* aBoard, int aNestLevel ) const
{ {
const BOARD_DESIGN_SETTINGS& dsnSettings = aBoard->GetDesignSettings(); const BOARD_DESIGN_SETTINGS& dsnSettings = aBoard->GetDesignSettings();

28
pcbnew/kicad_plugin.h
View File

@ -34,6 +34,16 @@ class BOARD_ITEM;
class FP_CACHE; class FP_CACHE;
class PCB_PARSER; class PCB_PARSER;
class NETINFO_MAPPING; class NETINFO_MAPPING;
class BOARD_DESIGN_SETTINGS;
class DIMENSION;
class EDGE_MODULE;
class DRAWSEGMENT;
class PCB_TARGET;
class D_PAD;
class TEXTE_MODULE;
class TRACK;
class ZONE_CONTAINER;
class TEXTE_PCB;
/// Current s-expression file format version. 2 was the last legacy format version. /// Current s-expression file format version. 2 was the last legacy format version.
@ -50,7 +60,8 @@ class NETINFO_MAPPING;
//#define SEXPR_BOARD_FILE_VERSION 20171130 // 3D model offset written using "offset" parameter //#define SEXPR_BOARD_FILE_VERSION 20171130 // 3D model offset written using "offset" parameter
//#define SEXPR_BOARD_FILE_VERSION 20190331 // hatched zones and chamfered round rect pads //#define SEXPR_BOARD_FILE_VERSION 20190331 // hatched zones and chamfered round rect pads
//#define SEXPR_BOARD_FILE_VERSION 20190421 // curves in custom pads //#define SEXPR_BOARD_FILE_VERSION 20190421 // curves in custom pads
#define SEXPR_BOARD_FILE_VERSION 20190516 // Remove segment count from zones //#define SEXPR_BOARD_FILE_VERSION 20190516 // Remove segment count from zones
#define SEXPR_BOARD_FILE_VERSION 20190605 // Add layer defaults
#define CTL_STD_LAYER_NAMES (1 << 0) ///< Use English Standard layer names #define CTL_STD_LAYER_NAMES (1 << 0) ///< Use English Standard layer names
#define CTL_OMIT_NETS (1 << 1) ///< Omit pads net names (useless in library) #define CTL_OMIT_NETS (1 << 1) ///< Omit pads net names (useless in library)
@ -75,18 +86,6 @@ class NETINFO_MAPPING;
#define CTL_FOR_BOARD (CTL_OMIT_INITIAL_COMMENTS) #define CTL_FOR_BOARD (CTL_OMIT_INITIAL_COMMENTS)
class DIMENSION;
class EDGE_MODULE;
class DRAWSEGMENT;
class PCB_TARGET;
class D_PAD;
class TEXTE_MODULE;
class TRACK;
class ZONE_CONTAINER;
class TEXTE_PCB;
/** /**
* Class PCB_IO * Class PCB_IO
* is a PLUGIN derivation for saving and loading Pcbnew s-expression formatted files. * is a PLUGIN derivation for saving and loading Pcbnew s-expression formatted files.
@ -205,6 +204,9 @@ protected:
/// formats the board setup information /// formats the board setup information
void formatSetup( BOARD* aBoard, int aNestLevel = 0 ) const; void formatSetup( BOARD* aBoard, int aNestLevel = 0 ) const;
/// formats the defaults subsection of the board setup
void formatDefaults( const BOARD_DESIGN_SETTINGS& aSettings, int aNestLevel ) const;
/// formats the General section of the file /// formats the General section of the file
void formatGeneral( BOARD* aBoard, int aNestLevel = 0 ) const; void formatGeneral( BOARD* aBoard, int aNestLevel = 0 ) const;

132
pcbnew/pcb_parser.cpp
View File

@ -1240,7 +1240,7 @@ void PCB_PARSER::parseSetup()
{ {
int viaSize = parseBoardUnits( "user via size" ); int viaSize = parseBoardUnits( "user via size" );
int viaDrill = parseBoardUnits( "user via drill" ); int viaDrill = parseBoardUnits( "user via drill" );
designSettings.m_ViasDimensionsList.push_back( VIA_DIMENSION( viaSize, viaDrill ) ); designSettings.m_ViasDimensionsList.emplace_back( VIA_DIMENSION( viaSize, viaDrill ) );
NeedRIGHT(); NeedRIGHT();
} }
break; break;
@ -1275,48 +1275,57 @@ void PCB_PARSER::parseSetup()
NeedRIGHT(); NeedRIGHT();
break; break;
// 6.0 TODO: change these names, or leave them? case T_user_diff_pair:
// 6.0 TODO: add LAYER_CLASS_OTHERS read/write {
// 6.0 TODO: add m_TextItalic read/write int width = parseBoardUnits( "user diff-pair width" );
// 6.0 TODO: add m_TextUpright read/write int gap = parseBoardUnits( "user diff-pair gap" );
int viaGap = parseBoardUnits( "user diff-pair via gap" );
designSettings.m_DiffPairDimensionsList.emplace_back( DIFF_PAIR_DIMENSION( width, gap, viaGap ) );
NeedRIGHT();
}
break;
case T_segment_width: case T_segment_width: // note: legacy (pre-6.0) token
designSettings.m_LineThickness[ LAYER_CLASS_COPPER ] = parseBoardUnits( T_segment_width ); designSettings.m_LineThickness[ LAYER_CLASS_COPPER ] = parseBoardUnits( T_segment_width );
NeedRIGHT(); NeedRIGHT();
break; break;
case T_edge_width: case T_edge_width: // note: legacy (pre-6.0) token
designSettings.m_LineThickness[ LAYER_CLASS_EDGES ] = parseBoardUnits( T_edge_width ); designSettings.m_LineThickness[ LAYER_CLASS_EDGES ] = parseBoardUnits( T_edge_width );
NeedRIGHT(); NeedRIGHT();
break; break;
case T_mod_edge_width: case T_mod_edge_width: // note: legacy (pre-6.0) token
designSettings.m_LineThickness[ LAYER_CLASS_SILK ] = parseBoardUnits( T_mod_edge_width ); designSettings.m_LineThickness[ LAYER_CLASS_SILK ] = parseBoardUnits( T_mod_edge_width );
NeedRIGHT(); NeedRIGHT();
break; break;
case T_pcb_text_width: case T_pcb_text_width: // note: legacy (pre-6.0) token
designSettings.m_TextThickness[ LAYER_CLASS_COPPER ] = parseBoardUnits( T_pcb_text_width ); designSettings.m_TextThickness[ LAYER_CLASS_COPPER ] = parseBoardUnits( T_pcb_text_width );
NeedRIGHT(); NeedRIGHT();
break; break;
case T_mod_text_width: case T_mod_text_width: // note: legacy (pre-6.0) token
designSettings.m_TextThickness[ LAYER_CLASS_SILK ] = parseBoardUnits( T_mod_text_width ); designSettings.m_TextThickness[ LAYER_CLASS_SILK ] = parseBoardUnits( T_mod_text_width );
NeedRIGHT(); NeedRIGHT();
break; break;
case T_pcb_text_size: case T_pcb_text_size: // note: legacy (pre-6.0) token
designSettings.m_TextSize[ LAYER_CLASS_COPPER ].x = parseBoardUnits( "pcb text width" ); designSettings.m_TextSize[ LAYER_CLASS_COPPER ].x = parseBoardUnits( "pcb text width" );
designSettings.m_TextSize[ LAYER_CLASS_COPPER ].y = parseBoardUnits( "pcb text height" ); designSettings.m_TextSize[ LAYER_CLASS_COPPER ].y = parseBoardUnits( "pcb text height" );
NeedRIGHT(); NeedRIGHT();
break; break;
case T_mod_text_size: case T_mod_text_size: // note: legacy (pre-6.0) token
designSettings.m_TextSize[ LAYER_CLASS_SILK ].x = parseBoardUnits( "module text width" ); designSettings.m_TextSize[ LAYER_CLASS_SILK ].x = parseBoardUnits( "module text width" );
designSettings.m_TextSize[ LAYER_CLASS_SILK ].y = parseBoardUnits( "module text height" ); designSettings.m_TextSize[ LAYER_CLASS_SILK ].y = parseBoardUnits( "module text height" );
NeedRIGHT(); NeedRIGHT();
break; break;
case T_defaults:
parseDefaults( designSettings );
break;
case T_pad_size: case T_pad_size:
{ {
wxSize sz; wxSize sz;
@ -1415,6 +1424,105 @@ void PCB_PARSER::parseSetup()
} }
void PCB_PARSER::parseDefaults( BOARD_DESIGN_SETTINGS& designSettings )
{
T token;
for( token = NextTok(); token != T_RIGHT; token = NextTok() )
{
if( token != T_LEFT )
Expecting( T_LEFT );
token = NextTok();
switch( token )
{
case T_edge_clearance:
designSettings.m_CopperEdgeClearance = parseBoardUnits( T_edge_clearance );
NeedRIGHT();
break;
case T_copper_line_width:
designSettings.m_LineThickness[ LAYER_CLASS_COPPER ] = parseBoardUnits( token );
NeedRIGHT();
break;
case T_copper_text_dims:
parseDefaultTextDims( designSettings, LAYER_CLASS_COPPER );
break;
case T_courtyard_line_width:
designSettings.m_LineThickness[ LAYER_CLASS_COURTYARD ] = parseBoardUnits( token );
NeedRIGHT();
break;
case T_edge_cuts_line_width:
designSettings.m_LineThickness[ LAYER_CLASS_EDGES ] = parseBoardUnits( token );
NeedRIGHT();
break;
case T_silk_line_width:
designSettings.m_LineThickness[ LAYER_CLASS_SILK ] = parseBoardUnits( token );
NeedRIGHT();
break;
case T_silk_text_dims:
parseDefaultTextDims( designSettings, LAYER_CLASS_SILK );
break;
case T_other_layers_line_width:
designSettings.m_LineThickness[ LAYER_CLASS_OTHERS ] = parseBoardUnits( token );
NeedRIGHT();
break;
case T_other_layers_text_dims:
parseDefaultTextDims( designSettings, LAYER_CLASS_OTHERS );
break;
default:
Unexpected( CurText() );
}
}
}
void PCB_PARSER::parseDefaultTextDims( BOARD_DESIGN_SETTINGS& aSettings, int aLayer )
{
T token;
for( token = NextTok(); token != T_RIGHT; token = NextTok() )
{
if( token == T_LEFT )
token = NextTok();
switch( token )
{
case T_size:
aSettings.m_TextSize[ aLayer ].x = parseBoardUnits( "default text size X" );
aSettings.m_TextSize[ aLayer ].y = parseBoardUnits( "default text size Y" );
NeedRIGHT();
break;
case T_thickness:
aSettings.m_TextThickness[ aLayer ] = parseBoardUnits( "default text width" );
NeedRIGHT();
break;
case T_italic:
aSettings.m_TextItalic[ aLayer ] = true;
break;
case T_keep_upright:
aSettings.m_TextUpright[ aLayer ] = true;
break;
default:
Expecting( "size, thickness, italic or keep_upright" );
}
}
}
void PCB_PARSER::parseNETINFO_ITEM() void PCB_PARSER::parseNETINFO_ITEM()
{ {
wxCHECK_RET( CurTok() == T_net, wxCHECK_RET( CurTok() == T_net,

3
pcbnew/pcb_parser.h
View File

@ -42,6 +42,7 @@
class BOARD; class BOARD;
class BOARD_ITEM; class BOARD_ITEM;
class D_PAD; class D_PAD;
class BOARD_DESIGN_SETTINGS;
class DIMENSION; class DIMENSION;
class DRAWSEGMENT; class DRAWSEGMENT;
class EDA_TEXT; class EDA_TEXT;
@ -121,6 +122,8 @@ class PCB_PARSER : public PCB_LEXER
void parseLayer( LAYER* aLayer ); void parseLayer( LAYER* aLayer );
void parseSetup(); void parseSetup();
void parseDefaults( BOARD_DESIGN_SETTINGS& aSettings );
void parseDefaultTextDims( BOARD_DESIGN_SETTINGS& aSettings, int aLayer );
void parseNETINFO_ITEM(); void parseNETINFO_ITEM();
void parseNETCLASS(); void parseNETCLASS();