diff --git a/pcbnew/drc/drc_engine.cpp b/pcbnew/drc/drc_engine.cpp
index 050fe63f32..a2d30de54f 100644
--- a/pcbnew/drc/drc_engine.cpp
+++ b/pcbnew/drc/drc_engine.cpp
@@ -100,10 +100,12 @@ void DRC_ENGINE::loadImplicitRules()
 
     DRC_CONSTRAINT widthConstraint( DRC_CONSTRAINT_TYPE_TRACK_WIDTH );
     widthConstraint.Value().SetMin( bds.m_TrackMinWidth );
+    widthConstraint.Value().SetOpt( bds.GetDefault()->GetTrackWidth() );
     rule->AddConstraint( widthConstraint );
 
     DRC_CONSTRAINT drillConstraint( DRC_CONSTRAINT_TYPE_HOLE_SIZE );
     drillConstraint.Value().SetMin( bds.m_MinThroughDrill );
+    drillConstraint.Value().SetOpt( bds.GetDefault()->GetViaDrill() );
     rule->AddConstraint( drillConstraint );
 
     DRC_CONSTRAINT annulusConstraint( DRC_CONSTRAINT_TYPE_ANNULAR_WIDTH );
@@ -112,6 +114,7 @@ void DRC_ENGINE::loadImplicitRules()
 
     DRC_CONSTRAINT diameterConstraint( DRC_CONSTRAINT_TYPE_VIA_DIAMETER );
     diameterConstraint.Value().SetMin( bds.m_ViasMinSize );
+    diameterConstraint.Value().SetOpt( bds.GetDefault()->GetViaDiameter() );
     rule->AddConstraint( diameterConstraint );
 
     DRC_CONSTRAINT edgeClearanceConstraint( DRC_CONSTRAINT_TYPE_EDGE_CLEARANCE );
@@ -134,6 +137,12 @@ void DRC_ENGINE::loadImplicitRules()
     silkToSilkClearanceConstraint.Value().SetMin( 0 );
     rule->AddConstraint( silkToSilkClearanceConstraint );
 
+    DRC_CONSTRAINT diffPairGapConstraint( DRC_CONSTRAINT_TYPE_DIFF_PAIR_GAP );
+    diffPairGapConstraint.Value().SetMin( bds.GetDefault()->GetClearance() );
+    diffPairGapConstraint.Value().SetOpt( bds.GetDefault()->GetClearance() );
+    rule->AddConstraint( diffPairGapConstraint );
+
+
     // 2) micro-via specific defaults (new DRC doesn't treat microvias in any special way)
 
     DRC_RULE* uViaRule = createImplicitRule( _( "board setup micro-via constraints" ));
@@ -142,10 +151,12 @@ void DRC_ENGINE::loadImplicitRules()
 
     DRC_CONSTRAINT uViaDrillConstraint( DRC_CONSTRAINT_TYPE_HOLE_SIZE );
     uViaDrillConstraint.Value().SetMin( bds.m_MicroViasMinDrill );
+    uViaDrillConstraint.Value().SetOpt( bds.GetDefault()->GetuViaDrill() );
     uViaRule->AddConstraint( uViaDrillConstraint );
 
     DRC_CONSTRAINT uViaDiameterConstraint( DRC_CONSTRAINT_TYPE_VIA_DIAMETER );
     uViaDiameterConstraint.Value().SetMin( bds.m_MicroViasMinSize );
+    uViaDiameterConstraint.Value().SetOpt( bds.GetDefault()->GetuViaDiameter() );
     uViaRule->AddConstraint( uViaDiameterConstraint );
 
     if( !bds.m_MicroViasAllowed )
diff --git a/pcbnew/drc/drc_engine.h b/pcbnew/drc/drc_engine.h
index 46363aa69a..8736be070c 100644
--- a/pcbnew/drc/drc_engine.h
+++ b/pcbnew/drc/drc_engine.h
@@ -177,6 +177,8 @@ public:
 
     DRC_TEST_PROVIDER* GetTestProvider( const wxString& name ) const;
 
+    static int IsNetADiffPair( BOARD* aBoard, int aNet, int& aNetP, int& aNetN );
+
 private:
     void addRule( DRC_RULE* rule )
     {