From 5f1976f3410ab9448b29794f25497d1b04e5185e Mon Sep 17 00:00:00 2001
From: Jeff Young <jeff@rokeby.ie>
Date: Fri, 25 Feb 2022 10:29:36 +0000
Subject: [PATCH] fixup! Better DRC checking when placing vias.

---
 pcbnew/tools/drawing_tool.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pcbnew/tools/drawing_tool.cpp b/pcbnew/tools/drawing_tool.cpp
index 5696b34388..84a704c041 100644
--- a/pcbnew/tools/drawing_tool.cpp
+++ b/pcbnew/tools/drawing_tool.cpp
@@ -2412,7 +2412,7 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent )
                 constraint = m_drcEngine->EvalRules( DISALLOW_CONSTRAINT, aVia, nullptr,
                                                      UNDEFINED_LAYER );
 
-                if( constraint.m_DisallowFlags && constraint.GetSeverity() != RPT_SEVERITY_IGNORE )
+                if( constraint.m_DisallowFlags )
                     return true;
 
                 return false;