From 5f8a0b0728e0d78152ca0cc5899a1ce0679467ad Mon Sep 17 00:00:00 2001
From: Jeff Young <jeff@rokeby.ie>
Date: Wed, 25 Oct 2023 16:06:26 +0100
Subject: [PATCH] Import a few more rules from Altium board files.

Fixes https://gitlab.com/kicad/code/kicad/-/issues/15585

(cherry picked from commit 6a2aeeeae2a4b0f9c9645f4c9fc638b6667e9eb9)
---
 pcbnew/plugins/altium/altium_parser_pcb.cpp | 21 ++++++++++++---
 pcbnew/plugins/altium/altium_parser_pcb.h   | 18 +++++++++++++
 pcbnew/plugins/altium/altium_pcb.cpp        | 29 +++++++++++++++++++++
 3 files changed, 65 insertions(+), 3 deletions(-)

diff --git a/pcbnew/plugins/altium/altium_parser_pcb.cpp b/pcbnew/plugins/altium/altium_parser_pcb.cpp
index 3b91d97ead..b36b4436df 100644
--- a/pcbnew/plugins/altium/altium_parser_pcb.cpp
+++ b/pcbnew/plugins/altium/altium_parser_pcb.cpp
@@ -531,15 +531,31 @@ ARULE6::ARULE6( ALTIUM_PARSER& aReader )
     else if( rulekind == wxT( "HoleSize" ) )
     {
         kind = ALTIUM_RULE_KIND::HOLE_SIZE;
+        minLimit = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "MINLIMIT" ), wxT( "1mil" ) );
+        maxLimit = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "MAXLIMIT" ), wxT( "150mil" ) );
     }
     else if( rulekind == wxT( "HoleToHoleClearance" ) )
     {
         kind = ALTIUM_RULE_KIND::HOLE_TO_HOLE_CLEARANCE;
+        clearanceGap = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "GAP" ), wxT( "10mil" ) );
+    }
+    else if( rulekind == wxT( "RoutingVias" ) )
+    {
+        kind = ALTIUM_RULE_KIND::ROUTING_VIAS;
+        width        = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "WIDTH" ), wxT( "20mil" ) );
+        minWidth     = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "MINWIDTH" ), wxT( "20mil" ) );
+        maxWidth     = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "MAXWIDTH" ), wxT( "50mil" ) );
+        holeWidth    = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "HOLEWIDTH" ), wxT( "10mil" ) );
+        minHoleWidth = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "MINHOLEWIDTH" ), wxT( "10mil" ) );
+        maxHoleWidth = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "MAXHOLEWIDTH" ), wxT( "28mil" ) );
     }
     else if( rulekind == wxT( "Width" ) )
     {
         kind = ALTIUM_RULE_KIND::WIDTH;
-    }
+        minLimit       = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "MINLIMIT" ), wxT( "6mil" ) );
+        maxLimit       = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "MAXLIMIT" ), wxT( "40mil" ) );
+        preferredWidth = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "PREFERREDWIDTH" ), wxT( "6mil" ) );
+}
     else if( rulekind == wxT( "PasteMaskExpansion" ) )
     {
         kind = ALTIUM_RULE_KIND::PASTE_MASK_EXPANSION;
@@ -548,8 +564,7 @@ ARULE6::ARULE6( ALTIUM_PARSER& aReader )
     else if( rulekind == wxT( "SolderMaskExpansion" ) )
     {
         kind = ALTIUM_RULE_KIND::SOLDER_MASK_EXPANSION;
-        soldermaskExpansion =
-                ALTIUM_PARSER::ReadKicadUnit( props, wxT( "EXPANSION" ), wxT( "4mil" ) );
+        soldermaskExpansion = ALTIUM_PARSER::ReadKicadUnit( props, wxT( "EXPANSION" ), wxT( "4mil" ) );
     }
     else if( rulekind == wxT( "PlaneClearance" ) )
     {
diff --git a/pcbnew/plugins/altium/altium_parser_pcb.h b/pcbnew/plugins/altium/altium_parser_pcb.h
index 4c9dfb40d3..53f39db5cc 100644
--- a/pcbnew/plugins/altium/altium_parser_pcb.h
+++ b/pcbnew/plugins/altium/altium_parser_pcb.h
@@ -108,6 +108,7 @@ enum class ALTIUM_RULE_KIND
     SOLDER_MASK_EXPANSION  = 8,
     PLANE_CLEARANCE        = 9,
     POLYGON_CONNECT        = 10,
+    ROUTING_VIAS           = 11
 };
 
 enum class ALTIUM_CONNECT_STYLE
@@ -499,8 +500,25 @@ struct ARULE6
     wxString scope2expr;
 
     // ALTIUM_RULE_KIND::CLEARANCE
+    // ALTIUM_RULE_KIND::HOLE_TO_HOLE_CLEARANCE
     int clearanceGap;
 
+    // ALTIUM_RULE_KIND::WIDTH
+    // ALTIUM_RULE_KIND::HOLE_SIZE
+    int minLimit;
+    int maxLimit;
+
+    // ALTIUM_RULE_KIND::WIDTH
+    int preferredWidth;
+
+    // ALTIUM_RULE_KIND::ROUTING_VIAS
+    int width;
+    int minWidth;
+    int maxWidth;
+    int holeWidth;
+    int minHoleWidth;
+    int maxHoleWidth;
+
     // ALTIUM_RULE_KIND::PLANE_CLEARANCE
     int planeclearanceClearance;
 
diff --git a/pcbnew/plugins/altium/altium_pcb.cpp b/pcbnew/plugins/altium/altium_pcb.cpp
index 0fb2a005db..6218e4051b 100644
--- a/pcbnew/plugins/altium/altium_pcb.cpp
+++ b/pcbnew/plugins/altium/altium_pcb.cpp
@@ -1901,6 +1901,35 @@ void ALTIUM_PCB::ParseRules6Data( const ALTIUM_COMPOUND_FILE&     aAltiumPcbFile
                 } );
     }
 
+    const ARULE6* clearanceRule = GetRuleDefault( ALTIUM_RULE_KIND::CLEARANCE );
+    const ARULE6* trackWidthRule = GetRuleDefault( ALTIUM_RULE_KIND::WIDTH );
+    const ARULE6* routingViasRule = GetRuleDefault( ALTIUM_RULE_KIND::ROUTING_VIAS );
+    const ARULE6* holeSizeRule = GetRuleDefault( ALTIUM_RULE_KIND::HOLE_SIZE );
+    const ARULE6* holeToHoleRule = GetRuleDefault( ALTIUM_RULE_KIND::HOLE_TO_HOLE_CLEARANCE );
+
+    if( clearanceRule )
+        m_board->GetDesignSettings().m_MinClearance = clearanceRule->clearanceGap;
+
+    if( trackWidthRule )
+    {
+        m_board->GetDesignSettings().m_TrackMinWidth = trackWidthRule->minLimit;
+        // TODO: construct a custom rule for preferredWidth and maxLimit values
+    }
+
+    if( routingViasRule )
+    {
+        m_board->GetDesignSettings().m_ViasMinSize = routingViasRule->minWidth;
+        m_board->GetDesignSettings().m_MinThroughDrill = routingViasRule->minHoleWidth;
+    }
+
+    if( holeSizeRule )
+    {
+        // TODO: construct a custom rule for minLimit / maxLimit values
+    }
+
+    if( holeToHoleRule )
+        m_board->GetDesignSettings().m_HoleToHoleMin = holeToHoleRule->clearanceGap;
+
     const ARULE6* soldermaskRule = GetRuleDefault( ALTIUM_RULE_KIND::SOLDER_MASK_EXPANSION );
     const ARULE6* pastemaskRule = GetRuleDefault( ALTIUM_RULE_KIND::PASTE_MASK_EXPANSION );