diff --git a/pcbnew/board_connected_item.cpp b/pcbnew/board_connected_item.cpp index 08fe69e3b3..e2a94eab86 100644 --- a/pcbnew/board_connected_item.cpp +++ b/pcbnew/board_connected_item.cpp @@ -86,8 +86,7 @@ int BOARD_CONNECTED_ITEM::GetOwnClearance( PCB_LAYER_ID aLayer, wxString* aSourc { BOARD_DESIGN_SETTINGS& bds = GetBoard()->GetDesignSettings(); - constraint = bds.m_DRCEngine->EvalRulesForItems( CLEARANCE_CONSTRAINT, this, nullptr, - aLayer ); + constraint = bds.m_DRCEngine->EvalRules( CLEARANCE_CONSTRAINT, this, nullptr, aLayer ); } if( constraint.Value().HasMin() ) diff --git a/pcbnew/drc/drc_engine.cpp b/pcbnew/drc/drc_engine.cpp index a66b790d32..8130222f51 100644 --- a/pcbnew/drc/drc_engine.cpp +++ b/pcbnew/drc/drc_engine.cpp @@ -709,9 +709,9 @@ void DRC_ENGINE::RunTests( EDA_UNITS aUnits, bool aReportAllTrackErrors, bool aT } -DRC_CONSTRAINT DRC_ENGINE::EvalRulesForItems( DRC_CONSTRAINT_T aConstraintId, - const BOARD_ITEM* a, const BOARD_ITEM* b, - PCB_LAYER_ID aLayer, REPORTER* aReporter ) +DRC_CONSTRAINT DRC_ENGINE::EvalRules( DRC_CONSTRAINT_T aConstraintId, const BOARD_ITEM* a, + const BOARD_ITEM* b, PCB_LAYER_ID aLayer, + REPORTER* aReporter ) { #define REPORT( s ) { if( aReporter ) { aReporter->Report( s ); } } #define UNITS aReporter ? aReporter->GetUnits() : EDA_UNITS::MILLIMETRES diff --git a/pcbnew/drc/drc_engine.h b/pcbnew/drc/drc_engine.h index 29b5e0b7a4..408347641e 100644 --- a/pcbnew/drc/drc_engine.h +++ b/pcbnew/drc/drc_engine.h @@ -74,8 +74,8 @@ std::function& aItem, wxPoint aPos )> DRC_ * PROGRESS_REPORTER and rule parse errors via a REPORTER, all set through various setter * calls. * - * Note that EvalRulesForItems() has yet another optional REPORTER for reporting resolution - * info to the user. + * Note that EvalRules() has yet another optional REPORTER for reporting resolution info to + * the user. */ class DRC_ENGINE { @@ -142,10 +142,9 @@ public: bool IsErrorLimitExceeded( int error_code ); - DRC_CONSTRAINT EvalRulesForItems( DRC_CONSTRAINT_T ruleID, const BOARD_ITEM* a, - const BOARD_ITEM* b = nullptr, - PCB_LAYER_ID aLayer = UNDEFINED_LAYER, - REPORTER* aReporter = nullptr ); + DRC_CONSTRAINT EvalRules( DRC_CONSTRAINT_T aConstraintId, const BOARD_ITEM* a, + const BOARD_ITEM* b, PCB_LAYER_ID aLayer, + REPORTER* aReporter = nullptr ); bool HasRulesForConstraintType( DRC_CONSTRAINT_T constraintID ); diff --git a/pcbnew/drc/drc_test_provider_annulus.cpp b/pcbnew/drc/drc_test_provider_annulus.cpp index f2f5dea009..53f94f676f 100644 --- a/pcbnew/drc/drc_test_provider_annulus.cpp +++ b/pcbnew/drc/drc_test_provider_annulus.cpp @@ -94,7 +94,9 @@ bool DRC_TEST_PROVIDER_ANNULUS::Run() if( !via ) return true; - auto constraint = m_drcEngine->EvalRulesForItems( ANNULAR_WIDTH_CONSTRAINT, via ); + // PADSTACKS TODO: once we have padstacks we'll need to run this per-layer.... + auto constraint = m_drcEngine->EvalRules( ANNULAR_WIDTH_CONSTRAINT, via, nullptr, + UNDEFINED_LAYER ); int annulus = ( via->GetWidth() - via->GetDrillValue() ) / 2; bool fail_min = false; bool fail_max = false; diff --git a/pcbnew/drc/drc_test_provider_copper_clearance.cpp b/pcbnew/drc/drc_test_provider_copper_clearance.cpp index e7e8648543..6dffa49163 100644 --- a/pcbnew/drc/drc_test_provider_copper_clearance.cpp +++ b/pcbnew/drc/drc_test_provider_copper_clearance.cpp @@ -254,7 +254,7 @@ bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackAgainstItem( TRACK* track, SHA if( testClearance ) { - constraint = m_drcEngine->EvalRulesForItems( CLEARANCE_CONSTRAINT, track, other, layer ); + constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, track, other, layer ); clearance = constraint.GetValue().Min(); } @@ -322,7 +322,8 @@ bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackAgainstItem( TRACK* track, SHA if( holeShape ) { - constraint = m_drcEngine->EvalRulesForItems( HOLE_CLEARANCE_CONSTRAINT, other, track ); + constraint = m_drcEngine->EvalRules( HOLE_CLEARANCE_CONSTRAINT, other, track, + track->GetLayer() ); clearance = constraint.GetValue().Min(); if( clearance >= 0 && trackShape->Collide( holeShape.get(), @@ -371,8 +372,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testItemAgainstZones( BOARD_ITEM* aItem if( aItem->GetBoundingBox().Intersects( zone->GetCachedBoundingBox() ) ) { - auto constraint = m_drcEngine->EvalRulesForItems( CLEARANCE_CONSTRAINT, aItem, zone, - aLayer ); + auto constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, aItem, zone, aLayer ); int clearance = constraint.GetValue().Min(); if( clearance < 0 ) @@ -558,8 +558,7 @@ bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadAgainstItem( PAD* pad, SHAPE* pa if( testHoles && pad->FlashLayer( layer ) && otherPad->GetDrillSize().x ) { - constraint = m_drcEngine->EvalRulesForItems( HOLE_CLEARANCE_CONSTRAINT, pad, - otherPad ); + constraint = m_drcEngine->EvalRules( HOLE_CLEARANCE_CONSTRAINT, pad, otherPad, layer ); clearance = constraint.GetValue().Min(); if( clearance >= 0 && padShape->Collide( otherPad->GetEffectiveHoleShape(), @@ -583,8 +582,7 @@ bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadAgainstItem( PAD* pad, SHAPE* pa if( testHoles && otherPad->FlashLayer( layer ) && pad->GetDrillSize().x ) { - constraint = m_drcEngine->EvalRulesForItems( HOLE_CLEARANCE_CONSTRAINT, pad, - otherPad ); + constraint = m_drcEngine->EvalRules( HOLE_CLEARANCE_CONSTRAINT, pad, otherPad, layer ); clearance = constraint.GetValue().Min(); if( clearance >= 0 && otherShape->Collide( pad->GetEffectiveHoleShape(), @@ -616,7 +614,7 @@ bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadAgainstItem( PAD* pad, SHAPE* pa if( testClearance ) { - constraint = m_drcEngine->EvalRulesForItems( CLEARANCE_CONSTRAINT, pad, other, layer ); + constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, pad, other, layer ); clearance = constraint.GetValue().Min(); if( clearance > 0 && padShape->Collide( otherShape.get(), @@ -768,8 +766,8 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZones() // Examine a candidate zone: compare zoneToTest to zoneRef // Get clearance used in zone to zone test. - auto constraint = m_drcEngine->EvalRulesForItems( CLEARANCE_CONSTRAINT, zoneRef, - zoneToTest ); + auto constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, zoneRef, zoneToTest, + layer ); int zone2zoneClearance = constraint.GetValue().Min(); // test for some corners of zoneRef inside zoneToTest diff --git a/pcbnew/drc/drc_test_provider_courtyard_clearance.cpp b/pcbnew/drc/drc_test_provider_courtyard_clearance.cpp index cfb5f50261..7feeab5580 100644 --- a/pcbnew/drc/drc_test_provider_courtyard_clearance.cpp +++ b/pcbnew/drc/drc_test_provider_courtyard_clearance.cpp @@ -166,8 +166,8 @@ void DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testCourtyardClearances() if( footprintFront.OutlineCount() > 0 && testFront.OutlineCount() > 0 && frontBBox.Intersects( testFront.BBoxFromCaches() ) ) { - constraint = m_drcEngine->EvalRulesForItems( COURTYARD_CLEARANCE_CONSTRAINT, - footprint, test, F_Cu ); + constraint = m_drcEngine->EvalRules( COURTYARD_CLEARANCE_CONSTRAINT, footprint, + test, F_Cu ); clearance = constraint.GetValue().Min(); if( clearance >= 0 && footprintFront.Collide( &testFront, clearance, &actual, &pos ) ) @@ -193,8 +193,8 @@ void DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testCourtyardClearances() if( footprintBack.OutlineCount() > 0 && testBack.OutlineCount() > 0 && backBBox.Intersects( testBack.BBoxFromCaches() ) ) { - constraint = m_drcEngine->EvalRulesForItems( COURTYARD_CLEARANCE_CONSTRAINT, - footprint, test, B_Cu ); + constraint = m_drcEngine->EvalRules( COURTYARD_CLEARANCE_CONSTRAINT, footprint, + test, B_Cu ); clearance = constraint.GetValue().Min(); if( clearance >= 0 && footprintBack.Collide( &testBack, clearance, &actual, &pos ) ) diff --git a/pcbnew/drc/drc_test_provider_diff_pair_coupling.cpp b/pcbnew/drc/drc_test_provider_diff_pair_coupling.cpp index b3f01fcba1..b336267bd7 100644 --- a/pcbnew/drc/drc_test_provider_diff_pair_coupling.cpp +++ b/pcbnew/drc/drc_test_provider_diff_pair_coupling.cpp @@ -296,9 +296,8 @@ bool test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run() for( int i = 0; i < 2; i++ ) { - auto constraint = m_drcEngine->EvalRulesForItems( constraintsToCheck[i], - item, nullptr, - item->GetLayer() ); + auto constraint = m_drcEngine->EvalRules( constraintsToCheck[ i ], item, + nullptr, item->GetLayer() ); if( constraint.IsNull() ) continue; diff --git a/pcbnew/drc/drc_test_provider_disallow.cpp b/pcbnew/drc/drc_test_provider_disallow.cpp index b845615c76..7666be78ad 100644 --- a/pcbnew/drc/drc_test_provider_disallow.cpp +++ b/pcbnew/drc/drc_test_provider_disallow.cpp @@ -76,7 +76,8 @@ bool DRC_TEST_PROVIDER_DISALLOW::Run() auto doCheckItem = [&]( BOARD_ITEM* item ) { - auto constraint = m_drcEngine->EvalRulesForItems( DISALLOW_CONSTRAINT, item ); + auto constraint = m_drcEngine->EvalRules( DISALLOW_CONSTRAINT, item, nullptr, + item->GetLayer() ); if( constraint.m_DisallowFlags ) { diff --git a/pcbnew/drc/drc_test_provider_edge_clearance.cpp b/pcbnew/drc/drc_test_provider_edge_clearance.cpp index f967e6e012..11429f5f93 100644 --- a/pcbnew/drc/drc_test_provider_edge_clearance.cpp +++ b/pcbnew/drc/drc_test_provider_edge_clearance.cpp @@ -85,8 +85,7 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::testAgainstEdge( BOARD_ITEM* item, SHAPE* { const std::shared_ptr& edgeShape = edge->GetEffectiveShape( Edge_Cuts ); - auto constraint = m_drcEngine->EvalRulesForItems( aConstraintType, edge, item ); - + auto constraint = m_drcEngine->EvalRules( aConstraintType, edge, item, item->GetLayer() ); int minClearance = constraint.GetValue().Min(); int actual; VECTOR2I pos; diff --git a/pcbnew/drc/drc_test_provider_hole_clearance.cpp b/pcbnew/drc/drc_test_provider_hole_clearance.cpp index 3bd1827779..3cd9d805fa 100644 --- a/pcbnew/drc/drc_test_provider_hole_clearance.cpp +++ b/pcbnew/drc/drc_test_provider_hole_clearance.cpp @@ -278,7 +278,8 @@ bool DRC_TEST_PROVIDER_HOLE_CLEARANCE::testHoleAgainstHole( BOARD_ITEM* aItem, S int actual = ( aHole->GetCenter() - otherHole->GetCenter() ).EuclideanNorm(); actual = std::max( 0, actual - aHole->GetRadius() - otherHole->GetRadius() ); - auto constraint = m_drcEngine->EvalRulesForItems( HOLE_TO_HOLE_CONSTRAINT, aItem, aOther ); + auto constraint = m_drcEngine->EvalRules( HOLE_TO_HOLE_CONSTRAINT, aItem, aOther, + UNDEFINED_LAYER /* holes pierce all layers */ ); int minClearance = constraint.GetValue().Min(); if( minClearance >= 0 && actual < minClearance ) diff --git a/pcbnew/drc/drc_test_provider_hole_size.cpp b/pcbnew/drc/drc_test_provider_hole_size.cpp index f204ab6bc0..aaf58a5803 100644 --- a/pcbnew/drc/drc_test_provider_hole_size.cpp +++ b/pcbnew/drc/drc_test_provider_hole_size.cpp @@ -129,7 +129,8 @@ void DRC_TEST_PROVIDER_HOLE_SIZE::checkPad( PAD* aPad ) if( holeMinor == 0 ) return; - auto constraint = m_drcEngine->EvalRulesForItems( HOLE_SIZE_CONSTRAINT, aPad ); + auto constraint = m_drcEngine->EvalRules( HOLE_SIZE_CONSTRAINT, aPad, nullptr, + UNDEFINED_LAYER /* holes are not layer-specific */ ); bool fail_min = false; bool fail_max = false; int constraintValue; @@ -193,7 +194,8 @@ void DRC_TEST_PROVIDER_HOLE_SIZE::checkVia( VIA* via, bool aExceedMicro, bool aE errorCode = DRCE_DRILL_OUT_OF_RANGE; } - auto constraint = m_drcEngine->EvalRulesForItems( HOLE_SIZE_CONSTRAINT, via ); + auto constraint = m_drcEngine->EvalRules( HOLE_SIZE_CONSTRAINT, via, nullptr, + UNDEFINED_LAYER /* holes are not layer-specific */ ); bool fail_min = false; bool fail_max = false; int constraintValue; diff --git a/pcbnew/drc/drc_test_provider_matched_length.cpp b/pcbnew/drc/drc_test_provider_matched_length.cpp index 05058b9456..24b606de0e 100644 --- a/pcbnew/drc/drc_test_provider_matched_length.cpp +++ b/pcbnew/drc/drc_test_provider_matched_length.cpp @@ -243,8 +243,8 @@ bool DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal( bool aDelayReportMode ) for( int i = 0; i < 3; i++ ) { - auto constraint = m_drcEngine->EvalRulesForItems( constraintsToCheck[i], item, - nullptr, item->GetLayer() ); + auto constraint = m_drcEngine->EvalRules( constraintsToCheck[i], item, nullptr, + item->GetLayer() ); if( constraint.IsNull() ) continue; diff --git a/pcbnew/drc/drc_test_provider_silk_clearance.cpp b/pcbnew/drc/drc_test_provider_silk_clearance.cpp index a04dbda694..3dc18c79dc 100644 --- a/pcbnew/drc/drc_test_provider_silk_clearance.cpp +++ b/pcbnew/drc/drc_test_provider_silk_clearance.cpp @@ -143,10 +143,9 @@ bool DRC_TEST_PROVIDER_SILK_CLEARANCE::Run() if( isInvisibleText( aRefItem->parent ) || isInvisibleText( aTestItem->parent ) ) return true; - auto constraint = m_drcEngine->EvalRulesForItems( SILK_CLEARANCE_CONSTRAINT, - aRefItem->parent, - aTestItem->parent, - aLayers.second ); + auto constraint = m_drcEngine->EvalRules( SILK_CLEARANCE_CONSTRAINT, + aRefItem->parent, aTestItem->parent, + aLayers.second ); if( constraint.IsNull() ) return true; diff --git a/pcbnew/drc/drc_test_provider_silk_to_mask.cpp b/pcbnew/drc/drc_test_provider_silk_to_mask.cpp index 499042d259..a885640fd3 100644 --- a/pcbnew/drc/drc_test_provider_silk_to_mask.cpp +++ b/pcbnew/drc/drc_test_provider_silk_to_mask.cpp @@ -128,9 +128,9 @@ bool DRC_TEST_PROVIDER_SILK_TO_MASK::Run() if( isInvisibleText( aTestItem->parent ) ) return true; - auto constraint = m_drcEngine->EvalRulesForItems( SILK_CLEARANCE_CONSTRAINT, - aRefItem->parent, - aTestItem->parent ); + auto constraint = m_drcEngine->EvalRules( SILK_CLEARANCE_CONSTRAINT, + aRefItem->parent, aTestItem->parent, + aLayers.first ); int minClearance = constraint.GetValue().Min(); diff --git a/pcbnew/drc/drc_test_provider_track_width.cpp b/pcbnew/drc/drc_test_provider_track_width.cpp index bddcd21baf..7bb1c90ec5 100644 --- a/pcbnew/drc/drc_test_provider_track_width.cpp +++ b/pcbnew/drc/drc_test_provider_track_width.cpp @@ -100,7 +100,8 @@ bool DRC_TEST_PROVIDER_TRACK_WIDTH::Run() return true; } - auto constraint = m_drcEngine->EvalRulesForItems( TRACK_WIDTH_CONSTRAINT, item ); + auto constraint = m_drcEngine->EvalRules( TRACK_WIDTH_CONSTRAINT, item, nullptr, + item->GetLayer() ); bool fail_min = false; bool fail_max = false; int constraintWidth; diff --git a/pcbnew/drc/drc_test_provider_via_diameter.cpp b/pcbnew/drc/drc_test_provider_via_diameter.cpp index 760bb0858e..9f84d98503 100644 --- a/pcbnew/drc/drc_test_provider_via_diameter.cpp +++ b/pcbnew/drc/drc_test_provider_via_diameter.cpp @@ -87,7 +87,9 @@ bool DRC_TEST_PROVIDER_VIA_DIAMETER::Run() if( !via ) return true; - auto constraint = m_drcEngine->EvalRulesForItems( VIA_DIAMETER_CONSTRAINT, item ); + // TODO: once we have padstacks this will need to run per-layer... + auto constraint = m_drcEngine->EvalRules( VIA_DIAMETER_CONSTRAINT, item, nullptr, + UNDEFINED_LAYER ); bool fail_min = false; bool fail_max = false; int constraintDiameter = 0; diff --git a/pcbnew/router/pns_kicad_iface.cpp b/pcbnew/router/pns_kicad_iface.cpp index 9944d7bf22..329d762d72 100644 --- a/pcbnew/router/pns_kicad_iface.cpp +++ b/pcbnew/router/pns_kicad_iface.cpp @@ -244,10 +244,7 @@ bool PNS_PCBNEW_RULE_RESOLVER::QueryConstraint( PNS::CONSTRAINT_TYPE aType, } if( parentA ) - { - hostConstraint = drcEngine->EvalRulesForItems( hostType, parentA, parentB, - (PCB_LAYER_ID) aLayer ); - } + hostConstraint = drcEngine->EvalRules( hostType, parentA, parentB, (PCB_LAYER_ID) aLayer ); if( hostConstraint.IsNull() ) return false; diff --git a/pcbnew/router/router_tool.cpp b/pcbnew/router/router_tool.cpp index 0c7c9b9a1a..da7752727e 100644 --- a/pcbnew/router/router_tool.cpp +++ b/pcbnew/router/router_tool.cpp @@ -909,14 +909,14 @@ int ROUTER_TOOL::handleLayerSwitch( const TOOL_EVENT& aEvent, bool aForceVia ) DRC_CONSTRAINT constraint; - constraint = bds.m_DRCEngine->EvalRulesForItems( VIA_DIAMETER_CONSTRAINT, &dummyVia, - nullptr, currentLayer ); + constraint = bds.m_DRCEngine->EvalRules( VIA_DIAMETER_CONSTRAINT, &dummyVia, nullptr, + currentLayer ); if( !constraint.IsNull() ) sizes.SetViaDiameter( constraint.m_Value.Opt() ); - constraint = bds.m_DRCEngine->EvalRulesForItems( HOLE_SIZE_CONSTRAINT, &dummyVia, nullptr, - currentLayer ); + constraint = bds.m_DRCEngine->EvalRules( HOLE_SIZE_CONSTRAINT, &dummyVia, nullptr, + currentLayer ); if( !constraint.IsNull() ) sizes.SetViaDrill( constraint.m_Value.Opt() ); diff --git a/pcbnew/tools/board_inspection_tool.cpp b/pcbnew/tools/board_inspection_tool.cpp index 5ac6c41e5e..39a8821b74 100644 --- a/pcbnew/tools/board_inspection_tool.cpp +++ b/pcbnew/tools/board_inspection_tool.cpp @@ -243,7 +243,7 @@ void BOARD_INSPECTION_TOOL::reportClearance( DRC_CONSTRAINT_T aClearanceType, PC footprint->BuildPolyCourtyards(); } - auto constraint = drcEngine.EvalRulesForItems( aClearanceType, aA, aB, aLayer, r ); + auto constraint = drcEngine.EvalRules( aClearanceType, aA, aB, aLayer, r ); int clearance = constraint.m_Value.Min(); wxString clearanceStr = StringFromValue( r->GetUnits(), clearance, true ); @@ -527,8 +527,8 @@ int BOARD_INSPECTION_TOOL::InspectConstraints( const TOOL_EVENT& aEvent ) } else { - auto constraint = drcEngine.EvalRulesForItems( TRACK_WIDTH_CONSTRAINT, item, nullptr, - UNDEFINED_LAYER, r ); + auto constraint = drcEngine.EvalRules( TRACK_WIDTH_CONSTRAINT, item, nullptr, + item->GetLayer(), r ); wxString min = _( "undefined" ); wxString max = _( "undefined" ); @@ -564,8 +564,9 @@ int BOARD_INSPECTION_TOOL::InspectConstraints( const TOOL_EVENT& aEvent ) } else { - auto constraint = drcEngine.EvalRulesForItems( VIA_DIAMETER_CONSTRAINT, item, nullptr, - UNDEFINED_LAYER, r ); + // PADSTACKS TODO: once we have padstacks we'll need to run this per-layer.... + auto constraint = drcEngine.EvalRules( VIA_DIAMETER_CONSTRAINT, item, nullptr, + UNDEFINED_LAYER, r ); wxString min = _( "undefined" ); wxString max = _( "undefined" ); @@ -598,8 +599,9 @@ int BOARD_INSPECTION_TOOL::InspectConstraints( const TOOL_EVENT& aEvent ) } else { - auto constraint = drcEngine.EvalRulesForItems( ANNULAR_WIDTH_CONSTRAINT, item, nullptr, - UNDEFINED_LAYER, r ); + // PADSTACKS TODO: once we have padstacks we'll need to run this per-layer.... + auto constraint = drcEngine.EvalRules( ANNULAR_WIDTH_CONSTRAINT, item, nullptr, + UNDEFINED_LAYER, r ); wxString min = _( "undefined" ); wxString max = _( "undefined" ); @@ -636,8 +638,9 @@ int BOARD_INSPECTION_TOOL::InspectConstraints( const TOOL_EVENT& aEvent ) } else { - auto constraint = drcEngine.EvalRulesForItems( HOLE_SIZE_CONSTRAINT, item, nullptr, - UNDEFINED_LAYER, r ); + // PADSTACKS TODO: once we have padstacks we'll need to run this per-layer.... + auto constraint = drcEngine.EvalRules( HOLE_SIZE_CONSTRAINT, item, nullptr, + UNDEFINED_LAYER, r ); wxString min = _( "undefined" ); @@ -672,8 +675,8 @@ int BOARD_INSPECTION_TOOL::InspectConstraints( const TOOL_EVENT& aEvent ) + " " + _( "Run DRC for a full analysis." ) + "" ); } - auto constraint = drcEngine.EvalRulesForItems( DISALLOW_CONSTRAINT, item, nullptr, - UNDEFINED_LAYER, r ); + auto constraint = drcEngine.EvalRules( DISALLOW_CONSTRAINT, item, nullptr, item->GetLayer(), + r ); r->Report( "" ); diff --git a/pcbnew/tools/drawing_tool.cpp b/pcbnew/tools/drawing_tool.cpp index e34f776bc3..61c004eb04 100644 --- a/pcbnew/tools/drawing_tool.cpp +++ b/pcbnew/tools/drawing_tool.cpp @@ -2172,8 +2172,8 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent ) for( PCB_LAYER_ID layer : aOther->GetLayerSet().Seq() ) { - DRC_CONSTRAINT constraint = m_drcEngine->EvalRulesForItems( CLEARANCE_CONSTRAINT, - aVia, aOther, layer ); + DRC_CONSTRAINT constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, aVia, + aOther, layer ); int clearance = constraint.GetValue().Min(); if( clearance >= 0 ) diff --git a/pcbnew/track.cpp b/pcbnew/track.cpp index 89c1792578..c9f9d0607b 100644 --- a/pcbnew/track.cpp +++ b/pcbnew/track.cpp @@ -122,8 +122,7 @@ void TRACK::GetWidthConstraints( int* aMin, int* aMax, wxString* aSource ) const { BOARD_DESIGN_SETTINGS& bds = GetBoard()->GetDesignSettings(); - constraint = bds.m_DRCEngine->EvalRulesForItems( TRACK_WIDTH_CONSTRAINT, this, nullptr, - GetLayer() ); + constraint = bds.m_DRCEngine->EvalRules( TRACK_WIDTH_CONSTRAINT, this, nullptr, GetLayer() ); } if( constraint.Value().HasMin() || constraint.Value().HasMax() ) @@ -156,8 +155,7 @@ int VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const { BOARD_DESIGN_SETTINGS& bds = GetBoard()->GetDesignSettings(); - constraint = bds.m_DRCEngine->EvalRulesForItems( ANNULAR_WIDTH_CONSTRAINT, this, nullptr, - aLayer ); + constraint = bds.m_DRCEngine->EvalRules( ANNULAR_WIDTH_CONSTRAINT, this, nullptr, aLayer ); } if( constraint.Value().HasMin() ) diff --git a/pcbnew/zone.cpp b/pcbnew/zone.cpp index a8c5618131..63d62a815c 100644 --- a/pcbnew/zone.cpp +++ b/pcbnew/zone.cpp @@ -1188,8 +1188,8 @@ bool ZONE::BuildSmoothedPoly( SHAPE_POLY_SET& aSmoothedPoly, PCB_LAYER_ID aLayer { BOARD_DESIGN_SETTINGS& bds = board->GetDesignSettings(); - DRC_CONSTRAINT c = bds.m_DRCEngine->EvalRulesForItems( EDGE_CLEARANCE_CONSTRAINT, this, - nullptr, UNDEFINED_LAYER ); + DRC_CONSTRAINT c = bds.m_DRCEngine->EvalRules( EDGE_CLEARANCE_CONSTRAINT, this, nullptr, + aLayer ); edgeClearance = c.Value().Min(); maxError = bds.m_MaxError; keepExternalFillets = bds.m_ZoneKeepExternalFillets; diff --git a/pcbnew/zone_filler.cpp b/pcbnew/zone_filler.cpp index 03b3b95933..dd6dab207f 100644 --- a/pcbnew/zone_filler.cpp +++ b/pcbnew/zone_filler.cpp @@ -675,7 +675,7 @@ void ZONE_FILLER::buildCopperItemClearances( const ZONE* aZone, PCB_LAYER_ID aLa [&bds]( DRC_CONSTRAINT_T aConstraint, const BOARD_ITEM* a, const BOARD_ITEM* b, PCB_LAYER_ID aEvalLayer ) -> int { - auto c = bds.m_DRCEngine->EvalRulesForItems( aConstraint, a, b, aEvalLayer ); + auto c = bds.m_DRCEngine->EvalRules( aConstraint, a, b, aEvalLayer ); return c.Value().Min(); };