From 6b4c366cb820de63a2bc8dbedb352aa067f230f9 Mon Sep 17 00:00:00 2001
From: Seth Hillbrand <seth@kipro-pcb.com>
Date: Tue, 7 Mar 2023 11:07:22 -0800
Subject: [PATCH] Cleanup DRC check for via layers

Vias should only be placed on the layers through which they pass.  if
they pass through front or back copper, then they also pass through the
tech layers on that side

This is an update to 9d3f4bef6a00231e031c6ce1e2f6d4e21e42aa2e
---
 .../drc_test_provider_physical_clearance.cpp  | 26 ++++++++++++-------
 1 file changed, 17 insertions(+), 9 deletions(-)

diff --git a/pcbnew/drc/drc_test_provider_physical_clearance.cpp b/pcbnew/drc/drc_test_provider_physical_clearance.cpp
index 902925ec7e..2f94611ade 100644
--- a/pcbnew/drc/drc_test_provider_physical_clearance.cpp
+++ b/pcbnew/drc/drc_test_provider_physical_clearance.cpp
@@ -145,7 +145,14 @@ bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::Run()
                 // Special-case holes and edge-cuts which pierce all physical layers
                 if( item->HasHole() )
                 {
-                    layers |= LSET::PhysicalLayersMask() | courtyards;
+                    if( layers.Contains( F_Cu ) )
+                        layers |= LSET::FrontBoardTechMask().set( F_CrtYd );
+
+                    if( layers.Contains( B_Cu ) )
+                        layers |= LSET::BackBoardTechMask().set( B_CrtYd );
+
+                    if( layers.Contains( F_Cu ) && layers.Contains( B_Cu ) )
+                        layers |= LSET::AllCuMask();
                 }
                 else if( item->Type() == PCB_FOOTPRINT_T )
                 {
@@ -637,10 +644,11 @@ int DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* aItem
 
         if( aItem->Type() == PCB_VIA_T )
         {
-            if( aItem->GetLayerSet().Contains( aLayer ) )
-                itemHoleShape = aItem->GetEffectiveHoleShape();
-            else
-                return violations;
+
+            wxCHECK_MSG( aItem->GetLayerSet().Contains( aLayer ), violations,
+                    wxT( "Bug!  Vias should only be checked for layers on which they exist" ) );
+
+            itemHoleShape = aItem->GetEffectiveHoleShape();
         }
         else if( aItem->HasHole() )
         {
@@ -649,10 +657,10 @@ int DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* aItem
 
         if( other->Type() == PCB_VIA_T )
         {
-            if( other->GetLayerSet().Contains( aLayer ) )
-                otherHoleShape = other->GetEffectiveHoleShape();
-            else
-                return violations;
+            wxCHECK_MSG( other->GetLayerSet().Contains( aLayer ), violations,
+                    wxT( "Bug!  Vias should only be checked for layers on which they exist" ) );
+
+            otherHoleShape = other->GetEffectiveHoleShape();
         }
         else if( other->HasHole() )
         {