diff --git a/common/drc_rules.keywords b/common/drc_rules.keywords
index 49e8585474..5a66370f4c 100644
--- a/common/drc_rules.keywords
+++ b/common/drc_rules.keywords
@@ -1,4 +1,4 @@
-annulus_width
+annular_width
 board_edge
 buried_via
 clearance
diff --git a/common/widgets/progress_reporter.cpp b/common/widgets/progress_reporter.cpp
index 1925101b90..bb3473fa14 100644
--- a/common/widgets/progress_reporter.cpp
+++ b/common/widgets/progress_reporter.cpp
@@ -30,7 +30,7 @@ PROGRESS_REPORTER::PROGRESS_REPORTER( int aNumPhases ) :
     m_phase( 0 ),
     m_numPhases( aNumPhases ),
     m_progress( 0 ),
-    m_maxProgress( 1 ),
+    m_maxProgress( 1000 ),
     m_cancelled( false )
 {
 }
@@ -71,8 +71,8 @@ void PROGRESS_REPORTER::SetMaxProgress( int aMaxProgress )
 
 void PROGRESS_REPORTER::SetCurrentProgress( double aProgress )
 {
-    m_maxProgress.store( 10000 );
-    m_progress.store( (int) (aProgress * 10000.0) );
+    m_maxProgress.store( 1000 );
+    m_progress.store( (int) (aProgress * 1000.0) );
 }
 
 
diff --git a/pcbnew/board_design_settings.cpp b/pcbnew/board_design_settings.cpp
index 15e2920eb5..c8d308c5b4 100644
--- a/pcbnew/board_design_settings.cpp
+++ b/pcbnew/board_design_settings.cpp
@@ -201,7 +201,7 @@ BOARD_DESIGN_SETTINGS::BOARD_DESIGN_SETTINGS( JSON_SETTINGS* aParent, const std:
             Millimeter2iu( DEFAULT_TRACKMINWIDTH ), Millimeter2iu( 0.01 ), Millimeter2iu( 25.0 ),
             MM_PER_IU ) );
 
-    m_params.emplace_back( new PARAM_SCALED<int>( "rules.min_via_annulus", &m_ViasMinAnnulus,
+    m_params.emplace_back( new PARAM_SCALED<int>( "rules.min_via_annular_width", &m_ViasMinAnnulus,
             Millimeter2iu( DEFAULT_VIASMINSIZE ), Millimeter2iu( 0.01 ), Millimeter2iu( 25.0 ),
             MM_PER_IU ) );
 
diff --git a/pcbnew/class_track.cpp b/pcbnew/class_track.cpp
index 437cc2746b..2f2c0b4bfe 100644
--- a/pcbnew/class_track.cpp
+++ b/pcbnew/class_track.cpp
@@ -140,7 +140,7 @@ int VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const
     if( !IsPadOnLayer( aLayer ) )
     {
         if( aSource )
-            *aSource = _( "removed annulus" );
+            *aSource = _( "removed annular ring" );
 
         return 0;
     }
@@ -151,7 +151,7 @@ int VIA::GetMinAnnulus( PCB_LAYER_ID aLayer, wxString* aSource ) const
     {
         BOARD_DESIGN_SETTINGS& bds = GetBoard()->GetDesignSettings();
 
-        constraint = bds.m_DRCEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_ANNULUS_WIDTH, this,
+        constraint = bds.m_DRCEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_ANNULAR_WIDTH, this,
                                                          nullptr, aLayer );
     }
 
@@ -707,7 +707,7 @@ void VIA::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>&
 
     int minAnnulus = GetMinAnnulus( GetLayer(), &source );
 
-    msg.Printf( _( "Min Annulus: %s" ), MessageTextFromValue( units, minAnnulus, true ) );
+    msg.Printf( _( "Min Annular Width: %s" ), MessageTextFromValue( units, minAnnulus, true ) );
     msg2.Printf( _( "(from %s)" ), source );
     aList.emplace_back( msg, msg2, BLACK );
 }
diff --git a/pcbnew/connectivity/connectivity_algo.cpp b/pcbnew/connectivity/connectivity_algo.cpp
index d8c031d625..f20b22808a 100644
--- a/pcbnew/connectivity/connectivity_algo.cpp
+++ b/pcbnew/connectivity/connectivity_algo.cpp
@@ -392,18 +392,49 @@ const CN_CONNECTIVITY_ALGO::CLUSTERS CN_CONNECTIVITY_ALGO::SearchClusters( CLUST
 }
 
 
-void CN_CONNECTIVITY_ALGO::Build( BOARD* aBoard )
+void reportProgress( PROGRESS_REPORTER* aReporter, int aCount, int aSize, int aDelta )
 {
+    if( aReporter && ( ( aCount % aDelta ) == 0 || aCount == aSize -  1 ) )
+    {
+        aReporter->SetCurrentProgress( (double) aCount / (double) aSize );
+        aReporter->KeepRefreshing( false );
+    }
+}
+
+
+void CN_CONNECTIVITY_ALGO::Build( BOARD* aBoard, PROGRESS_REPORTER* aReporter )
+{
+    const int delta = 100;  // Number of additions between 2 calls to the progress bar
+    int ii = 0;
+    int size = 0;
+
+    size += aBoard->Zones().size();
+    size += aBoard->Tracks().size();
+
+    for( MODULE* mod : aBoard->Modules() )
+        size += mod->Pads().size();
+
+    size *= 2;      // Our caller us gets the other half of the progress bar
+
     for( ZONE_CONTAINER* zone : aBoard->Zones() )
+    {
         Add( zone );
+        reportProgress( aReporter, ii++, size, delta );
+    }
 
     for( TRACK* tv : aBoard->Tracks() )
+    {
         Add( tv );
+        reportProgress( aReporter, ii++, size, delta );
+    }
 
     for( MODULE* mod : aBoard->Modules() )
     {
         for( D_PAD* pad : mod->Pads() )
+        {
             Add( pad );
+            reportProgress( aReporter, ii++, size, delta );
+        }
     }
 }
 
diff --git a/pcbnew/connectivity/connectivity_algo.h b/pcbnew/connectivity/connectivity_algo.h
index 38041194d2..46b0a52517 100644
--- a/pcbnew/connectivity/connectivity_algo.h
+++ b/pcbnew/connectivity/connectivity_algo.h
@@ -224,7 +224,7 @@ public:
         return m_dirtyNets.size();
     }
 
-    void    Build( BOARD* aBoard );
+    void    Build( BOARD* aBoard, PROGRESS_REPORTER* aReporter = nullptr );
     void    Build( const std::vector<BOARD_ITEM*>& aItems );
 
     void Clear();
diff --git a/pcbnew/connectivity/connectivity_data.cpp b/pcbnew/connectivity/connectivity_data.cpp
index 8a6b054d2e..5266553942 100644
--- a/pcbnew/connectivity/connectivity_data.cpp
+++ b/pcbnew/connectivity/connectivity_data.cpp
@@ -78,10 +78,10 @@ bool CONNECTIVITY_DATA::Update( BOARD_ITEM* aItem )
 }
 
 
-void CONNECTIVITY_DATA::Build( BOARD* aBoard )
+void CONNECTIVITY_DATA::Build( BOARD* aBoard, PROGRESS_REPORTER* aReporter )
 {
     m_connAlgo.reset( new CN_CONNECTIVITY_ALGO );
-    m_connAlgo->Build( aBoard );
+    m_connAlgo->Build( aBoard, aReporter );
 
     m_netclassMap.clear();
 
@@ -525,7 +525,7 @@ unsigned int CONNECTIVITY_DATA::GetNodeCount( int aNet ) const
 
     if( aNet < 0 )      // Node count for all nets
     {
-        for( const auto& net : m_nets )
+        for( const RN_NET* net : m_nets )
             sum += net->GetNodeCount();
     }
     else if( aNet < (int) m_nets.size() )
@@ -541,17 +541,15 @@ unsigned int CONNECTIVITY_DATA::GetPadCount( int aNet ) const
 {
     int n = 0;
 
-    for( auto&& pad : m_connAlgo->ItemList() )
+    for( CN_ITEM* pad : m_connAlgo->ItemList() )
     {
         if( !pad->Valid() || pad->Parent()->Type() != PCB_PAD_T)
             continue;
 
-        auto dpad = static_cast<D_PAD*>( pad->Parent() );
+        D_PAD* dpad = static_cast<D_PAD*>( pad->Parent() );
 
         if( aNet < 0 || aNet == dpad->GetNetCode() )
-        {
             n++;
-        }
     }
 
     return n;
@@ -560,14 +558,12 @@ unsigned int CONNECTIVITY_DATA::GetPadCount( int aNet ) const
 
 void CONNECTIVITY_DATA::GetUnconnectedEdges( std::vector<CN_EDGE>& aEdges) const
 {
-    for( auto rnNet : m_nets )
+    for( const RN_NET* rnNet : m_nets )
     {
         if( rnNet )
         {
-            for( const auto& edge : rnNet->GetEdges() )
-            {
+            for( const CN_EDGE& edge : rnNet->GetEdges() )
                 aEdges.push_back( edge );
-            }
         }
     }
 }
diff --git a/pcbnew/connectivity/connectivity_data.h b/pcbnew/connectivity/connectivity_data.h
index faa0f3bab5..fd6478e93d 100644
--- a/pcbnew/connectivity/connectivity_data.h
+++ b/pcbnew/connectivity/connectivity_data.h
@@ -93,7 +93,7 @@ public:
      * Function Build()
      * Builds the connectivity database for the board aBoard.
      */
-    void Build( BOARD* aBoard );
+    void Build( BOARD* aBoard, PROGRESS_REPORTER* aReporter = nullptr );
 
     /**
      * Function Build()
diff --git a/pcbnew/dialogs/dialog_drc.cpp b/pcbnew/dialogs/dialog_drc.cpp
index b5d9c59e94..5d8d0d2c59 100644
--- a/pcbnew/dialogs/dialog_drc.cpp
+++ b/pcbnew/dialogs/dialog_drc.cpp
@@ -159,9 +159,10 @@ void DIALOG_DRC::initValues()
 
 bool DIALOG_DRC::updateUI()
 {
-    int cur = std::max( 0, std::min( m_progress.load(), 10000 ) );
+    double cur = (double) m_progress.load() / m_maxProgress;
+    cur = std::max( 0.0, std::min( cur, 1.0 ) );
 
-    m_gauge->SetValue( cur );
+    m_gauge->SetValue( KiROUND( cur * 1000.0 ) );
     wxSafeYield( this );
 
     return !m_cancelled;
@@ -171,6 +172,7 @@ bool DIALOG_DRC::updateUI()
 void DIALOG_DRC::AdvancePhase( const wxString& aMessage )
 {
     PROGRESS_REPORTER::AdvancePhase( aMessage );
+    SetCurrentProgress( 0.0 );
 
     m_Messages->AppendText( aMessage + "\n" );
 }
diff --git a/pcbnew/dialogs/dialog_drc_base.cpp b/pcbnew/dialogs/dialog_drc_base.cpp
index 20a0b5feff..e65a32ad31 100644
--- a/pcbnew/dialogs/dialog_drc_base.cpp
+++ b/pcbnew/dialogs/dialog_drc_base.cpp
@@ -66,7 +66,7 @@ DIALOG_DRC_BASE::DIALOG_DRC_BASE( wxWindow* parent, wxWindowID id, const wxStrin
 	wxBoxSizer* bGaugeMargins;
 	bGaugeMargins = new wxBoxSizer( wxVERTICAL );
 
-	m_gauge = new wxGauge( m_panelMessages, wxID_ANY, 10000, wxDefaultPosition, wxDefaultSize, wxGA_HORIZONTAL );
+	m_gauge = new wxGauge( m_panelMessages, wxID_ANY, 1000, wxDefaultPosition, wxDefaultSize, wxGA_HORIZONTAL );
 	m_gauge->SetValue( 0 );
 	bGaugeMargins->Add( m_gauge, 0, wxALL|wxEXPAND, 5 );
 
diff --git a/pcbnew/dialogs/dialog_drc_base.fbp b/pcbnew/dialogs/dialog_drc_base.fbp
index a4a989090c..0e0e87f9c8 100644
--- a/pcbnew/dialogs/dialog_drc_base.fbp
+++ b/pcbnew/dialogs/dialog_drc_base.fbp
@@ -699,7 +699,7 @@
                                                                         <property name="permission">protected</property>
                                                                         <property name="pin_button">1</property>
                                                                         <property name="pos"></property>
-                                                                        <property name="range">10000</property>
+                                                                        <property name="range">1000</property>
                                                                         <property name="resize">Resizable</property>
                                                                         <property name="show">1</property>
                                                                         <property name="size"></property>
diff --git a/pcbnew/dialogs/panel_setup_feature_constraints_base.cpp b/pcbnew/dialogs/panel_setup_feature_constraints_base.cpp
index 330613ee00..106f5b53d5 100644
--- a/pcbnew/dialogs/panel_setup_feature_constraints_base.cpp
+++ b/pcbnew/dialogs/panel_setup_feature_constraints_base.cpp
@@ -211,7 +211,7 @@ PANEL_SETUP_FEATURE_CONSTRAINTS_BASE::PANEL_SETUP_FEATURE_CONSTRAINTS_BASE( wxWi
 	m_bitmapMinViaAnnulus = new wxStaticBitmap( this, wxID_ANY, wxNullBitmap, wxDefaultPosition, wxDefaultSize, 0 );
 	fgFeatureConstraints->Add( m_bitmapMinViaAnnulus, 0, wxALL|wxALIGN_CENTER_HORIZONTAL, 5 );
 
-	m_ViaMinAnnulusTitle = new wxStaticText( this, wxID_ANY, _("Minimum via annulus:"), wxDefaultPosition, wxDefaultSize, 0 );
+	m_ViaMinAnnulusTitle = new wxStaticText( this, wxID_ANY, _("Minimum annular width:"), wxDefaultPosition, wxDefaultSize, 0 );
 	m_ViaMinAnnulusTitle->Wrap( -1 );
 	fgFeatureConstraints->Add( m_ViaMinAnnulusTitle, 0, wxALIGN_CENTER_VERTICAL, 5 );
 
diff --git a/pcbnew/dialogs/panel_setup_feature_constraints_base.fbp b/pcbnew/dialogs/panel_setup_feature_constraints_base.fbp
index fd88335024..dd0a848ee3 100644
--- a/pcbnew/dialogs/panel_setup_feature_constraints_base.fbp
+++ b/pcbnew/dialogs/panel_setup_feature_constraints_base.fbp
@@ -2049,7 +2049,7 @@
                                         <property name="gripper">0</property>
                                         <property name="hidden">0</property>
                                         <property name="id">wxID_ANY</property>
-                                        <property name="label">Minimum via annulus:</property>
+                                        <property name="label">Minimum annular width:</property>
                                         <property name="markup">0</property>
                                         <property name="max_size"></property>
                                         <property name="maximize_button">0</property>
diff --git a/pcbnew/drc/drc_engine.cpp b/pcbnew/drc/drc_engine.cpp
index 3d2c51271e..e82cf4b958 100644
--- a/pcbnew/drc/drc_engine.cpp
+++ b/pcbnew/drc/drc_engine.cpp
@@ -107,7 +107,7 @@ void DRC_ENGINE::loadImplicitRules()
     drillConstraint.Value().SetMin( bds.m_MinThroughDrill );
     rule->AddConstraint( drillConstraint );
 
-    DRC_CONSTRAINT annulusConstraint( DRC_CONSTRAINT_TYPE_ANNULUS_WIDTH );
+    DRC_CONSTRAINT annulusConstraint( DRC_CONSTRAINT_TYPE_ANNULAR_WIDTH );
     annulusConstraint.Value().SetMin( bds.m_ViasMinAnnulus );
     rule->AddConstraint( annulusConstraint );
 
@@ -230,18 +230,18 @@ static wxString formatConstraint( const DRC_CONSTRAINT& constraint )
 
     std::vector<Formatter> formats =
     {
-        { DRC_CONSTRAINT_TYPE_UNKNOWN, "unknown", nullptr },
-        { DRC_CONSTRAINT_TYPE_CLEARANCE, "clearance", formatMinMax },
-        { DRC_CONSTRAINT_TYPE_HOLE_CLEARANCE, "hole_clearance", formatMinMax },
-        { DRC_CONSTRAINT_TYPE_EDGE_CLEARANCE, "edge_clearance", formatMinMax },
-        { DRC_CONSTRAINT_TYPE_HOLE_SIZE, "hole_size", formatMinMax },
+        { DRC_CONSTRAINT_TYPE_UNKNOWN,             "unknown",             nullptr },
+        { DRC_CONSTRAINT_TYPE_CLEARANCE,           "clearance",           formatMinMax },
+        { DRC_CONSTRAINT_TYPE_HOLE_CLEARANCE,      "hole_clearance",      formatMinMax },
+        { DRC_CONSTRAINT_TYPE_EDGE_CLEARANCE,      "edge_clearance",      formatMinMax },
+        { DRC_CONSTRAINT_TYPE_HOLE_SIZE,           "hole_size",           formatMinMax },
         { DRC_CONSTRAINT_TYPE_COURTYARD_CLEARANCE, "courtyard_clearance", formatMinMax },
-        { DRC_CONSTRAINT_TYPE_SILK_TO_PAD, "silk_to_pad", formatMinMax },
-        { DRC_CONSTRAINT_TYPE_SILK_TO_SILK, "silk_to_silk", formatMinMax },
-        { DRC_CONSTRAINT_TYPE_TRACK_WIDTH, "track_width", formatMinMax },
-        { DRC_CONSTRAINT_TYPE_ANNULUS_WIDTH, "annulus_width", formatMinMax },
-        { DRC_CONSTRAINT_TYPE_DISALLOW, "disallow", nullptr }, // fixme
-        { DRC_CONSTRAINT_TYPE_VIA_DIAMETER, "via_diameter", formatMinMax }
+        { DRC_CONSTRAINT_TYPE_SILK_TO_PAD,         "silk_to_pad",         formatMinMax },
+        { DRC_CONSTRAINT_TYPE_SILK_TO_SILK,        "silk_to_silk",        formatMinMax },
+        { DRC_CONSTRAINT_TYPE_TRACK_WIDTH,         "track_width",         formatMinMax },
+        { DRC_CONSTRAINT_TYPE_ANNULAR_WIDTH,       "annular_width",       formatMinMax },
+        { DRC_CONSTRAINT_TYPE_DISALLOW,            "disallow",            nullptr }, // fixme
+        { DRC_CONSTRAINT_TYPE_VIA_DIAMETER,        "via_diameter",        formatMinMax }
     };
 
     for( auto& fmt : formats )
diff --git a/pcbnew/drc/drc_engine.h b/pcbnew/drc/drc_engine.h
index 8a4595d1fa..b7f976b4d9 100644
--- a/pcbnew/drc/drc_engine.h
+++ b/pcbnew/drc/drc_engine.h
@@ -107,6 +107,7 @@ public:
      * Set an optional reporter for user-level progress info.
      */
     void SetProgressReporter( PROGRESS_REPORTER* aProgRep ) { m_progressReporter = aProgRep; }
+    PROGRESS_REPORTER* GetProgressReporter() const { return m_progressReporter; }
 
     /*
      * Set an optional reporter for rule parse/compile/run-time errors and log-level progress
diff --git a/pcbnew/drc/drc_item.cpp b/pcbnew/drc/drc_item.cpp
index 6b7dfc4ac2..ca11158d53 100644
--- a/pcbnew/drc/drc_item.cpp
+++ b/pcbnew/drc/drc_item.cpp
@@ -87,12 +87,12 @@ DRC_ITEM DRC_ITEM::holeNearHole( DRCE_DRILLED_HOLES_TOO_CLOSE,
         wxT( "hole_near_hole" ) );
 
 DRC_ITEM DRC_ITEM::trackWidth( DRCE_TRACK_WIDTH,
-        _( "Track width outside allowed limits" ),
+        _( "Track width" ),
         wxT( "track_width" ) );
 
-DRC_ITEM DRC_ITEM::annulus( DRCE_ANNULUS,
-        _( "Annulus" ),
-        wxT( "annulus" ) );
+DRC_ITEM DRC_ITEM::annularWidth( DRCE_ANNULAR_WIDTH,
+        _( "Annular width" ),
+        wxT( "annular_width" ) );
 
 DRC_ITEM DRC_ITEM::drillTooSmall( DRCE_TOO_SMALL_DRILL,
         _( "Drill too small" ),
@@ -103,7 +103,7 @@ DRC_ITEM DRC_ITEM::viaHoleLargerThanPad( DRCE_VIA_HOLE_BIGGER,
         wxT( "via_hole_larger_than_pad" ) );
 
 DRC_ITEM DRC_ITEM::viaDiameter( DRCE_VIA_DIAMETER,
-        _( "Via diameter outside allowed limits" ),
+        _( "Via diameter" ),
         wxT( "via_diameter" ) );
 
 DRC_ITEM DRC_ITEM::padstack( DRCE_PADSTACK,
@@ -181,7 +181,7 @@ std::vector<std::reference_wrapper<RC_ITEM>> DRC_ITEM::allItemTypes( {
             DRC_ITEM::holeNearHole,
             DRC_ITEM::holeClearance,
             DRC_ITEM::trackWidth,
-            DRC_ITEM::annulus,
+            DRC_ITEM::annularWidth,
             DRC_ITEM::drillTooSmall,
             DRC_ITEM::viaHoleLargerThanPad,
             DRC_ITEM::padstack,
@@ -219,7 +219,7 @@ std::shared_ptr<DRC_ITEM> DRC_ITEM::Create( int aErrorCode )
     case DRCE_DRILLED_HOLES_TOO_CLOSE:  return std::make_shared<DRC_ITEM>( holeNearHole );
     case DRCE_HOLE_CLEARANCE:           return std::make_shared<DRC_ITEM>( holeClearance );
     case DRCE_TRACK_WIDTH:              return std::make_shared<DRC_ITEM>( trackWidth );
-    case DRCE_ANNULUS:                  return std::make_shared<DRC_ITEM>( annulus );
+    case DRCE_ANNULAR_WIDTH:                  return std::make_shared<DRC_ITEM>( annularWidth );
     case DRCE_TOO_SMALL_DRILL:          return std::make_shared<DRC_ITEM>( drillTooSmall );
     case DRCE_VIA_HOLE_BIGGER:          return std::make_shared<DRC_ITEM>( viaHoleLargerThanPad );
     case DRCE_VIA_DIAMETER:             return std::make_shared<DRC_ITEM>( viaDiameter );
diff --git a/pcbnew/drc/drc_item.h b/pcbnew/drc/drc_item.h
index b1e9fa679c..f5d14ebb2b 100644
--- a/pcbnew/drc/drc_item.h
+++ b/pcbnew/drc/drc_item.h
@@ -46,7 +46,7 @@ enum PCB_DRC_CODE {
     DRCE_DRILLED_HOLES_TOO_CLOSE,        // overlapping drilled holes break drill bits
     DRCE_HOLE_CLEARANCE,                 //
     DRCE_TRACK_WIDTH,                    // Track width is too small or too large
-    DRCE_ANNULUS,                        // Via size and drill leave annulus too small or too large
+    DRCE_ANNULAR_WIDTH,                  // Via size and drill leave annulus too small or too large
     DRCE_TOO_SMALL_DRILL,                // Too small via or pad drill
     DRCE_VIA_HOLE_BIGGER,                // via's hole is bigger than its diameter
     DRCE_VIA_DIAMETER,                   // Via diameter checks (min/max)
@@ -125,7 +125,7 @@ private:
     static DRC_ITEM holeNearHole;
     static DRC_ITEM holeClearance;
     static DRC_ITEM trackWidth;
-    static DRC_ITEM annulus;
+    static DRC_ITEM annularWidth;
     static DRC_ITEM drillTooSmall;
     static DRC_ITEM viaHoleLargerThanPad;
     static DRC_ITEM viaDiameter;
diff --git a/pcbnew/drc/drc_rule.h b/pcbnew/drc/drc_rule.h
index 5b59b1e6c5..685dfeffbc 100644
--- a/pcbnew/drc/drc_rule.h
+++ b/pcbnew/drc/drc_rule.h
@@ -46,7 +46,7 @@ enum DRC_CONSTRAINT_TYPE_T
     DRC_CONSTRAINT_TYPE_SILK_TO_PAD,
     DRC_CONSTRAINT_TYPE_SILK_TO_SILK,
     DRC_CONSTRAINT_TYPE_TRACK_WIDTH,
-    DRC_CONSTRAINT_TYPE_ANNULUS_WIDTH,
+    DRC_CONSTRAINT_TYPE_ANNULAR_WIDTH,
     DRC_CONSTRAINT_TYPE_DISALLOW,
     DRC_CONSTRAINT_TYPE_VIA_DIAMETER
 };
diff --git a/pcbnew/drc/drc_rule_parser.cpp b/pcbnew/drc/drc_rule_parser.cpp
index 966d18490b..46d4f110a2 100644
--- a/pcbnew/drc/drc_rule_parser.cpp
+++ b/pcbnew/drc/drc_rule_parser.cpp
@@ -265,7 +265,7 @@ void DRC_RULES_PARSER::parseConstraint( DRC_RULE* aRule )
     if( (int) token == DSN_RIGHT || token == T_EOF )
     {
         msg.Printf( _( "Missing constraint type.|  Expected %s." ),
-                        "'clearance', 'track_width', 'annulus_width', 'hole', 'disallow'" );
+                        "'clearance', 'track_width', 'annular_width', 'hole', 'disallow'" );
         reportError( msg );
         return;
     }
@@ -280,12 +280,12 @@ void DRC_RULES_PARSER::parseConstraint( DRC_RULE* aRule )
     case T_silk_to_pad:         constraint.m_Type = DRC_CONSTRAINT_TYPE_SILK_TO_PAD;         break;
     case T_silk_to_silk:        constraint.m_Type = DRC_CONSTRAINT_TYPE_SILK_TO_SILK;        break;
     case T_track_width:         constraint.m_Type = DRC_CONSTRAINT_TYPE_TRACK_WIDTH;         break;
-    case T_annulus_width:       constraint.m_Type = DRC_CONSTRAINT_TYPE_ANNULUS_WIDTH;       break;
+    case T_annulus_width:       constraint.m_Type = DRC_CONSTRAINT_TYPE_ANNULAR_WIDTH;       break;
     case T_disallow:            constraint.m_Type = DRC_CONSTRAINT_TYPE_DISALLOW;            break;
     default:
         msg.Printf( _( "Unrecognized item '%s'.| Expected %s." ),
                     FromUTF8(),
-                    "'clearance', 'track_width', 'annulus_width', 'hole', 'disallow'."
+                    "'clearance', 'track_width', 'annular_width', 'hole', 'disallow'."
                    );
         reportError( msg );
     }
diff --git a/pcbnew/drc/drc_test_provider_annulus.cpp b/pcbnew/drc/drc_test_provider_annulus.cpp
index 1d4452ba1b..0f865e6a4d 100644
--- a/pcbnew/drc/drc_test_provider_annulus.cpp
+++ b/pcbnew/drc/drc_test_provider_annulus.cpp
@@ -70,7 +70,7 @@ bool DRC_TEST_PROVIDER_ANNULUS::Run()
 {
     const int delta = 250;  // This is the number of tests between 2 calls to the progress bar
 
-    if( !m_drcEngine->HasRulesForConstraintType( DRC_CONSTRAINT_TYPE_ANNULUS_WIDTH ) )
+    if( !m_drcEngine->HasRulesForConstraintType( DRC_CONSTRAINT_TYPE_ANNULAR_WIDTH ) )
     {
         reportAux( "No annulus constraints found. Skipping check." );
         return false;
@@ -82,7 +82,7 @@ bool DRC_TEST_PROVIDER_ANNULUS::Run()
     auto checkAnnulus =
             [&]( BOARD_ITEM* item ) -> bool
             {
-                if( m_drcEngine->IsErrorLimitExceeded( DRCE_ANNULUS ) )
+                if( m_drcEngine->IsErrorLimitExceeded( DRCE_ANNULAR_WIDTH ) )
                     return false;
 
                 int  v_min = 0;
@@ -93,7 +93,7 @@ bool DRC_TEST_PROVIDER_ANNULUS::Run()
                 if( !via )
                     return true;
 
-                auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_ANNULUS_WIDTH,
+                auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_ANNULAR_WIDTH,
                                                                   via );
                 int  annulus = ( via->GetWidth() - via->GetDrillValue() ) / 2;
                 bool fail_min = false;
@@ -115,19 +115,19 @@ bool DRC_TEST_PROVIDER_ANNULUS::Run()
 
                 if( fail_min || fail_max )
                 {
-                    std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ANNULUS );
+                    std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_ANNULAR_WIDTH );
 
                     if( fail_min )
-                        m_msg.Printf( drcItem->GetErrorText() + _( " (%s min annulus %s; actual %s)" ),
+                        m_msg.Printf( drcItem->GetErrorText() + _( " (%s min annular width %s; actual %s)" ),
                                       constraint.GetName(),
-                                      MessageTextFromValue( userUnits(), annulus, true ),
-                                      MessageTextFromValue( userUnits(), v_min, true ) );
+                                      MessageTextFromValue( userUnits(), v_min, true ),
+                                      MessageTextFromValue( userUnits(), annulus, true ) );
 
                     if( fail_max )
-                        m_msg.Printf( drcItem->GetErrorText() + _( " (%s max annulus %s; actual %s)" ),
+                        m_msg.Printf( drcItem->GetErrorText() + _( " (%s max annular width %s; actual %s)" ),
                                       constraint.GetName(),
-                                      MessageTextFromValue( userUnits(), annulus, true ),
-                                      MessageTextFromValue( userUnits(), v_max, true ) );
+                                      MessageTextFromValue( userUnits(), v_max, true ),
+                                      MessageTextFromValue( userUnits(), annulus, true ) );
 
                     drcItem->SetErrorMessage( m_msg );
                     drcItem->SetItems( item );
@@ -165,7 +165,7 @@ int DRC_TEST_PROVIDER_ANNULUS::GetNumPhases() const
 
 std::set<DRC_CONSTRAINT_TYPE_T> DRC_TEST_PROVIDER_ANNULUS::GetConstraintTypes() const
 {
-    return { DRC_CONSTRAINT_TYPE_ANNULUS_WIDTH };
+    return { DRC_CONSTRAINT_TYPE_ANNULAR_WIDTH };
 }
 
 
diff --git a/pcbnew/drc/drc_test_provider_connectivity.cpp b/pcbnew/drc/drc_test_provider_connectivity.cpp
index aa73c82665..3119ebf0f6 100644
--- a/pcbnew/drc/drc_test_provider_connectivity.cpp
+++ b/pcbnew/drc/drc_test_provider_connectivity.cpp
@@ -27,7 +27,6 @@
 #include <connectivity/connectivity_data.h>
 #include <connectivity/connectivity_algo.h>
 
-#include <drc/drc_engine.h>
 #include <drc/drc_item.h>
 #include <drc/drc_rule.h>
 #include <drc/drc_test_provider.h>
@@ -72,14 +71,23 @@ public:
 
 bool DRC_TEST_PROVIDER_CONNECTIVITY::Run()
 {
-    if( !reportPhase( _( "Checking dangling pads & vias..." ) ) )
+    if( !reportPhase( _( "Checking pad, via and zone connections..." ) ) )
         return false;
 
     BOARD* board = m_drcEngine->GetBoard();
 
     std::shared_ptr<CONNECTIVITY_DATA> connectivity = board->GetConnectivity();
+
+    // Rebuild just in case. This really needs to be reliable.
     connectivity->Clear();
-    connectivity->Build( board ); // just in case. This really needs to be reliable.
+    connectivity->Build( board, m_drcEngine->GetProgressReporter() );
+
+    int delta = 100;  // This is the number of tests between 2 calls to the progress bar
+    int ii = 0;
+    int count = board->Tracks().size() + board->Zones().size();
+
+    ii += count;      // We gave half of this phase to CONNECTIVITY_DATA::Build()
+    count += count;
 
     for( TRACK* track : board->Tracks() )
     {
@@ -93,6 +101,8 @@ bool DRC_TEST_PROVIDER_CONNECTIVITY::Run()
         else if( track->Type() == PCB_TRACE_T && exceedT )
             continue;
 
+        if( !reportProgress( ii++, count, delta ) )
+            break;
 
         // Test for dangling items
         int code = track->Type() == PCB_VIA_T ? DRCE_DANGLING_VIA : DRCE_DANGLING_TRACK;
@@ -106,9 +116,6 @@ bool DRC_TEST_PROVIDER_CONNECTIVITY::Run()
         }
     }
 
-    if( !reportPhase( _( "Checking starved zones..." ) ) )
-        return false;
-
     /* test starved zones */
     for( ZONE_CONTAINER* zone : board->Zones() )
     {
@@ -118,6 +125,9 @@ bool DRC_TEST_PROVIDER_CONNECTIVITY::Run()
         if( !zone->IsOnCopperLayer() )
             continue;
 
+        if( !reportProgress( ii++, count, delta ) )
+            break;
+
         int netcode = zone->GetNetCode();
         // a netcode < 0 or > 0 and no pad in net is a error or strange
         // perhaps a "dead" net, which happens when all pads in this net were removed
@@ -139,11 +149,18 @@ bool DRC_TEST_PROVIDER_CONNECTIVITY::Run()
     std::vector<CN_EDGE> edges;
     connectivity->GetUnconnectedEdges( edges );
 
+    delta = 250;
+    ii = 0;
+    count = edges.size();
+
     for( const CN_EDGE& edge : edges )
     {
         if( m_drcEngine->IsErrorLimitExceeded( DRCE_UNCONNECTED_ITEMS ) )
             break;
 
+        if( !reportProgress( ii++, count, delta ) )
+            break;
+
         std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_UNCONNECTED_ITEMS );
         drcItem->SetItems( edge.GetSourceNode()->Parent(), edge.GetTargetNode()->Parent() );
         reportViolation( drcItem, (wxPoint) edge.GetSourceNode()->Pos());
diff --git a/pcbnew/tools/pcb_inspection_tool.cpp b/pcbnew/tools/pcb_inspection_tool.cpp
index c4af49f9d0..34fddc6c3c 100644
--- a/pcbnew/tools/pcb_inspection_tool.cpp
+++ b/pcbnew/tools/pcb_inspection_tool.cpp
@@ -409,7 +409,7 @@ int PCB_INSPECTION_TOOL::InspectConstraints( const TOOL_EVENT& aEvent )
                                      item->GetSelectMenuText( r->GetUnits() ) ) );
         r->Report( "" );
 
-        constraint = drcEngine.EvalRulesForItems( DRC_CONSTRAINT_TYPE_ANNULUS_WIDTH, item,
+        constraint = drcEngine.EvalRulesForItems( DRC_CONSTRAINT_TYPE_ANNULAR_WIDTH, item,
                                                   nullptr, UNDEFINED_LAYER, r );
 
         min = _( "undefined" );