From 81fc710a5dd96847cafc76f12dfa580fbed4ec0e Mon Sep 17 00:00:00 2001 From: Jeff Young Date: Sat, 26 Jun 2021 10:11:22 +0100 Subject: [PATCH] Use consistent terminology. Fixes https://gitlab.com/kicad/code/kicad/issues/8681 --- include/board_design_settings.h | 2 +- pcbnew/CMakeLists.txt | 2 +- pcbnew/board_design_settings.cpp | 10 +++--- pcbnew/dialogs/panel_setup_constraints.cpp | 4 +-- pcbnew/dialogs/panel_setup_rules.cpp | 2 +- pcbnew/drc/drc_engine.cpp | 2 +- pcbnew/drc/drc_item.h | 2 +- ...pp => drc_test_provider_annular_width.cpp} | 34 +++++++++---------- .../cadstar/cadstar_pcb_archive_loader.cpp | 2 +- pcbnew/plugins/eagle/eagle_plugin.cpp | 4 +-- pcbnew/plugins/kicad/pcb_parser.cpp | 2 +- pcbnew/tools/pad_tool.cpp | 4 +-- pcbnew/zone_filler.cpp | 4 +-- qa/drc_proto/CMakeLists.txt | 2 +- qa/pns/CMakeLists.txt | 2 +- 15 files changed, 39 insertions(+), 39 deletions(-) rename pcbnew/drc/{drc_test_provider_annulus.cpp => drc_test_provider_annular_width.cpp} (85%) diff --git a/include/board_design_settings.h b/include/board_design_settings.h index 15de8fd3f2..a3547118fc 100644 --- a/include/board_design_settings.h +++ b/include/board_design_settings.h @@ -683,7 +683,7 @@ public: // connected track int m_MinClearance; // overall min clearance int m_TrackMinWidth; // overall min track width - int m_ViasMinAnnulus; // overall minimum width of the via copper ring + int m_ViasMinAnnularWidth; // overall minimum width of the via copper ring int m_ViasMinSize; // overall vias (not micro vias) min diameter int m_MinThroughDrill; // through hole (not micro vias) min drill diameter int m_MicroViasMinSize; // micro vias min diameter diff --git a/pcbnew/CMakeLists.txt b/pcbnew/CMakeLists.txt index cb84acdfe5..814cd2e053 100644 --- a/pcbnew/CMakeLists.txt +++ b/pcbnew/CMakeLists.txt @@ -228,7 +228,7 @@ set( PCBNEW_MICROWAVE_SRCS set( PCBNEW_DRC_SRCS drc/drc_results_provider.cpp drc/drc_test_provider.cpp - drc/drc_test_provider_annulus.cpp + drc/drc_test_provider_annular_width.cpp drc/drc_test_provider_disallow.cpp drc/drc_test_provider_connectivity.cpp drc/drc_test_provider_copper_clearance.cpp diff --git a/pcbnew/board_design_settings.cpp b/pcbnew/board_design_settings.cpp index b8e5c3bd90..9b0ceeec51 100644 --- a/pcbnew/board_design_settings.cpp +++ b/pcbnew/board_design_settings.cpp @@ -141,7 +141,7 @@ BOARD_DESIGN_SETTINGS::BOARD_DESIGN_SETTINGS( JSON_SETTINGS* aParent, const std: m_MinClearance = Millimeter2iu( DEFAULT_MINCLEARANCE ); m_TrackMinWidth = Millimeter2iu( DEFAULT_TRACKMINWIDTH ); - m_ViasMinAnnulus = Millimeter2iu( DEFAULT_VIASMINSIZE - DEFAULT_MINTHROUGHDRILL ) / 2; + m_ViasMinAnnularWidth = Millimeter2iu( DEFAULT_VIASMINSIZE - DEFAULT_MINTHROUGHDRILL ) / 2; m_ViasMinSize = Millimeter2iu( DEFAULT_VIASMINSIZE ); m_MinThroughDrill = Millimeter2iu( DEFAULT_MINTHROUGHDRILL ); m_MicroViasMinSize = Millimeter2iu( DEFAULT_MICROVIASMINSIZE ); @@ -216,9 +216,9 @@ BOARD_DESIGN_SETTINGS::BOARD_DESIGN_SETTINGS( JSON_SETTINGS* aParent, const std: Millimeter2iu( DEFAULT_TRACKMINWIDTH ), Millimeter2iu( 0.01 ), Millimeter2iu( 25.0 ), MM_PER_IU ) ); - m_params.emplace_back( new PARAM_SCALED( "rules.min_via_annular_width", &m_ViasMinAnnulus, - Millimeter2iu( DEFAULT_VIASMINSIZE ), Millimeter2iu( 0.01 ), Millimeter2iu( 25.0 ), - MM_PER_IU ) ); + m_params.emplace_back( new PARAM_SCALED( "rules.min_via_annular_width", + &m_ViasMinAnnularWidth, Millimeter2iu( DEFAULT_VIASMINSIZE ), Millimeter2iu( 0.01 ), + Millimeter2iu( 25.0 ), MM_PER_IU ) ); m_params.emplace_back( new PARAM_SCALED( "rules.min_via_diameter", &m_ViasMinSize, Millimeter2iu( DEFAULT_VIASMINSIZE ), Millimeter2iu( 0.01 ), Millimeter2iu( 25.0 ), @@ -678,7 +678,7 @@ void BOARD_DESIGN_SETTINGS::initFromOther( const BOARD_DESIGN_SETTINGS& aOther ) m_UseConnectedTrackWidth = aOther.m_UseConnectedTrackWidth; m_MinClearance = aOther.m_MinClearance; m_TrackMinWidth = aOther.m_TrackMinWidth; - m_ViasMinAnnulus = aOther.m_ViasMinAnnulus; + m_ViasMinAnnularWidth = aOther.m_ViasMinAnnularWidth; m_ViasMinSize = aOther.m_ViasMinSize; m_MinThroughDrill = aOther.m_MinThroughDrill; m_MicroViasMinSize = aOther.m_MicroViasMinSize; diff --git a/pcbnew/dialogs/panel_setup_constraints.cpp b/pcbnew/dialogs/panel_setup_constraints.cpp index 3f4025d071..5c639fcd8f 100644 --- a/pcbnew/dialogs/panel_setup_constraints.cpp +++ b/pcbnew/dialogs/panel_setup_constraints.cpp @@ -76,7 +76,7 @@ bool PANEL_SETUP_CONSTRAINTS::TransferDataToWindow() m_minClearance.SetValue( m_BrdSettings->m_MinClearance ); m_trackMinWidth.SetValue( m_BrdSettings->m_TrackMinWidth ); - m_viaMinAnnulus.SetValue( m_BrdSettings->m_ViasMinAnnulus ); + m_viaMinAnnulus.SetValue( m_BrdSettings->m_ViasMinAnnularWidth ); m_viaMinSize.SetValue(m_BrdSettings->m_ViasMinSize ); m_holeClearance.SetValue( m_BrdSettings->m_HoleClearance ); m_edgeClearance.SetValue( m_BrdSettings->m_CopperEdgeClearance ); @@ -134,7 +134,7 @@ bool PANEL_SETUP_CONSTRAINTS::TransferDataFromWindow() m_BrdSettings->m_MinClearance = m_minClearance.GetValue(); m_BrdSettings->m_TrackMinWidth = m_trackMinWidth.GetValue(); - m_BrdSettings->m_ViasMinAnnulus = m_viaMinAnnulus.GetValue(); + m_BrdSettings->m_ViasMinAnnularWidth = m_viaMinAnnulus.GetValue(); m_BrdSettings->m_ViasMinSize = m_viaMinSize.GetValue(); m_BrdSettings->m_HoleClearance = m_holeClearance.GetValue(); m_BrdSettings->SetCopperEdgeClearance( m_edgeClearance.GetValue() ); diff --git a/pcbnew/dialogs/panel_setup_rules.cpp b/pcbnew/dialogs/panel_setup_rules.cpp index de5315c8e7..3ca90a40eb 100644 --- a/pcbnew/dialogs/panel_setup_rules.cpp +++ b/pcbnew/dialogs/panel_setup_rules.cpp @@ -239,7 +239,7 @@ void PANEL_SETUP_RULES::onScintillaCharAdded( wxStyledTextEvent &aEvent ) } else if( sexprs.top() == "constraint" ) { - tokens = "annulus_width " + tokens = "annular_width " "clearance " "courtyard_clearance " "diff_pair_gap " diff --git a/pcbnew/drc/drc_engine.cpp b/pcbnew/drc/drc_engine.cpp index b86f4b3830..2808076012 100644 --- a/pcbnew/drc/drc_engine.cpp +++ b/pcbnew/drc/drc_engine.cpp @@ -156,7 +156,7 @@ void DRC_ENGINE::loadImplicitRules() rule->AddConstraint( drillConstraint ); DRC_CONSTRAINT annulusConstraint( ANNULAR_WIDTH_CONSTRAINT ); - annulusConstraint.Value().SetMin( bds.m_ViasMinAnnulus ); + annulusConstraint.Value().SetMin( bds.m_ViasMinAnnularWidth ); rule->AddConstraint( annulusConstraint ); DRC_CONSTRAINT diameterConstraint( VIA_DIAMETER_CONSTRAINT ); diff --git a/pcbnew/drc/drc_item.h b/pcbnew/drc/drc_item.h index 667abcafbc..185af6d410 100644 --- a/pcbnew/drc/drc_item.h +++ b/pcbnew/drc/drc_item.h @@ -48,7 +48,7 @@ enum PCB_DRC_CODE { DRCE_DRILLED_HOLES_COLOCATED, // two holes at the same location DRCE_HOLE_CLEARANCE, // DRCE_TRACK_WIDTH, // Track width is too small or too large - DRCE_ANNULAR_WIDTH, // Via size and drill leave annulus too small or too large + DRCE_ANNULAR_WIDTH, // Via size and drill leave annular ring too small DRCE_DRILL_OUT_OF_RANGE, // Too small via or pad drill DRCE_VIA_DIAMETER, // Via diameter checks (min/max) DRCE_PADSTACK, // something is wrong with a pad or via stackup diff --git a/pcbnew/drc/drc_test_provider_annulus.cpp b/pcbnew/drc/drc_test_provider_annular_width.cpp similarity index 85% rename from pcbnew/drc/drc_test_provider_annulus.cpp rename to pcbnew/drc/drc_test_provider_annular_width.cpp index 4095f7f8d0..0bde18c48e 100644 --- a/pcbnew/drc/drc_test_provider_annulus.cpp +++ b/pcbnew/drc/drc_test_provider_annular_width.cpp @@ -32,21 +32,21 @@ Via/pad annular ring width test. Checks if there's sufficient copper ring around PTH/NPTH holes (vias/pads) Errors generated: - - DRCE_ANNULUS + - DRCE_ANNULAR_WIDTH Todo: - check pad holes too. - pad stack support (different IAR/OAR values depending on layer) */ -class DRC_TEST_PROVIDER_ANNULUS : public DRC_TEST_PROVIDER +class DRC_TEST_PROVIDER_ANNULAR_WIDTH : public DRC_TEST_PROVIDER { public: - DRC_TEST_PROVIDER_ANNULUS() + DRC_TEST_PROVIDER_ANNULAR_WIDTH() { } - virtual ~DRC_TEST_PROVIDER_ANNULUS() + virtual ~DRC_TEST_PROVIDER_ANNULAR_WIDTH() { } @@ -54,7 +54,7 @@ public: virtual const wxString GetName() const override { - return "annulus"; + return "annular_width"; }; virtual const wxString GetDescription() const override @@ -68,7 +68,7 @@ public: }; -bool DRC_TEST_PROVIDER_ANNULUS::Run() +bool DRC_TEST_PROVIDER_ANNULAR_WIDTH::Run() { if( m_drcEngine->IsErrorLimitExceeded( DRCE_ANNULAR_WIDTH ) ) { @@ -80,14 +80,14 @@ bool DRC_TEST_PROVIDER_ANNULUS::Run() if( !m_drcEngine->HasRulesForConstraintType( ANNULAR_WIDTH_CONSTRAINT ) ) { - reportAux( "No annulus constraints found. Tests not run." ); + reportAux( "No annular width constraints found. Tests not run." ); return true; // continue with other tests } if( !reportPhase( _( "Checking via annular rings..." ) ) ) return false; // DRC cancelled - auto checkAnnulus = + auto checkAnnularWidth = [&]( BOARD_ITEM* item ) -> bool { if( m_drcEngine->IsErrorLimitExceeded( DRCE_ANNULAR_WIDTH ) ) @@ -104,20 +104,20 @@ bool DRC_TEST_PROVIDER_ANNULUS::Run() // PADSTACKS TODO: once we have padstacks we'll need to run this per-layer.... auto constraint = m_drcEngine->EvalRules( ANNULAR_WIDTH_CONSTRAINT, via, nullptr, UNDEFINED_LAYER ); - int annulus = ( via->GetWidth() - via->GetDrillValue() ) / 2; + int annularWidth = ( via->GetWidth() - via->GetDrillValue() ) / 2; bool fail_min = false; bool fail_max = false; if( constraint.Value().HasMin() ) { v_min = constraint.Value().Min(); - fail_min = annulus < v_min; + fail_min = annularWidth < v_min; } if( constraint.Value().HasMax() ) { v_max = constraint.Value().Max(); - fail_max = annulus > v_max; + fail_max = annularWidth > v_max; } if( fail_min || fail_max ) @@ -128,13 +128,13 @@ bool DRC_TEST_PROVIDER_ANNULUS::Run() m_msg.Printf( _( "(%s min annular width %s; actual %s)" ), constraint.GetName(), MessageTextFromValue( userUnits(), v_min ), - MessageTextFromValue( userUnits(), annulus ) ); + MessageTextFromValue( userUnits(), annularWidth ) ); if( fail_max ) m_msg.Printf( _( "(%s max annular width %s; actual %s)" ), constraint.GetName(), MessageTextFromValue( userUnits(), v_max ), - MessageTextFromValue( userUnits(), annulus ) ); + MessageTextFromValue( userUnits(), annularWidth ) ); drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + m_msg ); drcItem->SetItems( item ); @@ -154,7 +154,7 @@ bool DRC_TEST_PROVIDER_ANNULUS::Run() if( !reportProgress( ii++, board->Tracks().size(), delta ) ) break; - if( !checkAnnulus( item ) ) + if( !checkAnnularWidth( item ) ) return false; // DRC cancelled } @@ -164,13 +164,13 @@ bool DRC_TEST_PROVIDER_ANNULUS::Run() } -int DRC_TEST_PROVIDER_ANNULUS::GetNumPhases() const +int DRC_TEST_PROVIDER_ANNULAR_WIDTH::GetNumPhases() const { return 1; } -std::set DRC_TEST_PROVIDER_ANNULUS::GetConstraintTypes() const +std::set DRC_TEST_PROVIDER_ANNULAR_WIDTH::GetConstraintTypes() const { return { ANNULAR_WIDTH_CONSTRAINT }; } @@ -178,5 +178,5 @@ std::set DRC_TEST_PROVIDER_ANNULUS::GetConstraintTypes() const namespace detail { -static DRC_REGISTER_TEST_PROVIDER dummy; +static DRC_REGISTER_TEST_PROVIDER dummy; } diff --git a/pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp b/pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp index 25b5d3c0e5..4bac908eee 100644 --- a/pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp +++ b/pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp @@ -626,7 +626,7 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadDesignRules() ds.m_TrackMinWidth = getKiCadLength( Assignments.Technology.MinRouteWidth ); ds.m_ViasMinSize = ds.m_TrackMinWidth; // Not specified, assumed same as track width - ds.m_ViasMinAnnulus = ds.m_TrackMinWidth / 2; // Not specified, assumed half track width + ds.m_ViasMinAnnularWidth = ds.m_TrackMinWidth / 2; // Not specified, assumed half track width ds.m_MinThroughDrill = PCB_IU_PER_MM * 0.0508; // CADSTAR does not specify a minimum hole size // so set to minimum permitted in KiCad (2 mils) ds.m_HoleClearance = ds.m_CopperEdgeClearance; // Not specified, assumed same as edge diff --git a/pcbnew/plugins/eagle/eagle_plugin.cpp b/pcbnew/plugins/eagle/eagle_plugin.cpp index 70dca93574..fef2df12fa 100644 --- a/pcbnew/plugins/eagle/eagle_plugin.cpp +++ b/pcbnew/plugins/eagle/eagle_plugin.cpp @@ -401,8 +401,8 @@ BOARD* EAGLE_PLUGIN::Load( const wxString& aFileName, BOARD* aAppendToMe, if( m_min_hole < designSettings.m_MinThroughDrill ) designSettings.m_MinThroughDrill = m_min_hole; - if( m_min_annulus < designSettings.m_ViasMinAnnulus ) - designSettings.m_ViasMinAnnulus = m_min_annulus; + if( m_min_annulus < designSettings.m_ViasMinAnnularWidth ) + designSettings.m_ViasMinAnnularWidth = m_min_annulus; if( m_rules->mdWireWire ) { diff --git a/pcbnew/plugins/kicad/pcb_parser.cpp b/pcbnew/plugins/kicad/pcb_parser.cpp index cda86efa11..94a0b867b8 100644 --- a/pcbnew/plugins/kicad/pcb_parser.cpp +++ b/pcbnew/plugins/kicad/pcb_parser.cpp @@ -1732,7 +1732,7 @@ void PCB_PARSER::parseSetup() break; case T_via_min_annulus: - designSettings.m_ViasMinAnnulus = parseBoardUnits( T_via_min_annulus ); + designSettings.m_ViasMinAnnularWidth = parseBoardUnits( T_via_min_annulus ); m_board->m_LegacyDesignSettingsLoaded = true; NeedRIGHT(); break; diff --git a/pcbnew/tools/pad_tool.cpp b/pcbnew/tools/pad_tool.cpp index e6208114ab..822b05bb1e 100644 --- a/pcbnew/tools/pad_tool.cpp +++ b/pcbnew/tools/pad_tool.cpp @@ -691,8 +691,8 @@ void PAD_TOOL::recombinePad( PAD* aPad ) ERROR_INSIDE ); aPad->SetAnchorPadShape( PAD_SHAPE::CIRCLE ); - wxSize minAnnulus( Millimeter2iu( 0.2 ), Millimeter2iu( 0.2 ) ); - aPad->SetSize( aPad->GetDrillSize() + minAnnulus ); + wxSize minAnnularRingWidth( Millimeter2iu( 0.2 ), Millimeter2iu( 0.2 ) ); + aPad->SetSize( aPad->GetDrillSize() + minAnnularRingWidth ); aPad->SetOffset( wxPoint( 0, 0 ) ); PCB_SHAPE* shape = new PCB_SHAPE; diff --git a/pcbnew/zone_filler.cpp b/pcbnew/zone_filler.cpp index 6d3e3c8a84..b035945520 100644 --- a/pcbnew/zone_filler.cpp +++ b/pcbnew/zone_filler.cpp @@ -1570,9 +1570,9 @@ bool ZONE_FILLER::addHatchFillTypeOnZone( const ZONE* aZone, PCB_LAYER_ID aLayer // enough. int pad_width = std::min( pad->GetSize().x, pad->GetSize().y ); int slot_width = std::min( pad->GetDrillSize().x, pad->GetDrillSize().y ); - int min_annulus = ( pad_width - slot_width ) / 2; + int min_annular_ring_width = ( pad_width - slot_width ) / 2; int clearance = std::max( min_apron_radius - pad_width / 2, - outline_margin - min_annulus ); + outline_margin - min_annular_ring_width ); clearance = std::max( 0, clearance - linethickness / 2 ); pad->TransformShapeWithClearanceToPolygon( aprons, aLayer, clearance, diff --git a/qa/drc_proto/CMakeLists.txt b/qa/drc_proto/CMakeLists.txt index 926f0f9406..d3dea5d406 100644 --- a/qa/drc_proto/CMakeLists.txt +++ b/qa/drc_proto/CMakeLists.txt @@ -40,7 +40,7 @@ add_executable( drc_proto ../../pcbnew/drc/drc_test_provider_hole_size.cpp ../../pcbnew/drc/drc_test_provider_disallow.cpp ../../pcbnew/drc/drc_test_provider_track_width.cpp - ../../pcbnew/drc/drc_test_provider_annulus.cpp + ../../pcbnew/drc/drc_test_provider_annular_width.cpp ../../pcbnew/drc/drc_test_provider_connectivity.cpp ../../pcbnew/drc/drc_test_provider_courtyard_clearance.cpp ../../pcbnew/drc/drc_test_provider_via_diameter.cpp diff --git a/qa/pns/CMakeLists.txt b/qa/pns/CMakeLists.txt index 2a9305430c..2502d71f6c 100644 --- a/qa/pns/CMakeLists.txt +++ b/qa/pns/CMakeLists.txt @@ -39,7 +39,7 @@ add_executable( test_pns ../../pcbnew/drc/drc_test_provider_hole_size.cpp ../../pcbnew/drc/drc_test_provider_disallow.cpp ../../pcbnew/drc/drc_test_provider_track_width.cpp - ../../pcbnew/drc/drc_test_provider_annulus.cpp + ../../pcbnew/drc/drc_test_provider_annular_width.cpp ../../pcbnew/drc/drc_test_provider_connectivity.cpp ../../pcbnew/drc/drc_test_provider_courtyard_clearance.cpp ../../pcbnew/drc/drc_test_provider_via_diameter.cpp