diff --git a/pcbnew/router/pns_kicad_iface.cpp b/pcbnew/router/pns_kicad_iface.cpp
index 8003c9e899..22d51ccba8 100644
--- a/pcbnew/router/pns_kicad_iface.cpp
+++ b/pcbnew/router/pns_kicad_iface.cpp
@@ -415,6 +415,8 @@ bool PNS_KICAD_IFACE_BASE::ImportSizes( PNS::SIZES_SETTINGS& aSizes, PNS::ITEM*
     BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
     PNS::CONSTRAINT        constraint;
 
+    aSizes.SetMinClearance( bds.m_MinClearance );
+
     int  trackWidth = bds.m_TrackMinWidth;
     bool found = false;
 
diff --git a/pcbnew/router/pns_router.cpp b/pcbnew/router/pns_router.cpp
index 9a36b40045..d8c9221bcf 100644
--- a/pcbnew/router/pns_router.cpp
+++ b/pcbnew/router/pns_router.cpp
@@ -185,6 +185,15 @@ bool ROUTER::isStartingPointRoutable( const VECTOR2I& aWhere, ITEM* aStartItem,
     if( Settings().CanViolateDRC() && Settings().Mode() == RM_MarkObstacles )
         return true;
 
+    if( m_mode == PNS_MODE_ROUTE_DIFF_PAIR )
+    {
+        if( m_sizes.DiffPairGap() < m_sizes.MinClearance() )
+        {
+            SetFailureReason( _( "Diff pair gap is less than board minimum clearance." ) );
+            return false;
+        }
+    }
+
     ITEM_SET candidates = QueryHoverItems( aWhere );
 
     for( ITEM* item : candidates.Items() )
diff --git a/pcbnew/router/pns_sizes_settings.h b/pcbnew/router/pns_sizes_settings.h
index 52a62f2eca..68297007db 100644
--- a/pcbnew/router/pns_sizes_settings.h
+++ b/pcbnew/router/pns_sizes_settings.h
@@ -54,6 +54,9 @@ public:
     void ClearLayerPairs();
     void AddLayerPair( int aL1, int aL2 );
 
+    int MinClearance() const { return m_minClearance; }
+    void SetMinClearance( int aClearance ) { m_minClearance = aClearance; }
+
     int TrackWidth() const { return m_trackWidth; }
     void SetTrackWidth( int aWidth ) { m_trackWidth = aWidth; }
 
@@ -96,6 +99,7 @@ public:
     VIATYPE ViaType() const { return m_viaType; }
 
 private:
+    int     m_minClearance;
     int     m_trackWidth;
 
     VIATYPE m_viaType;