Add a bunch more zone fill and DRC regression tests.
Also tries to fix a compile issue on gcc.
This commit is contained in:
Jeff Young
parent
b8bb04c432
commit
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(kicad_pcb (version 20200512) (host pcbnew "(5.99.0-1700-gd72a778f1)")
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(general
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(thickness 1.6)
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(drawings 4)
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(tracks 14)
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(modules 2)
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(nets 4)
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)
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(paper "A4")
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(layers
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(0 "F.Cu" signal)
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(31 "B.Cu" signal)
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(32 "B.Adhes" user)
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(33 "F.Adhes" user)
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(34 "B.Paste" user)
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(35 "F.Paste" user)
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(36 "B.SilkS" user)
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(37 "F.SilkS" user)
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(38 "B.Mask" user)
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(39 "F.Mask" user)
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(40 "Dwgs.User" user)
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(41 "Cmts.User" user)
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(42 "Eco1.User" user)
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(43 "Eco2.User" user)
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(44 "Edge.Cuts" user)
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(45 "Margin" user)
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(46 "B.CrtYd" user)
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(47 "F.CrtYd" user)
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(48 "B.Fab" user)
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(49 "F.Fab" user)
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)
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(setup
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(stackup
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(layer "F.SilkS" (type "Top Silk Screen"))
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(layer "F.Paste" (type "Top Solder Paste"))
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(layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
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(layer "F.Cu" (type "copper") (thickness 0.035))
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(layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
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(layer "B.Cu" (type "copper") (thickness 0.035))
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(layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
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(layer "B.Paste" (type "Bottom Solder Paste"))
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(layer "B.SilkS" (type "Bottom Silk Screen"))
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(copper_finish "None")
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(dielectric_constraints no)
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)
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(last_trace_width 0.25)
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(trace_clearance 0.2)
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(zone_clearance 0.508)
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(zone_45_only no)
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(trace_min 0.2)
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(clearance_min 0.15)
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(via_min_annulus 0.05)
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(via_min_size 0.4)
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(through_hole_min 0.3)
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(via_size 0.8)
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(via_drill 0.4)
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(uvia_size 0.3)
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(uvia_drill 0.1)
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(uvias_allowed no)
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(uvia_min_size 0.2)
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(uvia_min_drill 0.1)
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(max_error 0.005)
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(defaults
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(edge_clearance 0.01)
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(edge_cuts_line_width 0.05)
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(courtyard_line_width 0.05)
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(copper_line_width 0.2)
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(copper_text_dims (size 1.5 1.5) (thickness 0.3))
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(silk_line_width 0.12)
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(silk_text_dims (size 1 1) (thickness 0.15))
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(fab_layers_line_width 0.1)
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(fab_layers_text_dims (size 1 1) (thickness 0.15))
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(other_layers_line_width 0.1)
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(other_layers_text_dims (size 1 1) (thickness 0.15))
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(dimension_units 0)
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(dimension_precision 1)
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)
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(pad_size 1.524 1.524)
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(pad_drill 0.762)
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(pad_to_mask_clearance 0.05)
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(aux_axis_origin 0 0)
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(visible_elements 7FFFFFFF)
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(pcbplotparams
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(layerselection 0x010fc_ffffffff)
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(usegerberextensions false)
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(usegerberattributes true)
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(usegerberadvancedattributes true)
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(creategerberjobfile true)
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(svguseinch false)
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(svgprecision 6)
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(excludeedgelayer true)
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(linewidth 0.100000)
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(plotframeref false)
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(viasonmask false)
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(mode 1)
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(useauxorigin false)
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(hpglpennumber 1)
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(hpglpenspeed 20)
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(hpglpendiameter 15.000000)
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(psnegative false)
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(psa4output false)
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(plotreference true)
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(plotvalue true)
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(plotinvisibletext false)
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(sketchpadsonfab false)
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(subtractmaskfromsilk false)
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(outputformat 1)
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(mirror false)
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(drillshape 1)
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(scaleselection 1)
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(outputdirectory "")
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)
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)
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(net 0 "")
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(net 1 "Net-(J1-Pad1)")
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(net 2 "Net-(J1-Pad2)")
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(net 3 "Net-(J1-Pad3)")
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(net_class "Default" "This is the default net class."
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(clearance 0.2)
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(trace_width 0.25)
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(via_dia 0.8)
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(via_drill 0.4)
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(uvia_dia 0.3)
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(uvia_drill 0.1)
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(add_net "Net-(J1-Pad1)")
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(add_net "Net-(J1-Pad2)")
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(add_net "Net-(J1-Pad3)")
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)
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(module "Resistors_SMD:R_0805" (layer "B.Cu") (tedit 58E0A804) (tstamp 3461ae3d-9a09-475a-b78b-3f772cd40bd8)
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(at 120.6246 66.2432 -90)
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(descr "Resistor SMD 0805, reflow soldering, Vishay (see dcrcw.pdf)")
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(tags "resistor 0805")
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(path "/c6c78989-e8f2-4abf-a6f7-7545bc8c1e66")
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(attr smd)
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(fp_text reference "R1" (at 0 1.65 -90) (layer "B.SilkS")
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(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
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)
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(fp_text value "R" (at 0 -1.75 -90) (layer "B.Fab")
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(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
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)
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(fp_text user "${REFERENCE}" (at 0 0 -90) (layer "B.Fab")
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(effects (font (size 0.5 0.5) (thickness 0.075)) (justify mirror))
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)
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(fp_line (start -1 -0.62) (end -1 0.62) (layer "B.Fab") (width 0.1))
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(fp_line (start 1 -0.62) (end -1 -0.62) (layer "B.Fab") (width 0.1))
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(fp_line (start 1 0.62) (end 1 -0.62) (layer "B.Fab") (width 0.1))
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(fp_line (start -1 0.62) (end 1 0.62) (layer "B.Fab") (width 0.1))
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(fp_line (start 0.6 -0.88) (end -0.6 -0.88) (layer "B.SilkS") (width 0.12))
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(fp_line (start -0.6 0.88) (end 0.6 0.88) (layer "B.SilkS") (width 0.12))
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(fp_line (start -1.55 0.9) (end 1.55 0.9) (layer "B.CrtYd") (width 0.05))
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(fp_line (start -1.55 0.9) (end -1.55 -0.9) (layer "B.CrtYd") (width 0.05))
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(fp_line (start 1.55 -0.9) (end 1.55 0.9) (layer "B.CrtYd") (width 0.05))
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(fp_line (start 1.55 -0.9) (end -1.55 -0.9) (layer "B.CrtYd") (width 0.05))
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(pad "1" smd rect (at -0.95 0 270) (size 0.7 1.3) (layers "B.Cu" "B.Paste" "B.Mask")
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(net 2 "Net-(J1-Pad2)") (tstamp 90f73341-fd35-4de5-811f-b9b78b7d229a))
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(pad "2" smd rect (at 0.95 0 270) (size 0.7 1.3) (layers "B.Cu" "B.Paste" "B.Mask")
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(net 1 "Net-(J1-Pad1)") (tstamp 47920df1-0b43-4346-93df-a8b91e0462ad))
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(model "${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0805.wrl"
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(at (xyz 0 0 0))
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(scale (xyz 1 1 1))
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(rotate (xyz 0 0 0))
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)
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)
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(module "Connectors_JST:JST_SH_SM03B-SRSS-TB_03x1.00mm_Angled" (layer "F.Cu") (tedit 56B07436) (tstamp f857536b-311d-42f4-b594-3442deba239a)
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(at 129.4384 68.7324 45)
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(descr "http://www.jst-mfg.com/product/pdf/eng/eSH.pdf")
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(tags "connector jst sh")
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(path "/c9eee9ba-3bcb-475c-9e6f-0d52e9a7040e")
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(attr smd)
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(fp_text reference "J1" (at -1 -4 45) (layer "F.SilkS")
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_text value "Conn_01x03_MountingPin" (at 0 4.5 45) (layer "F.Fab")
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_circle (center -2 -2.1875) (end -1.75 -2.1875) (layer "F.SilkS") (width 0.12))
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(fp_line (start -1.4 2.6375) (end 1.4 2.6375) (layer "F.SilkS") (width 0.12))
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(fp_line (start -2.5 0.7375) (end -2.5 -1.6125) (layer "F.SilkS") (width 0.12))
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(fp_line (start -2 -1.6125) (end -2 -0.4125) (layer "F.SilkS") (width 0.12))
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(fp_line (start -2 -0.4125) (end -2 -0.4125) (layer "F.SilkS") (width 0.12))
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||||||
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(fp_line (start 2.5 -0.4125) (end 2.5 -0.4125) (layer "F.SilkS") (width 0.12))
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||||||
|
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||||||
|
(fp_line (start -3.4 3.35) (end -3.4 -3.25) (layer "F.CrtYd") (width 0.05))
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||||||
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||||||
|
(fp_line (start 3.4 -3.25) (end 3.4 3.35) (layer "F.CrtYd") (width 0.05))
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||||||
|
(fp_line (start 3.4 3.35) (end -3.4 3.35) (layer "F.CrtYd") (width 0.05))
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||||||
|
(pad "1" smd rect (at -1 -1.9375 45) (size 0.6 1.55) (layers "F.Cu" "F.Paste" "F.Mask")
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||||||
|
(net 1 "Net-(J1-Pad1)") (pinfunction "Pin_1") (tstamp 099c08a9-a815-4ce0-9362-538d726d9c02))
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||||||
|
(pad "2" smd rect (at 0 -1.9375 45) (size 0.6 1.55) (layers "F.Cu" "F.Paste" "F.Mask")
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||||||
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||||||
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(pad "3" smd rect (at 1 -1.9375 45) (size 0.6 1.55) (layers "F.Cu" "F.Paste" "F.Mask")
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(net 3 "Net-(J1-Pad3)") (pinfunction "Pin_3") (tstamp d787d991-8b10-43a9-bda8-a84559d3dc5e))
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||||||
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(pad "" smd rect (at -2.3 1.9375 45) (size 1.2 1.8) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp cbfaecaf-5ba8-4cbb-9cfa-cbddd3860580))
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||||||
|
(pad "" smd rect (at 2.3 1.9375 45) (size 1.2 1.8) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp e42e1bc3-504c-4630-a5aa-7fd2d9ffd69c))
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)
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||||||
|
|
||||||
|
(gr_line (start 117.3988 76.708) (end 117.221 61.4934) (layer "Edge.Cuts") (width 0.05) (tstamp a78f509c-e1b9-49ba-b3bc-521279981534))
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||||||
|
(gr_line (start 144.526 76.7334) (end 117.3988 76.708) (layer "Edge.Cuts") (width 0.05) (tstamp 1af6783c-0a42-45b6-abd7-0e08b693db24))
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||||||
|
(gr_line (start 144.4752 61.4934) (end 144.526 76.7334) (layer "Edge.Cuts") (width 0.05) (tstamp 960d3bc1-a0ab-4fa3-a303-ae1d5a790b4e))
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||||||
|
(gr_line (start 117.221 61.4934) (end 144.4752 61.4934) (layer "Edge.Cuts") (width 0.05) (tstamp cad22098-0b03-4042-9a5c-03067b33df4d))
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(via (at 124.46 67.183) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 1) (tstamp 7b7eb598-0a34-4575-82d5-4d2df1fe2e26))
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||||||
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(segment (start 124.46 67.183) (end 120.6348 67.183) (width 0.25) (layer "B.Cu") (net 1) (tstamp b716ea7e-5437-4b8d-8adf-5979da4797b9))
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||||||
|
(segment (start 124.4702 67.1932) (end 124.46 67.183) (width 0.25) (layer "F.Cu") (net 1) (tstamp 1f4cc5f0-d4f2-4f12-a730-002967d6caba))
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|
(segment (start 126.484987 67.1932) (end 124.4702 67.1932) (width 0.25) (layer "F.Cu") (net 1) (tstamp ac60baa0-d37f-46b7-9bfd-03e838b95ff8))
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|
(segment (start 120.6348 67.183) (end 120.6246 67.1932) (width 0.25) (layer "B.Cu") (net 1) (tstamp 053efa3b-b9a1-4cf2-81fd-d147958ee55d))
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||||||
|
(segment (start 122.6972 65.2932) (end 122.7124 65.278) (width 0.25) (layer "B.Cu") (net 2) (tstamp 8c3c3ad4-2e40-4f60-8fe5-e54ba27216a3))
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|
(segment (start 120.6246 65.2932) (end 122.6972 65.2932) (width 0.25) (layer "B.Cu") (net 2) (tstamp 55d4b264-ae4c-4659-850b-136c1131f417))
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||||||
|
(segment (start 122.809 65.278) (end 125.984 65.278) (width 0.25) (layer "F.Cu") (net 2) (tstamp 1b5d08ed-ff43-4c82-838f-e6a90263c9e3))
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||||||
|
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|
||||||
|
(via (at 122.809 65.278) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 2) (tstamp 72763d28-3414-4cb5-bb01-a5c4893d09aa))
|
||||||
|
(segment (start 125.984 65.278) (end 125.9992 65.2932) (width 0.25) (layer "F.Cu") (net 2) (tstamp 031e06b2-25e2-4767-9f44-bb8f03d23c74))
|
||||||
|
(segment (start 126.4768 67.1932) (end 126.484987 67.1932) (width 0.25) (layer "F.Cu") (net 1) (tstamp a8f164c7-3d2a-426f-800b-6816271944cc))
|
||||||
|
(segment (start 126.484987 67.1932) (end 127.361274 68.069487) (width 0.25) (layer "F.Cu") (net 1) (tstamp 59eb23d6-d62d-41f2-906e-00448418d1b2))
|
||||||
|
(segment (start 125.9992 65.2932) (end 127.5842 66.8782) (width 0.25) (layer "F.Cu") (net 2) (tstamp 998f5b2f-974e-461a-af95-91a3471df90b))
|
||||||
|
|
||||||
|
)
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,460 @@
|
||||||
|
{
|
||||||
|
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|
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|
||||||
|
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|
||||||
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|
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|
||||||
|
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|
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|
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|
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|
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|
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|
||||||
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|
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|
||||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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|
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|
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|
||||||
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|
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|
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|
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|
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|
||||||
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|
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|
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|
||||||
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|
||||||
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|
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|
||||||
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|
||||||
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|
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|
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|
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|
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|
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|
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|
||||||
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|
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|
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|
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|
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|
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|
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|
||||||
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|
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|
||||||
|
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|
||||||
|
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|
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|
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|
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|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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Load Diff
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|
||||||
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|
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||||||
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|
||||||
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|
||||||
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|
||||||
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||||||
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|
||||||
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||||||
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||||||
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|
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|
||||||
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|
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|
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|
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|
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|
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|
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||||||
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||||||
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|
||||||
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|
||||||
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|
||||||
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(xy 92.71 79.724)
|
||||||
|
(xy 92.730357 79.43937)
|
||||||
|
(xy 92.791014 79.160535)
|
||||||
|
(xy 92.890736 78.89317)
|
||||||
|
(xy 93.027493 78.642718)
|
||||||
|
(xy 93.198501 78.414279)
|
||||||
|
(xy 93.400279 78.212501)
|
||||||
|
(xy 93.628718 78.041493)
|
||||||
|
(xy 93.87917 77.904736)
|
||||||
|
(xy 94.146535 77.805014)
|
||||||
|
(xy 94.42537 77.744357)
|
||||||
|
(xy 94.653074 77.728071)
|
||||||
|
(xy 94.710001 77.724)
|
||||||
|
(xy 198.151999 77.724)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
@ -0,0 +1,372 @@
|
||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"design_settings": {
|
||||||
|
"defaults": {
|
||||||
|
"board_outline_line_width": 0.09999999999999999,
|
||||||
|
"copper_line_width": 0.19999999999999998,
|
||||||
|
"copper_text_italic": false,
|
||||||
|
"copper_text_size_h": 1.5,
|
||||||
|
"copper_text_size_v": 1.5,
|
||||||
|
"copper_text_thickness": 0.3,
|
||||||
|
"copper_text_upright": false,
|
||||||
|
"courtyard_line_width": 0.049999999999999996,
|
||||||
|
"dimension_precision": 1,
|
||||||
|
"dimension_units": 0,
|
||||||
|
"fab_line_width": 0.09999999999999999,
|
||||||
|
"fab_text_italic": false,
|
||||||
|
"fab_text_size_h": 1.0,
|
||||||
|
"fab_text_size_v": 1.0,
|
||||||
|
"fab_text_thickness": 0.15,
|
||||||
|
"fab_text_upright": false,
|
||||||
|
"other_line_width": 0.15,
|
||||||
|
"other_text_italic": false,
|
||||||
|
"other_text_size_h": 1.0,
|
||||||
|
"other_text_size_v": 1.0,
|
||||||
|
"other_text_thickness": 0.15,
|
||||||
|
"other_text_upright": false,
|
||||||
|
"pads": {
|
||||||
|
"drill": 1.2,
|
||||||
|
"height": 2.4,
|
||||||
|
"width": 2.4
|
||||||
|
},
|
||||||
|
"silk_line_width": 0.15,
|
||||||
|
"silk_text_italic": false,
|
||||||
|
"silk_text_size_h": 1.0,
|
||||||
|
"silk_text_size_v": 1.0,
|
||||||
|
"silk_text_thickness": 0.15,
|
||||||
|
"silk_text_upright": false,
|
||||||
|
"zones": {
|
||||||
|
"45_degree_only": false,
|
||||||
|
"min_clearance": 0.19999999999999998
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"diff_pair_dimensions": [
|
||||||
|
{
|
||||||
|
"gap": 0.25,
|
||||||
|
"via_gap": 0.25,
|
||||||
|
"width": 0.2
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"drc_exclusions": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"rule_severities": {
|
||||||
|
"clearance": "error",
|
||||||
|
"copper_edge_clearance": "error",
|
||||||
|
"courtyards_overlap": "error",
|
||||||
|
"drill_too_small": "error",
|
||||||
|
"duplicate_footprints": "warning",
|
||||||
|
"extra_footprint": "warning",
|
||||||
|
"hole_near_hole": "error",
|
||||||
|
"invalid_outline": "error",
|
||||||
|
"item_on_disabled_layer": "error",
|
||||||
|
"items_not_allowed": "error",
|
||||||
|
"keepout": "error",
|
||||||
|
"malformed_courtyard": "error",
|
||||||
|
"microvia_drill_too_small": "error",
|
||||||
|
"microvia_too_small": "error",
|
||||||
|
"missing_courtyard": "ignore",
|
||||||
|
"missing_footprint": "warning",
|
||||||
|
"npth_inside_courtyard": "ignore",
|
||||||
|
"padstack": "error",
|
||||||
|
"pth_inside_courtyard": "ignore",
|
||||||
|
"shorting_items": "error",
|
||||||
|
"track_dangling": "warning",
|
||||||
|
"track_width": "error",
|
||||||
|
"tracks_crossing": "error",
|
||||||
|
"unconnected_items": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"via_annulus": "error",
|
||||||
|
"via_dangling": "warning",
|
||||||
|
"via_hole_larger_than_pad": "error",
|
||||||
|
"via_too_small": "error",
|
||||||
|
"zone_has_empty_net": "error",
|
||||||
|
"zones_intersect": "error"
|
||||||
|
},
|
||||||
|
"rules": {
|
||||||
|
"allow_blind_buried_vias": false,
|
||||||
|
"allow_microvias": false,
|
||||||
|
"max_error": 0.005,
|
||||||
|
"min_clearance": 0.0,
|
||||||
|
"min_copper_edge_clearance": 0.0,
|
||||||
|
"min_hole_to_hole": 0.25,
|
||||||
|
"min_microvia_diameter": 0.19999999999999998,
|
||||||
|
"min_microvia_drill": 0.09999999999999999,
|
||||||
|
"min_through_hole_diameter": 0.3,
|
||||||
|
"min_track_width": 0.19999999999999998,
|
||||||
|
"min_via_annulus": 0.049999999999999996,
|
||||||
|
"min_via_diameter": 0.39999999999999997,
|
||||||
|
"solder_mask_clearance": 0.0,
|
||||||
|
"solder_mask_min_width": 0.0,
|
||||||
|
"solder_paste_clearance": 0.0,
|
||||||
|
"solder_paste_margin_ratio": 0.0
|
||||||
|
},
|
||||||
|
"track_widths": [
|
||||||
|
0.25
|
||||||
|
],
|
||||||
|
"via_dimensions": [
|
||||||
|
{
|
||||||
|
"diameter": 0.8,
|
||||||
|
"drill": 0.4
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"zones_allow_external_fillets": false,
|
||||||
|
"zones_use_no_outline": true
|
||||||
|
},
|
||||||
|
"layer_presets": []
|
||||||
|
},
|
||||||
|
"boards": [],
|
||||||
|
"cvpcb": {
|
||||||
|
"equivalence_files": []
|
||||||
|
},
|
||||||
|
"erc": {
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"pin_map": [
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"rule_severities": {
|
||||||
|
"bus_definition_conflict": "error",
|
||||||
|
"bus_label_syntax": "error",
|
||||||
|
"bus_to_bus_conflict": "error",
|
||||||
|
"bus_to_net_conflict": "error",
|
||||||
|
"different_unit_footprint": "error",
|
||||||
|
"different_unit_net": "error",
|
||||||
|
"duplicate_sheet_names": "error",
|
||||||
|
"global_label_dangling": "error",
|
||||||
|
"hier_label_mismatch": "error",
|
||||||
|
"label_dangling": "error",
|
||||||
|
"multiple_net_names": "error",
|
||||||
|
"net_not_bus_member": "error",
|
||||||
|
"no_connect_connected": "error",
|
||||||
|
"no_connect_dangling": "error",
|
||||||
|
"pin_not_connected": "error",
|
||||||
|
"pin_not_driven": "error",
|
||||||
|
"pin_to_pin": "error",
|
||||||
|
"similar_labels": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"wire_dangling": "error"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"libraries": {
|
||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "test.kicad_pro",
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_settings": {
|
||||||
|
"classes": [
|
||||||
|
{
|
||||||
|
"bus_width": 5.0,
|
||||||
|
"clearance": 0.2,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.25,
|
||||||
|
"via_diameter": 0.8,
|
||||||
|
"via_drill": 0.4,
|
||||||
|
"wire_width": 5.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_colors": null
|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "",
|
||||||
|
"vmrl": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": ""
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"drawing": {
|
||||||
|
"default_bus_thickness": 12.0,
|
||||||
|
"default_junction_size": 40.0,
|
||||||
|
"default_line_thickness": 6.0,
|
||||||
|
"default_text_size": 50.0,
|
||||||
|
"default_wire_thickness": 6.0,
|
||||||
|
"field_names": [],
|
||||||
|
"pin_symbol_size": 25.0,
|
||||||
|
"text_offset_ratio": 0.35
|
||||||
|
},
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_format_name": "",
|
||||||
|
"page_layout_descr_file": "",
|
||||||
|
"plot_directory": "",
|
||||||
|
"spice_adjust_passive_values": false,
|
||||||
|
"spice_external_command": "spice \"%I\"",
|
||||||
|
"subpart_first_id": 65,
|
||||||
|
"subpart_id_separator": 0
|
||||||
|
},
|
||||||
|
"sheets": [
|
||||||
|
[
|
||||||
|
"6b283b09-4ae5-4474-9b11-e8fce1cb6c8d",
|
||||||
|
""
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"text_variables": {
|
||||||
|
"REVISION": "69"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,150 @@
|
||||||
|
(kicad_pcb (version 20201002) (generator pcbnew)
|
||||||
|
|
||||||
|
(general
|
||||||
|
(thickness 0.6)
|
||||||
|
)
|
||||||
|
|
||||||
|
(paper "A4" portrait)
|
||||||
|
(layers
|
||||||
|
(0 "F.Cu" signal)
|
||||||
|
(31 "B.Cu" signal)
|
||||||
|
(34 "B.Paste" user)
|
||||||
|
(35 "F.Paste" user)
|
||||||
|
(36 "B.SilkS" user "B.Silkscreen")
|
||||||
|
(37 "F.SilkS" user "F.Silkscreen")
|
||||||
|
(38 "B.Mask" user)
|
||||||
|
(39 "F.Mask" user)
|
||||||
|
(40 "Dwgs.User" user "User.Drawings")
|
||||||
|
(41 "Cmts.User" user "User.Comments")
|
||||||
|
(42 "Eco1.User" user "User.Eco1")
|
||||||
|
(43 "Eco2.User" user "User.Eco2")
|
||||||
|
(44 "Edge.Cuts" user)
|
||||||
|
(45 "Margin" user)
|
||||||
|
(46 "B.CrtYd" user "B.Courtyard")
|
||||||
|
(47 "F.CrtYd" user "F.Courtyard")
|
||||||
|
(48 "B.Fab" user)
|
||||||
|
(49 "F.Fab" user)
|
||||||
|
)
|
||||||
|
|
||||||
|
(setup
|
||||||
|
(grid_origin 118.35 87.8)
|
||||||
|
(pcbplotparams
|
||||||
|
(layerselection 0x0020000_7ffffffe)
|
||||||
|
(disableapertmacros false)
|
||||||
|
(usegerberextensions true)
|
||||||
|
(usegerberattributes false)
|
||||||
|
(usegerberadvancedattributes false)
|
||||||
|
(creategerberjobfile false)
|
||||||
|
(svguseinch false)
|
||||||
|
(svgprecision 6)
|
||||||
|
(excludeedgelayer false)
|
||||||
|
(plotframeref false)
|
||||||
|
(viasonmask false)
|
||||||
|
(mode 1)
|
||||||
|
(useauxorigin false)
|
||||||
|
(hpglpennumber 1)
|
||||||
|
(hpglpenspeed 20)
|
||||||
|
(hpglpendiameter 15.000000)
|
||||||
|
(psnegative false)
|
||||||
|
(psa4output false)
|
||||||
|
(plotreference true)
|
||||||
|
(plotvalue false)
|
||||||
|
(plotinvisibletext false)
|
||||||
|
(sketchpadsonfab false)
|
||||||
|
(subtractmaskfromsilk false)
|
||||||
|
(outputformat 1)
|
||||||
|
(mirror false)
|
||||||
|
(drillshape 0)
|
||||||
|
(scaleselection 1)
|
||||||
|
(outputdirectory "output/")
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
|
||||||
|
(net 0 "")
|
||||||
|
|
||||||
|
(module "Library:QFN-20_EPthermal_4x4_Pitch0.5mm" (layer "F.Cu") (tedit 5A577FBB) (tstamp 45b7cde5-bc80-41b4-aa8e-41957f86bdb8)
|
||||||
|
(at 111.85 167.8)
|
||||||
|
(solder_mask_margin 0.05)
|
||||||
|
(attr smd)
|
||||||
|
(fp_text reference "U1" (at 3.1212 2.10262) (layer "F.SilkS")
|
||||||
|
(effects (font (size 0.6 0.6) (thickness 0.125)))
|
||||||
|
(tstamp 8b4262ff-30a3-4738-9376-1c809710ad89)
|
||||||
|
)
|
||||||
|
(fp_text value "DRV8662" (at -0.95 1.55) (layer "F.Fab")
|
||||||
|
(effects (font (size 0.2 0.2) (thickness 0.04)))
|
||||||
|
(tstamp 5f9a7236-4a12-4d4e-8a5e-887c58ad8dec)
|
||||||
|
)
|
||||||
|
(fp_line (start 1.5 2.15) (end 2.15 2.15) (layer "F.SilkS") (width 0.15) (tstamp 327d2c64-87cf-402c-afdd-ed5a14beeb7e))
|
||||||
|
(fp_line (start -1.5 2.15) (end -2.15 2.15) (layer "F.SilkS") (width 0.15) (tstamp 6a1ed244-ec32-45a6-b784-c506ab3c221b))
|
||||||
|
(fp_line (start -1.5 -2.15) (end -2.45 -2.15) (layer "F.SilkS") (width 0.15) (tstamp 75225048-9669-4639-ac49-c0a544a1eafa))
|
||||||
|
(fp_line (start 1.5 -2.15) (end 2.15 -2.15) (layer "F.SilkS") (width 0.15) (tstamp 7944d492-4921-47c1-a264-5b48b2ae90a5))
|
||||||
|
(fp_line (start 2.15 2.15) (end 2.15 1.5) (layer "F.SilkS") (width 0.15) (tstamp 7c24d088-1c24-4609-910e-7f97e05d7552))
|
||||||
|
(fp_line (start 2.15 -2.15) (end 2.15 -1.5) (layer "F.SilkS") (width 0.15) (tstamp c3ec1833-b076-414f-805b-967aa57886cd))
|
||||||
|
(fp_line (start -2.15 2.15) (end -2.15 1.5) (layer "F.SilkS") (width 0.15) (tstamp d2f67dea-2553-4e93-891f-77c862864ea6))
|
||||||
|
(fp_line (start -2.7 -2.7) (end 2.7 -2.7) (layer "F.CrtYd") (width 0.05) (tstamp 36f09194-9ad6-4b52-b405-d3bd5ea8e9e6))
|
||||||
|
(fp_line (start 2.7 2.7) (end -2.7 2.7) (layer "F.CrtYd") (width 0.05) (tstamp 6e9c91e8-ae74-4418-8f8a-46261d4f8e63))
|
||||||
|
(fp_line (start -2.7 2.7) (end -2.7 -2.7) (layer "F.CrtYd") (width 0.05) (tstamp deb91194-cc4f-4bb7-bf04-6785f76afef6))
|
||||||
|
(fp_line (start 2.7 -2.7) (end 2.7 2.7) (layer "F.CrtYd") (width 0.05) (tstamp e00ef1b1-d5b2-4815-8652-d067f42c7c52))
|
||||||
|
(fp_line (start 2 -2) (end -1 -2) (layer "F.Fab") (width 0.15) (tstamp 3a9112de-af1c-4faf-b4ab-9a961b86ff75))
|
||||||
|
(fp_line (start -2 -1) (end -2 2) (layer "F.Fab") (width 0.15) (tstamp 4e9f2468-ca53-4094-a969-dad35490bef5))
|
||||||
|
(fp_line (start -2 2) (end 2 2) (layer "F.Fab") (width 0.15) (tstamp 7d98b9b4-7fa5-4ec2-b289-94599c56eb28))
|
||||||
|
(fp_line (start 2 2) (end 2 -2) (layer "F.Fab") (width 0.15) (tstamp a8e95b8b-1ba3-4b98-a49a-a1379bbfc6a4))
|
||||||
|
(fp_line (start -1 -2) (end -2 -1) (layer "F.Fab") (width 0.15) (tstamp bb4d5b22-c955-448b-ba2c-e21d20421eb0))
|
||||||
|
(pad "" smd rect (at 0.7 -0.45 180) (size 1.15 0.5) (layers "F.Paste")
|
||||||
|
(solder_paste_margin -0.001) (solder_paste_margin_ratio -0.00001) (tstamp 53be17fd-90aa-45c2-8960-2aac1f09b2b7))
|
||||||
|
(pad "" smd rect (at 0.45 0 270) (size 2.5 0.5) (layers "F.Paste")
|
||||||
|
(solder_paste_margin -0.001) (solder_paste_margin_ratio -0.00001) (tstamp 7b955d4c-951f-47ab-9cb9-d3535edabc4d))
|
||||||
|
(pad "" smd rect (at -0.7 -0.45 180) (size 1.15 0.5) (layers "F.Paste")
|
||||||
|
(solder_paste_margin -0.001) (solder_paste_margin_ratio -0.00001) (tstamp 7f5d1a78-4bf0-4a63-a6a7-e9f734b54bca))
|
||||||
|
(pad "" smd rect (at -0.7 0.45 180) (size 1.15 0.5) (layers "F.Paste")
|
||||||
|
(solder_paste_margin -0.001) (solder_paste_margin_ratio -0.00001) (tstamp 8b4516fb-bc3a-404c-a00d-38569b343da5))
|
||||||
|
(pad "" smd rect (at 0.7 0.45 180) (size 1.15 0.5) (layers "F.Paste")
|
||||||
|
(solder_paste_margin -0.001) (solder_paste_margin_ratio -0.00001) (tstamp c8fba975-8e7c-403e-ae9c-49154d2b6189))
|
||||||
|
(pad "" smd rect (at -0.45 0 270) (size 2.5 0.5) (layers "F.Paste")
|
||||||
|
(solder_paste_margin -0.001) (solder_paste_margin_ratio -0.00001) (tstamp ef12e846-e57f-4e28-9f2e-3f00e11c197e))
|
||||||
|
(pad "1" smd oval (at -2 -1 90) (size 0.28 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 768a7468-1753-4223-902f-76af41e9fac5))
|
||||||
|
(pad "2" smd oval (at -2 -0.5 90) (size 0.28 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 6b1c48fe-8c58-4c07-84bd-19466c67d61e))
|
||||||
|
(pad "3" smd oval (at -2 0 90) (size 0.28 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp b4e991e0-48e3-4f1e-8958-eb74f1605ff3))
|
||||||
|
(pad "4" smd oval (at -2 0.5 90) (size 0.28 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp c469c387-729d-49e0-ba07-d3274e6750f2))
|
||||||
|
(pad "5" smd oval (at -2 1 90) (size 0.28 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 91136658-66ff-4f6e-a83a-eb428d0a82ec))
|
||||||
|
(pad "6" smd oval (at -1 2) (size 0.28 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp e6e435c1-f3b5-432d-baed-6a3b0d037e6f))
|
||||||
|
(pad "7" smd oval (at -0.5 2) (size 0.28 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 648b167b-9735-4366-8574-8291918326c0))
|
||||||
|
(pad "8" smd oval (at 0 2) (size 0.28 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp d4fc124e-fd92-44fe-bfff-dbde2578cede))
|
||||||
|
(pad "9" smd oval (at 0.5 2) (size 0.28 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 5a9cc9c0-cb48-4734-8d45-42b2d71efaa8))
|
||||||
|
(pad "10" smd oval (at 1 2) (size 0.28 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 5f46267a-8bbd-46df-b186-11bf6c0aeae2))
|
||||||
|
(pad "11" smd oval (at 2 1 90) (size 0.28 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 6e62e90e-49b3-4580-80df-b98eb8e6bdd3))
|
||||||
|
(pad "12" smd oval (at 2 0.5 90) (size 0.28 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 688d58dc-5cb4-4847-94fb-89376c16c1b1))
|
||||||
|
(pad "13" smd oval (at 2 0 90) (size 0.28 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 4e747f0e-c64a-47de-bbfc-9a80d6053f48))
|
||||||
|
(pad "14" smd oval (at 2 -0.5 90) (size 0.28 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp a86fee9b-e895-4625-af7b-1bbbcaa60a1b))
|
||||||
|
(pad "15" smd oval (at 2 -1 90) (size 0.28 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3a07e109-54f7-47e0-b916-a4bf49106377))
|
||||||
|
(pad "16" smd oval (at 1 -2) (size 0.28 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp b79e63c3-00af-402c-9f78-8748b728dabb))
|
||||||
|
(pad "17" smd oval (at 0.5 -2) (size 0.28 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp c49d8a2a-516e-4c7c-8a70-3d52e15a470e))
|
||||||
|
(pad "18" smd oval (at 0 -2) (size 0.28 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 73f5fd23-6004-41c3-93d4-82d07b0b753f))
|
||||||
|
(pad "19" smd oval (at -0.5 -2) (size 0.28 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 8c8282eb-b554-4fc9-a715-20220d73947d))
|
||||||
|
(pad "20" smd oval (at -1 -2) (size 0.28 0.9) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp b05e47c7-918e-499c-a5da-c457afef2e5c))
|
||||||
|
(pad "21" smd rect (at 0 0) (size 2.69 2.69) (layers "F.Cu" "F.Mask")
|
||||||
|
(solder_paste_margin -0.1) (solder_paste_margin_ratio -0.5) (tstamp 0ee5314f-6106-43e6-98d8-f37806cc06dc))
|
||||||
|
(pad "21" thru_hole circle (at 0 0) (size 0.45 0.45) (drill 0.3) (layers *.Cu)
|
||||||
|
(solder_paste_margin_ratio -0.5) (tstamp 2dc81eab-8a72-457b-8a91-39614ced35b3))
|
||||||
|
(pad "21" thru_hole circle (at 0.9 -0.9) (size 0.45 0.45) (drill 0.3) (layers *.Cu)
|
||||||
|
(solder_paste_margin_ratio -0.5) (tstamp 52012ffa-7aa6-4d85-84f0-9f2f9f9df1c4))
|
||||||
|
(pad "21" thru_hole circle (at 0 0.9) (size 0.45 0.45) (drill 0.3) (layers *.Cu)
|
||||||
|
(solder_paste_margin_ratio -0.5) (tstamp 5225ad7d-bb06-4401-bdb8-110ab2b0aade))
|
||||||
|
(pad "21" thru_hole circle (at 0.9 0.9) (size 0.45 0.45) (drill 0.3) (layers *.Cu)
|
||||||
|
(solder_paste_margin_ratio -0.5) (tstamp 6ea7d2d3-6d72-47b6-87b1-f7adc48bf14a))
|
||||||
|
(pad "21" thru_hole circle (at -0.9 -0.9) (size 0.45 0.45) (drill 0.3) (layers *.Cu)
|
||||||
|
(solder_paste_margin_ratio -0.5) (tstamp 70d30e2f-895f-491c-9c54-437a2ccac849))
|
||||||
|
(pad "21" thru_hole circle (at 0 -0.9) (size 0.45 0.45) (drill 0.3) (layers *.Cu)
|
||||||
|
(solder_paste_margin_ratio -0.5) (tstamp 77d71e37-7032-46a2-8537-6d07e9ba2472))
|
||||||
|
(pad "21" smd rect (at 0 0) (size 2.69 2.69) (layers "B.Cu")
|
||||||
|
(solder_paste_margin -0.1) (solder_paste_margin_ratio -0.5) (tstamp 8450d738-e08f-4bb2-8086-d58a63ba384c))
|
||||||
|
(pad "21" thru_hole circle (at -0.9 0) (size 0.45 0.45) (drill 0.3) (layers *.Cu)
|
||||||
|
(solder_paste_margin_ratio -0.5) (tstamp 8ff0f344-6a82-4ed0-96d9-64833fc41a86))
|
||||||
|
(pad "21" thru_hole circle (at 0.9 0) (size 0.45 0.45) (drill 0.3) (layers *.Cu)
|
||||||
|
(solder_paste_margin_ratio -0.5) (tstamp bfcd3d32-8e9a-4760-ae2b-b32e0778299a))
|
||||||
|
(pad "21" thru_hole circle (at -0.9 0.9) (size 0.45 0.45) (drill 0.3) (layers *.Cu)
|
||||||
|
(solder_paste_margin_ratio -0.5) (tstamp dba7fae7-a726-4eff-bcfe-fa5080a06b44))
|
||||||
|
)
|
||||||
|
|
||||||
|
)
|
||||||
|
|
@ -0,0 +1,429 @@
|
||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"design_settings": {
|
||||||
|
"defaults": {
|
||||||
|
"board_outline_line_width": 0.09999999999999999,
|
||||||
|
"copper_line_width": 0.19999999999999998,
|
||||||
|
"copper_text_italic": false,
|
||||||
|
"copper_text_size_h": 1.5,
|
||||||
|
"copper_text_size_v": 1.5,
|
||||||
|
"copper_text_thickness": 0.3,
|
||||||
|
"copper_text_upright": false,
|
||||||
|
"courtyard_line_width": 0.049999999999999996,
|
||||||
|
"dimension_precision": 1,
|
||||||
|
"dimension_units": 0,
|
||||||
|
"dimensions": {
|
||||||
|
"arrow_length": 1270000,
|
||||||
|
"extension_offset": 500000,
|
||||||
|
"keep_text_aligned": true,
|
||||||
|
"suppress_zeroes": false,
|
||||||
|
"text_position": 0,
|
||||||
|
"units_format": 1
|
||||||
|
},
|
||||||
|
"fab_line_width": 0.09999999999999999,
|
||||||
|
"fab_text_italic": false,
|
||||||
|
"fab_text_size_h": 1.0,
|
||||||
|
"fab_text_size_v": 1.0,
|
||||||
|
"fab_text_thickness": 0.15,
|
||||||
|
"fab_text_upright": false,
|
||||||
|
"other_line_width": 0.15,
|
||||||
|
"other_text_italic": false,
|
||||||
|
"other_text_size_h": 1.0,
|
||||||
|
"other_text_size_v": 1.0,
|
||||||
|
"other_text_thickness": 0.15,
|
||||||
|
"other_text_upright": false,
|
||||||
|
"pads": {
|
||||||
|
"drill": 0.762,
|
||||||
|
"height": 1.524,
|
||||||
|
"width": 1.524
|
||||||
|
},
|
||||||
|
"silk_line_width": 0.15,
|
||||||
|
"silk_text_italic": false,
|
||||||
|
"silk_text_size_h": 1.0,
|
||||||
|
"silk_text_size_v": 1.0,
|
||||||
|
"silk_text_thickness": 0.15,
|
||||||
|
"silk_text_upright": false,
|
||||||
|
"zones": {
|
||||||
|
"45_degree_only": false,
|
||||||
|
"min_clearance": 0.508
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"diff_pair_dimensions": [
|
||||||
|
{
|
||||||
|
"gap": 0.0,
|
||||||
|
"via_gap": 0.0,
|
||||||
|
"width": 0.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"drc_exclusions": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"rule_severities": {
|
||||||
|
"annular_width": "error",
|
||||||
|
"clearance": "error",
|
||||||
|
"copper_edge_clearance": "error",
|
||||||
|
"courtyards_overlap": "error",
|
||||||
|
"diff_pair_gap_out_of_range": "error",
|
||||||
|
"diff_pair_uncoupled_length_too_long": "error",
|
||||||
|
"drill_too_small": "error",
|
||||||
|
"duplicate_footprints": "warning",
|
||||||
|
"extra_footprint": "warning",
|
||||||
|
"hole_clearance": "error",
|
||||||
|
"hole_near_hole": "error",
|
||||||
|
"invalid_outline": "error",
|
||||||
|
"item_on_disabled_layer": "error",
|
||||||
|
"items_not_allowed": "error",
|
||||||
|
"keepout": "error",
|
||||||
|
"length_out_of_range": "error",
|
||||||
|
"malformed_courtyard": "error",
|
||||||
|
"microvia_drill_too_small": "error",
|
||||||
|
"missing_courtyard": "ignore",
|
||||||
|
"missing_footprint": "warning",
|
||||||
|
"net_conflict": "warning",
|
||||||
|
"npth_inside_courtyard": "ignore",
|
||||||
|
"padstack": "error",
|
||||||
|
"pth_inside_courtyard": "ignore",
|
||||||
|
"shorting_items": "error",
|
||||||
|
"silk_over_copper": "error",
|
||||||
|
"silk_overlap": "error",
|
||||||
|
"skew_out_of_range": "error",
|
||||||
|
"too_many_vias": "error",
|
||||||
|
"track_dangling": "warning",
|
||||||
|
"track_width": "error",
|
||||||
|
"tracks_crossing": "error",
|
||||||
|
"unconnected_items": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"via_dangling": "warning",
|
||||||
|
"via_hole_larger_than_pad": "error",
|
||||||
|
"zone_has_empty_net": "error",
|
||||||
|
"zones_intersect": "error"
|
||||||
|
},
|
||||||
|
"rules": {
|
||||||
|
"allow_blind_buried_vias": false,
|
||||||
|
"allow_microvias": false,
|
||||||
|
"max_error": 0.005,
|
||||||
|
"min_clearance": 0.0,
|
||||||
|
"min_copper_edge_clearance": 0.01,
|
||||||
|
"min_hole_to_hole": 0.25,
|
||||||
|
"min_microvia_diameter": 0.19999999999999998,
|
||||||
|
"min_microvia_drill": 0.09999999999999999,
|
||||||
|
"min_silk_clearance": 0.0,
|
||||||
|
"min_through_hole_diameter": 0.3,
|
||||||
|
"min_track_width": 0.19999999999999998,
|
||||||
|
"min_via_annular_width": 0.049999999999999996,
|
||||||
|
"min_via_annulus": 0.049999999999999996,
|
||||||
|
"min_via_diameter": 0.39999999999999997,
|
||||||
|
"solder_mask_clearance": 0.0,
|
||||||
|
"solder_mask_min_width": 0.0,
|
||||||
|
"solder_paste_clearance": 0.0,
|
||||||
|
"solder_paste_margin_ratio": 0.0
|
||||||
|
},
|
||||||
|
"track_widths": [
|
||||||
|
0.2
|
||||||
|
],
|
||||||
|
"via_dimensions": [
|
||||||
|
{
|
||||||
|
"diameter": 0.6,
|
||||||
|
"drill": 0.3
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"zones_allow_external_fillets": false,
|
||||||
|
"zones_use_no_outline": true
|
||||||
|
},
|
||||||
|
"layer_presets": []
|
||||||
|
},
|
||||||
|
"boards": [],
|
||||||
|
"cvpcb": {
|
||||||
|
"equivalence_files": []
|
||||||
|
},
|
||||||
|
"erc": {
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"pin_map": [
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"rule_severities": {
|
||||||
|
"bus_definition_conflict": "error",
|
||||||
|
"bus_label_syntax": "error",
|
||||||
|
"bus_to_bus_conflict": "error",
|
||||||
|
"bus_to_net_conflict": "error",
|
||||||
|
"different_unit_footprint": "error",
|
||||||
|
"different_unit_net": "error",
|
||||||
|
"duplicate_sheet_names": "error",
|
||||||
|
"global_label_dangling": "warning",
|
||||||
|
"hier_label_mismatch": "error",
|
||||||
|
"label_dangling": "error",
|
||||||
|
"lib_symbol_issues": "warning",
|
||||||
|
"multiple_net_names": "warning",
|
||||||
|
"net_not_bus_member": "warning",
|
||||||
|
"no_connect_connected": "error",
|
||||||
|
"no_connect_dangling": "error",
|
||||||
|
"pin_not_connected": "error",
|
||||||
|
"pin_not_driven": "error",
|
||||||
|
"pin_to_pin": "warning",
|
||||||
|
"similar_labels": "warning",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"wire_dangling": "error"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"libraries": {
|
||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "hole_pad_clearance.kicad_pro",
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_settings": {
|
||||||
|
"classes": [
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.2,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.2,
|
||||||
|
"via_diameter": 0.6,
|
||||||
|
"via_drill": 0.3,
|
||||||
|
"wire_width": 6.0
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.2,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "3volt",
|
||||||
|
"nets": [],
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.25,
|
||||||
|
"via_diameter": 0.6,
|
||||||
|
"via_drill": 0.3,
|
||||||
|
"wire_width": 6.0
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.2,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Power",
|
||||||
|
"nets": [],
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.5,
|
||||||
|
"via_diameter": 0.6,
|
||||||
|
"via_drill": 0.3,
|
||||||
|
"wire_width": 6.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_colors": null
|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "",
|
||||||
|
"vmrl": "",
|
||||||
|
"vrml": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": ""
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"drawing": {
|
||||||
|
"default_bus_thickness": 12.0,
|
||||||
|
"default_junction_size": 40.0,
|
||||||
|
"default_line_thickness": 6.0,
|
||||||
|
"default_text_size": 50.0,
|
||||||
|
"default_wire_thickness": 6.0,
|
||||||
|
"field_names": [],
|
||||||
|
"intersheets_ref_prefix": "",
|
||||||
|
"intersheets_ref_short": false,
|
||||||
|
"intersheets_ref_show": false,
|
||||||
|
"intersheets_ref_suffix": "",
|
||||||
|
"pin_symbol_size": 25.0,
|
||||||
|
"text_offset_ratio": 0.3
|
||||||
|
},
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_format_name": "Pcbnew",
|
||||||
|
"page_layout_descr_file": "",
|
||||||
|
"plot_directory": "output/",
|
||||||
|
"spice_adjust_passive_values": false,
|
||||||
|
"spice_external_command": "spice \"%I\"",
|
||||||
|
"subpart_first_id": 65,
|
||||||
|
"subpart_id_separator": 0
|
||||||
|
},
|
||||||
|
"sheets": [
|
||||||
|
[
|
||||||
|
"eae8b250-f694-468f-ad9f-c2e3304daf14",
|
||||||
|
""
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"text_variables": {}
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,463 @@
|
||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"design_settings": {
|
||||||
|
"defaults": {
|
||||||
|
"board_outline_line_width": 0.15239999999999998,
|
||||||
|
"copper_line_width": 0.15239999999999998,
|
||||||
|
"copper_text_italic": false,
|
||||||
|
"copper_text_size_h": 0.8128,
|
||||||
|
"copper_text_size_v": 0.8128,
|
||||||
|
"copper_text_thickness": 0.15239999999999998,
|
||||||
|
"copper_text_upright": false,
|
||||||
|
"courtyard_line_width": 0.049999999999999996,
|
||||||
|
"dimension_precision": 1,
|
||||||
|
"dimension_units": 0,
|
||||||
|
"dimensions": {
|
||||||
|
"arrow_length": 1270000,
|
||||||
|
"extension_offset": 500000,
|
||||||
|
"keep_text_aligned": true,
|
||||||
|
"suppress_zeroes": false,
|
||||||
|
"text_position": 0,
|
||||||
|
"units_format": 1
|
||||||
|
},
|
||||||
|
"fab_line_width": 0.15239999999999998,
|
||||||
|
"fab_text_italic": false,
|
||||||
|
"fab_text_size_h": 1.0,
|
||||||
|
"fab_text_size_v": 1.0,
|
||||||
|
"fab_text_thickness": 0.15,
|
||||||
|
"fab_text_upright": false,
|
||||||
|
"other_line_width": 0.15239999999999998,
|
||||||
|
"other_text_italic": false,
|
||||||
|
"other_text_size_h": 1.0,
|
||||||
|
"other_text_size_v": 1.0,
|
||||||
|
"other_text_thickness": 0.15,
|
||||||
|
"other_text_upright": false,
|
||||||
|
"pads": {
|
||||||
|
"drill": 0.0,
|
||||||
|
"height": 1.80086,
|
||||||
|
"width": 2.49936
|
||||||
|
},
|
||||||
|
"silk_line_width": 0.15239999999999998,
|
||||||
|
"silk_text_italic": false,
|
||||||
|
"silk_text_size_h": 0.8128,
|
||||||
|
"silk_text_size_v": 0.8128,
|
||||||
|
"silk_text_thickness": 0.15239999999999998,
|
||||||
|
"silk_text_upright": false,
|
||||||
|
"zones": {
|
||||||
|
"45_degree_only": false,
|
||||||
|
"min_clearance": 0.2032
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"diff_pair_dimensions": [
|
||||||
|
{
|
||||||
|
"gap": 0.0,
|
||||||
|
"via_gap": 0.0,
|
||||||
|
"width": 0.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"drc_exclusions": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"rule_severities": {
|
||||||
|
"annular_width": "error",
|
||||||
|
"clearance": "error",
|
||||||
|
"copper_edge_clearance": "error",
|
||||||
|
"courtyards_overlap": "error",
|
||||||
|
"diff_pair_gap_out_of_range": "error",
|
||||||
|
"diff_pair_uncoupled_length_too_long": "error",
|
||||||
|
"drill_too_small": "error",
|
||||||
|
"duplicate_footprints": "warning",
|
||||||
|
"extra_footprint": "warning",
|
||||||
|
"hole_clearance": "error",
|
||||||
|
"hole_near_hole": "error",
|
||||||
|
"invalid_outline": "error",
|
||||||
|
"item_on_disabled_layer": "error",
|
||||||
|
"items_not_allowed": "error",
|
||||||
|
"keepout": "error",
|
||||||
|
"length_out_of_range": "error",
|
||||||
|
"malformed_courtyard": "error",
|
||||||
|
"microvia_drill_too_small": "error",
|
||||||
|
"missing_courtyard": "ignore",
|
||||||
|
"missing_footprint": "warning",
|
||||||
|
"net_conflict": "warning",
|
||||||
|
"npth_inside_courtyard": "ignore",
|
||||||
|
"padstack": "error",
|
||||||
|
"pth_inside_courtyard": "ignore",
|
||||||
|
"shorting_items": "error",
|
||||||
|
"silk_over_copper": "error",
|
||||||
|
"silk_overlap": "error",
|
||||||
|
"skew_out_of_range": "error",
|
||||||
|
"too_many_vias": "error",
|
||||||
|
"track_dangling": "warning",
|
||||||
|
"track_width": "error",
|
||||||
|
"tracks_crossing": "error",
|
||||||
|
"unconnected_items": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"via_dangling": "warning",
|
||||||
|
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|
||||||
|
"zone_has_empty_net": "error",
|
||||||
|
"zones_intersect": "error"
|
||||||
|
},
|
||||||
|
"rules": {
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
0.3048,
|
||||||
|
0.4064,
|
||||||
|
0.508,
|
||||||
|
0.6096,
|
||||||
|
0.8128,
|
||||||
|
1.016,
|
||||||
|
1.27,
|
||||||
|
1.524,
|
||||||
|
1.778,
|
||||||
|
2.032
|
||||||
|
],
|
||||||
|
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|
||||||
|
{
|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
{
|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
{
|
||||||
|
"diameter": 0.7,
|
||||||
|
"drill": 0.4
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"diameter": 0.8,
|
||||||
|
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|
||||||
|
},
|
||||||
|
{
|
||||||
|
"diameter": 0.9,
|
||||||
|
"drill": 0.6
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"diameter": 1.0,
|
||||||
|
"drill": 0.7
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"zones_allow_external_fillets": false,
|
||||||
|
"zones_use_no_outline": false
|
||||||
|
},
|
||||||
|
"layer_presets": []
|
||||||
|
},
|
||||||
|
"boards": [],
|
||||||
|
"cvpcb": {
|
||||||
|
"equivalence_files": []
|
||||||
|
},
|
||||||
|
"erc": {
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
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|
||||||
|
[
|
||||||
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|
||||||
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||||||
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|
||||||
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||||||
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[
|
||||||
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|
||||||
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||||||
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||||||
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||||||
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||||||
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|
||||||
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|
||||||
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|
||||||
|
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||||||
|
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|
||||||
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[
|
||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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[
|
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||||||
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||||||
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||||||
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|
||||||
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|
||||||
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1,
|
||||||
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2
|
||||||
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|
||||||
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[
|
||||||
|
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|
||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
1,
|
||||||
|
1,
|
||||||
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1,
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||||||
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1,
|
||||||
|
1,
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||||||
|
1,
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||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
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0,
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||||||
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1,
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||||||
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0,
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||||||
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1,
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||||||
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0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
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2,
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||||||
|
0,
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||||||
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1,
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||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
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1,
|
||||||
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0,
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||||||
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1,
|
||||||
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0,
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||||||
|
2,
|
||||||
|
0,
|
||||||
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0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
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||||||
|
1,
|
||||||
|
0,
|
||||||
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1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"rule_severities": {
|
||||||
|
"bus_definition_conflict": "error",
|
||||||
|
"bus_label_syntax": "error",
|
||||||
|
"bus_to_bus_conflict": "error",
|
||||||
|
"bus_to_net_conflict": "error",
|
||||||
|
"different_unit_footprint": "error",
|
||||||
|
"different_unit_net": "error",
|
||||||
|
"duplicate_sheet_names": "error",
|
||||||
|
"global_label_dangling": "error",
|
||||||
|
"hier_label_mismatch": "error",
|
||||||
|
"label_dangling": "error",
|
||||||
|
"lib_symbol_issues": "warning",
|
||||||
|
"multiple_net_names": "error",
|
||||||
|
"net_not_bus_member": "error",
|
||||||
|
"no_connect_connected": "error",
|
||||||
|
"no_connect_dangling": "error",
|
||||||
|
"pin_not_connected": "error",
|
||||||
|
"pin_not_driven": "error",
|
||||||
|
"pin_to_pin": "warning",
|
||||||
|
"similar_labels": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"wire_dangling": "error"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"libraries": {
|
||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "001.04.010.1020.kicad_pro",
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_settings": {
|
||||||
|
"classes": [
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.2,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.254,
|
||||||
|
"via_diameter": 0.6,
|
||||||
|
"via_drill": 0.3,
|
||||||
|
"wire_width": 6.0
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"bus_width": 6.0,
|
||||||
|
"clearance": 0.4,
|
||||||
|
"diff_pair_gap": 0.2032,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2032,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.6,
|
||||||
|
"microvia_drill": 0.3,
|
||||||
|
"name": "100V",
|
||||||
|
"nets": [],
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.254,
|
||||||
|
"via_diameter": 0.6,
|
||||||
|
"via_drill": 0.3,
|
||||||
|
"wire_width": 6.0
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"bus_width": 6.0,
|
||||||
|
"clearance": 0.8,
|
||||||
|
"diff_pair_gap": 0.508,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.508,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.6,
|
||||||
|
"microvia_drill": 0.3,
|
||||||
|
"name": "170V",
|
||||||
|
"nets": [
|
||||||
|
"/170V"
|
||||||
|
],
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.4064,
|
||||||
|
"via_diameter": 0.6,
|
||||||
|
"via_drill": 0.3,
|
||||||
|
"wire_width": 6.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"hidden_nets": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_colors": null
|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "../../Mech/001.04.010.1020.step",
|
||||||
|
"vmrl": "../../Mech/001.04.010.0620.wrl",
|
||||||
|
"vrml": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": ""
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"drawing": {
|
||||||
|
"default_bus_thickness": 12.0,
|
||||||
|
"default_junction_size": 20.0,
|
||||||
|
"default_line_thickness": 6.0,
|
||||||
|
"default_text_size": 40.0,
|
||||||
|
"default_wire_thickness": 6.0,
|
||||||
|
"field_names": [],
|
||||||
|
"intersheets_ref_prefix": "[",
|
||||||
|
"intersheets_ref_short": false,
|
||||||
|
"intersheets_ref_show": false,
|
||||||
|
"intersheets_ref_suffix": "]",
|
||||||
|
"pin_symbol_size": 25.0,
|
||||||
|
"text_offset_ratio": 0.3
|
||||||
|
},
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_format_name": "",
|
||||||
|
"page_layout_descr_file": "",
|
||||||
|
"plot_directory": "",
|
||||||
|
"spice_adjust_passive_values": false,
|
||||||
|
"spice_external_command": "spice \"%I\"",
|
||||||
|
"subpart_first_id": 65,
|
||||||
|
"subpart_id_separator": 0
|
||||||
|
},
|
||||||
|
"sheets": [
|
||||||
|
[
|
||||||
|
"8fbdd1bf-c6bc-48ff-8b55-861d7eb93f67",
|
||||||
|
""
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"text_variables": {}
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,494 @@
|
||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"design_settings": {
|
||||||
|
"defaults": {
|
||||||
|
"board_outline_line_width": 0.049999999999999996,
|
||||||
|
"copper_line_width": 0.19999999999999998,
|
||||||
|
"copper_text_italic": false,
|
||||||
|
"copper_text_size_h": 1.5,
|
||||||
|
"copper_text_size_v": 1.5,
|
||||||
|
"copper_text_thickness": 0.3,
|
||||||
|
"copper_text_upright": true,
|
||||||
|
"courtyard_line_width": 0.049999999999999996,
|
||||||
|
"dimension_precision": 1,
|
||||||
|
"dimension_units": 2,
|
||||||
|
"dimensions": {
|
||||||
|
"arrow_length": 1270000,
|
||||||
|
"extension_offset": 500000,
|
||||||
|
"keep_text_aligned": true,
|
||||||
|
"suppress_zeroes": false,
|
||||||
|
"text_position": 0,
|
||||||
|
"units_format": 1
|
||||||
|
},
|
||||||
|
"fab_line_width": 0.09999999999999999,
|
||||||
|
"fab_text_italic": false,
|
||||||
|
"fab_text_size_h": 1.0,
|
||||||
|
"fab_text_size_v": 1.0,
|
||||||
|
"fab_text_thickness": 0.15,
|
||||||
|
"fab_text_upright": true,
|
||||||
|
"other_line_width": 0.09999999999999999,
|
||||||
|
"other_text_italic": false,
|
||||||
|
"other_text_size_h": 1.0,
|
||||||
|
"other_text_size_v": 1.0,
|
||||||
|
"other_text_thickness": 0.15,
|
||||||
|
"other_text_upright": true,
|
||||||
|
"pads": {
|
||||||
|
"drill": 0.0,
|
||||||
|
"height": 1.0,
|
||||||
|
"width": 1.0
|
||||||
|
},
|
||||||
|
"silk_line_width": 0.12,
|
||||||
|
"silk_text_italic": false,
|
||||||
|
"silk_text_size_h": 1.0,
|
||||||
|
"silk_text_size_v": 1.0,
|
||||||
|
"silk_text_thickness": 0.15,
|
||||||
|
"silk_text_upright": true,
|
||||||
|
"zones": {
|
||||||
|
"45_degree_only": false,
|
||||||
|
"min_clearance": 0.19999999999999998
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"diff_pair_dimensions": [
|
||||||
|
{
|
||||||
|
"gap": 0.0,
|
||||||
|
"via_gap": 0.0,
|
||||||
|
"width": 0.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"drc_exclusions": [
|
||||||
|
"clearance|87150000|140800000|713a642e-4662-4581-a311-4a183ae3a0a4|0e2e2e70-712c-4a91-9883-5badae873369",
|
||||||
|
"courtyards_overlap|102580000|139229999|00000000-0000-0000-0000-00005db27222|00000000-0000-0000-0000-00005e4ffe1e",
|
||||||
|
"courtyards_overlap|102580000|142700000|00000000-0000-0000-0000-00005db270f4|00000000-0000-0000-0000-00005e4ffe1e",
|
||||||
|
"courtyards_overlap|116660000|142900000|00000000-0000-0000-0000-00005db26ea8|00000000-0000-0000-0000-00005db2741b",
|
||||||
|
"courtyards_overlap|126820000|142900000|00000000-0000-0000-0000-00005db272bc|00000000-0000-0000-0000-00005db2741b",
|
||||||
|
"courtyards_overlap|144725000|118017468|00000000-0000-0000-0000-00005d888938|00000000-0000-0000-0000-00005e2b4dc2",
|
||||||
|
"courtyards_overlap|86925000|140617468|00000000-0000-0000-0000-00005db273cf|00000000-0000-0000-0000-00005e2b4dc5"
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 2
|
||||||
|
},
|
||||||
|
"rule_severities": {
|
||||||
|
"annular_width": "error",
|
||||||
|
"clearance": "error",
|
||||||
|
"copper_edge_clearance": "ignore",
|
||||||
|
"courtyards_overlap": "error",
|
||||||
|
"diff_pair_gap_out_of_range": "error",
|
||||||
|
"diff_pair_uncoupled_length_too_long": "error",
|
||||||
|
"drill_out_of_range": "error",
|
||||||
|
"duplicate_footprints": "warning",
|
||||||
|
"extra_footprint": "warning",
|
||||||
|
"hole_clearance": "error",
|
||||||
|
"hole_near_hole": "error",
|
||||||
|
"invalid_outline": "error",
|
||||||
|
"item_on_disabled_layer": "error",
|
||||||
|
"items_not_allowed": "error",
|
||||||
|
"length_out_of_range": "error",
|
||||||
|
"malformed_courtyard": "error",
|
||||||
|
"microvia_drill_out_of_range": "error",
|
||||||
|
"missing_courtyard": "ignore",
|
||||||
|
"missing_footprint": "warning",
|
||||||
|
"net_conflict": "warning",
|
||||||
|
"npth_inside_courtyard": "ignore",
|
||||||
|
"padstack": "error",
|
||||||
|
"pth_inside_courtyard": "ignore",
|
||||||
|
"shorting_items": "error",
|
||||||
|
"silk_over_copper": "ignore",
|
||||||
|
"silk_overlap": "ignore",
|
||||||
|
"skew_out_of_range": "error",
|
||||||
|
"too_many_vias": "error",
|
||||||
|
"track_dangling": "warning",
|
||||||
|
"track_width": "error",
|
||||||
|
"tracks_crossing": "error",
|
||||||
|
"unconnected_items": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"via_dangling": "warning",
|
||||||
|
"zone_has_empty_net": "error",
|
||||||
|
"zones_intersect": "error"
|
||||||
|
},
|
||||||
|
"rules": {
|
||||||
|
"allow_blind_buried_vias": false,
|
||||||
|
"allow_microvias": false,
|
||||||
|
"max_error": 0.005,
|
||||||
|
"min_clearance": 0.0,
|
||||||
|
"min_copper_edge_clearance": 0.01,
|
||||||
|
"min_hole_clearance": 0.0,
|
||||||
|
"min_hole_to_hole": 0.25,
|
||||||
|
"min_microvia_diameter": 0.19999999999999998,
|
||||||
|
"min_microvia_drill": 0.09999999999999999,
|
||||||
|
"min_silk_clearance": 0.0,
|
||||||
|
"min_through_hole_diameter": 0.3,
|
||||||
|
"min_track_width": 0.19999999999999998,
|
||||||
|
"min_via_annular_width": 0.049999999999999996,
|
||||||
|
"min_via_annulus": 0.049999999999999996,
|
||||||
|
"min_via_diameter": 0.39999999999999997,
|
||||||
|
"use_height_for_length_calcs": true
|
||||||
|
},
|
||||||
|
"track_widths": [
|
||||||
|
0.25,
|
||||||
|
0.2,
|
||||||
|
0.4,
|
||||||
|
1.0,
|
||||||
|
2.0
|
||||||
|
],
|
||||||
|
"via_dimensions": [
|
||||||
|
{
|
||||||
|
"diameter": 0.85,
|
||||||
|
"drill": 0.4
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"zones_allow_external_fillets": false,
|
||||||
|
"zones_use_no_outline": true
|
||||||
|
},
|
||||||
|
"layer_presets": [
|
||||||
|
{
|
||||||
|
"activeLayer": -2,
|
||||||
|
"layers": [
|
||||||
|
3,
|
||||||
|
4,
|
||||||
|
5,
|
||||||
|
6,
|
||||||
|
7,
|
||||||
|
8,
|
||||||
|
9,
|
||||||
|
10,
|
||||||
|
11,
|
||||||
|
12,
|
||||||
|
13,
|
||||||
|
14,
|
||||||
|
15,
|
||||||
|
16,
|
||||||
|
17,
|
||||||
|
18,
|
||||||
|
19,
|
||||||
|
20,
|
||||||
|
21,
|
||||||
|
22,
|
||||||
|
23,
|
||||||
|
24,
|
||||||
|
25,
|
||||||
|
26,
|
||||||
|
27,
|
||||||
|
28,
|
||||||
|
29,
|
||||||
|
30,
|
||||||
|
41,
|
||||||
|
44,
|
||||||
|
49,
|
||||||
|
50
|
||||||
|
],
|
||||||
|
"name": "Fabrication",
|
||||||
|
"renderLayers": [
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
129,
|
||||||
|
130,
|
||||||
|
131,
|
||||||
|
133,
|
||||||
|
134,
|
||||||
|
135,
|
||||||
|
136,
|
||||||
|
137,
|
||||||
|
138,
|
||||||
|
139,
|
||||||
|
143,
|
||||||
|
144
|
||||||
|
]
|
||||||
|
}
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"boards": [],
|
||||||
|
"cvpcb": {
|
||||||
|
"equivalence_files": []
|
||||||
|
},
|
||||||
|
"erc": {
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"pin_map": [
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
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|
||||||
|
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|
||||||
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||||||
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||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
[
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
2,
|
||||||
|
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|
||||||
|
2,
|
||||||
|
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|
||||||
|
],
|
||||||
|
[
|
||||||
|
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|
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||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"rule_severities": {
|
||||||
|
"bus_definition_conflict": "error",
|
||||||
|
"bus_label_syntax": "error",
|
||||||
|
"bus_to_bus_conflict": "error",
|
||||||
|
"bus_to_net_conflict": "error",
|
||||||
|
"different_unit_footprint": "error",
|
||||||
|
"different_unit_net": "error",
|
||||||
|
"duplicate_sheet_names": "error",
|
||||||
|
"global_label_dangling": "error",
|
||||||
|
"hier_label_mismatch": "error",
|
||||||
|
"label_dangling": "error",
|
||||||
|
"lib_symbol_issues": "warning",
|
||||||
|
"multiple_net_names": "error",
|
||||||
|
"net_not_bus_member": "error",
|
||||||
|
"no_connect_connected": "error",
|
||||||
|
"no_connect_dangling": "error",
|
||||||
|
"pin_not_connected": "error",
|
||||||
|
"pin_not_driven": "error",
|
||||||
|
"pin_to_pin": "warning",
|
||||||
|
"similar_labels": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"wire_dangling": "error"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"libraries": {
|
||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "LoRaNode.kicad_pro",
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_settings": {
|
||||||
|
"classes": [
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.2,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.25,
|
||||||
|
"via_diameter": 0.85,
|
||||||
|
"via_drill": 0.4,
|
||||||
|
"wire_width": 6.0
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.25,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "antenna",
|
||||||
|
"nets": [
|
||||||
|
"/ANTENNA"
|
||||||
|
],
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 1.27,
|
||||||
|
"via_diameter": 0.85,
|
||||||
|
"via_drill": 0.4,
|
||||||
|
"wire_width": 6.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_colors": null
|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "",
|
||||||
|
"vmrl": "",
|
||||||
|
"vrml": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": ""
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"drawing": {
|
||||||
|
"default_bus_thickness": 12.0,
|
||||||
|
"default_junction_size": 40.0,
|
||||||
|
"default_line_thickness": 6.0,
|
||||||
|
"default_text_size": 50.0,
|
||||||
|
"default_wire_thickness": 6.0,
|
||||||
|
"field_names": [],
|
||||||
|
"intersheets_ref_prefix": "[",
|
||||||
|
"intersheets_ref_short": false,
|
||||||
|
"intersheets_ref_show": false,
|
||||||
|
"intersheets_ref_suffix": "]",
|
||||||
|
"pin_symbol_size": 25.0,
|
||||||
|
"text_offset_ratio": 0.3
|
||||||
|
},
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_format_name": "",
|
||||||
|
"page_layout_descr_file": "",
|
||||||
|
"plot_directory": "./",
|
||||||
|
"spice_adjust_passive_values": false,
|
||||||
|
"spice_external_command": "spice \"%I\"",
|
||||||
|
"subpart_first_id": 65,
|
||||||
|
"subpart_id_separator": 0
|
||||||
|
},
|
||||||
|
"sheets": [
|
||||||
|
[
|
||||||
|
"285a99a7-a1a2-4aa6-812b-d3c3533a57d7",
|
||||||
|
""
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"00000000-0000-0000-0000-00005d8236a8",
|
||||||
|
"battery-protection"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"00000000-0000-0000-0000-00005d8260b7",
|
||||||
|
"voltage-regulation"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"00000000-0000-0000-0000-00005d825820",
|
||||||
|
"RS485-interface"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"00000000-0000-0000-0000-00005d84b44c",
|
||||||
|
"I2C-interface"
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"text_variables": {}
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,397 @@
|
||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"design_settings": {
|
||||||
|
"defaults": {
|
||||||
|
"board_outline_line_width": 0.049999999999999996,
|
||||||
|
"copper_line_width": 0.19999999999999998,
|
||||||
|
"copper_text_italic": false,
|
||||||
|
"copper_text_size_h": 1.5,
|
||||||
|
"copper_text_size_v": 1.5,
|
||||||
|
"copper_text_thickness": 0.3,
|
||||||
|
"copper_text_upright": false,
|
||||||
|
"courtyard_line_width": 0.049999999999999996,
|
||||||
|
"dimension_precision": 4,
|
||||||
|
"dimension_units": 0,
|
||||||
|
"dimensions": {
|
||||||
|
"arrow_length": 1270000,
|
||||||
|
"extension_offset": 500000,
|
||||||
|
"keep_text_aligned": true,
|
||||||
|
"suppress_zeroes": false,
|
||||||
|
"text_position": 0,
|
||||||
|
"units_format": 1
|
||||||
|
},
|
||||||
|
"fab_line_width": 0.09999999999999999,
|
||||||
|
"fab_text_italic": false,
|
||||||
|
"fab_text_size_h": 1.0,
|
||||||
|
"fab_text_size_v": 1.0,
|
||||||
|
"fab_text_thickness": 0.15,
|
||||||
|
"fab_text_upright": false,
|
||||||
|
"other_line_width": 0.09999999999999999,
|
||||||
|
"other_text_italic": false,
|
||||||
|
"other_text_size_h": 1.0,
|
||||||
|
"other_text_size_v": 1.0,
|
||||||
|
"other_text_thickness": 0.15,
|
||||||
|
"other_text_upright": false,
|
||||||
|
"pads": {
|
||||||
|
"drill": 0.762,
|
||||||
|
"height": 1.524,
|
||||||
|
"width": 1.524
|
||||||
|
},
|
||||||
|
"silk_line_width": 0.12,
|
||||||
|
"silk_text_italic": false,
|
||||||
|
"silk_text_size_h": 1.0,
|
||||||
|
"silk_text_size_v": 1.0,
|
||||||
|
"silk_text_thickness": 0.15,
|
||||||
|
"silk_text_upright": false,
|
||||||
|
"zones": {
|
||||||
|
"45_degree_only": false,
|
||||||
|
"min_clearance": 0.508
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"diff_pair_dimensions": [
|
||||||
|
{
|
||||||
|
"gap": 0.0,
|
||||||
|
"via_gap": 0.0,
|
||||||
|
"width": 0.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"drc_exclusions": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"rule_severities": {
|
||||||
|
"annular_width": "error",
|
||||||
|
"clearance": "error",
|
||||||
|
"copper_edge_clearance": "error",
|
||||||
|
"courtyards_overlap": "error",
|
||||||
|
"diff_pair_gap_out_of_range": "error",
|
||||||
|
"diff_pair_uncoupled_length_too_long": "error",
|
||||||
|
"drill_too_small": "error",
|
||||||
|
"duplicate_footprints": "warning",
|
||||||
|
"extra_footprint": "warning",
|
||||||
|
"hole_clearance": "error",
|
||||||
|
"hole_near_hole": "error",
|
||||||
|
"invalid_outline": "error",
|
||||||
|
"item_on_disabled_layer": "error",
|
||||||
|
"items_not_allowed": "error",
|
||||||
|
"keepout": "error",
|
||||||
|
"length_out_of_range": "error",
|
||||||
|
"malformed_courtyard": "error",
|
||||||
|
"microvia_drill_too_small": "error",
|
||||||
|
"missing_courtyard": "ignore",
|
||||||
|
"missing_footprint": "warning",
|
||||||
|
"net_conflict": "warning",
|
||||||
|
"npth_inside_courtyard": "ignore",
|
||||||
|
"padstack": "error",
|
||||||
|
"pth_inside_courtyard": "ignore",
|
||||||
|
"shorting_items": "error",
|
||||||
|
"silk_over_copper": "error",
|
||||||
|
"silk_overlap": "error",
|
||||||
|
"skew_out_of_range": "error",
|
||||||
|
"too_many_vias": "error",
|
||||||
|
"track_dangling": "warning",
|
||||||
|
"track_width": "error",
|
||||||
|
"tracks_crossing": "error",
|
||||||
|
"unconnected_items": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"via_dangling": "warning",
|
||||||
|
"via_hole_larger_than_pad": "error",
|
||||||
|
"zone_has_empty_net": "error",
|
||||||
|
"zones_intersect": "error"
|
||||||
|
},
|
||||||
|
"rules": {
|
||||||
|
"allow_blind_buried_vias": false,
|
||||||
|
"allow_microvias": false,
|
||||||
|
"max_error": 0.005,
|
||||||
|
"min_clearance": 0.0,
|
||||||
|
"min_copper_edge_clearance": 0.01,
|
||||||
|
"min_hole_to_hole": 0.25,
|
||||||
|
"min_microvia_diameter": 0.19999999999999998,
|
||||||
|
"min_microvia_drill": 0.09999999999999999,
|
||||||
|
"min_silk_clearance": 0.0,
|
||||||
|
"min_through_hole_diameter": 0.3,
|
||||||
|
"min_track_width": 0.19999999999999998,
|
||||||
|
"min_via_annular_width": 0.049999999999999996,
|
||||||
|
"min_via_annulus": 0.049999999999999996,
|
||||||
|
"min_via_diameter": 0.39999999999999997,
|
||||||
|
"solder_mask_clearance": 0.0,
|
||||||
|
"solder_mask_min_width": 0.0,
|
||||||
|
"solder_paste_clearance": 0.0,
|
||||||
|
"solder_paste_margin_ratio": -0.0
|
||||||
|
},
|
||||||
|
"track_widths": [
|
||||||
|
0.25,
|
||||||
|
0.7,
|
||||||
|
0.8,
|
||||||
|
1.0,
|
||||||
|
1.5
|
||||||
|
],
|
||||||
|
"via_dimensions": [
|
||||||
|
{
|
||||||
|
"diameter": 0.8,
|
||||||
|
"drill": 0.4
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"zones_allow_external_fillets": false,
|
||||||
|
"zones_use_no_outline": true
|
||||||
|
},
|
||||||
|
"layer_presets": []
|
||||||
|
},
|
||||||
|
"boards": [],
|
||||||
|
"cvpcb": {
|
||||||
|
"equivalence_files": []
|
||||||
|
},
|
||||||
|
"erc": {
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"pin_map": [
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
1,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
1,
|
||||||
|
0,
|
||||||
|
2,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"rule_severities": {
|
||||||
|
"bus_definition_conflict": "error",
|
||||||
|
"bus_label_syntax": "error",
|
||||||
|
"bus_to_bus_conflict": "error",
|
||||||
|
"bus_to_net_conflict": "error",
|
||||||
|
"different_unit_footprint": "error",
|
||||||
|
"different_unit_net": "error",
|
||||||
|
"duplicate_sheet_names": "error",
|
||||||
|
"global_label_dangling": "error",
|
||||||
|
"hier_label_mismatch": "error",
|
||||||
|
"label_dangling": "error",
|
||||||
|
"lib_symbol_issues": "warning",
|
||||||
|
"multiple_net_names": "error",
|
||||||
|
"net_not_bus_member": "error",
|
||||||
|
"no_connect_connected": "error",
|
||||||
|
"no_connect_dangling": "error",
|
||||||
|
"pin_not_connected": "error",
|
||||||
|
"pin_not_driven": "error",
|
||||||
|
"pin_to_pin": "warning",
|
||||||
|
"similar_labels": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"wire_dangling": "error"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"libraries": {
|
||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "moas_ii_adapter.kicad_pro",
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_settings": {
|
||||||
|
"classes": [
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.2,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.25,
|
||||||
|
"via_diameter": 0.8,
|
||||||
|
"via_drill": 0.4,
|
||||||
|
"wire_width": 6.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_colors": null
|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "",
|
||||||
|
"vmrl": "",
|
||||||
|
"vrml": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": ""
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"drawing": {
|
||||||
|
"default_bus_thickness": 12.0,
|
||||||
|
"default_junction_size": 40.0,
|
||||||
|
"default_line_thickness": 6.0,
|
||||||
|
"default_text_size": 50.0,
|
||||||
|
"default_wire_thickness": 6.0,
|
||||||
|
"field_names": [],
|
||||||
|
"intersheets_ref_prefix": "",
|
||||||
|
"intersheets_ref_short": false,
|
||||||
|
"intersheets_ref_show": false,
|
||||||
|
"intersheets_ref_suffix": "",
|
||||||
|
"pin_symbol_size": 25.0,
|
||||||
|
"text_offset_ratio": 0.3
|
||||||
|
},
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_format_name": "",
|
||||||
|
"page_layout_descr_file": "",
|
||||||
|
"plot_directory": "",
|
||||||
|
"spice_adjust_passive_values": false,
|
||||||
|
"spice_external_command": "spice \"%I\"",
|
||||||
|
"subpart_first_id": 65,
|
||||||
|
"subpart_id_separator": 0
|
||||||
|
},
|
||||||
|
"sheets": [
|
||||||
|
[
|
||||||
|
"4d0c44c6-6b27-4aba-bf02-414b7fcd0edc",
|
||||||
|
""
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"text_variables": {}
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,639 @@
|
||||||
|
(kicad_pcb (version 20201116) (generator pcbnew)
|
||||||
|
|
||||||
|
(general
|
||||||
|
(thickness 1.6)
|
||||||
|
)
|
||||||
|
|
||||||
|
(paper "A4")
|
||||||
|
(layers
|
||||||
|
(0 "F.Cu" signal)
|
||||||
|
(1 "In1.Cu" signal)
|
||||||
|
(2 "In2.Cu" signal)
|
||||||
|
(31 "B.Cu" signal)
|
||||||
|
(32 "B.Adhes" user "B.Adhesive")
|
||||||
|
(33 "F.Adhes" user "F.Adhesive")
|
||||||
|
(34 "B.Paste" user)
|
||||||
|
(35 "F.Paste" user)
|
||||||
|
(36 "B.SilkS" user "B.Silkscreen")
|
||||||
|
(37 "F.SilkS" user "F.Silkscreen")
|
||||||
|
(38 "B.Mask" user)
|
||||||
|
(39 "F.Mask" user)
|
||||||
|
(40 "Dwgs.User" user "User.Drawings")
|
||||||
|
(41 "Cmts.User" user "User.Comments")
|
||||||
|
(42 "Eco1.User" user "User.Eco1")
|
||||||
|
(43 "Eco2.User" user "User.Eco2")
|
||||||
|
(44 "Edge.Cuts" user)
|
||||||
|
(45 "Margin" user)
|
||||||
|
(46 "B.CrtYd" user "B.Courtyard")
|
||||||
|
(47 "F.CrtYd" user "F.Courtyard")
|
||||||
|
(48 "B.Fab" user)
|
||||||
|
(49 "F.Fab" user)
|
||||||
|
(50 "User.1" user)
|
||||||
|
(51 "User.2" user)
|
||||||
|
(52 "User.3" user)
|
||||||
|
(53 "User.4" user)
|
||||||
|
(54 "User.5" user)
|
||||||
|
(55 "User.6" user)
|
||||||
|
(56 "User.7" user)
|
||||||
|
(57 "User.8" user)
|
||||||
|
(58 "User.9" user)
|
||||||
|
)
|
||||||
|
|
||||||
|
(setup
|
||||||
|
(stackup
|
||||||
|
(layer "F.SilkS" (type "Top Silk Screen"))
|
||||||
|
(layer "F.Paste" (type "Top Solder Paste"))
|
||||||
|
(layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
|
||||||
|
(layer "F.Cu" (type "copper") (thickness 0.035))
|
||||||
|
(layer "dielectric 1" (type "core") (thickness 0.48) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
|
||||||
|
(layer "In1.Cu" (type "copper") (thickness 0.035))
|
||||||
|
(layer "dielectric 2" (type "prepreg") (thickness 0.48) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
|
||||||
|
(layer "In2.Cu" (type "copper") (thickness 0.035))
|
||||||
|
(layer "dielectric 3" (type "core") (thickness 0.48) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
|
||||||
|
(layer "B.Cu" (type "copper") (thickness 0.035))
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||||||
|
(layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
|
||||||
|
(layer "B.Paste" (type "Bottom Solder Paste"))
|
||||||
|
(layer "B.SilkS" (type "Bottom Silk Screen"))
|
||||||
|
(copper_finish "None")
|
||||||
|
(dielectric_constraints no)
|
||||||
|
)
|
||||||
|
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|
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(usegerberadvancedattributes true)
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||||||
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(creategerberjobfile true)
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(svguseinch false)
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||||||
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(svgprecision 6)
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||||||
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(excludeedgelayer true)
|
||||||
|
(plotframeref false)
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||||||
|
(viasonmask false)
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||||||
|
(mode 1)
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||||||
|
(useauxorigin true)
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||||||
|
(hpglpennumber 1)
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||||||
|
(hpglpenspeed 20)
|
||||||
|
(hpglpendiameter 15.000000)
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||||||
|
(psnegative false)
|
||||||
|
(psa4output false)
|
||||||
|
(plotreference true)
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||||||
|
(plotvalue true)
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||||||
|
(plotinvisibletext false)
|
||||||
|
(sketchpadsonfab false)
|
||||||
|
(subtractmaskfromsilk false)
|
||||||
|
(outputformat 1)
|
||||||
|
(mirror false)
|
||||||
|
(drillshape 0)
|
||||||
|
(scaleselection 1)
|
||||||
|
(outputdirectory "fab/")
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
|
||||||
|
(net 0 "")
|
||||||
|
(net 1 "Net-(R1-Pad1)")
|
||||||
|
(net 2 "Net-(R1-Pad2)")
|
||||||
|
|
||||||
|
(footprint "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" (layer "F.Cu")
|
||||||
|
(tedit 5FB6CEC8) (tstamp 99b5e202-e70f-49ef-bc79-6f62add5c353)
|
||||||
|
(at 144.2 110.9)
|
||||||
|
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
|
||||||
|
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
|
||||||
|
(property "Sheet file" "test.kicad_sch")
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||||||
|
(property "Sheet name" "")
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|
(path "/fe10a8c5-aa6b-49c6-97da-ef22c8a7d6b1")
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|
(attr through_hole)
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|
(effects (font (size 1 1) (thickness 0.15)))
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|
(tstamp dc6a85c5-1373-48f5-801f-8353d6150d97)
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||||||
|
)
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||||||
|
(fp_text value "R" (at 5.08 2.37) (layer "F.Fab")
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||||||
|
(effects (font (size 1 1) (thickness 0.15)))
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||||||
|
(tstamp 54f122a9-f6f0-4010-89a2-c63ed0b072e8)
|
||||||
|
)
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||||||
|
(fp_text user "${REFERENCE}" (at 5.08 0) (layer "F.Fab")
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||||||
|
(effects (font (size 1 1) (thickness 0.15)))
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||||||
|
(tstamp 43b14f3d-6695-4178-b31c-03715d66001f)
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||||||
|
)
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
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||||||
|
(fp_line (start -1.05 1.5) (end 11.21 1.5) (layer "F.CrtYd") (width 0.05) (tstamp 89c4e76b-608a-4502-9469-d967c196e40a))
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||||||
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(fp_line (start 11.21 -1.5) (end -1.05 -1.5) (layer "F.CrtYd") (width 0.05) (tstamp 92852050-1b71-4917-8d26-f93dc412df2e))
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||||||
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||||||
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||||||
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||||||
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||||||
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|
||||||
|
(pad "1" thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
|
||||||
|
(net 1 "Net-(R1-Pad1)") (tstamp e9dab5f1-8b89-45ae-aba6-6f3f4a89b2d9))
|
||||||
|
(pad "2" thru_hole oval (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (remove_unused_layers) (keep_end_layers)
|
||||||
|
(net 2 "Net-(R1-Pad2)") (tstamp e86d43b5-574b-4ad2-822f-04321fcfe0e6))
|
||||||
|
(model "${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl"
|
||||||
|
(offset (xyz 0 0 0))
|
||||||
|
(scale (xyz 1 1 1))
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||||||
|
(rotate (xyz 0 0 0))
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
(footprint "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" (layer "F.Cu")
|
||||||
|
(tedit 5AE5139B) (tstamp 9f0fdfb7-5afd-4e01-bc66-870043786ed7)
|
||||||
|
(at 144.2 114.2)
|
||||||
|
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=10.16mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
|
||||||
|
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
|
||||||
|
(property "Sheet file" "test.kicad_sch")
|
||||||
|
(property "Sheet name" "")
|
||||||
|
(path "/35d87359-818c-4384-9a2a-921785d44ad3")
|
||||||
|
(attr through_hole)
|
||||||
|
(fp_text reference "R2" (at 5.08 2.3) (layer "F.SilkS")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp 6e897e0d-094b-4b95-b195-8828d28b5f6d)
|
||||||
|
)
|
||||||
|
(fp_text value "R" (at 5.08 2.37) (layer "F.Fab")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp 824f60d7-bd4f-4249-b12d-344f11be7794)
|
||||||
|
)
|
||||||
|
(fp_text user "${REFERENCE}" (at 5.08 0) (layer "F.Fab")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
(tstamp eec75d38-496e-497d-bae0-328f860c5560)
|
||||||
|
)
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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||||||
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||||||
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||||||
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|
||||||
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||||||
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||||||
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||||||
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||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
||||||
|
|
||||||
|
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|
||||||
|
|
||||||
|
(zone (net 1) (net_name "Net-(R1-Pad1)") (layer "In1.Cu") (tstamp 3f1aa6d3-8c39-415b-b94d-0780428d0aa0) (hatch edge 0.508)
|
||||||
|
(connect_pads (clearance 0.508))
|
||||||
|
(min_thickness 0.254) (filled_areas_thickness no)
|
||||||
|
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|
||||||
|
(polygon
|
||||||
|
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|
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|
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|
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|
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|
||||||
|
)
|
||||||
|
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|
||||||
|
(filled_polygon
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||||||
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
|
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|
||||||
|
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|
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|
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|
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|
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|
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|
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|
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|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.05,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "diffferrr",
|
||||||
|
"nets": [
|
||||||
|
"/asdf_N",
|
||||||
|
"/asdf_P"
|
||||||
|
],
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.2,
|
||||||
|
"via_diameter": 0.8,
|
||||||
|
"via_drill": 0.4,
|
||||||
|
"wire_width": 6.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_colors": null
|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "",
|
||||||
|
"vrml": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": ""
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"drawing": {
|
||||||
|
"default_bus_thickness": 12.0,
|
||||||
|
"default_junction_size": 40.0,
|
||||||
|
"default_line_thickness": 6.0,
|
||||||
|
"default_text_size": 50.0,
|
||||||
|
"default_wire_thickness": 6.0,
|
||||||
|
"field_names": [],
|
||||||
|
"intersheets_ref_own_page": false,
|
||||||
|
"intersheets_ref_prefix": "",
|
||||||
|
"intersheets_ref_short": false,
|
||||||
|
"intersheets_ref_show": false,
|
||||||
|
"intersheets_ref_suffix": "",
|
||||||
|
"junction_size_choice": 3,
|
||||||
|
"pin_symbol_size": 25.0,
|
||||||
|
"text_offset_ratio": 0.3
|
||||||
|
},
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_format_name": "",
|
||||||
|
"page_layout_descr_file": "",
|
||||||
|
"plot_directory": "",
|
||||||
|
"spice_adjust_passive_values": false,
|
||||||
|
"spice_external_command": "spice \"%I\"",
|
||||||
|
"subpart_first_id": 65,
|
||||||
|
"subpart_id_separator": 0
|
||||||
|
},
|
||||||
|
"sheets": [
|
||||||
|
[
|
||||||
|
"f0a8c45c-12da-43b8-aa6d-6e36945224a3",
|
||||||
|
""
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"text_variables": {}
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,494 @@
|
||||||
|
{
|
||||||
|
"board": {
|
||||||
|
"design_settings": {
|
||||||
|
"defaults": {
|
||||||
|
"board_outline_line_width": 0.049999999999999996,
|
||||||
|
"copper_line_width": 0.19999999999999998,
|
||||||
|
"copper_text_italic": false,
|
||||||
|
"copper_text_size_h": 1.5,
|
||||||
|
"copper_text_size_v": 1.5,
|
||||||
|
"copper_text_thickness": 0.3,
|
||||||
|
"copper_text_upright": true,
|
||||||
|
"courtyard_line_width": 0.049999999999999996,
|
||||||
|
"dimension_precision": 1,
|
||||||
|
"dimension_units": 2,
|
||||||
|
"dimensions": {
|
||||||
|
"arrow_length": 1270000,
|
||||||
|
"extension_offset": 500000,
|
||||||
|
"keep_text_aligned": true,
|
||||||
|
"suppress_zeroes": false,
|
||||||
|
"text_position": 0,
|
||||||
|
"units_format": 1
|
||||||
|
},
|
||||||
|
"fab_line_width": 0.09999999999999999,
|
||||||
|
"fab_text_italic": false,
|
||||||
|
"fab_text_size_h": 1.0,
|
||||||
|
"fab_text_size_v": 1.0,
|
||||||
|
"fab_text_thickness": 0.15,
|
||||||
|
"fab_text_upright": true,
|
||||||
|
"other_line_width": 0.09999999999999999,
|
||||||
|
"other_text_italic": false,
|
||||||
|
"other_text_size_h": 1.0,
|
||||||
|
"other_text_size_v": 1.0,
|
||||||
|
"other_text_thickness": 0.15,
|
||||||
|
"other_text_upright": true,
|
||||||
|
"pads": {
|
||||||
|
"drill": 0.762,
|
||||||
|
"height": 1.524,
|
||||||
|
"width": 1.524
|
||||||
|
},
|
||||||
|
"silk_line_width": 0.12,
|
||||||
|
"silk_text_italic": false,
|
||||||
|
"silk_text_size_h": 1.0,
|
||||||
|
"silk_text_size_v": 1.0,
|
||||||
|
"silk_text_thickness": 0.15,
|
||||||
|
"silk_text_upright": true,
|
||||||
|
"zones": {
|
||||||
|
"45_degree_only": false,
|
||||||
|
"min_clearance": 0.19999999999999998
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"diff_pair_dimensions": [
|
||||||
|
{
|
||||||
|
"gap": 0.0,
|
||||||
|
"via_gap": 0.0,
|
||||||
|
"width": 0.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"drc_exclusions": [
|
||||||
|
"clearance|87150000|140800000|713a642e-4662-4581-a311-4a183ae3a0a4|0e2e2e70-712c-4a91-9883-5badae873369",
|
||||||
|
"courtyards_overlap|102580000|139229999|00000000-0000-0000-0000-00005db27222|00000000-0000-0000-0000-00005e4ffe1e",
|
||||||
|
"courtyards_overlap|102580000|142700000|00000000-0000-0000-0000-00005db270f4|00000000-0000-0000-0000-00005e4ffe1e",
|
||||||
|
"courtyards_overlap|116660000|142900000|00000000-0000-0000-0000-00005db26ea8|00000000-0000-0000-0000-00005db2741b",
|
||||||
|
"courtyards_overlap|126820000|142900000|00000000-0000-0000-0000-00005db272bc|00000000-0000-0000-0000-00005db2741b",
|
||||||
|
"courtyards_overlap|144725000|118017468|00000000-0000-0000-0000-00005d888938|00000000-0000-0000-0000-00005e2b4dc2",
|
||||||
|
"courtyards_overlap|86925000|140617468|00000000-0000-0000-0000-00005db273cf|00000000-0000-0000-0000-00005e2b4dc5"
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 2
|
||||||
|
},
|
||||||
|
"rule_severities": {
|
||||||
|
"annular_width": "error",
|
||||||
|
"clearance": "error",
|
||||||
|
"copper_edge_clearance": "ignore",
|
||||||
|
"courtyards_overlap": "error",
|
||||||
|
"diff_pair_gap_out_of_range": "error",
|
||||||
|
"diff_pair_uncoupled_length_too_long": "error",
|
||||||
|
"drill_out_of_range": "error",
|
||||||
|
"duplicate_footprints": "warning",
|
||||||
|
"extra_footprint": "warning",
|
||||||
|
"hole_clearance": "error",
|
||||||
|
"hole_near_hole": "error",
|
||||||
|
"invalid_outline": "error",
|
||||||
|
"item_on_disabled_layer": "error",
|
||||||
|
"items_not_allowed": "error",
|
||||||
|
"length_out_of_range": "error",
|
||||||
|
"malformed_courtyard": "error",
|
||||||
|
"microvia_drill_out_of_range": "error",
|
||||||
|
"missing_courtyard": "ignore",
|
||||||
|
"missing_footprint": "warning",
|
||||||
|
"net_conflict": "warning",
|
||||||
|
"npth_inside_courtyard": "ignore",
|
||||||
|
"padstack": "error",
|
||||||
|
"pth_inside_courtyard": "ignore",
|
||||||
|
"shorting_items": "error",
|
||||||
|
"silk_over_copper": "ignore",
|
||||||
|
"silk_overlap": "ignore",
|
||||||
|
"skew_out_of_range": "error",
|
||||||
|
"too_many_vias": "error",
|
||||||
|
"track_dangling": "warning",
|
||||||
|
"track_width": "error",
|
||||||
|
"tracks_crossing": "error",
|
||||||
|
"unconnected_items": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"via_dangling": "warning",
|
||||||
|
"zone_has_empty_net": "error",
|
||||||
|
"zones_intersect": "error"
|
||||||
|
},
|
||||||
|
"rules": {
|
||||||
|
"allow_blind_buried_vias": false,
|
||||||
|
"allow_microvias": false,
|
||||||
|
"max_error": 0.005,
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"min_hole_to_hole": 0.25,
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
"min_through_hole_diameter": 0.3,
|
||||||
|
"min_track_width": 0.19999999999999998,
|
||||||
|
"min_via_annular_width": 0.049999999999999996,
|
||||||
|
"min_via_annulus": 0.049999999999999996,
|
||||||
|
"min_via_diameter": 0.39999999999999997,
|
||||||
|
"use_height_for_length_calcs": true
|
||||||
|
},
|
||||||
|
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|
||||||
|
0.25,
|
||||||
|
0.2,
|
||||||
|
0.4,
|
||||||
|
1.0,
|
||||||
|
2.0
|
||||||
|
],
|
||||||
|
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|
||||||
|
{
|
||||||
|
"diameter": 0.85,
|
||||||
|
"drill": 0.4
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"zones_allow_external_fillets": false,
|
||||||
|
"zones_use_no_outline": true
|
||||||
|
},
|
||||||
|
"layer_presets": [
|
||||||
|
{
|
||||||
|
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|
||||||
|
"layers": [
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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||||||
|
7,
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||||||
|
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|
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||||||
|
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|
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|
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||||||
|
12,
|
||||||
|
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|
||||||
|
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|
||||||
|
15,
|
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|
16,
|
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|
17,
|
||||||
|
18,
|
||||||
|
19,
|
||||||
|
20,
|
||||||
|
21,
|
||||||
|
22,
|
||||||
|
23,
|
||||||
|
24,
|
||||||
|
25,
|
||||||
|
26,
|
||||||
|
27,
|
||||||
|
28,
|
||||||
|
29,
|
||||||
|
30,
|
||||||
|
41,
|
||||||
|
44,
|
||||||
|
49,
|
||||||
|
50
|
||||||
|
],
|
||||||
|
"name": "Fabrication",
|
||||||
|
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|
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129,
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|
130,
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|
131,
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133,
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|
134,
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|
135,
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|
136,
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|
137,
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|
138,
|
||||||
|
139,
|
||||||
|
143,
|
||||||
|
144
|
||||||
|
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|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
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||||||
|
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[
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[
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[
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|
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|
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[
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2,
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0,
|
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2
|
||||||
|
],
|
||||||
|
[
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
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2,
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||||||
|
2,
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||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2,
|
||||||
|
2
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"rule_severities": {
|
||||||
|
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|
||||||
|
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|
||||||
|
"bus_to_bus_conflict": "error",
|
||||||
|
"bus_to_net_conflict": "error",
|
||||||
|
"different_unit_footprint": "error",
|
||||||
|
"different_unit_net": "error",
|
||||||
|
"duplicate_sheet_names": "error",
|
||||||
|
"global_label_dangling": "error",
|
||||||
|
"hier_label_mismatch": "error",
|
||||||
|
"label_dangling": "error",
|
||||||
|
"lib_symbol_issues": "warning",
|
||||||
|
"multiple_net_names": "error",
|
||||||
|
"net_not_bus_member": "error",
|
||||||
|
"no_connect_connected": "error",
|
||||||
|
"no_connect_dangling": "error",
|
||||||
|
"pin_not_connected": "error",
|
||||||
|
"pin_not_driven": "error",
|
||||||
|
"pin_to_pin": "warning",
|
||||||
|
"similar_labels": "error",
|
||||||
|
"unresolved_variable": "error",
|
||||||
|
"wire_dangling": "error"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"libraries": {
|
||||||
|
"pinned_footprint_libs": [],
|
||||||
|
"pinned_symbol_libs": []
|
||||||
|
},
|
||||||
|
"meta": {
|
||||||
|
"filename": "LoRaNode.kicad_pro",
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_settings": {
|
||||||
|
"classes": [
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.2,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "Default",
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 0.25,
|
||||||
|
"via_diameter": 0.85,
|
||||||
|
"via_drill": 0.4,
|
||||||
|
"wire_width": 6.0
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"bus_width": 12.0,
|
||||||
|
"clearance": 0.25,
|
||||||
|
"diff_pair_gap": 0.25,
|
||||||
|
"diff_pair_via_gap": 0.25,
|
||||||
|
"diff_pair_width": 0.2,
|
||||||
|
"line_style": 0,
|
||||||
|
"microvia_diameter": 0.3,
|
||||||
|
"microvia_drill": 0.1,
|
||||||
|
"name": "antenna",
|
||||||
|
"nets": [
|
||||||
|
"/ANTENNA"
|
||||||
|
],
|
||||||
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"track_width": 1.27,
|
||||||
|
"via_diameter": 0.85,
|
||||||
|
"via_drill": 0.4,
|
||||||
|
"wire_width": 6.0
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"meta": {
|
||||||
|
"version": 1
|
||||||
|
},
|
||||||
|
"net_colors": null
|
||||||
|
},
|
||||||
|
"pcbnew": {
|
||||||
|
"last_paths": {
|
||||||
|
"gencad": "",
|
||||||
|
"idf": "",
|
||||||
|
"netlist": "",
|
||||||
|
"specctra_dsn": "",
|
||||||
|
"step": "",
|
||||||
|
"vmrl": "",
|
||||||
|
"vrml": ""
|
||||||
|
},
|
||||||
|
"page_layout_descr_file": ""
|
||||||
|
},
|
||||||
|
"schematic": {
|
||||||
|
"drawing": {
|
||||||
|
"default_bus_thickness": 12.0,
|
||||||
|
"default_junction_size": 40.0,
|
||||||
|
"default_line_thickness": 6.0,
|
||||||
|
"default_text_size": 50.0,
|
||||||
|
"default_wire_thickness": 6.0,
|
||||||
|
"field_names": [],
|
||||||
|
"intersheets_ref_prefix": "[",
|
||||||
|
"intersheets_ref_short": false,
|
||||||
|
"intersheets_ref_show": false,
|
||||||
|
"intersheets_ref_suffix": "]",
|
||||||
|
"pin_symbol_size": 25.0,
|
||||||
|
"text_offset_ratio": 0.3
|
||||||
|
},
|
||||||
|
"legacy_lib_dir": "",
|
||||||
|
"legacy_lib_list": [],
|
||||||
|
"meta": {
|
||||||
|
"version": 0
|
||||||
|
},
|
||||||
|
"net_format_name": "",
|
||||||
|
"page_layout_descr_file": "",
|
||||||
|
"plot_directory": "./",
|
||||||
|
"spice_adjust_passive_values": false,
|
||||||
|
"spice_external_command": "spice \"%I\"",
|
||||||
|
"subpart_first_id": 65,
|
||||||
|
"subpart_id_separator": 0
|
||||||
|
},
|
||||||
|
"sheets": [
|
||||||
|
[
|
||||||
|
"285a99a7-a1a2-4aa6-812b-d3c3533a57d7",
|
||||||
|
""
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"00000000-0000-0000-0000-00005d8236a8",
|
||||||
|
"battery-protection"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"00000000-0000-0000-0000-00005d8260b7",
|
||||||
|
"voltage-regulation"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"00000000-0000-0000-0000-00005d825820",
|
||||||
|
"RS485-interface"
|
||||||
|
],
|
||||||
|
[
|
||||||
|
"00000000-0000-0000-0000-00005d84b44c",
|
||||||
|
"I2C-interface"
|
||||||
|
]
|
||||||
|
],
|
||||||
|
"text_variables": {}
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,306 @@
|
||||||
|
(kicad_pcb (version 20190605) (host pcbnew "6.0.0-unknown-7b5b807~86~ubuntu18.04.1")
|
||||||
|
|
||||||
|
(general
|
||||||
|
(thickness 1.6)
|
||||||
|
(drawings 4)
|
||||||
|
(tracks 9)
|
||||||
|
(modules 1)
|
||||||
|
(nets 3)
|
||||||
|
)
|
||||||
|
|
||||||
|
(page "A4")
|
||||||
|
(layers
|
||||||
|
(0 "F.Cu" signal)
|
||||||
|
(31 "B.Cu" signal)
|
||||||
|
(32 "B.Adhes" user)
|
||||||
|
(33 "F.Adhes" user)
|
||||||
|
(34 "B.Paste" user)
|
||||||
|
(35 "F.Paste" user)
|
||||||
|
(36 "B.SilkS" user)
|
||||||
|
(37 "F.SilkS" user)
|
||||||
|
(38 "B.Mask" user)
|
||||||
|
(39 "F.Mask" user)
|
||||||
|
(40 "Dwgs.User" user)
|
||||||
|
(41 "Cmts.User" user)
|
||||||
|
(42 "Eco1.User" user)
|
||||||
|
(43 "Eco2.User" user)
|
||||||
|
(44 "Edge.Cuts" user)
|
||||||
|
(45 "Margin" user)
|
||||||
|
(46 "B.CrtYd" user)
|
||||||
|
(47 "F.CrtYd" user)
|
||||||
|
(48 "B.Fab" user)
|
||||||
|
(49 "F.Fab" user)
|
||||||
|
)
|
||||||
|
|
||||||
|
(setup
|
||||||
|
(last_trace_width 0.25)
|
||||||
|
(trace_clearance 0.2)
|
||||||
|
(zone_clearance 0.153)
|
||||||
|
(zone_45_only no)
|
||||||
|
(trace_min 0.1534)
|
||||||
|
(via_size 0.8)
|
||||||
|
(via_drill 0.4)
|
||||||
|
(via_min_size 0.4)
|
||||||
|
(via_min_drill 0.3)
|
||||||
|
(uvia_size 0.3)
|
||||||
|
(uvia_drill 0.1)
|
||||||
|
(uvias_allowed no)
|
||||||
|
(uvia_min_size 0.2)
|
||||||
|
(uvia_min_drill 0.1)
|
||||||
|
(max_error 0.005)
|
||||||
|
(defaults
|
||||||
|
(edge_clearance 0.01)
|
||||||
|
(edge_cuts_line_width 0.05)
|
||||||
|
(courtyard_line_width 0.05)
|
||||||
|
(copper_line_width 0.2)
|
||||||
|
(copper_text_dims (size 1.5 1.5) (thickness 0.3) keep_upright)
|
||||||
|
(silk_line_width 0.12)
|
||||||
|
(silk_text_dims (size 1 1) (thickness 0.15) keep_upright)
|
||||||
|
(other_layers_line_width 0.1)
|
||||||
|
(other_layers_text_dims (size 1 1) (thickness 0.15) keep_upright)
|
||||||
|
)
|
||||||
|
(pad_size 1.524 1.524)
|
||||||
|
(pad_drill 0.762)
|
||||||
|
(pad_to_mask_clearance 0.051)
|
||||||
|
(solder_mask_min_width 0.25)
|
||||||
|
(aux_axis_origin 0 0)
|
||||||
|
(visible_elements FFFFFF7F)
|
||||||
|
(pcbplotparams
|
||||||
|
(layerselection 0x010fc_ffffffff)
|
||||||
|
(usegerberextensions false)
|
||||||
|
(usegerberattributes false)
|
||||||
|
(usegerberadvancedattributes false)
|
||||||
|
(creategerberjobfile false)
|
||||||
|
(excludeedgelayer true)
|
||||||
|
(linewidth 0.100000)
|
||||||
|
(plotframeref false)
|
||||||
|
(viasonmask false)
|
||||||
|
(mode 1)
|
||||||
|
(useauxorigin false)
|
||||||
|
(hpglpennumber 1)
|
||||||
|
(hpglpenspeed 20)
|
||||||
|
(hpglpendiameter 15.000000)
|
||||||
|
(psnegative false)
|
||||||
|
(psa4output false)
|
||||||
|
(plotreference true)
|
||||||
|
(plotvalue true)
|
||||||
|
(plotinvisibletext false)
|
||||||
|
(padsonsilk false)
|
||||||
|
(subtractmaskfromsilk false)
|
||||||
|
(outputformat 1)
|
||||||
|
(mirror false)
|
||||||
|
(drillshape 1)
|
||||||
|
(scaleselection 1)
|
||||||
|
(outputdirectory ""))
|
||||||
|
)
|
||||||
|
|
||||||
|
(net 0 "")
|
||||||
|
(net 1 "GND")
|
||||||
|
(net 2 "+5V")
|
||||||
|
|
||||||
|
(net_class "Default" "This is the default net class."
|
||||||
|
(clearance 0.2)
|
||||||
|
(trace_width 0.25)
|
||||||
|
(via_dia 0.8)
|
||||||
|
(via_drill 0.4)
|
||||||
|
(uvia_dia 0.3)
|
||||||
|
(uvia_drill 0.1)
|
||||||
|
(add_net "+5V")
|
||||||
|
(add_net "GND")
|
||||||
|
)
|
||||||
|
|
||||||
|
(module "Resistor_SMD:R_0603_1608Metric" (layer "F.Cu") (tedit 5B301BBD) (tstamp 5D3DB920)
|
||||||
|
(at 79.75 51.75 270)
|
||||||
|
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
|
||||||
|
(tags "resistor")
|
||||||
|
(path "/5D3DC317")
|
||||||
|
(attr smd)
|
||||||
|
(fp_text reference "R1" (at 0 -1.43 90) (layer "F.SilkS")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
)
|
||||||
|
(fp_text value "R" (at 0 1.43 90) (layer "F.Fab")
|
||||||
|
(effects (font (size 1 1) (thickness 0.15)))
|
||||||
|
)
|
||||||
|
(fp_text user "%R" (at 0 0 90) (layer "F.Fab")
|
||||||
|
(effects (font (size 0.4 0.4) (thickness 0.06)))
|
||||||
|
)
|
||||||
|
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer "F.CrtYd") (width 0.05))
|
||||||
|
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer "F.CrtYd") (width 0.05))
|
||||||
|
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer "F.CrtYd") (width 0.05))
|
||||||
|
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer "F.CrtYd") (width 0.05))
|
||||||
|
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer "F.SilkS") (width 0.12))
|
||||||
|
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer "F.SilkS") (width 0.12))
|
||||||
|
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer "F.Fab") (width 0.1))
|
||||||
|
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer "F.Fab") (width 0.1))
|
||||||
|
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer "F.Fab") (width 0.1))
|
||||||
|
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer "F.Fab") (width 0.1))
|
||||||
|
(pad "2" smd roundrect (at 0.7875 0 270) (size 0.875 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 1 "GND"))
|
||||||
|
(pad "1" smd roundrect (at -0.7875 0 270) (size 0.875 0.95) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
||||||
|
(net 2 "+5V"))
|
||||||
|
(model "${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl"
|
||||||
|
(at (xyz 0 0 0))
|
||||||
|
(scale (xyz 1 1 1))
|
||||||
|
(rotate (xyz 0 0 0))
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
||||||
|
(gr_line (start 72.5 92) (end 72.5 45.25) (layer "Edge.Cuts") (width 0.05))
|
||||||
|
(gr_line (start 140.5 92) (end 72.5 92) (layer "Edge.Cuts") (width 0.05))
|
||||||
|
(gr_line (start 140.5 45.25) (end 140.5 92) (layer "Edge.Cuts") (width 0.05))
|
||||||
|
(gr_line (start 72.5 45.25) (end 140.5 45.25) (layer "Edge.Cuts") (width 0.05))
|
||||||
|
|
||||||
|
(via (at 74.5 47.25) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 1))
|
||||||
|
(via (at 78.75 47.25) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 1))
|
||||||
|
(via (at 86 47.25) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 1))
|
||||||
|
(via (at 74.25 52) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 1))
|
||||||
|
(via (at 74.75 60) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 1))
|
||||||
|
(via (at 89 50.75) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 1))
|
||||||
|
(via (at 89 58.5) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 1))
|
||||||
|
(via (at 79.75 53.75) (size 0.8) (drill 0.4) (layers "F.Cu" "B.Cu") (net 1))
|
||||||
|
(segment (start 79.75 52.5375) (end 79.75 53.75) (width 0.25) (layer "F.Cu") (net 1))
|
||||||
|
|
||||||
|
(zone (net 1) (net_name "GND") (layer "F.Cu") (tstamp 0) (hatch edge 0.508)
|
||||||
|
(connect_pads yes (clearance 0.254))
|
||||||
|
(min_thickness 0.254)
|
||||||
|
(fill yes (thermal_gap 0.508) (thermal_bridge_width 0.508) (smoothing fillet) (radius 0.5))
|
||||||
|
(polygon
|
||||||
|
(pts
|
||||||
|
(xy 73.5 46.5) (xy 90 46.5) (xy 90 91.5) (xy 73.5 91.5)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
(filled_polygon
|
||||||
|
(pts
|
||||||
|
(xy 89.596517 46.639794) (xy 89.686456 46.677048) (xy 89.763689 46.736311) (xy 89.822952 46.813544) (xy 89.860206 46.903483)
|
||||||
|
(xy 89.874 47.008258) (xy 89.874 51.624) (xy 84.38 51.624) (xy 84.38 48.245875) (xy 84.377287 48.20449)
|
||||||
|
(xy 84.358634 48.062803) (xy 84.337197 47.9828) (xy 84.280927 47.84695) (xy 84.239514 47.775221) (xy 84.149999 47.658564)
|
||||||
|
(xy 84.091436 47.600001) (xy 83.974779 47.510486) (xy 83.90305 47.469073) (xy 83.7672 47.412803) (xy 83.687197 47.391366)
|
||||||
|
(xy 83.54551 47.372713) (xy 83.504125 47.37) (xy 76.245875 47.37) (xy 76.20449 47.372713) (xy 76.062803 47.391366)
|
||||||
|
(xy 75.9828 47.412803) (xy 75.84695 47.469073) (xy 75.775221 47.510486) (xy 75.658564 47.600001) (xy 75.600001 47.658564)
|
||||||
|
(xy 75.510486 47.775221) (xy 75.469073 47.84695) (xy 75.412803 47.9828) (xy 75.391366 48.062803) (xy 75.372713 48.20449)
|
||||||
|
(xy 75.37 48.245875) (xy 75.37 89.004125) (xy 75.372713 89.04551) (xy 75.391366 89.187197) (xy 75.412803 89.2672)
|
||||||
|
(xy 75.469073 89.40305) (xy 75.510486 89.474779) (xy 75.600001 89.591436) (xy 75.658564 89.649999) (xy 75.775221 89.739514)
|
||||||
|
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(filled_polygon
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)
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||||||
|
(priority 2)
|
||||||
|
(connect_pads yes (clearance 0.153))
|
||||||
|
(min_thickness 0.153)
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||||||
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(fill yes (thermal_gap 0.2) (thermal_bridge_width 0.508) (smoothing fillet) (radius 0.5))
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||||||
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(polygon
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||||||
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||||||
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||||||
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||||||
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(min_thickness 0.153)
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||||||
|
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|
||||||
|
(xy 80.929274 56.502116) (xy 80.925188 59.495633) (xy 80.909963 59.610168) (xy 80.867554 59.712257) (xy 80.800184 59.799911)
|
||||||
|
(xy 80.71244 59.86716) (xy 80.610287 59.909432) (xy 80.495739 59.9245) (xy 79.491307 59.9245) (xy 79.37656 59.90938)
|
||||||
|
(xy 79.274263 59.866966) (xy 79.186446 59.799503) (xy 79.119097 59.711587) (xy 79.076824 59.609234) (xy 79.061861 59.494471)
|
||||||
|
(xy 79.067648 55.254367) (xy 79.082873 55.139832) (xy 79.125282 55.037743) (xy 79.192652 54.950089) (xy 79.280396 54.88284)
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||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
)
|
||||||
|
|
@ -41,6 +41,7 @@ set( QA_PCBNEW_SRCS
|
||||||
|
|
||||||
drc/test_drc_courtyard_invalid.cpp
|
drc/test_drc_courtyard_invalid.cpp
|
||||||
drc/test_drc_courtyard_overlap.cpp
|
drc/test_drc_courtyard_overlap.cpp
|
||||||
|
drc/test_drc_regressions.cpp
|
||||||
|
|
||||||
plugins/altium/test_altium_rule_transformer.cpp
|
plugins/altium/test_altium_rule_transformer.cpp
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,153 @@
|
||||||
|
/*
|
||||||
|
* This program source code file is part of KiCad, a free EDA CAD application.
|
||||||
|
*
|
||||||
|
* Copyright (C) 201 KiCad Developers, see AUTHORS.txt for contributors.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License
|
||||||
|
* as published by the Free Software Foundation; either version 2
|
||||||
|
* of the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, you may find one here:
|
||||||
|
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
|
||||||
|
* or you may search the http://www.gnu.org website for the version 2 license,
|
||||||
|
* or you may write to the Free Software Foundation, Inc.,
|
||||||
|
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <string>
|
||||||
|
|
||||||
|
#include <wx/toplevel.h>
|
||||||
|
|
||||||
|
#include <qa_utils/wx_utils/unit_test_utils.h>
|
||||||
|
#include <pcbnew_utils/board_file_utils.h>
|
||||||
|
#include <board.h>
|
||||||
|
#include <board_design_settings.h>
|
||||||
|
#include <pad.h>
|
||||||
|
#include <pcb_track.h>
|
||||||
|
#include <footprint.h>
|
||||||
|
#include <drc/drc_item.h>
|
||||||
|
#include <drc/drc_engine.h>
|
||||||
|
#include <zone_filler.h>
|
||||||
|
#include <board_commit.h>
|
||||||
|
#include <tool/tool_manager.h>
|
||||||
|
#include <zone_filler_tool.h>
|
||||||
|
#include <settings/settings_manager.h>
|
||||||
|
|
||||||
|
struct DRC_REGRESSION_TEST_FIXTURE
|
||||||
|
{
|
||||||
|
DRC_REGRESSION_TEST_FIXTURE() :
|
||||||
|
m_settingsManager( true /* headless */ )
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void loadBoard( const wxString& relPath )
|
||||||
|
{
|
||||||
|
if( m_board )
|
||||||
|
{
|
||||||
|
m_board->SetProject( nullptr );
|
||||||
|
m_board = nullptr;
|
||||||
|
}
|
||||||
|
|
||||||
|
std::string boardPath = KI_TEST::GetPcbnewTestDataDir() + relPath + ".kicad_pcb";
|
||||||
|
wxString projectPath = KI_TEST::GetPcbnewTestDataDir() + relPath + ".kicad_pro";
|
||||||
|
|
||||||
|
wxFileName pro( projectPath );
|
||||||
|
|
||||||
|
if( pro.Exists() )
|
||||||
|
m_settingsManager.LoadProject( pro.GetFullPath() );
|
||||||
|
|
||||||
|
m_board = KI_TEST::ReadBoardFromFileOrStream( boardPath );
|
||||||
|
|
||||||
|
if( pro.Exists() )
|
||||||
|
m_board->SetProject( &m_settingsManager.Prj() );
|
||||||
|
|
||||||
|
m_DRCEngine = std::make_shared<DRC_ENGINE>( m_board.get(), &m_board->GetDesignSettings() );
|
||||||
|
m_DRCEngine->InitEngine( wxFileName() );
|
||||||
|
m_board->GetDesignSettings().m_DRCEngine = m_DRCEngine;
|
||||||
|
|
||||||
|
m_toolMgr = std::make_unique<TOOL_MANAGER>();
|
||||||
|
m_toolMgr->SetEnvironment( m_board.get(), nullptr, nullptr, nullptr, nullptr );
|
||||||
|
m_toolMgr->RegisterTool( new ZONE_FILLER_TOOL );
|
||||||
|
}
|
||||||
|
|
||||||
|
void fillZones( int aFillVersion )
|
||||||
|
{
|
||||||
|
ZONE_FILLER_TOOL* fillerTool = m_toolMgr->GetTool<ZONE_FILLER_TOOL>();
|
||||||
|
BOARD_COMMIT commit( fillerTool );
|
||||||
|
ZONE_FILLER filler( m_board.get(), &commit );
|
||||||
|
std::vector<ZONE*> toFill;
|
||||||
|
|
||||||
|
m_board->GetDesignSettings().m_ZoneFillVersion = aFillVersion;
|
||||||
|
|
||||||
|
for( ZONE* zone : m_board->Zones() )
|
||||||
|
toFill.push_back( zone );
|
||||||
|
|
||||||
|
if( filler.Fill( toFill, false, nullptr ) )
|
||||||
|
commit.Push( _( "Fill Zone(s)" ), false, false );
|
||||||
|
}
|
||||||
|
|
||||||
|
SETTINGS_MANAGER m_settingsManager;
|
||||||
|
|
||||||
|
std::unique_ptr<BOARD> m_board;
|
||||||
|
std::unique_ptr<TOOL_MANAGER> m_toolMgr;
|
||||||
|
std::shared_ptr<DRC_ENGINE> m_DRCEngine;
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
BOOST_FIXTURE_TEST_SUITE( TestDRCRegressions, DRC_REGRESSION_TEST_FIXTURE )
|
||||||
|
|
||||||
|
constexpr int delta = KiROUND( 0.006 * IU_PER_MM );
|
||||||
|
|
||||||
|
|
||||||
|
BOOST_AUTO_TEST_CASE( DRCRegressions )
|
||||||
|
{
|
||||||
|
for( const wxString& relPath : { "issue4139",
|
||||||
|
"issue4774",
|
||||||
|
"issue5978",
|
||||||
|
"issue5990",
|
||||||
|
"issue6443",
|
||||||
|
"issue7975",
|
||||||
|
"issue8407" } )
|
||||||
|
{
|
||||||
|
loadBoard( relPath );
|
||||||
|
fillZones( 6 );
|
||||||
|
|
||||||
|
std::vector<DRC_ITEM> violations;
|
||||||
|
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
|
||||||
|
|
||||||
|
bds.m_DRCSeverities[ DRCE_INVALID_OUTLINE ] = SEVERITY::RPT_SEVERITY_WARNING;
|
||||||
|
bds.m_DRCSeverities[ DRCE_UNCONNECTED_ITEMS ] = SEVERITY::RPT_SEVERITY_WARNING;
|
||||||
|
|
||||||
|
m_DRCEngine->SetViolationHandler(
|
||||||
|
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
|
||||||
|
{
|
||||||
|
if( bds.GetSeverity( aItem->GetErrorCode() ) == SEVERITY::RPT_SEVERITY_ERROR )
|
||||||
|
violations.push_back( *aItem );
|
||||||
|
} );
|
||||||
|
|
||||||
|
m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
||||||
|
|
||||||
|
BOOST_TEST_MESSAGE( wxString::Format( "DRC regression: %s, %s",
|
||||||
|
relPath,
|
||||||
|
violations.empty() ? "passed" : "failed" ) );
|
||||||
|
|
||||||
|
if( !violations.empty() )
|
||||||
|
{
|
||||||
|
std::map<KIID, EDA_ITEM*> itemMap;
|
||||||
|
m_board->FillItemMap( itemMap );
|
||||||
|
|
||||||
|
for( const DRC_ITEM& item : violations )
|
||||||
|
BOOST_ERROR( item.ShowReport( EDA_UNITS::INCHES, RPT_SEVERITY_ERROR, itemMap ) );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
BOOST_AUTO_TEST_SUITE_END()
|
||||||
|
|
@ -55,8 +55,8 @@ struct ZONE_FILL_TEST_FIXTURE
|
||||||
m_board = nullptr;
|
m_board = nullptr;
|
||||||
}
|
}
|
||||||
|
|
||||||
wxString boardPath = KI_TEST::GetPcbnewTestDataDir() + relPath + ".kicad_pcb";
|
std::string boardPath = KI_TEST::GetPcbnewTestDataDir() + relPath + ".kicad_pcb";
|
||||||
wxString projectPath = KI_TEST::GetPcbnewTestDataDir() + relPath + ".kicad_pro";
|
wxString projectPath = KI_TEST::GetPcbnewTestDataDir() + relPath + ".kicad_pro";
|
||||||
|
|
||||||
wxFileName pro( projectPath );
|
wxFileName pro( projectPath );
|
||||||
|
|
||||||
|
|
@ -106,50 +106,6 @@ BOOST_FIXTURE_TEST_SUITE( TestZoneFiller, ZONE_FILL_TEST_FIXTURE )
|
||||||
constexpr int delta = KiROUND( 0.006 * IU_PER_MM );
|
constexpr int delta = KiROUND( 0.006 * IU_PER_MM );
|
||||||
|
|
||||||
|
|
||||||
BOOST_AUTO_TEST_CASE( RegressionZoneFillTests )
|
|
||||||
{
|
|
||||||
for( const wxString& relPath : { "issue2568", "issue3812", "issue5320", "issue5830",
|
|
||||||
"issue6284", "issue7086" } )
|
|
||||||
{
|
|
||||||
loadBoard( relPath );
|
|
||||||
|
|
||||||
for( int fillVersion : { 5, 6 } )
|
|
||||||
{
|
|
||||||
fillZones( fillVersion );
|
|
||||||
|
|
||||||
std::vector<DRC_ITEM> violations;
|
|
||||||
|
|
||||||
m_DRCEngine->SetViolationHandler(
|
|
||||||
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
|
|
||||||
{
|
|
||||||
if( aItem->GetErrorCode() == DRCE_CLEARANCE )
|
|
||||||
violations.push_back( *aItem );
|
|
||||||
} );
|
|
||||||
|
|
||||||
m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
|
||||||
|
|
||||||
if( violations.empty() )
|
|
||||||
{
|
|
||||||
BOOST_TEST_MESSAGE( wxString::Format( "Passed: %s (V%d fill algo)",
|
|
||||||
relPath,
|
|
||||||
fillVersion ) );
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
std::map<KIID, EDA_ITEM*> itemMap;
|
|
||||||
m_board->FillItemMap( itemMap );
|
|
||||||
|
|
||||||
for( const DRC_ITEM& item : violations )
|
|
||||||
{
|
|
||||||
BOOST_ERROR( item.ShowReport( EDA_UNITS::MILLIMETRES, RPT_SEVERITY_ERROR,
|
|
||||||
itemMap ) );
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
BOOST_AUTO_TEST_CASE( BasicZoneFills )
|
BOOST_AUTO_TEST_CASE( BasicZoneFills )
|
||||||
{
|
{
|
||||||
loadBoard( "zone_filler" );
|
loadBoard( "zone_filler" );
|
||||||
|
|
@ -236,4 +192,92 @@ BOOST_AUTO_TEST_CASE( BasicZoneFills )
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
BOOST_AUTO_TEST_CASE( NotchedZones )
|
||||||
|
{
|
||||||
|
loadBoard( "notched_zones" );
|
||||||
|
|
||||||
|
// Older algorithms had trouble where the filleted zones intersected and left notches.
|
||||||
|
// See:
|
||||||
|
// https://gitlab.com/kicad/code/kicad/-/issues/2737
|
||||||
|
// https://gitlab.com/kicad/code/kicad/-/issues/2752
|
||||||
|
|
||||||
|
// First, run a sanity check to validate that the saved board still has holes.
|
||||||
|
SHAPE_POLY_SET frontCopper;
|
||||||
|
|
||||||
|
for( ZONE* zone : m_board->Zones() )
|
||||||
|
{
|
||||||
|
if( zone->GetLayerSet().Contains( F_Cu ) )
|
||||||
|
{
|
||||||
|
frontCopper.BooleanAdd( zone->GetFilledPolysList( F_Cu ),
|
||||||
|
SHAPE_POLY_SET::PM_STRICTLY_SIMPLE );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
BOOST_CHECK_GT( frontCopper.OutlineCount(), 2 );
|
||||||
|
|
||||||
|
// Now re-fill and make sure the holes are gone.
|
||||||
|
fillZones( 6 );
|
||||||
|
frontCopper = SHAPE_POLY_SET();
|
||||||
|
|
||||||
|
for( ZONE* zone : m_board->Zones() )
|
||||||
|
{
|
||||||
|
if( zone->GetLayerSet().Contains( F_Cu ) )
|
||||||
|
{
|
||||||
|
frontCopper.BooleanAdd( zone->GetFilledPolysList( F_Cu ),
|
||||||
|
SHAPE_POLY_SET::PM_STRICTLY_SIMPLE );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
BOOST_CHECK_EQUAL( frontCopper.OutlineCount(), 2 );
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
BOOST_AUTO_TEST_CASE( RegressionZoneFillTests )
|
||||||
|
{
|
||||||
|
for( const wxString& relPath : { "issue2568",
|
||||||
|
"issue3812",
|
||||||
|
"issue5102",
|
||||||
|
"issue5320",
|
||||||
|
"issue5567",
|
||||||
|
"issue5830",
|
||||||
|
"issue6039",
|
||||||
|
"issue6260",
|
||||||
|
"issue6284",
|
||||||
|
"issue7086" } )
|
||||||
|
{
|
||||||
|
loadBoard( relPath );
|
||||||
|
|
||||||
|
for( int fillVersion : { 5, 6 } )
|
||||||
|
{
|
||||||
|
fillZones( fillVersion );
|
||||||
|
|
||||||
|
std::vector<DRC_ITEM> violations;
|
||||||
|
|
||||||
|
m_DRCEngine->SetViolationHandler(
|
||||||
|
[&]( const std::shared_ptr<DRC_ITEM>& aItem, wxPoint aPos )
|
||||||
|
{
|
||||||
|
if( aItem->GetErrorCode() == DRCE_CLEARANCE )
|
||||||
|
violations.push_back( *aItem );
|
||||||
|
} );
|
||||||
|
|
||||||
|
m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false );
|
||||||
|
|
||||||
|
BOOST_TEST_MESSAGE( wxString::Format( "Zone fill regression: %s, V%d fill algo %s",
|
||||||
|
relPath,
|
||||||
|
fillVersion,
|
||||||
|
violations.empty() ? "passed" : "failed" ) );
|
||||||
|
|
||||||
|
if( !violations.empty() )
|
||||||
|
{
|
||||||
|
std::map<KIID, EDA_ITEM*> itemMap;
|
||||||
|
m_board->FillItemMap( itemMap );
|
||||||
|
|
||||||
|
for( const DRC_ITEM& v : violations )
|
||||||
|
BOOST_ERROR( v.ShowReport( EDA_UNITS::INCHES, RPT_SEVERITY_ERROR, itemMap ) );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
BOOST_AUTO_TEST_SUITE_END()
|
BOOST_AUTO_TEST_SUITE_END()
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue