diff --git a/pcbnew/class_track.cpp b/pcbnew/class_track.cpp index f7e87a75f1..0b31d1c589 100644 --- a/pcbnew/class_track.cpp +++ b/pcbnew/class_track.cpp @@ -629,13 +629,7 @@ unsigned int VIA::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const if( !onVisibleLayer && m_ViaType != VIATYPE::THROUGH ) return HIDE; - switch( m_ViaType ) - { - case VIATYPE::THROUGH: return aView->IsLayerVisible( LAYER_VIA_THROUGH ) ? 0 : HIDE; - case VIATYPE::BLIND_BURIED: return aView->IsLayerVisible( LAYER_VIA_BBLIND ) ? 0 : HIDE; - case VIATYPE::MICROVIA: return aView->IsLayerVisible( LAYER_VIA_MICROVIA ) ? 0 : HIDE; - default: return 0; - } + return aView->IsLayerVisible( LAYER_VIAS ) ? 0 : HIDE; } return HIDE; diff --git a/pcbnew/pcb_base_frame.cpp b/pcbnew/pcb_base_frame.cpp index 87194fde8e..723d16cb9a 100644 --- a/pcbnew/pcb_base_frame.cpp +++ b/pcbnew/pcb_base_frame.cpp @@ -452,9 +452,9 @@ GENERAL_COLLECTORS_GUIDE PCB_BASE_FRAME::GetCollectorsGuide() guide.SetIgnoreThroughHolePads( ! m_Pcb->IsElementVisible( LAYER_PADS_TH ) ); guide.SetIgnoreModulesVals( ! m_Pcb->IsElementVisible( LAYER_MOD_VALUES ) ); guide.SetIgnoreModulesRefs( ! m_Pcb->IsElementVisible( LAYER_MOD_REFERENCES ) ); - guide.SetIgnoreThroughVias( ! m_Pcb->IsElementVisible( LAYER_VIA_THROUGH ) ); - guide.SetIgnoreBlindBuriedVias( ! m_Pcb->IsElementVisible( LAYER_VIA_BBLIND ) ); - guide.SetIgnoreMicroVias( ! m_Pcb->IsElementVisible( LAYER_VIA_MICROVIA ) ); + guide.SetIgnoreThroughVias( ! m_Pcb->IsElementVisible( LAYER_VIAS ) ); + guide.SetIgnoreBlindBuriedVias( ! m_Pcb->IsElementVisible( LAYER_VIAS ) ); + guide.SetIgnoreMicroVias( ! m_Pcb->IsElementVisible( LAYER_VIAS ) ); guide.SetIgnoreTracks( ! m_Pcb->IsElementVisible( LAYER_TRACKS ) ); return guide; diff --git a/pcbnew/pcbnew_printout.cpp b/pcbnew/pcbnew_printout.cpp index 97da16960e..8c64deadcd 100644 --- a/pcbnew/pcbnew_printout.cpp +++ b/pcbnew/pcbnew_printout.cpp @@ -152,10 +152,7 @@ void PCBNEW_PRINTOUT::setupViewLayers( KIGFX::VIEW& aView, const LSET& aLayerSet setVisibility( LAYER_PADS_TH ); setVisibility( LAYER_TRACKS ); - setVisibility( LAYER_VIA_THROUGH ); - setVisibility( LAYER_VIA_BBLIND ); - setVisibility( LAYER_VIA_MICROVIA ); - setVisibility( LAYER_NON_PLATEDHOLES ); + setVisibility( LAYER_VIAS ); setVisibility( LAYER_NO_CONNECTS ); setVisibility( LAYER_DRC_WARNING ); diff --git a/pcbnew/tools/selection_tool.cpp b/pcbnew/tools/selection_tool.cpp index fa375007f3..7742bb8580 100644 --- a/pcbnew/tools/selection_tool.cpp +++ b/pcbnew/tools/selection_tool.cpp @@ -463,9 +463,9 @@ const GENERAL_COLLECTORS_GUIDE SELECTION_TOOL::getCollectorsGuide() const guide.SetIgnoreThroughHolePads( padsDisabled || ! board()->IsElementVisible( LAYER_PADS_TH ) ); guide.SetIgnoreModulesVals( ! board()->IsElementVisible( LAYER_MOD_VALUES ) ); guide.SetIgnoreModulesRefs( ! board()->IsElementVisible( LAYER_MOD_REFERENCES ) ); - guide.SetIgnoreThroughVias( ! board()->IsElementVisible( LAYER_VIA_THROUGH ) ); - guide.SetIgnoreBlindBuriedVias( ! board()->IsElementVisible( LAYER_VIA_BBLIND ) ); - guide.SetIgnoreMicroVias( ! board()->IsElementVisible( LAYER_VIA_MICROVIA ) ); + guide.SetIgnoreThroughVias( ! board()->IsElementVisible( LAYER_VIAS ) ); + guide.SetIgnoreBlindBuriedVias( ! board()->IsElementVisible( LAYER_VIAS ) ); + guide.SetIgnoreMicroVias( ! board()->IsElementVisible( LAYER_VIAS ) ); guide.SetIgnoreTracks( ! board()->IsElementVisible( LAYER_TRACKS ) ); return guide; @@ -1808,42 +1808,20 @@ bool SELECTION_TOOL::Selectable( const BOARD_ITEM* aItem, bool checkVisibilityOn case PCB_TRACE_T: case PCB_ARC_T: - { - if( !board()->IsElementVisible( LAYER_TRACKS ) ) - return false; - } + if( !board()->IsElementVisible( LAYER_TRACKS ) ) + return false; break; case PCB_VIA_T: - { - const VIA* via = static_cast( aItem ); + { + if( !board()->IsElementVisible( LAYER_VIAS ) ) + return false; - // Check if appropriate element layer is visible - switch( via->GetViaType() ) - { - case VIATYPE::THROUGH: - if( !board()->IsElementVisible( LAYER_VIA_THROUGH ) ) - return false; - break; + const VIA* via = static_cast( aItem ); - case VIATYPE::BLIND_BURIED: - if( !board()->IsElementVisible( LAYER_VIA_BBLIND ) ) - return false; - break; - - case VIATYPE::MICROVIA: - if( !board()->IsElementVisible( LAYER_VIA_MICROVIA ) ) - return false; - break; - - default: - wxFAIL; - return false; - } - - // For vias it is enough if only one of its layers is visible - return ( board()->GetVisibleLayers() & via->GetLayerSet() ).any(); - } + // For vias it is enough if only one of its layers is visible + return ( board()->GetVisibleLayers() & via->GetLayerSet() ).any(); + } case PCB_MODULE_T: { @@ -1855,19 +1833,19 @@ bool SELECTION_TOOL::Selectable( const BOARD_ITEM* aItem, bool checkVisibilityOn MODULE* module = const_cast( static_cast( aItem ) ); - for( auto item : module->GraphicalItems() ) + for( BOARD_ITEM* item : module->GraphicalItems() ) { if( Selectable( item, true ) ) return true; } - for( auto pad : module->Pads() ) + for( D_PAD* pad : module->Pads() ) { if( Selectable( pad, true ) ) return true; } - for( auto zone : module->Zones() ) + for( ZONE_CONTAINER* zone : module->Zones() ) { if( Selectable( zone, true ) ) return true;