diff --git a/translation/pofiles/bg.po b/translation/pofiles/bg.po index 6d45c7f3cc..70ff919829 100644 --- a/translation/pofiles/bg.po +++ b/translation/pofiles/bg.po @@ -2,7 +2,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2011-11-29 21:48+0200\n" "Last-Translator: Evgeniy Ivanov \n" "Language-Team: KiCad Team \n" @@ -4506,7 +4506,7 @@ msgid "Shape" msgstr "Форма" #: common/eda_shape.cpp:574 common/eda_shape.cpp:584 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:181 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:173 #: pcbnew/pcb_track.cpp:686 msgid "Radius" msgstr "Радиус" @@ -4541,8 +4541,8 @@ msgstr "Комп. отпечатъци" #: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:155 #: pcbnew/fp_text.cpp:305 pcbnew/fp_text_grid_table.cpp:105 pcbnew/pad.cpp:1008 #: pcbnew/pcb_target.cpp:158 pcbnew/pcb_target.cpp:204 pcbnew/pcb_text.cpp:127 -#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1132 pcbnew/pcb_track.cpp:1149 -#: pcbnew/pcb_track.cpp:1168 +#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1127 pcbnew/pcb_track.cpp:1144 +#: pcbnew/pcb_track.cpp:1163 msgid "Width" msgstr "Ширина" @@ -4595,14 +4595,14 @@ msgstr "Започни DRC" msgid "Start Y" msgstr "Започни DRC" -#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1140 -#: pcbnew/pcb_track.cpp:1157 +#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1135 +#: pcbnew/pcb_track.cpp:1152 #, fuzzy msgid "End X" msgstr "Край на инструмент" -#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1142 -#: pcbnew/pcb_track.cpp:1159 +#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1137 +#: pcbnew/pcb_track.cpp:1154 #, fuzzy msgid "End Y" msgstr "Край на инструмент" @@ -4689,7 +4689,7 @@ msgstr "Ляво" #: pagelayout_editor/dialogs/properties_frame_base.cpp:89 #: pagelayout_editor/dialogs/properties_frame_base.cpp:105 #: pcbnew/dialogs/dialog_dimension_properties_base.cpp:315 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:179 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:171 #: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:117 #: pcbnew/dialogs/dialog_text_properties_base.cpp:145 msgid "Center" @@ -4965,7 +4965,7 @@ msgstr "Неуспешно отв. на файл \"%s\"" #: common/grid_tricks.cpp:278 common/tool/actions.cpp:153 #: eeschema/tools/ee_actions.cpp:148 pcbnew/dialogs/panel_setup_rules.cpp:112 -#: pcbnew/tools/edit_tool.cpp:2011 +#: pcbnew/tools/edit_tool.cpp:2016 #, fuzzy msgid "Cut" msgstr "По избор" @@ -4997,7 +4997,7 @@ msgstr "" #: common/grid_tricks.cpp:284 common/tool/actions.cpp:191 #: kicad/project_tree_pane.cpp:771 pcbnew/dialogs/panel_setup_rules.cpp:115 -#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2013 +#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2018 msgid "Delete" msgstr "Изтрий" @@ -5640,8 +5640,8 @@ msgid "Invalid size %lld: too large" msgstr "" #: common/plugins/eagle/eagle_parser.cpp:281 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:373 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:389 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:366 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:382 #, c-format msgid "Invalid Arc with radius %f and angle %f" msgstr "" @@ -17705,7 +17705,7 @@ msgstr "Избор на слой:" #: pcbnew/fp_text_grid_table.cpp:109 pcbnew/pad.cpp:980 #: pcbnew/pcb_dimension.cpp:353 pcbnew/pcb_dimension.cpp:1087 #: pcbnew/pcb_shape.cpp:159 pcbnew/pcb_target.cpp:155 pcbnew/pcb_text.cpp:120 -#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1173 +#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1168 #: pcbnew/tools/board_inspection_tool.cpp:238 #: pcbnew/tools/board_inspection_tool.cpp:385 #: pcbnew/tools/board_inspection_tool.cpp:461 @@ -21965,14 +21965,14 @@ msgstr "Други:" msgid "no layers" msgstr "2 слоя" -#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1134 -#: pcbnew/pcb_track.cpp:1151 +#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1129 +#: pcbnew/pcb_track.cpp:1146 #, fuzzy msgid "Position X" msgstr "Позиция X" -#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1137 -#: pcbnew/pcb_track.cpp:1154 +#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1132 +#: pcbnew/pcb_track.cpp:1149 #, fuzzy msgid "Position Y" msgstr "Позиция Y" @@ -26057,66 +26057,66 @@ msgstr "Неочаквана грешка при съхранение на ко msgid "Error loading footprint library table." msgstr "Архивирай или добави отпечатъци в библиотечен файл" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:178 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:170 #, fuzzy msgid "Circle Properties" msgstr "Настройки на извод" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:191 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:183 #, fuzzy msgid "Arc Properties" msgstr "Настройки" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:197 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:189 #, fuzzy msgid "Polygon Properties" msgstr "Настройки на извод" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:203 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:195 #, fuzzy msgid "Rectangle Properties" msgstr "Настройки на извод" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:209 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:201 #, fuzzy msgid "Line Segment Properties" msgstr "Библ. настройки на компонента" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:343 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:336 #, fuzzy msgid "Modify drawing properties" msgstr "Настройки за чертане" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:368 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:361 #, fuzzy msgid "The arc angle cannot be zero." msgstr "Класът на верига по подразбиране неможе да бъде премахнат" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:415 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:427 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:433 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:388 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:398 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:408 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:420 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:426 #, fuzzy msgid "The item thickness must be greater than zero." msgstr " Vout трябва да е по-голямо от vref" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:402 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 #, fuzzy msgid "The radius must be greater than zero." msgstr " Vout трябва да е по-голямо от vref" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:412 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 #, fuzzy msgid "The rectangle cannot be empty." msgstr "Класът на верига по подразбиране неможе да бъде премахнат" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:421 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:414 #, fuzzy msgid "The polygon outline thickness must be >= 0." msgstr " Vout трябва да е по-голямо от vref" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 #, fuzzy msgid "Error List" msgstr "Грешки" @@ -28469,19 +28469,19 @@ msgid "Via type:" msgstr "Форма на прох.отв.:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 #, fuzzy msgid "Through" msgstr "Проходна връзка" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 #, fuzzy msgid "Micro" msgstr "Микро проходна връзка" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 #, fuzzy msgid "Blind/buried" msgstr "Скрит/-а" @@ -30022,216 +30022,6 @@ msgstr "" msgid "Check rule syntax" msgstr "Провери модул" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 #, fuzzy msgid "Default properties for new dimension objects:" @@ -30893,13 +30683,13 @@ msgstr "Старт на запълване..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -30909,7 +30699,7 @@ msgstr "Старт на запълване..." msgid "(%s clearance %s; actual %s)" msgstr "Локална стойност на отст. на маската:" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, fuzzy, c-format msgid "(nets %s and %s)" msgstr "Елемент %d %c" @@ -32708,7 +32498,7 @@ msgstr "Завърти извод" msgid "Castellated" msgstr "Изчисли" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Диаметър" @@ -33082,7 +32872,7 @@ msgstr "Сляп/погребан прох.отв." msgid "Through Via" msgstr "Проходна връзка" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Свредел" @@ -33105,27 +32895,27 @@ msgstr "Извод %s, %s, %s" msgid "Track %s on %s, length %s" msgstr "Извод %s, %s, %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 #, fuzzy msgid "Origin X" msgstr "Начало на решетката" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 #, fuzzy msgid "Origin Y" msgstr "Начало на решетката" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 #, fuzzy msgid "Layer Top" msgstr "Слой" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 #, fuzzy msgid "Layer Bottom" msgstr "Дъно" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 #, fuzzy msgid "Via Type" msgstr "Форма на прох.отв.:" @@ -35576,27 +35366,27 @@ msgstr "Завърти" msgid "Change Side / Flip" msgstr "Промяна на размера на прох.отв. и свредлото" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 #, fuzzy msgid "Move exact" msgstr "Премести текст" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, fuzzy, c-format msgid "Duplicated %d item(s)" msgstr "Дублиране" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 #, fuzzy msgid "Select reference point for the copy..." msgstr "Установи нач.коорд. за решетката" -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 #, fuzzy msgid "Selection copied" msgstr "Избор на верига" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 #, fuzzy msgid "Copy canceled" msgstr "Копирай етикет" @@ -38156,47 +37946,47 @@ msgstr "Добави клас на верига" msgid "Presets (Ctrl+Tab):" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 #, fuzzy msgid "Save preset..." msgstr "Съхрани като" -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 #, fuzzy msgid "Delete preset..." msgstr "Изтрий лист" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 #, fuzzy msgid "Layer preset name:" msgstr "Избор на слой:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 #, fuzzy msgid "Save Layer Preset" msgstr "Запази платка" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 #, fuzzy msgid "Presets" msgstr "Нулиране" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 #, fuzzy msgid "Delete Preset" msgstr "Изтрий лист" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 #, fuzzy msgid "Select preset:" msgstr "Избор на неопроводена връзка" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 #, fuzzy msgid "Open Preferences" msgstr "Предпочитания" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." diff --git a/translation/pofiles/ca.po b/translation/pofiles/ca.po index 43f0db147a..f8026ee7c9 100644 --- a/translation/pofiles/ca.po +++ b/translation/pofiles/ca.po @@ -3,7 +3,7 @@ msgid "" msgstr "" "Project-Id-Version: kicad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-08-15 01:21+0000\n" "Last-Translator: Arnau Llovet Vidal \n" "Language-Team: Catalan \n" @@ -4238,7 +4238,7 @@ msgid "Shape" msgstr "Forma" #: common/eda_shape.cpp:574 common/eda_shape.cpp:584 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:181 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:173 #: pcbnew/pcb_track.cpp:686 msgid "Radius" msgstr "Radi" @@ -4272,8 +4272,8 @@ msgstr "Punts" #: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:155 #: pcbnew/fp_text.cpp:305 pcbnew/fp_text_grid_table.cpp:105 pcbnew/pad.cpp:1008 #: pcbnew/pcb_target.cpp:158 pcbnew/pcb_target.cpp:204 pcbnew/pcb_text.cpp:127 -#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1132 pcbnew/pcb_track.cpp:1149 -#: pcbnew/pcb_track.cpp:1168 +#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1127 pcbnew/pcb_track.cpp:1144 +#: pcbnew/pcb_track.cpp:1163 msgid "Width" msgstr "Amplada" @@ -4321,13 +4321,13 @@ msgstr "Inici X" msgid "Start Y" msgstr "Inici Y" -#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1140 -#: pcbnew/pcb_track.cpp:1157 +#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1135 +#: pcbnew/pcb_track.cpp:1152 msgid "End X" msgstr "Final X" -#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1142 -#: pcbnew/pcb_track.cpp:1159 +#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1137 +#: pcbnew/pcb_track.cpp:1154 msgid "End Y" msgstr "Final Y" @@ -4413,7 +4413,7 @@ msgstr "Esquerra" #: pagelayout_editor/dialogs/properties_frame_base.cpp:89 #: pagelayout_editor/dialogs/properties_frame_base.cpp:105 #: pcbnew/dialogs/dialog_dimension_properties_base.cpp:315 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:179 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:171 #: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:117 #: pcbnew/dialogs/dialog_text_properties_base.cpp:145 msgid "Center" @@ -4695,7 +4695,7 @@ msgstr "No es pot copiar el fitxer '%s'." #: common/grid_tricks.cpp:278 common/tool/actions.cpp:153 #: eeschema/tools/ee_actions.cpp:148 pcbnew/dialogs/panel_setup_rules.cpp:112 -#: pcbnew/tools/edit_tool.cpp:2011 +#: pcbnew/tools/edit_tool.cpp:2016 msgid "Cut" msgstr "Retalla" @@ -4725,7 +4725,7 @@ msgstr "Enganxa les cel·les del porta-retalls a la matriu en la cel·la actual" #: common/grid_tricks.cpp:284 common/tool/actions.cpp:191 #: kicad/project_tree_pane.cpp:771 pcbnew/dialogs/panel_setup_rules.cpp:115 -#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2013 +#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2018 msgid "Delete" msgstr "Elimina" @@ -5308,8 +5308,8 @@ msgid "Invalid size %lld: too large" msgstr "Mida no vàlida %lld: massa llarg" #: common/plugins/eagle/eagle_parser.cpp:281 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:373 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:389 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:366 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:382 #, c-format msgid "Invalid Arc with radius %f and angle %f" msgstr "Arc invàlid amb radi %f i angle %f" @@ -17086,7 +17086,7 @@ msgstr "Selecciona capa: %s" #: pcbnew/fp_text_grid_table.cpp:109 pcbnew/pad.cpp:980 #: pcbnew/pcb_dimension.cpp:353 pcbnew/pcb_dimension.cpp:1087 #: pcbnew/pcb_shape.cpp:159 pcbnew/pcb_target.cpp:155 pcbnew/pcb_text.cpp:120 -#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1173 +#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1168 #: pcbnew/tools/board_inspection_tool.cpp:238 #: pcbnew/tools/board_inspection_tool.cpp:385 #: pcbnew/tools/board_inspection_tool.cpp:461 @@ -21153,13 +21153,13 @@ msgstr "Altres" msgid "no layers" msgstr "Sense capes" -#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1134 -#: pcbnew/pcb_track.cpp:1151 +#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1129 +#: pcbnew/pcb_track.cpp:1146 msgid "Position X" msgstr "Posició X" -#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1137 -#: pcbnew/pcb_track.cpp:1154 +#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1132 +#: pcbnew/pcb_track.cpp:1149 msgid "Position Y" msgstr "Posició Y" @@ -25059,60 +25059,60 @@ msgstr "" msgid "Error loading footprint library table." msgstr "Error en carregar la taula de les biblioteques d'empremtes." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:178 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:170 msgid "Circle Properties" msgstr "Propietats del cercle" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:191 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:183 msgid "Arc Properties" msgstr "Propietats de l'arc" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:197 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:189 #, fuzzy msgid "Polygon Properties" msgstr "Propietats del pin" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:203 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:195 #, fuzzy msgid "Rectangle Properties" msgstr "Propietats del cercle" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:209 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:201 msgid "Line Segment Properties" msgstr "Propietats del segment de línia" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:343 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:336 msgid "Modify drawing properties" msgstr "Modifica les propietats del dibuix" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:368 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:361 #, fuzzy msgid "The arc angle cannot be zero." msgstr "L'angle de l'arc ha de ser més gran que zero." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:415 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:427 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:433 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:388 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:398 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:408 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:420 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:426 msgid "The item thickness must be greater than zero." msgstr "El gruix de l'element ha de ser més gran que zero." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:402 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 msgid "The radius must be greater than zero." msgstr "El radi ha de ser més gran que zero." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:412 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 #, fuzzy msgid "The rectangle cannot be empty." msgstr "L'angle de l'arc ha de ser més gran que zero." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:421 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:414 #, fuzzy msgid "The polygon outline thickness must be >= 0." msgstr "El gruix de l'element ha de ser més gran que zero." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Llista dels errors" @@ -27320,17 +27320,17 @@ msgid "Via type:" msgstr "Tipus de via:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "" @@ -28805,216 +28805,6 @@ msgstr "" msgid "Check rule syntax" msgstr "" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "Propietats per defecte pels nous objectes de dimensió:" @@ -29642,13 +29432,13 @@ msgstr "S'estan verificant les zones..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29658,7 +29448,7 @@ msgstr "S'estan verificant les zones..." msgid "(%s clearance %s; actual %s)" msgstr "(%s marge %s; actual %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, fuzzy, c-format msgid "(nets %s and %s)" msgstr "Rescata %s com a %s" @@ -31411,7 +31201,7 @@ msgstr "Repeteix el pin" msgid "Castellated" msgstr "Calcula" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Diàmetre" @@ -31761,7 +31551,7 @@ msgstr "Via cega o enterrada" msgid "Through Via" msgstr "A través d'una via" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Perforació" @@ -31784,25 +31574,25 @@ msgstr "Pista (arc) %s sobre %s, longitud %s" msgid "Track %s on %s, length %s" msgstr "Pista %s sobre (%s), longitud %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "Origen X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "Origen Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 #, fuzzy msgid "Layer Top" msgstr "Capa" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 #, fuzzy msgid "Layer Bottom" msgstr "Inferior" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "Tipus de via" @@ -34209,24 +33999,24 @@ msgstr "Gira" msgid "Change Side / Flip" msgstr "Canvia la mida de la via i de la perforació" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "S'ha(n) duplicat %d element(s)" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "Selecciona el punt de referència per la còpia..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "Selecció copiada" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 #, fuzzy msgid "Copy canceled" msgstr "Cancel·la" @@ -36652,44 +36442,44 @@ msgstr "Afegeix una altra classe de xarxa" msgid "Presets (Ctrl+Tab):" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "Desa pre-ajustament..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "Elimina pre-ajustament..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 #, fuzzy msgid "Layer preset name:" msgstr "Selecció de la capa:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 #, fuzzy msgid "Save Layer Preset" msgstr "Selecció del parell de capes" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 #, fuzzy msgid "Presets" msgstr "Restableix" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 #, fuzzy msgid "Delete Preset" msgstr "Elimina la xarxa" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "Selecciona predefinició:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 #, fuzzy msgid "Open Preferences" msgstr "&Preferències" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." diff --git a/translation/pofiles/cs.po b/translation/pofiles/cs.po index 4b1fcfc0a4..c09168ae8b 100644 --- a/translation/pofiles/cs.po +++ b/translation/pofiles/cs.po @@ -14,7 +14,7 @@ msgid "" msgstr "" "Project-Id-Version: kicad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-10-03 10:53+0000\n" "Last-Translator: Jan Straka \n" "Language-Team: Czech \n" @@ -4201,7 +4201,7 @@ msgid "Shape" msgstr "Tvar" #: common/eda_shape.cpp:574 common/eda_shape.cpp:584 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:181 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:173 #: pcbnew/pcb_track.cpp:686 msgid "Radius" msgstr "Poloměr" @@ -4235,8 +4235,8 @@ msgstr "Body" #: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:155 #: pcbnew/fp_text.cpp:305 pcbnew/fp_text_grid_table.cpp:105 pcbnew/pad.cpp:1008 #: pcbnew/pcb_target.cpp:158 pcbnew/pcb_target.cpp:204 pcbnew/pcb_text.cpp:127 -#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1132 pcbnew/pcb_track.cpp:1149 -#: pcbnew/pcb_track.cpp:1168 +#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1127 pcbnew/pcb_track.cpp:1144 +#: pcbnew/pcb_track.cpp:1163 msgid "Width" msgstr "Šířka" @@ -4284,13 +4284,13 @@ msgstr "Začátek X" msgid "Start Y" msgstr "Začátek Y" -#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1140 -#: pcbnew/pcb_track.cpp:1157 +#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1135 +#: pcbnew/pcb_track.cpp:1152 msgid "End X" msgstr "Konec X" -#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1142 -#: pcbnew/pcb_track.cpp:1159 +#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1137 +#: pcbnew/pcb_track.cpp:1154 msgid "End Y" msgstr "Konec Y" @@ -4376,7 +4376,7 @@ msgstr "Vlevo" #: pagelayout_editor/dialogs/properties_frame_base.cpp:89 #: pagelayout_editor/dialogs/properties_frame_base.cpp:105 #: pcbnew/dialogs/dialog_dimension_properties_base.cpp:315 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:179 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:171 #: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:117 #: pcbnew/dialogs/dialog_text_properties_base.cpp:145 msgid "Center" @@ -4657,7 +4657,7 @@ msgstr "Nelze kopírovat soubor '%s'." #: common/grid_tricks.cpp:278 common/tool/actions.cpp:153 #: eeschema/tools/ee_actions.cpp:148 pcbnew/dialogs/panel_setup_rules.cpp:112 -#: pcbnew/tools/edit_tool.cpp:2011 +#: pcbnew/tools/edit_tool.cpp:2016 msgid "Cut" msgstr "Vyjmout" @@ -4685,7 +4685,7 @@ msgstr "Vložit buňky ze schránky do matice v aktuální buňce" #: common/grid_tricks.cpp:284 common/tool/actions.cpp:191 #: kicad/project_tree_pane.cpp:771 pcbnew/dialogs/panel_setup_rules.cpp:115 -#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2013 +#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2018 msgid "Delete" msgstr "Smazat" @@ -5264,8 +5264,8 @@ msgid "Invalid size %lld: too large" msgstr "Neplatná velikost %lld: příliš velká" #: common/plugins/eagle/eagle_parser.cpp:281 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:373 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:389 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:366 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:382 #, c-format msgid "Invalid Arc with radius %f and angle %f" msgstr "Neplatný oblouk s poloměrem %f a úhlem %f" @@ -16854,7 +16854,7 @@ msgstr "Výběr vrstvy: %s" #: pcbnew/fp_text_grid_table.cpp:109 pcbnew/pad.cpp:980 #: pcbnew/pcb_dimension.cpp:353 pcbnew/pcb_dimension.cpp:1087 #: pcbnew/pcb_shape.cpp:159 pcbnew/pcb_target.cpp:155 pcbnew/pcb_text.cpp:120 -#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1173 +#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1168 #: pcbnew/tools/board_inspection_tool.cpp:238 #: pcbnew/tools/board_inspection_tool.cpp:385 #: pcbnew/tools/board_inspection_tool.cpp:461 @@ -20806,13 +20806,13 @@ msgstr "a další" msgid "no layers" msgstr "žádné vrstvy" -#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1134 -#: pcbnew/pcb_track.cpp:1151 +#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1129 +#: pcbnew/pcb_track.cpp:1146 msgid "Position X" msgstr "Pozice X" -#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1137 -#: pcbnew/pcb_track.cpp:1154 +#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1132 +#: pcbnew/pcb_track.cpp:1149 msgid "Position Y" msgstr "Pozice Y" @@ -24573,55 +24573,55 @@ msgstr "" msgid "Error loading footprint library table." msgstr "Chyba načtení tabulky knihovny pouzder." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:178 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:170 msgid "Circle Properties" msgstr "Vlastnosti kružnice" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:191 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:183 msgid "Arc Properties" msgstr "Vlastnosti oblouku" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:197 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:189 msgid "Polygon Properties" msgstr "Mnohoúhelník Vlastnosti" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:203 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:195 msgid "Rectangle Properties" msgstr "Vlastnosti obdélníku" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:209 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:201 msgid "Line Segment Properties" msgstr "Vlastnosti segmentu čáry" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:343 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:336 msgid "Modify drawing properties" msgstr "Upravit vlastnosti kresby" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:368 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:361 msgid "The arc angle cannot be zero." msgstr "Úhel oblouku nemůže být nulový." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:415 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:427 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:433 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:388 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:398 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:408 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:420 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:426 msgid "The item thickness must be greater than zero." msgstr "Tloušťka položky musí být větší než nula." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:402 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 msgid "The radius must be greater than zero." msgstr "Poloměr musí být větší než nula." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:412 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 msgid "The rectangle cannot be empty." msgstr "Obdélník nemůže být prázdný." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:421 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:414 msgid "The polygon outline thickness must be >= 0." msgstr "Tloušťka obrysu polygonu musí být> = 0." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Seznam chyb" @@ -26772,17 +26772,17 @@ msgid "Via type:" msgstr "Typ prokovu:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "Průchozí" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "Mikro" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Slepé/vnořené" @@ -28212,216 +28212,6 @@ msgstr "Pravidla DRC:" msgid "Check rule syntax" msgstr "Kontrola syntaxe pravidla" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "Výchozí vlastnosti pro nové prvky typu kóty:" @@ -29046,13 +28836,13 @@ msgstr "Kontrola zón..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29062,7 +28852,7 @@ msgstr "Kontrola zón..." msgid "(%s clearance %s; actual %s)" msgstr "(%s izolační mezera %s; aktuální %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(sítě %s a %s)" @@ -30763,7 +30553,7 @@ msgstr "Chladič" msgid "Castellated" msgstr "Vypočítat" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Průměr" @@ -31106,7 +30896,7 @@ msgstr "Slepé/vnořené prokovy" msgid "Through Via" msgstr "Průchozí prokov" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Vrtání" @@ -31129,23 +30919,23 @@ msgstr "Spoj (oblouk) %s na %s, délka %s" msgid "Track %s on %s, length %s" msgstr "Spoj %s na %s, délka %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "Počátek X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "Počátek Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "Horní vrstva" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "Spodní vrstva" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "Typ prokovu" @@ -31813,7 +31603,7 @@ msgstr "" "ekvivalent v KiCadu. Místo toho se používá plná výplň." #: pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp:3567 -#, c-format, fuzzy +#, fuzzy, c-format msgid "" "The CADSTAR Hatching code '%s' has %d hatches defined. KiCad only supports 2 " "hatches (crosshatching) 90 degrees apart. The imported hatching is " @@ -33627,25 +33417,25 @@ msgstr "Otočit" msgid "Change Side / Flip" msgstr "Změnit stranu / Obrátit" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "Přesunout přesně" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "Duplikována %d položka(y)" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 #, fuzzy msgid "Select reference point for the copy..." msgstr "Vybrat referenční bod pro kopírování..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "Výběr zkopírován" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "Kopírování zrušeno" @@ -35927,39 +35717,39 @@ msgstr "Skrýt všechny ostatní třídy sítí" msgid "Presets (Ctrl+Tab):" msgstr "Přednastavuje (Ctrl+Tab):" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "Uložit předvolbu..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "Smazat předvolbu..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "Název předvolby vrstvy:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "Uložit předvolbu vrstvy" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "Předvolby" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "Smazat předvolbu" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "Vybrat předvolbu:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "Otevřít Předvolby" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." diff --git a/translation/pofiles/da.po b/translation/pofiles/da.po index a8fbd3f593..2b00e484c3 100644 --- a/translation/pofiles/da.po +++ b/translation/pofiles/da.po @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2021-08-20 19:52+0000\n" "Last-Translator: Seth Hillbrand \n" "Language-Team: Danish = 0." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Fejlliste" @@ -27520,17 +27520,17 @@ msgid "Via type:" msgstr "Via type:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "igennem" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "Micro" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Blind / begravet" @@ -28997,216 +28997,6 @@ msgstr "DRC-regler:" msgid "Check rule syntax" msgstr "Tjek regelsyntaks" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "Standardegenskaber for nye dimensionobjekter:" @@ -29831,13 +29621,13 @@ msgstr "Kontrol af zoneudfyldning ..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29847,7 +29637,7 @@ msgstr "Kontrol af zoneudfyldning ..." msgid "(%s clearance %s; actual %s)" msgstr "(%s clearance %s; faktisk %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(net %s og %s)" @@ -31602,7 +31392,7 @@ msgstr "Kølelegeme" msgid "Castellated" msgstr "Castelleret" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Diameter" @@ -31953,7 +31743,7 @@ msgstr "Blind / Begravet Via" msgid "Through Via" msgstr "Gennem Via" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Bore" @@ -31976,23 +31766,23 @@ msgstr "Spor %s på %s, længde %s" msgid "Track %s on %s, length %s" msgstr "Spor %s på %s, længde %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "Oprindelse X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "Oprindelse Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "Layer Top" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "Lagbund" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "Via Type" @@ -34568,24 +34358,24 @@ msgstr "Roter" msgid "Change Side / Flip" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "Flyt nøjagtigt" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "Kopieret %d vare (r)" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "Vælg referencepunkt for kopien ..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "Valg kopieret" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 #, fuzzy msgid "Copy canceled" msgstr "Kopi annulleret" @@ -36859,39 +36649,39 @@ msgstr "Skjul alle andre netklasser" msgid "Presets (Ctrl+Tab):" msgstr "(Ctrl + Tab)" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "Gem forudindstilling ..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "Slet forudindstilling ..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "Lagets forudindstillede navn:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "Gem lagindstilling" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "Forudindstilling" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "Slet forudindstilling" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "Vælg forudindstilling:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "Åben præferencer" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." diff --git a/translation/pofiles/de.po b/translation/pofiles/de.po index c1eb3710da..1a3fb92a98 100644 --- a/translation/pofiles/de.po +++ b/translation/pofiles/de.po @@ -14,7 +14,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad i18n Deutsch\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-08-21 02:52+0000\n" "Last-Translator: Seth Hillbrand \n" "Language-Team: German \n" @@ -4265,7 +4265,7 @@ msgid "Shape" msgstr "Form" #: common/eda_shape.cpp:574 common/eda_shape.cpp:584 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:181 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:173 #: pcbnew/pcb_track.cpp:686 msgid "Radius" msgstr "Radius" @@ -4299,8 +4299,8 @@ msgstr "Punkte" #: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:155 #: pcbnew/fp_text.cpp:305 pcbnew/fp_text_grid_table.cpp:105 pcbnew/pad.cpp:1008 #: pcbnew/pcb_target.cpp:158 pcbnew/pcb_target.cpp:204 pcbnew/pcb_text.cpp:127 -#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1132 pcbnew/pcb_track.cpp:1149 -#: pcbnew/pcb_track.cpp:1168 +#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1127 pcbnew/pcb_track.cpp:1144 +#: pcbnew/pcb_track.cpp:1163 msgid "Width" msgstr "Breite" @@ -4348,13 +4348,13 @@ msgstr "Start X" msgid "Start Y" msgstr "Start Y" -#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1140 -#: pcbnew/pcb_track.cpp:1157 +#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1135 +#: pcbnew/pcb_track.cpp:1152 msgid "End X" msgstr "Ende X" -#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1142 -#: pcbnew/pcb_track.cpp:1159 +#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1137 +#: pcbnew/pcb_track.cpp:1154 msgid "End Y" msgstr "Ende Y" @@ -4440,7 +4440,7 @@ msgstr "Links" #: pagelayout_editor/dialogs/properties_frame_base.cpp:89 #: pagelayout_editor/dialogs/properties_frame_base.cpp:105 #: pcbnew/dialogs/dialog_dimension_properties_base.cpp:315 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:179 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:171 #: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:117 #: pcbnew/dialogs/dialog_text_properties_base.cpp:145 msgid "Center" @@ -4731,7 +4731,7 @@ msgstr "Datei \"%s\" konnte nicht kopiert werden." #: common/grid_tricks.cpp:278 common/tool/actions.cpp:153 #: eeschema/tools/ee_actions.cpp:148 pcbnew/dialogs/panel_setup_rules.cpp:112 -#: pcbnew/tools/edit_tool.cpp:2011 +#: pcbnew/tools/edit_tool.cpp:2016 msgid "Cut" msgstr "Ausschneiden" @@ -4762,7 +4762,7 @@ msgstr "" #: common/grid_tricks.cpp:284 common/tool/actions.cpp:191 #: kicad/project_tree_pane.cpp:771 pcbnew/dialogs/panel_setup_rules.cpp:115 -#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2013 +#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2018 msgid "Delete" msgstr "Entfernen" @@ -5343,8 +5343,8 @@ msgid "Invalid size %lld: too large" msgstr "Ungültige Größe %lld: zu groß" #: common/plugins/eagle/eagle_parser.cpp:281 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:373 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:389 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:366 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:382 #, c-format msgid "Invalid Arc with radius %f and angle %f" msgstr "Ungültiger Bogen mit Radius %f und Winkel %f" @@ -17126,7 +17126,7 @@ msgstr "Wähle Lage: %s" #: pcbnew/fp_text_grid_table.cpp:109 pcbnew/pad.cpp:980 #: pcbnew/pcb_dimension.cpp:353 pcbnew/pcb_dimension.cpp:1087 #: pcbnew/pcb_shape.cpp:159 pcbnew/pcb_target.cpp:155 pcbnew/pcb_text.cpp:120 -#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1173 +#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1168 #: pcbnew/tools/board_inspection_tool.cpp:238 #: pcbnew/tools/board_inspection_tool.cpp:385 #: pcbnew/tools/board_inspection_tool.cpp:461 @@ -21144,13 +21144,13 @@ msgstr "und andere" msgid "no layers" msgstr "Keine Lagen" -#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1134 -#: pcbnew/pcb_track.cpp:1151 +#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1129 +#: pcbnew/pcb_track.cpp:1146 msgid "Position X" msgstr "Position X" -#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1137 -#: pcbnew/pcb_track.cpp:1154 +#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1132 +#: pcbnew/pcb_track.cpp:1149 msgid "Position Y" msgstr "Position Y" @@ -25006,55 +25006,55 @@ msgstr "" msgid "Error loading footprint library table." msgstr "Fehler beim Laden der Footprintbibliothek-Tabelle." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:178 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:170 msgid "Circle Properties" msgstr "Kreis-Eigenschaften" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:191 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:183 msgid "Arc Properties" msgstr "Kreisbogen-Eigenschaften" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:197 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:189 msgid "Polygon Properties" msgstr "Polygon-Eigenschaften" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:203 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:195 msgid "Rectangle Properties" msgstr "Rechteck-Eigenschaften" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:209 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:201 msgid "Line Segment Properties" msgstr "Liniensegment-Eigenschaften" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:343 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:336 msgid "Modify drawing properties" msgstr "Darstellungs-Eigenschaften" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:368 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:361 msgid "The arc angle cannot be zero." msgstr "Der Bogenwinkel darf nicht Null sein." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:415 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:427 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:433 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:388 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:398 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:408 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:420 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:426 msgid "The item thickness must be greater than zero." msgstr "Die Breite des Elements muss größer als 0 sein." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:402 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 msgid "The radius must be greater than zero." msgstr "Der Radius muss größer als 0 sein." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:412 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 msgid "The rectangle cannot be empty." msgstr "Das Rechteck darf nicht leer sein." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:421 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:414 msgid "The polygon outline thickness must be >= 0." msgstr "Die Polygon Konturenstärke muss auf >=0 gesetzt werden." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Fehlerliste" @@ -27262,17 +27262,17 @@ msgid "Via type:" msgstr "Via-Typ:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "Durchkontaktierung" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "Mikro" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Blind/vergraben" @@ -28784,433 +28784,6 @@ msgstr "DRC-Regeln:" msgid "Check rule syntax" msgstr "Überprüfen Sie die Regelsyntax" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" -"### Übergeordnete Bestimmungen\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Regel-Bestimmungen\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Einschränkungs-Typen\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Element-Typen\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Beispiele\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Hinweise\n" -"\n" -"Die Versionsbestimmung muss die erste Bestimmung sein. Sie zeigt die Version " -"der Datei an, sodass\n" -"zukünftige Parser der Datei die Version bestimmen können.\n" -"Sie sollte auf \"1\" gesetzt sein.\n" -"\n" -"Regeln sollten nach ihrer Spezifität geordnet werden. Spätere Regeln haben " -"Vorrang\n" -"vor früheren Regeln; sobald eine passende Regel gefunden wurde, werden " -"keine\n" -"weiteren Regeln mehr geprüft.\n" -"\n" -"Verwenden Sie Strg+/, um die Zeile(n) zu kommentieren oder zu " -"entkommentieren.\n" -"


\n" -"\n" -"### Ausdrucks-Funktionen\n" -"\n" -"Alle Funktionsparameter unterstützen einfache Wildcards (`*` und `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"Wahr, wenn ein Teil von `A` innerhalb des wesentlichen Sperrbereichs des " -"angegebenen Footprints liegt.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"Wahr, wenn ein Teil von `A` innerhalb des vorderseitigen Sperrbereichs des " -"angegebenen Footprints liegt.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"Wahr, wenn ein Teil von `A` innerhalb des rückseitigen Sperrbereichs des " -"angegebenen Footprints liegt.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"Wahr, wenn ein Teil von `A` innerhalb des angegebenen Zonenumrisses liegt.\n" -"

\n" -"\n" -" A.isPlated()\n" -"Wahr, wenn `A` ein metallisiertes Loch hat.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"Wahr, wenn `A` Teil des angegebenen Differenzialpaars ist.\n" -"`` ist der Basisname des Differenzialpaars. Beispielsweise passt " -"`inDiffPair('/CLK')`\n" -"zu Elementen in den `/CLK_P`- und `/CLK_N`-Netzen.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"Wahr, wenn `A` und `B` Teile des selben Differenzialpaars sind.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"Wahr, wenn `A` Mitglied der angegebenen Gruppe ist. Erlaubt verschachtelte " -"Gruppen.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"Wahr, wenn `A` auf der angegebenen Lage existiert. Der Lagenname kann einer " -"der Namen aus\n" -"Platinenaufbau > Platineneditor-Lagen oder der interne Name\n" -"(wie `F.Cu`).\n" -"\n" -"Hinweis: Dies gibt wahr zurück, wenn `A` auf der angegebenen Lage liegt, " -"unabhängig\n" -"davon, ob diese Regel für die angegebene Lage angewendet wird.\n" -"Für letzteres die `(layer \"layer_name\")`-Bestimmung in der Regel " -"benutzen.\n" -"


\n" -"\n" -"### Weitere Beispiele\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Via' && A.Net != B.Net" -"\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B.Net" -"\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type == 'Pad' && B.Type == 'Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer == 'Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "Standardwerte für neue Bemaßungsobjekte:" @@ -29814,13 +29387,13 @@ msgstr "Prüfe Zonen ..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29830,7 +29403,7 @@ msgstr "Prüfe Zonen ..." msgid "(%s clearance %s; actual %s)" msgstr "(%s Abstand %s; tatsächlich %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(Netze %s und %s)" @@ -31578,7 +31151,7 @@ msgstr "Kühlkörper" msgid "Castellated" msgstr "Castellated (Halbloch)" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Durchmesser" @@ -31921,7 +31494,7 @@ msgstr "Blinde/Vergrabene Vias" msgid "Through Via" msgstr "Durchkontaktierung" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Bohrung" @@ -31944,23 +31517,23 @@ msgstr "Leiterbahn (Bogen) %s auf %s, Länge %s" msgid "Track %s on %s, length %s" msgstr "Leiterbahn %s auf %s, Länge %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "Ursprung X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "Ursprung Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "Lage Oben" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "Lage Unten" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "Via-Typ" @@ -34520,24 +34093,24 @@ msgstr "Drehen" msgid "Change Side / Flip" msgstr "Seite wechseln / spiegeln" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "Exakt verschieben" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "%d doppelte(s) Element(e)" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "Bezugspunkt für das Kopieren setzen ..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "Auswahl kopiert" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "Kopieren abgebrochen" @@ -36782,39 +36355,39 @@ msgstr "Alle anderen Netzklassen verbergen" msgid "Presets (Ctrl+Tab):" msgstr "Voreinstellungen (Strg+Tab):" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "Voreinstellung speichern..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "Voreinstellung löschen..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "Name der Lagen-Voreinstellung:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "Lagen-Voreinstellung speichern" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "Voreinstellungen" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "Voreinstellung löschen" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "Voreinstellung wählen:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "Einstellungen öffnen" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." @@ -37120,6 +36693,437 @@ msgstr "KiCad-Schaltplan" msgid "KiCad Printed Circuit Board" msgstr "KiCad-Leiterplatte" +#~ msgid "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('/CLK')`\n" +#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" +#~ msgstr "" +#~ "### Übergeordnete Bestimmungen\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Regel-Bestimmungen\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Einschränkungs-Typen\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Element-Typen\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Beispiele\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Hinweise\n" +#~ "\n" +#~ "Die Versionsbestimmung muss die erste Bestimmung sein. Sie zeigt die " +#~ "Version der Datei an, sodass\n" +#~ "zukünftige Parser der Datei die Version bestimmen können.\n" +#~ "Sie sollte auf \"1\" gesetzt sein.\n" +#~ "\n" +#~ "Regeln sollten nach ihrer Spezifität geordnet werden. Spätere Regeln " +#~ "haben Vorrang\n" +#~ "vor früheren Regeln; sobald eine passende Regel gefunden wurde, werden " +#~ "keine\n" +#~ "weiteren Regeln mehr geprüft.\n" +#~ "\n" +#~ "Verwenden Sie Strg+/, um die Zeile(n) zu kommentieren oder zu " +#~ "entkommentieren.\n" +#~ "


\n" +#~ "\n" +#~ "### Ausdrucks-Funktionen\n" +#~ "\n" +#~ "Alle Funktionsparameter unterstützen einfache Wildcards (`*` und `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "Wahr, wenn ein Teil von `A` innerhalb des wesentlichen Sperrbereichs des " +#~ "angegebenen Footprints liegt.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "Wahr, wenn ein Teil von `A` innerhalb des vorderseitigen Sperrbereichs " +#~ "des angegebenen Footprints liegt.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "Wahr, wenn ein Teil von `A` innerhalb des rückseitigen Sperrbereichs des " +#~ "angegebenen Footprints liegt.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "Wahr, wenn ein Teil von `A` innerhalb des angegebenen Zonenumrisses " +#~ "liegt.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "Wahr, wenn `A` ein metallisiertes Loch hat.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "Wahr, wenn `A` Teil des angegebenen Differenzialpaars ist.\n" +#~ "`` ist der Basisname des Differenzialpaars. Beispielsweise " +#~ "passt `inDiffPair('/CLK')`\n" +#~ "zu Elementen in den `/CLK_P`- und `/CLK_N`-Netzen.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "Wahr, wenn `A` und `B` Teile des selben Differenzialpaars sind.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "Wahr, wenn `A` Mitglied der angegebenen Gruppe ist. Erlaubt " +#~ "verschachtelte Gruppen.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "Wahr, wenn `A` auf der angegebenen Lage existiert. Der Lagenname kann " +#~ "einer der Namen aus\n" +#~ "Platinenaufbau > Platineneditor-Lagen oder der interne Name\n" +#~ "(wie `F.Cu`).\n" +#~ "\n" +#~ "Hinweis: Dies gibt wahr zurück, wenn `A` auf der angegebenen Lage liegt, " +#~ "unabhängig\n" +#~ "davon, ob diese Regel für die angegebene Lage angewendet wird.\n" +#~ "Für letzteres die `(layer \"layer_name\")`-Bestimmung in der Regel " +#~ "benutzen.\n" +#~ "


\n" +#~ "\n" +#~ "### Weitere Beispiele\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == 'Pad' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer == 'Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" + #, fuzzy, c-format #~ msgid "Unable to locate padstack %s in file %s\n" #~ msgstr "Kann Archivdatei \"%s\" nicht erstellen\n" diff --git a/translation/pofiles/el.po b/translation/pofiles/el.po index 342fdcdc25..cfe542c40e 100644 --- a/translation/pofiles/el.po +++ b/translation/pofiles/el.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2021-11-21 21:17+0000\n" "Last-Translator: aris-kimi \n" "Language-Team: Greek = 0." msgstr "Το πάχος του πολύγωνου πρέπει να είναι > = 0." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Λίστα Σφαλμάτων" @@ -27228,17 +27228,17 @@ msgid "Via type:" msgstr "Τύπος διέλευσης:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "Διαμπερές" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "Micro" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Τυφλό/ενταφιασμένο" @@ -28750,432 +28750,6 @@ msgstr "Κανόνες ΕΚΣ:" msgid "Check rule syntax" msgstr "Ελέγξτε τη σύνταξη κανόνων" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -#, fuzzy -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" -"### Κανόνες ανώτατου επιπέδου \n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Κανόνες\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Τύποι περιορισμών\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Τύποι αντικειμένων\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Παραδείγματα\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Σημειώσεις\n" -"\n" -"Ο κανόνας για την έκδοση πρέπει να είναι ο πρώτος κανόνας. Υποδεικνύει την " -"έκδοση του συντακτικού του αρχείου ώστε \n" -"μελλοντικοί αναγνώστες κανόνων να μπορούν να το αναβαθμίσουν αυτόματα. " -"Πρέπει να έχει την\n" -"τιμή \"1\".\n" -"\n" -"Οι κανόνες θα πρέπει να ταξινομούνται κατά ειδικότητα. Μεταγενέστεροι " -"κανόνες υπερισχύουν των προγενέστερων, όταν εντοπιστεί κανόνας που " -"ικανοποιείται δεν ελέγχονται άλλοι κανόνες.\n" -"\n" -"Χρήση Ctrl+/για μετατροπή γραμμής σε σχόλιο.\n" -"


\n" -"\n" -"### Εκφράσεις συναρτήσεων\n" -"\n" -"Όλες οι παράμετροι των συναρτήσεων υποστηρίζουν τα απλά wildcards (`*` και `?" -"`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"Αληθές εαν κάποιο μέρος του `A` βρεθεί εντός της περιοχής του επιλεγμένου " -"αποτυπώματος.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"Αληθές εαν κάποιο μέρος του `A` βρεθεί εντός της εμπρόσθιας περιοχής του " -"επιλεγμένου αποτυπώματος.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"Αληθές εαν κάποιο μέρος του `A` βρεθεί εντός της πίσω περιοχής του " -"επιλεγμένου αποτυπώματος.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"Αληθές εαν κάποιο μέρος του `A` βρεθεί εντός του περιγράμματος της " -"επιλεγμένης ζώνης.\n" -"

\n" -"\n" -" A.isPlated()\n" -"Αληθές εαν το`A` περιέχει επιμεταλλωμένη οπή.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"Αληθές εαν το `A` περιέχει δίκτυο που αποτελεί μέρος του επιλεγμένου " -"διαφορικού ζεύγους.\n" -"`` είναι το βασικό όνομα του διαφορικού ζεύγους. Για παράδειγμα, " -"`inDiffPair('CLK')`\n" -"ταιριάζει με τα δίκτυα `CLK_P` και `CLK_N`.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"Αληθές εαν το `A` και το `B` αποτελούν μέλη του ίδιου διαφορικού ζεύγους.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"Αληθές εαν το `A` αποτελεί μέλος της επιλεγμένης ομάδας. Εμπεριέχει " -"εμφωλευμένη ομαδοποίηση.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"Αληθές εαν το `A` υπάρχει στο επιλεγμένο επίπεδο. Το όνομα του επιπέδου " -"μπορεί να είναι\n" -"είτε εκείνο που αποδώθηκε στο Ρύθμιση Πλακέτας > Επίπεδα Επεξεργαστή " -"Πλακέτας ή\n" -"το κανονικό όνομα (πχ: `F.Cu`).\n" -"\n" -"NB: επιστρέφει αληθές εαν το `A` υπάρχει στο επιλεγμένο επίπεδο, ανεξάρτητα\n" -"από το εαν ο κανόνας αξιολογείται για εκείνο το επίπεδο ή όχι.\n" -"Για αυτή τη χρήση `(layer \"layer_name\")` είναι η ρήτρα στον κανόνα.\n" -"


\n" -"\n" -"### Περισσότερα παραδείγματα\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\" \n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\" \n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\" \n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" -" \n" -" (rule \"Pad to Track Clearance\" \n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\" \n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -" \n" -" (rule \"Max Drill Hole Size PTH\" \n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "Προεπιλεγμένες ιδιότητες για νέα αντικείμενα διαστάσεων:" @@ -29780,13 +29354,13 @@ msgstr "Έλεγχος γεμίσματος ζωνών..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29796,7 +29370,7 @@ msgstr "Έλεγχος γεμίσματος ζωνών..." msgid "(%s clearance %s; actual %s)" msgstr "(%s διάκενο %s; πραγματικό %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(nets %s και %s)" @@ -31523,7 +31097,7 @@ msgstr "Ψύκτρα" msgid "Castellated" msgstr "Οδοντωτό" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Διάμετρος" @@ -31865,7 +31439,7 @@ msgstr "Τυφλή/Ενταφιασμένη Διέλευση" msgid "Through Via" msgstr "Διαμπερή Διέλευση" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Διάτρηση" @@ -31888,23 +31462,23 @@ msgstr "Διάδρομος %s σε %s, μήκος %s" msgid "Track %s on %s, length %s" msgstr "Διάδρομος %s σε %s, μήκος %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "Προέλευση Χ" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "Προέλευση Ψ" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "Επίπεδo" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "Κάτω" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "Τύπος Διέλευσης" @@ -34470,24 +34044,24 @@ msgstr "Περιστροφή" msgid "Change Side / Flip" msgstr "Αλλαγή Πλευράς / Αναποδογύρισμα" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "Μετακίνηση ακριβείας" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "Αναπαράχθηκαν %d αντικείμενα" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "Επιλογή σημείου αναφοράς για το αντίγραφο..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "Επιλογή αντιγράφηκε" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "Αντιγραφή ακυρώθηκε" @@ -36722,39 +36296,39 @@ msgstr "Απόκρυψη Όλων των Άλλων Κλάσεων Δικτύο msgid "Presets (Ctrl+Tab):" msgstr "Προκαθορισμένα (Ctrl + Tab):" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "Αποθήκευση προεπιλογής..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "Διαγραφή προεπιλογής..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "Προεπιλεγμένο όνομα επιπέδου:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "Αποθήκευση Προεπιλογής Επιπέδου" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "Προεπιλογές" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "Διαγραφή Προεπιλογής" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "Επιλογή προεπιλογής:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "Άνοιγμα Προτιμήσεων" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." @@ -37063,6 +36637,439 @@ msgstr "Σχηματικό KiCad" msgid "KiCad Printed Circuit Board" msgstr "Πλακέτα Τυπωμένου Κυκλώματος KiCad" +#, fuzzy +#~ msgid "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('/CLK')`\n" +#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" +#~ msgstr "" +#~ "### Κανόνες ανώτατου επιπέδου \n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Κανόνες\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Τύποι περιορισμών\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Τύποι αντικειμένων\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Παραδείγματα\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Σημειώσεις\n" +#~ "\n" +#~ "Ο κανόνας για την έκδοση πρέπει να είναι ο πρώτος κανόνας. Υποδεικνύει " +#~ "την έκδοση του συντακτικού του αρχείου ώστε \n" +#~ "μελλοντικοί αναγνώστες κανόνων να μπορούν να το αναβαθμίσουν αυτόματα. " +#~ "Πρέπει να έχει την\n" +#~ "τιμή \"1\".\n" +#~ "\n" +#~ "Οι κανόνες θα πρέπει να ταξινομούνται κατά ειδικότητα. Μεταγενέστεροι " +#~ "κανόνες υπερισχύουν των προγενέστερων, όταν εντοπιστεί κανόνας που " +#~ "ικανοποιείται δεν ελέγχονται άλλοι κανόνες.\n" +#~ "\n" +#~ "Χρήση Ctrl+/για μετατροπή γραμμής σε σχόλιο.\n" +#~ "


\n" +#~ "\n" +#~ "### Εκφράσεις συναρτήσεων\n" +#~ "\n" +#~ "Όλες οι παράμετροι των συναρτήσεων υποστηρίζουν τα απλά wildcards (`*` " +#~ "και `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "Αληθές εαν κάποιο μέρος του `A` βρεθεί εντός της περιοχής του επιλεγμένου " +#~ "αποτυπώματος.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "Αληθές εαν κάποιο μέρος του `A` βρεθεί εντός της εμπρόσθιας περιοχής του " +#~ "επιλεγμένου αποτυπώματος.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "Αληθές εαν κάποιο μέρος του `A` βρεθεί εντός της πίσω περιοχής του " +#~ "επιλεγμένου αποτυπώματος.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "Αληθές εαν κάποιο μέρος του `A` βρεθεί εντός του περιγράμματος της " +#~ "επιλεγμένης ζώνης.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "Αληθές εαν το`A` περιέχει επιμεταλλωμένη οπή.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "Αληθές εαν το `A` περιέχει δίκτυο που αποτελεί μέρος του επιλεγμένου " +#~ "διαφορικού ζεύγους.\n" +#~ "`` είναι το βασικό όνομα του διαφορικού ζεύγους. Για " +#~ "παράδειγμα, `inDiffPair('CLK')`\n" +#~ "ταιριάζει με τα δίκτυα `CLK_P` και `CLK_N`.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "Αληθές εαν το `A` και το `B` αποτελούν μέλη του ίδιου διαφορικού " +#~ "ζεύγους.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "Αληθές εαν το `A` αποτελεί μέλος της επιλεγμένης ομάδας. Εμπεριέχει " +#~ "εμφωλευμένη ομαδοποίηση.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "Αληθές εαν το `A` υπάρχει στο επιλεγμένο επίπεδο. Το όνομα του επιπέδου " +#~ "μπορεί να είναι\n" +#~ "είτε εκείνο που αποδώθηκε στο Ρύθμιση Πλακέτας > Επίπεδα Επεξεργαστή " +#~ "Πλακέτας ή\n" +#~ "το κανονικό όνομα (πχ: `F.Cu`).\n" +#~ "\n" +#~ "NB: επιστρέφει αληθές εαν το `A` υπάρχει στο επιλεγμένο επίπεδο, " +#~ "ανεξάρτητα\n" +#~ "από το εαν ο κανόνας αξιολογείται για εκείνο το επίπεδο ή όχι.\n" +#~ "Για αυτή τη χρήση `(layer \"layer_name\")` είναι η ρήτρα στον κανόνα.\n" +#~ "


\n" +#~ "\n" +#~ "### Περισσότερα παραδείγματα\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\" \n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\" \n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\" \n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" +#~ " \n" +#~ " (rule \"Pad to Track Clearance\" \n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\" \n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ " \n" +#~ " (rule \"Max Drill Hole Size PTH\" \n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" + #, fuzzy, c-format #~ msgid "Unable to locate padstack %s in file %s\n" #~ msgstr "Αδυναμία δημιουργίας αρχείου zip \"%s\"\n" diff --git a/translation/pofiles/en.po b/translation/pofiles/en.po index ff2cafae02..96ce142a77 100644 --- a/translation/pofiles/en.po +++ b/translation/pofiles/en.po @@ -2,7 +2,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2018-07-15 17:07+0200\n" "Last-Translator: Simon Richter \n" "Language-Team: Simon Richter \n" @@ -20092,421 +20092,6 @@ msgstr "DRC rules:" msgid "Check rule syntax" msgstr "Check rule syntax" -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" - msgid "Default properties for new dimension objects:" msgstr "Default properties for new dimension objects:" @@ -26417,6 +26002,429 @@ msgstr "KiCad Schematic" msgid "KiCad Printed Circuit Board" msgstr "KiCad Printed Circuit Board" +#~ msgid "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('/CLK')`\n" +#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" +#~ msgstr "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('/CLK')`\n" +#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" + #, c-format #~ msgid "Unable to locate padstack %s in file %s\n" #~ msgstr "Unable to locate padstack %s in file %s\n" diff --git a/translation/pofiles/es.po b/translation/pofiles/es.po index b7548870ec..847020ddb9 100644 --- a/translation/pofiles/es.po +++ b/translation/pofiles/es.po @@ -13,7 +13,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad Spanish Translation\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-05-18 06:39+0000\n" "Last-Translator: VicSanRoPe \n" "Language-Team: Spanish \n" @@ -4237,7 +4237,7 @@ msgid "Shape" msgstr "Forma" #: common/eda_shape.cpp:574 common/eda_shape.cpp:584 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:181 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:173 #: pcbnew/pcb_track.cpp:686 msgid "Radius" msgstr "Radio" @@ -4271,8 +4271,8 @@ msgstr "Puntos" #: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:155 #: pcbnew/fp_text.cpp:305 pcbnew/fp_text_grid_table.cpp:105 pcbnew/pad.cpp:1008 #: pcbnew/pcb_target.cpp:158 pcbnew/pcb_target.cpp:204 pcbnew/pcb_text.cpp:127 -#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1132 pcbnew/pcb_track.cpp:1149 -#: pcbnew/pcb_track.cpp:1168 +#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1127 pcbnew/pcb_track.cpp:1144 +#: pcbnew/pcb_track.cpp:1163 msgid "Width" msgstr "Ancho" @@ -4320,13 +4320,13 @@ msgstr "Inicio X" msgid "Start Y" msgstr "Inicio Y" -#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1140 -#: pcbnew/pcb_track.cpp:1157 +#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1135 +#: pcbnew/pcb_track.cpp:1152 msgid "End X" msgstr "Final X" -#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1142 -#: pcbnew/pcb_track.cpp:1159 +#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1137 +#: pcbnew/pcb_track.cpp:1154 msgid "End Y" msgstr "Final Y" @@ -4412,7 +4412,7 @@ msgstr "Izquierda" #: pagelayout_editor/dialogs/properties_frame_base.cpp:89 #: pagelayout_editor/dialogs/properties_frame_base.cpp:105 #: pcbnew/dialogs/dialog_dimension_properties_base.cpp:315 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:179 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:171 #: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:117 #: pcbnew/dialogs/dialog_text_properties_base.cpp:145 msgid "Center" @@ -4697,7 +4697,7 @@ msgstr "No puede copiarse al archivo '%s'." #: common/grid_tricks.cpp:278 common/tool/actions.cpp:153 #: eeschema/tools/ee_actions.cpp:148 pcbnew/dialogs/panel_setup_rules.cpp:112 -#: pcbnew/tools/edit_tool.cpp:2011 +#: pcbnew/tools/edit_tool.cpp:2016 msgid "Cut" msgstr "Cortar" @@ -4727,7 +4727,7 @@ msgstr "Pegar celdas del portapapeles a la matriz en la celda activa" #: common/grid_tricks.cpp:284 common/tool/actions.cpp:191 #: kicad/project_tree_pane.cpp:771 pcbnew/dialogs/panel_setup_rules.cpp:115 -#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2013 +#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2018 msgid "Delete" msgstr "Eliminar" @@ -5311,8 +5311,8 @@ msgid "Invalid size %lld: too large" msgstr "Tamaño no válido %lld: demasiado grande" #: common/plugins/eagle/eagle_parser.cpp:281 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:373 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:389 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:366 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:382 #, c-format msgid "Invalid Arc with radius %f and angle %f" msgstr "Arco no válido con radio %f y ángulo %f" @@ -17047,7 +17047,7 @@ msgstr "Seleccionar capa: %s" #: pcbnew/fp_text_grid_table.cpp:109 pcbnew/pad.cpp:980 #: pcbnew/pcb_dimension.cpp:353 pcbnew/pcb_dimension.cpp:1087 #: pcbnew/pcb_shape.cpp:159 pcbnew/pcb_target.cpp:155 pcbnew/pcb_text.cpp:120 -#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1173 +#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1168 #: pcbnew/tools/board_inspection_tool.cpp:238 #: pcbnew/tools/board_inspection_tool.cpp:385 #: pcbnew/tools/board_inspection_tool.cpp:461 @@ -21071,13 +21071,13 @@ msgstr "y otros" msgid "no layers" msgstr "sin capas" -#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1134 -#: pcbnew/pcb_track.cpp:1151 +#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1129 +#: pcbnew/pcb_track.cpp:1146 msgid "Position X" msgstr "Posición X" -#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1137 -#: pcbnew/pcb_track.cpp:1154 +#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1132 +#: pcbnew/pcb_track.cpp:1149 msgid "Position Y" msgstr "Posición Y" @@ -24924,55 +24924,55 @@ msgstr "" msgid "Error loading footprint library table." msgstr "Error al cargar la tabla de librerías de huellas." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:178 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:170 msgid "Circle Properties" msgstr "Propiedades del círculo" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:191 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:183 msgid "Arc Properties" msgstr "Propiedades del arco" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:197 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:189 msgid "Polygon Properties" msgstr "Propiedades del polígono" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:203 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:195 msgid "Rectangle Properties" msgstr "Propiedades del rectángulo" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:209 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:201 msgid "Line Segment Properties" msgstr "Propiedades del segmento" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:343 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:336 msgid "Modify drawing properties" msgstr "Modificar las propiedades de dibujo" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:368 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:361 msgid "The arc angle cannot be zero." msgstr "El ángulo del arco no puede ser cero." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:415 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:427 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:433 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:388 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:398 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:408 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:420 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:426 msgid "The item thickness must be greater than zero." msgstr "El grosor del elemento debe ser mayor de cero." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:402 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 msgid "The radius must be greater than zero." msgstr "El radio debe ser mayor de cero." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:412 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 msgid "The rectangle cannot be empty." msgstr "El rectángulo no puede estar vacío." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:421 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:414 msgid "The polygon outline thickness must be >= 0." msgstr "El grosor del perímetro del polígono debe ser >=." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Lista de errores" @@ -27179,17 +27179,17 @@ msgid "Via type:" msgstr "Tipo de vía:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "Pasante" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "Micro" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Ciega/Enterrada" @@ -28686,429 +28686,6 @@ msgstr "Reglas de DRC:" msgid "Check rule syntax" msgstr "Verificar reglas de sintaxis" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -#, fuzzy -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" -"### Cláusulas de nivel superior\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Cláusulas de reglas\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Tipos de requerimientos\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Tipos de elementos\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Ejemplos\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notas\n" -"\n" -"La cláusula de versión tiene que ser la primera cláusula.\n" -"Indica la versión de sintaxis del archivo para que analizadores de reglas\n" -"futuros puedan realizar actualizaciones automáticas. Debería ser fijado a " -"\"1\".\n" -"\n" -"Las reglas deberían ser ordenadas por especificidad.\n" -"Las reglas posteriores tienen precedencia sobre las reglas anteriores;\n" -"una vez que se encuentra una regla coincidente, no se comprobarán más " -"reglas.\n" -"\n" -"Use Ctrl+/ para comentar o descomentar la(s) línea(s).\n" -"


\n" -"\n" -"### Funciones de expresión\n" -"\n" -"Todos los parámetros de funciones soportan comodines simples (`*` y `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"Verdadero si alguna parte de `A`se encuentra dentro del patio de la huella " -"principal dada.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"Verdadero si alguna parte de `A`se encuentra dentro del patio de la huella " -"frontal dada.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"Verdadero si alguna parte de `A`se encuentra dentro del patio de la huella " -"trasera dada.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"Verdadero si alguna parte de `A`se encuentra dentro del contorno de la zona " -"dada.\n" -"

\n" -"\n" -" A.isPlated()\n" -"Verdadero si `A` tiene un orificio revestido.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"Verdadero si `A` tiene una red que es parte del par diferencial " -"especificado.\n" -"`` es el nombre base del par diferencial. Por ejemplo, " -"`inDiffPair('CLK')`\n" -"coincide con los elementos en las redes `CLK_P` y `CLK_N`.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"Verdadero si `A` y `B` son miembros del mismo par diferencial.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"Verdadero si `A` es un miembro del grupo dado. Incluye membresía anidada.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"Verdadero si`A` existe en la capa dada. El nombre de la capa puede ser\n" -"el asignado en Configuración de placa > Capas del editor de placas,\n" -"o el nombre canónico (ej: `F.Cu`).\n" -"\n" -"Note: esto devuelve verdadero si `A`está en la capa dada, " -"independientemente\n" -"de si la regla está siendo evaluada en esa capa o no.\n" -"Para lo último, use la cláusula `(layer \"layer_name\")` en la regla.\n" -"


\n" -"\n" -"### Más ejemplos\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # Previene serigrafía sobre vías teñidas\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\" \n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\" \n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\" \n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" -" \n" -" (rule \"Pad to Track Clearance\" \n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\" \n" -" (constraint hole (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -" \n" -" (rule \"Max Drill Hole Size PTH\" \n" -" (constraint hole (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Especifica un espacio óptimo para un par diferencial particular\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" -"\n" -" # Especifica un margen mayor alrededor de cualquier par diferencial\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "Propiedades por defecto para nuevos objetos de dimensión:" @@ -29715,13 +29292,13 @@ msgstr "Comprobando zonas..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29731,7 +29308,7 @@ msgstr "Comprobando zonas..." msgid "(%s clearance %s; actual %s)" msgstr "(%s margen %s; real %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(redes %s y %s)" @@ -31470,7 +31047,7 @@ msgstr "Disipador" msgid "Castellated" msgstr "Castellado" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Diámetro" @@ -31809,7 +31386,7 @@ msgstr "Vía ciega/enterrada" msgid "Through Via" msgstr "Vía pasante" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Taladro" @@ -31832,23 +31409,23 @@ msgstr "Pista (arco) %s en %s, longitud %s" msgid "Track %s on %s, length %s" msgstr "Pista %s en (%s), longitud %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "Origen X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "Origen Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "Capa superior" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "Capa inferior" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "Tipo de vía" @@ -34412,24 +33989,24 @@ msgstr "Rotar" msgid "Change Side / Flip" msgstr "Cambiar lado / Voltear" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "Mover con exactitud" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "Elemento(s) duplicado(s) %d" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "Seleccione el punto de referencia para la copia..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "La selección fue copiada" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "La copia fue cancelada" @@ -36667,39 +36244,39 @@ msgstr "Ocultar todas las otras clases de redes" msgid "Presets (Ctrl+Tab):" msgstr "Ajustes por defecto (Ctrl+Tab):" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "Guardar ajuste por defecto..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "Eliminar ajuste por defecto..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "Nombre de ajuste por defecto de capa:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "Guardar ajuste por defecto de capa" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "Ajustes por defecto" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "Eliminar ajuste por defecto" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "Seleccionar ajuste por defecto:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "Abrir preferencias" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." @@ -37005,6 +36582,437 @@ msgstr "Esquema de KiCad" msgid "KiCad Printed Circuit Board" msgstr "Placa de circuito impreso de KiCad" +#, fuzzy +#~ msgid "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('/CLK')`\n" +#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" +#~ msgstr "" +#~ "### Cláusulas de nivel superior\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Cláusulas de reglas\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Tipos de requerimientos\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Tipos de elementos\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Ejemplos\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notas\n" +#~ "\n" +#~ "La cláusula de versión tiene que ser la primera cláusula.\n" +#~ "Indica la versión de sintaxis del archivo para que analizadores de " +#~ "reglas\n" +#~ "futuros puedan realizar actualizaciones automáticas. Debería ser fijado a " +#~ "\"1\".\n" +#~ "\n" +#~ "Las reglas deberían ser ordenadas por especificidad.\n" +#~ "Las reglas posteriores tienen precedencia sobre las reglas anteriores;\n" +#~ "una vez que se encuentra una regla coincidente, no se comprobarán más " +#~ "reglas.\n" +#~ "\n" +#~ "Use Ctrl+/ para comentar o descomentar la(s) línea(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Funciones de expresión\n" +#~ "\n" +#~ "Todos los parámetros de funciones soportan comodines simples (`*` y `?" +#~ "`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "Verdadero si alguna parte de `A`se encuentra dentro del patio de la " +#~ "huella principal dada.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "Verdadero si alguna parte de `A`se encuentra dentro del patio de la " +#~ "huella frontal dada.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "Verdadero si alguna parte de `A`se encuentra dentro del patio de la " +#~ "huella trasera dada.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "Verdadero si alguna parte de `A`se encuentra dentro del contorno de la " +#~ "zona dada.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "Verdadero si `A` tiene un orificio revestido.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "Verdadero si `A` tiene una red que es parte del par diferencial " +#~ "especificado.\n" +#~ "`` es el nombre base del par diferencial. Por ejemplo, " +#~ "`inDiffPair('CLK')`\n" +#~ "coincide con los elementos en las redes `CLK_P` y `CLK_N`.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "Verdadero si `A` y `B` son miembros del mismo par diferencial.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "Verdadero si `A` es un miembro del grupo dado. Incluye membresía " +#~ "anidada.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "Verdadero si`A` existe en la capa dada. El nombre de la capa puede ser\n" +#~ "el asignado en Configuración de placa > Capas del editor de placas,\n" +#~ "o el nombre canónico (ej: `F.Cu`).\n" +#~ "\n" +#~ "Note: esto devuelve verdadero si `A`está en la capa dada, " +#~ "independientemente\n" +#~ "de si la regla está siendo evaluada en esa capa o no.\n" +#~ "Para lo último, use la cláusula `(layer \"layer_name\")` en la regla.\n" +#~ "


\n" +#~ "\n" +#~ "### Más ejemplos\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # Previene serigrafía sobre vías teñidas\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\" \n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\" \n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\" \n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" +#~ " \n" +#~ " (rule \"Pad to Track Clearance\" \n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\" \n" +#~ " (constraint hole (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ " \n" +#~ " (rule \"Max Drill Hole Size PTH\" \n" +#~ " (constraint hole (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Especifica un espacio óptimo para un par diferencial particular\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" +#~ "\n" +#~ " # Especifica un margen mayor alrededor de cualquier par diferencial\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" + #, fuzzy, c-format #~ msgid "Unable to locate padstack %s in file %s\n" #~ msgstr "No puede crearse el archivo '%s'.\n" diff --git a/translation/pofiles/es_MX.po b/translation/pofiles/es_MX.po index 5c836cb531..70c445f34b 100644 --- a/translation/pofiles/es_MX.po +++ b/translation/pofiles/es_MX.po @@ -12,7 +12,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad Spanish Translation\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-07-04 20:18+0000\n" "Last-Translator: Ulices \n" "Language-Team: Spanish (Mexico) = 0." msgstr "El grosor del perímetro del polígono debe ser >=." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Lista de errores" @@ -27168,17 +27168,17 @@ msgid "Via type:" msgstr "Tipo de vía:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "Pasante" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "Micro" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Ciega/Enterrada" @@ -28675,429 +28675,6 @@ msgstr "Reglas de DRC:" msgid "Check rule syntax" msgstr "Verificar reglas de sintaxis" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" -"### Cláusulas de nivel superior\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Cláusulas de reglas\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Tipos de restricciones\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Tipos de elementos\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Ejemplos\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notas\n" -"\n" -"La cláusula de versión tiene que ser la primera cláusula.\n" -"Indica la versión de sintaxis del archivo para que analizadores de\n" -"reglas futuros puedan realizar actualizaciones automáticas.\n" -"Debería ser fijado a \"1\".\n" -"\n" -"Las reglas deberían ser ordenadas por especificidad.\n" -"Las reglas posteriores tienen precedencia sobre las reglas anteriores;\n" -"una vez que se encuentra una regla coincidente, no se comprobarán más " -"reglas.\n" -"\n" -"Use Ctrl+/ para comentar o descomentar la(s) línea(s).\n" -"


\n" -"\n" -"### Funciones de expresión\n" -"\n" -"Todos los parámetros de funciones soportan comodines simples (`*` y `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"Verdadero si alguna parte de `A`se encuentra dentro del patio de la huella " -"principal dada.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"Verdadero si alguna parte de `A`se encuentra dentro del patio de la huella " -"frontal dada.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"Verdadero si alguna parte de `A`se encuentra dentro del patio de la huella " -"trasera dada.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"Verdadero si alguna parte de `A`se encuentra dentro del contorno de la zona " -"dada.\n" -"

\n" -"\n" -" A.isPlated()\n" -"Verdadero si `A` tiene un orificio revestido.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"Verdadero si `A` tiene una red que es parte del par diferencial " -"especificado.\n" -"`` es el nombre base del par diferencial. Por ejemplo, " -"`inDiffPair('CLK')`\n" -"coincide con los elementos en las redes `CLK_P` y `CLK_N`.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"Verdadero si `A` y `B` son miembros del mismo par diferencial.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"Verdadero si `A` es un miembro del grupo dado. Incluye membresía anidada.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"Verdadero si`A` existe en la capa dada. El nombre de la capa puede ser el " -"asignado\n" -"en Configuración de placa > Capas del editor de placas, o el nombre canónico " -"(ej: `F.Cu`).\n" -"\n" -"Note: esto devuelve verdadero si `A`está en la capa dada, independientemente " -"de\n" -"si la regla está siendo evaluada en esa capa o no.\n" -"Para lo último, use la cláusula `(layer \"layer_name\")` en la regla.\n" -"


\n" -"\n" -"### Más ejemplos\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # Previene serigrafía sobre vías teñidas\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\" \n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance betwen Pads of Different Nets\" \n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\" \n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" -" \n" -" (rule \"Pad to Track Clearance\" \n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\" \n" -" (constraint hole (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -" \n" -" (rule \"Max Drill Hole Size PTH\" \n" -" (constraint hole (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Especifica un espacio óptimo para un par diferencial particular\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" -"\n" -" # Especifica un margen mayor alrededor de cualquier par diferencial\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "Propiedades por defecto para nuevos objetos de dimensión:" @@ -29700,13 +29277,13 @@ msgstr "Comprobando zonas..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29716,7 +29293,7 @@ msgstr "Comprobando zonas..." msgid "(%s clearance %s; actual %s)" msgstr "(%s margen %s; real %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(redes %s y %s)" @@ -31457,7 +31034,7 @@ msgstr "Disipador" msgid "Castellated" msgstr "Castellado" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Diámetro" @@ -31796,7 +31373,7 @@ msgstr "Vía ciega/enterrada" msgid "Through Via" msgstr "Vía pasante" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Taladro" @@ -31819,23 +31396,23 @@ msgstr "Pista (arco) %s en %s, longitud %s" msgid "Track %s on %s, length %s" msgstr "Pista %s en (%s), longitud %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "Origen X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "Origen Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "Capa superior" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "Capa inferior" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "Tipo de vía" @@ -34395,24 +33972,24 @@ msgstr "Rotar" msgid "Change Side / Flip" msgstr "Cambiar lado / Voltear" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "Mover con exactitud" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "Elemento(s) duplicado(s) %d" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "Seleccione el punto de referencia para la copia..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "La selección fue copiada" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "Copia cancelada" @@ -36650,39 +36227,39 @@ msgstr "Ocultar todas las otras clases de redes" msgid "Presets (Ctrl+Tab):" msgstr "Preajustes (Ctrl+Tab):" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "Guardar ajuste por defecto..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "Eliminar ajuste por defecto..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "Nombre de ajuste por defecto de capa:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "Guardar ajuste por defecto de capa" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "Ajustes por defecto" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "Eliminar ajuste por defecto" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "Seleccionar ajuste por defecto:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "Abrir preferencias" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." @@ -36988,6 +36565,436 @@ msgstr "Esquema de KiCad" msgid "KiCad Printed Circuit Board" msgstr "Placa de circuito impreso de KiCad" +#~ msgid "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('/CLK')`\n" +#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" +#~ msgstr "" +#~ "### Cláusulas de nivel superior\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Cláusulas de reglas\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Tipos de restricciones\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Tipos de elementos\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Ejemplos\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notas\n" +#~ "\n" +#~ "La cláusula de versión tiene que ser la primera cláusula.\n" +#~ "Indica la versión de sintaxis del archivo para que analizadores de\n" +#~ "reglas futuros puedan realizar actualizaciones automáticas.\n" +#~ "Debería ser fijado a \"1\".\n" +#~ "\n" +#~ "Las reglas deberían ser ordenadas por especificidad.\n" +#~ "Las reglas posteriores tienen precedencia sobre las reglas anteriores;\n" +#~ "una vez que se encuentra una regla coincidente, no se comprobarán más " +#~ "reglas.\n" +#~ "\n" +#~ "Use Ctrl+/ para comentar o descomentar la(s) línea(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Funciones de expresión\n" +#~ "\n" +#~ "Todos los parámetros de funciones soportan comodines simples (`*` y `?" +#~ "`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "Verdadero si alguna parte de `A`se encuentra dentro del patio de la " +#~ "huella principal dada.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "Verdadero si alguna parte de `A`se encuentra dentro del patio de la " +#~ "huella frontal dada.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "Verdadero si alguna parte de `A`se encuentra dentro del patio de la " +#~ "huella trasera dada.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "Verdadero si alguna parte de `A`se encuentra dentro del contorno de la " +#~ "zona dada.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "Verdadero si `A` tiene un orificio revestido.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "Verdadero si `A` tiene una red que es parte del par diferencial " +#~ "especificado.\n" +#~ "`` es el nombre base del par diferencial. Por ejemplo, " +#~ "`inDiffPair('CLK')`\n" +#~ "coincide con los elementos en las redes `CLK_P` y `CLK_N`.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "Verdadero si `A` y `B` son miembros del mismo par diferencial.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "Verdadero si `A` es un miembro del grupo dado. Incluye membresía " +#~ "anidada.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "Verdadero si`A` existe en la capa dada. El nombre de la capa puede ser el " +#~ "asignado\n" +#~ "en Configuración de placa > Capas del editor de placas, o el nombre " +#~ "canónico (ej: `F.Cu`).\n" +#~ "\n" +#~ "Note: esto devuelve verdadero si `A`está en la capa dada, " +#~ "independientemente de\n" +#~ "si la regla está siendo evaluada en esa capa o no.\n" +#~ "Para lo último, use la cláusula `(layer \"layer_name\")` en la regla.\n" +#~ "


\n" +#~ "\n" +#~ "### Más ejemplos\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # Previene serigrafía sobre vías teñidas\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\" \n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance betwen Pads of Different Nets\" \n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\" \n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" +#~ " \n" +#~ " (rule \"Pad to Track Clearance\" \n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\" \n" +#~ " (constraint hole (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ " \n" +#~ " (rule \"Max Drill Hole Size PTH\" \n" +#~ " (constraint hole (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Especifica un espacio óptimo para un par diferencial particular\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" +#~ "\n" +#~ " # Especifica un margen mayor alrededor de cualquier par diferencial\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" + #, fuzzy, c-format #~ msgid "Unable to locate padstack %s in file %s\n" #~ msgstr "No puede crearse el archivo '%s'.\n" diff --git a/translation/pofiles/fi.po b/translation/pofiles/fi.po index 57049622e0..43e8b71f4f 100644 --- a/translation/pofiles/fi.po +++ b/translation/pofiles/fi.po @@ -12,7 +12,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-09-21 11:23+0000\n" "Last-Translator: Henrik Kauhanen \n" "Language-Team: Finnish \n" @@ -4230,7 +4230,7 @@ msgid "Shape" msgstr "Muoto" #: common/eda_shape.cpp:574 common/eda_shape.cpp:584 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:181 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:173 #: pcbnew/pcb_track.cpp:686 msgid "Radius" msgstr "Säde" @@ -4264,8 +4264,8 @@ msgstr "Pisteet" #: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:155 #: pcbnew/fp_text.cpp:305 pcbnew/fp_text_grid_table.cpp:105 pcbnew/pad.cpp:1008 #: pcbnew/pcb_target.cpp:158 pcbnew/pcb_target.cpp:204 pcbnew/pcb_text.cpp:127 -#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1132 pcbnew/pcb_track.cpp:1149 -#: pcbnew/pcb_track.cpp:1168 +#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1127 pcbnew/pcb_track.cpp:1144 +#: pcbnew/pcb_track.cpp:1163 msgid "Width" msgstr "Leveys" @@ -4313,13 +4313,13 @@ msgstr "Alku X" msgid "Start Y" msgstr "Alku Y" -#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1140 -#: pcbnew/pcb_track.cpp:1157 +#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1135 +#: pcbnew/pcb_track.cpp:1152 msgid "End X" msgstr "Loppu X" -#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1142 -#: pcbnew/pcb_track.cpp:1159 +#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1137 +#: pcbnew/pcb_track.cpp:1154 msgid "End Y" msgstr "Loppu Y" @@ -4405,7 +4405,7 @@ msgstr "Vasemmalle" #: pagelayout_editor/dialogs/properties_frame_base.cpp:89 #: pagelayout_editor/dialogs/properties_frame_base.cpp:105 #: pcbnew/dialogs/dialog_dimension_properties_base.cpp:315 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:179 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:171 #: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:117 #: pcbnew/dialogs/dialog_text_properties_base.cpp:145 msgid "Center" @@ -4689,7 +4689,7 @@ msgstr "Tiedostoa '%s' ei voi kopioida." #: common/grid_tricks.cpp:278 common/tool/actions.cpp:153 #: eeschema/tools/ee_actions.cpp:148 pcbnew/dialogs/panel_setup_rules.cpp:112 -#: pcbnew/tools/edit_tool.cpp:2011 +#: pcbnew/tools/edit_tool.cpp:2016 msgid "Cut" msgstr "Leikkaa" @@ -4717,7 +4717,7 @@ msgstr "Liitä leikepöydän solut matriisiin nykyisessä solussa" #: common/grid_tricks.cpp:284 common/tool/actions.cpp:191 #: kicad/project_tree_pane.cpp:771 pcbnew/dialogs/panel_setup_rules.cpp:115 -#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2013 +#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2018 msgid "Delete" msgstr "Poista" @@ -5298,8 +5298,8 @@ msgid "Invalid size %lld: too large" msgstr "Virheellinen koko %ll d: liian suuri" #: common/plugins/eagle/eagle_parser.cpp:281 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:373 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:389 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:366 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:382 #, c-format msgid "Invalid Arc with radius %f and angle %f" msgstr "Virheellinen kaari säteellä %f ja kulmalla %f" @@ -16931,7 +16931,7 @@ msgstr "Valitse kerros: %s" #: pcbnew/fp_text_grid_table.cpp:109 pcbnew/pad.cpp:980 #: pcbnew/pcb_dimension.cpp:353 pcbnew/pcb_dimension.cpp:1087 #: pcbnew/pcb_shape.cpp:159 pcbnew/pcb_target.cpp:155 pcbnew/pcb_text.cpp:120 -#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1173 +#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1168 #: pcbnew/tools/board_inspection_tool.cpp:238 #: pcbnew/tools/board_inspection_tool.cpp:385 #: pcbnew/tools/board_inspection_tool.cpp:461 @@ -20918,13 +20918,13 @@ msgstr "ja muut" msgid "no layers" msgstr "ei kerroksia" -#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1134 -#: pcbnew/pcb_track.cpp:1151 +#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1129 +#: pcbnew/pcb_track.cpp:1146 msgid "Position X" msgstr "Sijainti X" -#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1137 -#: pcbnew/pcb_track.cpp:1154 +#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1132 +#: pcbnew/pcb_track.cpp:1149 msgid "Position Y" msgstr "Sijainti Y" @@ -24745,57 +24745,57 @@ msgstr "" msgid "Error loading footprint library table." msgstr "Virhe jalanjälkikirjastotaulukon lataamisessa." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:178 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:170 msgid "Circle Properties" msgstr "Ympyrän ominaisuudet" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:191 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:183 msgid "Arc Properties" msgstr "Kaaren ominaisuudet" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:197 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:189 msgid "Polygon Properties" msgstr "Monikulmion ominaisuudet" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:203 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:195 msgid "Rectangle Properties" msgstr "Suorakulmion ominaisuudet" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:209 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:201 msgid "Line Segment Properties" msgstr "Linjasegmentin ominaisuudet" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:343 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:336 msgid "Modify drawing properties" msgstr "Muokkaa piirustuksen ominaisuuksia" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:368 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:361 msgid "The arc angle cannot be zero." msgstr "Kaarikulma ei voi olla nolla." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:415 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:427 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:433 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:388 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:398 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:408 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:420 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:426 #, fuzzy msgid "The item thickness must be greater than zero." msgstr "Jäljevälin on oltava suurempi kuin 0." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:402 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 #, fuzzy msgid "The radius must be greater than zero." msgstr "Jäljevälin on oltava suurempi kuin 0." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:412 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 msgid "The rectangle cannot be empty." msgstr "Suorakulmio ei voi olla tyhjä." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:421 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:414 msgid "The polygon outline thickness must be >= 0." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Virheluettelo" @@ -26976,17 +26976,17 @@ msgid "Via type:" msgstr "Läpivientityyppi:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "Kautta" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "Mikro" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Sokea / haudattu" @@ -28462,425 +28462,6 @@ msgstr "DRC-säännöt:" msgid "Check rule syntax" msgstr "Tarkista säännön syntaksit" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" -"### Ylätason lausekkeet\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Sääntölausekkeet\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Rajoitustyypit\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Kohdetyypit\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Esimerkkejä\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Huomioita\n" -"\n" -"Versiolausekkeen tulee olla ensimmäisenä lausekkeena. Se kertoo tiedoston " -"syntaksin version \n" -"jotta tulevat versiot sääntökäsittelijöistä voivat tehdä automaattisia " -"päivityksiä. \n" -"Version tulee olla \"1\".\n" -"\n" -"Sääntöjen tulee olla täsmällisyysjärjestyksessä. Jäljempänä olevat säännöt\n" -"ovat etusijalla aiempiin nähden; täsmäävän säännön löydyttyä\n" -"loppuja sääntöjä ei enää katsota.\n" -"\n" -"Käytä Ctrl+/ rivien kommentoimiseksi päälle/pois.\n" -"


\n" -"\n" -"### Lausekefunktiot\n" -"\n" -"Kaikki funktioparametrit tukevat villejä kortteja (`*` ja `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"Tosi jos mikään osa `A`:sta on kyseisen jalanjäljen kokonaisen piha-alueen " -"sisällä.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"Tosi jos mikään osa `A`:sta on kyseisen jalanjäljen yläpuolen piha-alueen " -"sisällä.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"Tosi jos mikään osa `A`:sta on kyseisen jalanjäljen alapuolen piha-alueen " -"sisällä.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"Tosi jos mikään osa `A`:sta on kyseisen vyöhykkeen ulkoviivojen sisällä.\n" -"

\n" -"\n" -" A.isPlated()\n" -"Tosi jos `A` jossa on pinnoitettu reikä.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"Tosi jos `A`:lla on net joka on osa kyseistä differentiaaliparia.\n" -"`` on differentiaaliparin perusnimi. Esimerkiksi " -"`inDiffPair('CLK')`\n" -"täsmää net:teihin `CLK_P` ja `CLK_N`.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"Tosi jos `A` and `B` kuuluvat samaan differentiaalipariin.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"Tosi jos `A` kuuluu kyseiseen ryhmään. Mukaanlukien sisäkkäiset jäsenyydet.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"Tosi jos `A` löytyy kyseiseltä tasolta. Tason nimi voi olla joko\n" -" Board Setup > Board Editor Layers annettu tai\n" -"kanoninen nimi (esim. `F.Cu`).\n" -"\n" -"Huomaa: Tämä antaa toden jos `A` on kyseisellä tasolla, siitä riippumatta\n" -"että käsitelläänkö sääntöä ylipäätään tätä kerrosta vasten vai ei.\n" -"Tätä varten käytä `(layer \"layer_name\")` lauseketta säännössä.\n" -"


\n" -"\n" -"### Lisää esimerkkejä\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\" \n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\" \n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\" \n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" -" \n" -" (rule \"Pad to Track Clearance\" \n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\" \n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -" \n" -" (rule \"Max Drill Hole Size PTH\" \n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "Uusien ulottuvuusobjektien oletusominaisuudet:" @@ -29481,13 +29062,13 @@ msgstr "Tarkistetaan vyöhykkeet..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29497,7 +29078,7 @@ msgstr "Tarkistetaan vyöhykkeet..." msgid "(%s clearance %s; actual %s)" msgstr "(%s välys %s; todellinen %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(verkot %s ja %s)" @@ -31206,7 +30787,7 @@ msgstr "Jäähdytyselementti" msgid "Castellated" msgstr "Uritettu" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Halkaisija" @@ -31544,7 +31125,7 @@ msgstr "Piiloläpivienti" msgid "Through Via" msgstr "Läpiviennin kautta" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Pora" @@ -31567,23 +31148,23 @@ msgstr "Johdin (kaari) %s %s, pituus %s" msgid "Track %s on %s, length %s" msgstr "Johdin %s %s, pituus %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "Aloituspiste X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "Aloituspiste Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "Kerroksen yläosa" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "Kerroksen pohja" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "Läpiviennin Tyyppi" @@ -34095,24 +33676,24 @@ msgstr "Käännä" msgid "Change Side / Flip" msgstr "Vaihda Puolta / Käännä" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "Siirrä tarkasti" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "Kopioitu %d kohde (tta)" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "Valitse kopion viitepiste ..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "Valinta kopioitu" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "Kopiointi peruutettu" @@ -36332,39 +35913,39 @@ msgstr "Piilota Kaikki Muut Verkkoluokat" msgid "Presets (Ctrl+Tab):" msgstr "Esiasetukset (Ctrl+Sarkain):" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "Tallenna esiasetus ..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "Poista esiasetus ..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "Tason esiasetettu nimi:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "Tallenna Kerroksen Esiasetus" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "Esiasetukset" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "Poista Esiasetus" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "Valitse esiasetus:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "Avaa Asetukset" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." @@ -36670,6 +36251,433 @@ msgstr "KiCad Kytkentäkaavio" msgid "KiCad Printed Circuit Board" msgstr "KiCad Painettu Piirilevy" +#~ msgid "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('/CLK')`\n" +#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" +#~ msgstr "" +#~ "### Ylätason lausekkeet\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Sääntölausekkeet\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rajoitustyypit\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Kohdetyypit\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Esimerkkejä\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Huomioita\n" +#~ "\n" +#~ "Versiolausekkeen tulee olla ensimmäisenä lausekkeena. Se kertoo " +#~ "tiedoston syntaksin version \n" +#~ "jotta tulevat versiot sääntökäsittelijöistä voivat tehdä automaattisia " +#~ "päivityksiä. \n" +#~ "Version tulee olla \"1\".\n" +#~ "\n" +#~ "Sääntöjen tulee olla täsmällisyysjärjestyksessä. Jäljempänä olevat " +#~ "säännöt\n" +#~ "ovat etusijalla aiempiin nähden; täsmäävän säännön löydyttyä\n" +#~ "loppuja sääntöjä ei enää katsota.\n" +#~ "\n" +#~ "Käytä Ctrl+/ rivien kommentoimiseksi päälle/pois.\n" +#~ "


\n" +#~ "\n" +#~ "### Lausekefunktiot\n" +#~ "\n" +#~ "Kaikki funktioparametrit tukevat villejä kortteja (`*` ja `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "Tosi jos mikään osa `A`:sta on kyseisen jalanjäljen kokonaisen piha-" +#~ "alueen sisällä.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "Tosi jos mikään osa `A`:sta on kyseisen jalanjäljen yläpuolen piha-alueen " +#~ "sisällä.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "Tosi jos mikään osa `A`:sta on kyseisen jalanjäljen alapuolen piha-alueen " +#~ "sisällä.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "Tosi jos mikään osa `A`:sta on kyseisen vyöhykkeen ulkoviivojen sisällä.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "Tosi jos `A` jossa on pinnoitettu reikä.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "Tosi jos `A`:lla on net joka on osa kyseistä differentiaaliparia.\n" +#~ "`` on differentiaaliparin perusnimi. Esimerkiksi " +#~ "`inDiffPair('CLK')`\n" +#~ "täsmää net:teihin `CLK_P` ja `CLK_N`.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "Tosi jos `A` and `B` kuuluvat samaan differentiaalipariin.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "Tosi jos `A` kuuluu kyseiseen ryhmään. Mukaanlukien sisäkkäiset " +#~ "jäsenyydet.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "Tosi jos `A` löytyy kyseiseltä tasolta. Tason nimi voi olla joko\n" +#~ " Board Setup > Board Editor Layers annettu tai\n" +#~ "kanoninen nimi (esim. `F.Cu`).\n" +#~ "\n" +#~ "Huomaa: Tämä antaa toden jos `A` on kyseisellä tasolla, siitä " +#~ "riippumatta\n" +#~ "että käsitelläänkö sääntöä ylipäätään tätä kerrosta vasten vai ei.\n" +#~ "Tätä varten käytä `(layer \"layer_name\")` lauseketta säännössä.\n" +#~ "


\n" +#~ "\n" +#~ "### Lisää esimerkkejä\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\" \n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\" \n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\" \n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" +#~ " \n" +#~ " (rule \"Pad to Track Clearance\" \n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\" \n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ " \n" +#~ " (rule \"Max Drill Hole Size PTH\" \n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" + #, fuzzy, c-format #~ msgid "Unable to locate padstack %s in file %s\n" #~ msgstr "Arkistotiedostoa \"%s\" ei voitu luoda\n" diff --git a/translation/pofiles/fr.po b/translation/pofiles/fr.po index 6669c19361..60fbba8639 100644 --- a/translation/pofiles/fr.po +++ b/translation/pofiles/fr.po @@ -2,7 +2,7 @@ msgid "" msgstr "" "Project-Id-Version: kicad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-02-15 10:10+0100\n" "Last-Translator: \n" "Language-Team: jp-charras\n" @@ -4254,7 +4254,7 @@ msgid "Shape" msgstr "Forme" #: common/eda_shape.cpp:574 common/eda_shape.cpp:584 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:181 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:173 #: pcbnew/pcb_track.cpp:686 msgid "Radius" msgstr "Rayon" @@ -4288,8 +4288,8 @@ msgstr "Points" #: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:155 #: pcbnew/fp_text.cpp:305 pcbnew/fp_text_grid_table.cpp:105 pcbnew/pad.cpp:1008 #: pcbnew/pcb_target.cpp:158 pcbnew/pcb_target.cpp:204 pcbnew/pcb_text.cpp:127 -#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1132 pcbnew/pcb_track.cpp:1149 -#: pcbnew/pcb_track.cpp:1168 +#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1127 pcbnew/pcb_track.cpp:1144 +#: pcbnew/pcb_track.cpp:1163 msgid "Width" msgstr "Largeur" @@ -4337,13 +4337,13 @@ msgstr "Départ X" msgid "Start Y" msgstr "Départ Y" -#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1140 -#: pcbnew/pcb_track.cpp:1157 +#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1135 +#: pcbnew/pcb_track.cpp:1152 msgid "End X" msgstr "Fin X" -#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1142 -#: pcbnew/pcb_track.cpp:1159 +#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1137 +#: pcbnew/pcb_track.cpp:1154 msgid "End Y" msgstr "Fin Y" @@ -4429,7 +4429,7 @@ msgstr "Gauche" #: pagelayout_editor/dialogs/properties_frame_base.cpp:89 #: pagelayout_editor/dialogs/properties_frame_base.cpp:105 #: pcbnew/dialogs/dialog_dimension_properties_base.cpp:315 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:179 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:171 #: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:117 #: pcbnew/dialogs/dialog_text_properties_base.cpp:145 msgid "Center" @@ -4719,7 +4719,7 @@ msgstr "Impossible de copier le fichier '%s'." #: common/grid_tricks.cpp:278 common/tool/actions.cpp:153 #: eeschema/tools/ee_actions.cpp:148 pcbnew/dialogs/panel_setup_rules.cpp:112 -#: pcbnew/tools/edit_tool.cpp:2011 +#: pcbnew/tools/edit_tool.cpp:2016 msgid "Cut" msgstr "Couper" @@ -4750,7 +4750,7 @@ msgstr "" #: common/grid_tricks.cpp:284 common/tool/actions.cpp:191 #: kicad/project_tree_pane.cpp:771 pcbnew/dialogs/panel_setup_rules.cpp:115 -#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2013 +#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2018 msgid "Delete" msgstr "Supprimer" @@ -5332,8 +5332,8 @@ msgid "Invalid size %lld: too large" msgstr "Taille %lld non valide: trop grande" #: common/plugins/eagle/eagle_parser.cpp:281 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:373 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:389 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:366 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:382 #, c-format msgid "Invalid Arc with radius %f and angle %f" msgstr "Arc non valide avec le rayon %f et l’angle %f" @@ -17100,7 +17100,7 @@ msgstr "Sélection couche: %s" #: pcbnew/fp_text_grid_table.cpp:109 pcbnew/pad.cpp:980 #: pcbnew/pcb_dimension.cpp:353 pcbnew/pcb_dimension.cpp:1087 #: pcbnew/pcb_shape.cpp:159 pcbnew/pcb_target.cpp:155 pcbnew/pcb_text.cpp:120 -#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1173 +#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1168 #: pcbnew/tools/board_inspection_tool.cpp:238 #: pcbnew/tools/board_inspection_tool.cpp:385 #: pcbnew/tools/board_inspection_tool.cpp:461 @@ -21120,13 +21120,13 @@ msgstr "et autres" msgid "no layers" msgstr "aucune couche" -#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1134 -#: pcbnew/pcb_track.cpp:1151 +#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1129 +#: pcbnew/pcb_track.cpp:1146 msgid "Position X" msgstr "Position X" -#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1137 -#: pcbnew/pcb_track.cpp:1154 +#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1132 +#: pcbnew/pcb_track.cpp:1149 msgid "Position Y" msgstr "Position Y" @@ -24974,57 +24974,57 @@ msgstr "" msgid "Error loading footprint library table." msgstr "Erreur lors du chargement de la table des librairie d'empreintes." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:178 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:170 msgid "Circle Properties" msgstr "Propriétés du Cercle" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:191 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:183 msgid "Arc Properties" msgstr "Propriétés de l'Arc" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:197 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:189 msgid "Polygon Properties" msgstr "Propriétés du Polygone" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:203 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:195 msgid "Rectangle Properties" msgstr "Propriétés du Rectangle" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:209 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:201 msgid "Line Segment Properties" msgstr "Propriétés du Segment de Droite" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:343 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:336 msgid "Modify drawing properties" msgstr "Modifier les propriétés de l'élément graphique" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:368 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:361 msgid "The arc angle cannot be zero." msgstr "L'angle de l'arc doit être différent de zéro." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:415 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:427 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:433 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:388 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:398 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:408 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:420 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:426 #, fuzzy msgid "The item thickness must be greater than zero." msgstr "La distance entre pistes doit être plus grande que 0." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:402 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 #, fuzzy msgid "The radius must be greater than zero." msgstr "La distance entre pistes doit être plus grande que 0." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:412 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 msgid "The rectangle cannot be empty." msgstr "Le rectangle ne peut pas être vide." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:421 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:414 msgid "The polygon outline thickness must be >= 0." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Liste des Erreurs" @@ -27237,17 +27237,17 @@ msgid "Via type:" msgstr "Type via:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "Traversant" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "Micro" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Aveugle/Enterrée" @@ -28751,422 +28751,6 @@ msgstr "Règles DRC:" msgid "Check rule syntax" msgstr "Vérification de la syntaxe de la règle" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "Propritétés par défaut pour les nouveaux élements type cote:" @@ -29768,13 +29352,13 @@ msgstr "Vérification des zones..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29784,7 +29368,7 @@ msgstr "Vérification des zones..." msgid "(%s clearance %s; actual %s)" msgstr "(%s isolation %s; réel %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(nets %s et %s)" @@ -31522,7 +31106,7 @@ msgstr "Radiateur thermique" msgid "Castellated" msgstr "Castellated" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Diamètre" @@ -31861,7 +31445,7 @@ msgstr "Via Aveugle/Enterrée" msgid "Through Via" msgstr "Via Traversante" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Perçage" @@ -31884,23 +31468,23 @@ msgstr "Piste (arc) %s sur %s, long. %s" msgid "Track %s on %s, length %s" msgstr "Piste %s sur %s, long. %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "Origine X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "Origine Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "Couche Dessus" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "Couche Dessous" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "Type Via" @@ -34445,24 +34029,24 @@ msgstr "Rotation" msgid "Change Side / Flip" msgstr "Changer Côté / Retourner" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "Déplacer exactement" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "%d élément(s) dupliqué(s)" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "Sélectionnez le point de référence pour la copie..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "Sélection copiée." -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "Copie annulée" @@ -36709,39 +36293,39 @@ msgstr "Cacher Toutes les Autres Netclasses" msgid "Presets (Ctrl+Tab):" msgstr "Préréglages (Ctrl+Tab) :" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "Sauver préréglage..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "Supprimer préréglage..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "Nom de préréglage de couches :" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "Sauver Préréglage de Couches" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "Préréglages" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "Supprimer Préréglage" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "Sélection préréglage :" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "Ouvrir Préférences" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." @@ -37048,6 +36632,429 @@ msgstr "Schématique KiCad" msgid "KiCad Printed Circuit Board" msgstr "Fichier Circuit Imprimé KiCad" +#~ msgid "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('/CLK')`\n" +#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" +#~ msgstr "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('/CLK')`\n" +#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" + #, fuzzy, c-format #~ msgid "Unable to locate padstack %s in file %s\n" #~ msgstr "Impossible de charger le fichier %s" diff --git a/translation/pofiles/hu.po b/translation/pofiles/hu.po index d9ac92635e..0f5a2671aa 100644 --- a/translation/pofiles/hu.po +++ b/translation/pofiles/hu.po @@ -3,7 +3,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-04-28 11:12+0000\n" "Last-Translator: Miklós Márton \n" "Language-Team: Hungarian \n" @@ -4404,7 +4404,7 @@ msgid "Shape" msgstr "Alak" #: common/eda_shape.cpp:574 common/eda_shape.cpp:584 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:181 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:173 #: pcbnew/pcb_track.cpp:686 msgid "Radius" msgstr "Sugár" @@ -4439,8 +4439,8 @@ msgstr "Pont vonszolása" #: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:155 #: pcbnew/fp_text.cpp:305 pcbnew/fp_text_grid_table.cpp:105 pcbnew/pad.cpp:1008 #: pcbnew/pcb_target.cpp:158 pcbnew/pcb_target.cpp:204 pcbnew/pcb_text.cpp:127 -#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1132 pcbnew/pcb_track.cpp:1149 -#: pcbnew/pcb_track.cpp:1168 +#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1127 pcbnew/pcb_track.cpp:1144 +#: pcbnew/pcb_track.cpp:1163 msgid "Width" msgstr "Szélesség" @@ -4491,14 +4491,14 @@ msgstr "Kezdő Y:" msgid "Start Y" msgstr "Kezdő Y:" -#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1140 -#: pcbnew/pcb_track.cpp:1157 +#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1135 +#: pcbnew/pcb_track.cpp:1152 #, fuzzy msgid "End X" msgstr "Vég X:" -#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1142 -#: pcbnew/pcb_track.cpp:1159 +#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1137 +#: pcbnew/pcb_track.cpp:1154 #, fuzzy msgid "End Y" msgstr "Vég Y:" @@ -4585,7 +4585,7 @@ msgstr "Balra" #: pagelayout_editor/dialogs/properties_frame_base.cpp:89 #: pagelayout_editor/dialogs/properties_frame_base.cpp:105 #: pcbnew/dialogs/dialog_dimension_properties_base.cpp:315 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:179 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:171 #: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:117 #: pcbnew/dialogs/dialog_text_properties_base.cpp:145 msgid "Center" @@ -4887,7 +4887,7 @@ msgstr "A(z) \"%s\" fájl nem másolható." #: common/grid_tricks.cpp:278 common/tool/actions.cpp:153 #: eeschema/tools/ee_actions.cpp:148 pcbnew/dialogs/panel_setup_rules.cpp:112 -#: pcbnew/tools/edit_tool.cpp:2011 +#: pcbnew/tools/edit_tool.cpp:2016 msgid "Cut" msgstr "Kivágás" @@ -4916,7 +4916,7 @@ msgstr "" #: common/grid_tricks.cpp:284 common/tool/actions.cpp:191 #: kicad/project_tree_pane.cpp:771 pcbnew/dialogs/panel_setup_rules.cpp:115 -#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2013 +#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2018 msgid "Delete" msgstr "Töröl" @@ -5566,8 +5566,8 @@ msgid "Invalid size %lld: too large" msgstr "Érvénytelen méret, túl nagy: %lld" #: common/plugins/eagle/eagle_parser.cpp:281 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:373 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:389 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:366 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:382 #, c-format msgid "Invalid Arc with radius %f and angle %f" msgstr "Érvénytelen körív %f sugárral és %f° nyílással" @@ -17339,7 +17339,7 @@ msgstr "Réteg kiválasztása:" #: pcbnew/fp_text_grid_table.cpp:109 pcbnew/pad.cpp:980 #: pcbnew/pcb_dimension.cpp:353 pcbnew/pcb_dimension.cpp:1087 #: pcbnew/pcb_shape.cpp:159 pcbnew/pcb_target.cpp:155 pcbnew/pcb_text.cpp:120 -#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1173 +#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1168 #: pcbnew/tools/board_inspection_tool.cpp:238 #: pcbnew/tools/board_inspection_tool.cpp:385 #: pcbnew/tools/board_inspection_tool.cpp:461 @@ -21521,14 +21521,14 @@ msgstr " és további" msgid "no layers" msgstr "nem réteg" -#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1134 -#: pcbnew/pcb_track.cpp:1151 +#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1129 +#: pcbnew/pcb_track.cpp:1146 #, fuzzy msgid "Position X" msgstr "X pozíció:" -#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1137 -#: pcbnew/pcb_track.cpp:1154 +#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1132 +#: pcbnew/pcb_track.cpp:1149 #, fuzzy msgid "Position Y" msgstr "Y pozíció:" @@ -25531,57 +25531,57 @@ msgstr "" msgid "Error loading footprint library table." msgstr "Hiba történt az alkatrészrajzolat könyvtártáblázat betöltése során" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:178 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:170 msgid "Circle Properties" msgstr "Kör tulajdonságok" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:191 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:183 msgid "Arc Properties" msgstr "Körív tulajdonságok" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:197 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:189 msgid "Polygon Properties" msgstr "Sokszög tulajdonságok" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:203 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:195 #, fuzzy msgid "Rectangle Properties" msgstr "Kör tulajdonságok" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:209 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:201 msgid "Line Segment Properties" msgstr "Vonalszegmens tulajdonságok" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:343 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:336 msgid "Modify drawing properties" msgstr "Rajzelem tulajdonságok módosítása" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:368 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:361 msgid "The arc angle cannot be zero." msgstr "A körív nyílásszöge nem lehet nulla." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:415 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:427 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:433 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:388 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:398 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:408 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:420 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:426 msgid "The item thickness must be greater than zero." msgstr "Az elem vastagságának nullánál nagyobbnak kell lennie." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:402 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 msgid "The radius must be greater than zero." msgstr "A sugárnak nullánál nagyobbnak kell lennie." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:412 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 #, fuzzy msgid "The rectangle cannot be empty." msgstr "A körív nyílásszöge nem lehet nulla." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:421 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:414 msgid "The polygon outline thickness must be >= 0." msgstr "A sokszög körvonal vastagsága nem lehet negatív." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Hibalista" @@ -27856,17 +27856,17 @@ msgid "Via type:" msgstr "Via típus:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "Átmenő" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "μVia" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Zsák/eltemetett" @@ -29390,216 +29390,6 @@ msgstr "" msgid "Check rule syntax" msgstr "" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 #, fuzzy msgid "Default properties for new dimension objects:" @@ -30266,13 +30056,13 @@ msgstr "Zónakitöltések ellenőrzése..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -30282,7 +30072,7 @@ msgstr "Zónakitöltések ellenőrzése..." msgid "(%s clearance %s; actual %s)" msgstr "lokális távolságtartás és szigetelési távolság beállítások" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, fuzzy, c-format msgid "(nets %s and %s)" msgstr "a %c és %c részegységben" @@ -32098,7 +31888,7 @@ msgstr "Rajzjel láb ismétlése" msgid "Castellated" msgstr "Számolás" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Forrszem átmérő" @@ -32474,7 +32264,7 @@ msgstr "Zsák/eltemetett via" msgid "Through Via" msgstr "Átmenő via" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Furat" @@ -32497,27 +32287,27 @@ msgstr "Vezetősáv %s %s a(z) %s rétegen, hossza: %s" msgid "Track %s on %s, length %s" msgstr "Vezetősáv %s %s a(z) %s rétegen, hossza: %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 #, fuzzy msgid "Origin X" msgstr "Kezdőpont" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 #, fuzzy msgid "Origin Y" msgstr "Kezdőpont" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 #, fuzzy msgid "Layer Top" msgstr "Réteg" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 #, fuzzy msgid "Layer Bottom" msgstr "Alulra" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 #, fuzzy msgid "Via Type" msgstr "Via típus:" @@ -35017,26 +34807,26 @@ msgstr "Forgatás" msgid "Change Side / Flip" msgstr "Via átmérő és furat módosítása" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "Mozgatás pontosan" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "%d azonos elem" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 #, fuzzy msgid "Select reference point for the copy..." msgstr "Referencia pont megadása másoláshoz..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 #, fuzzy msgid "Selection copied" msgstr "Kijelölés másolva." -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 #, fuzzy msgid "Copy canceled" msgstr "Másolás megszakítva." @@ -37482,47 +37272,47 @@ msgstr "Egy új vezetékosztály hozzáadása" msgid "Presets (Ctrl+Tab):" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 #, fuzzy msgid "Save preset..." msgstr "Mentés másként" -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 #, fuzzy msgid "Delete preset..." msgstr "Vezeték törlése" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 #, fuzzy msgid "Layer preset name:" msgstr "Rétegválasztás:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 #, fuzzy msgid "Save Layer Preset" msgstr "Könyvtárak mentése" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 #, fuzzy msgid "Presets" msgstr "Visszaállítás" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 #, fuzzy msgid "Delete Preset" msgstr "Vezeték törlése" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 #, fuzzy msgid "Select preset:" msgstr "Légvezetékek kiválasztása" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 #, fuzzy msgid "Open Preferences" msgstr "Beállítások" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." diff --git a/translation/pofiles/id.po b/translation/pofiles/id.po index cf8cec634f..07726b2e67 100644 --- a/translation/pofiles/id.po +++ b/translation/pofiles/id.po @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2021-11-22 17:30+0000\n" "Last-Translator: whenwesober \n" "Language-Team: Indonesian = 0." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "" @@ -25998,17 +25998,17 @@ msgid "Via type:" msgstr "" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "" @@ -27394,216 +27394,6 @@ msgstr "" msgid "Check rule syntax" msgstr "" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "" @@ -28202,13 +27992,13 @@ msgstr "" #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -28218,7 +28008,7 @@ msgstr "" msgid "(%s clearance %s; actual %s)" msgstr "" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "" @@ -29912,7 +29702,7 @@ msgstr "" msgid "Castellated" msgstr "" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "" @@ -30249,7 +30039,7 @@ msgstr "" msgid "Through Via" msgstr "" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "" @@ -30272,23 +30062,23 @@ msgstr "" msgid "Track %s on %s, length %s" msgstr "" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "" @@ -32664,24 +32454,24 @@ msgstr "Rotasi" msgid "Change Side / Flip" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "" -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "" @@ -34886,39 +34676,39 @@ msgstr "" msgid "Presets (Ctrl+Tab):" msgstr "Preset (Ctrl+Tab):" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "Simpan preset..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "Hapus preset..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "Nama layer preset:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "Simpan Layer Preset" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "Hapus Preset" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "Pilih preset:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "Buka Preferensi" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." diff --git a/translation/pofiles/it.po b/translation/pofiles/it.po index e662e5037b..7edc9708ef 100644 --- a/translation/pofiles/it.po +++ b/translation/pofiles/it.po @@ -102,7 +102,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-06-09 19:41+0200\n" "Last-Translator: Marco Ciampa \n" "Language-Team: Italian = 0." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Elenco errori" @@ -27033,17 +27033,17 @@ msgid "Via type:" msgstr "Tipo via:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "Passante" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "Micro" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Cieco/sepolto" @@ -28536,216 +28536,6 @@ msgstr "Regole DRC:" msgid "Check rule syntax" msgstr "Controlla la sintassi regole" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "Proprietà predefinite per i nuovi oggetti dimensione:" @@ -29348,13 +29138,13 @@ msgstr "Controllo zone..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29364,7 +29154,7 @@ msgstr "Controllo zone..." msgid "(%s clearance %s; actual %s)" msgstr "(%s distanza %s; attuale %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(coll %s e %s)" @@ -31089,7 +30879,7 @@ msgstr "Dissipatore" msgid "Castellated" msgstr "Dentellati" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Diametro" @@ -31427,7 +31217,7 @@ msgstr "Via cieco/sepolto" msgid "Through Via" msgstr "Via passanti" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Foro" @@ -31450,23 +31240,23 @@ msgstr "Pista (arco) %s su %s, lung. %s" msgid "Track %s on %s, length %s" msgstr "Pista %s su %s, lung. %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "X origine" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "Y origine" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "Strato superiore" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "Strato inferiore" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "Tipo via" @@ -34005,24 +33795,24 @@ msgstr "Ruota" msgid "Change Side / Flip" msgstr "Cambia lato / ribalta" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "Sposta esattamente" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "%d elementi duplicati" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "Selezionare il punto di riferimento per la copia..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "Selezione copiata" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "Copia annullata" @@ -36253,39 +36043,39 @@ msgstr "Nascondi tutte le altre netclass" msgid "Presets (Ctrl+Tab):" msgstr "Preimpostazioni (Ctrl+Tab):" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "Salva preimpostazione..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "Cancella preimpostazione..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "Nome preimpostazione strato:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "Salva preimpostazione strato" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "Reimpostazioni" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "Cancella preimpostazione" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "Seleziona preimpostazione:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "Apri preferenze" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." diff --git a/translation/pofiles/ja.po b/translation/pofiles/ja.po index dc0f231067..77f9561bba 100644 --- a/translation/pofiles/ja.po +++ b/translation/pofiles/ja.po @@ -5,7 +5,7 @@ msgid "" msgstr "" "Project-Id-Version: kicad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-09-10 09:21+0000\n" "Last-Translator: Tokita, Hiroshi \n" "Language-Team: Japanese \n" @@ -4193,7 +4193,7 @@ msgid "Shape" msgstr "形状" #: common/eda_shape.cpp:574 common/eda_shape.cpp:584 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:181 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:173 #: pcbnew/pcb_track.cpp:686 msgid "Radius" msgstr "半径" @@ -4227,8 +4227,8 @@ msgstr "ポイント" #: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:155 #: pcbnew/fp_text.cpp:305 pcbnew/fp_text_grid_table.cpp:105 pcbnew/pad.cpp:1008 #: pcbnew/pcb_target.cpp:158 pcbnew/pcb_target.cpp:204 pcbnew/pcb_text.cpp:127 -#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1132 pcbnew/pcb_track.cpp:1149 -#: pcbnew/pcb_track.cpp:1168 +#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1127 pcbnew/pcb_track.cpp:1144 +#: pcbnew/pcb_track.cpp:1163 msgid "Width" msgstr "幅" @@ -4276,13 +4276,13 @@ msgstr "始点X" msgid "Start Y" msgstr "始点Y" -#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1140 -#: pcbnew/pcb_track.cpp:1157 +#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1135 +#: pcbnew/pcb_track.cpp:1152 msgid "End X" msgstr "終点 X" -#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1142 -#: pcbnew/pcb_track.cpp:1159 +#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1137 +#: pcbnew/pcb_track.cpp:1154 msgid "End Y" msgstr "終点 Y" @@ -4368,7 +4368,7 @@ msgstr "左" #: pagelayout_editor/dialogs/properties_frame_base.cpp:89 #: pagelayout_editor/dialogs/properties_frame_base.cpp:105 #: pcbnew/dialogs/dialog_dimension_properties_base.cpp:315 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:179 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:171 #: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:117 #: pcbnew/dialogs/dialog_text_properties_base.cpp:145 msgid "Center" @@ -4653,7 +4653,7 @@ msgstr "ファイル '%s' をコピーできません。" #: common/grid_tricks.cpp:278 common/tool/actions.cpp:153 #: eeschema/tools/ee_actions.cpp:148 pcbnew/dialogs/panel_setup_rules.cpp:112 -#: pcbnew/tools/edit_tool.cpp:2011 +#: pcbnew/tools/edit_tool.cpp:2016 msgid "Cut" msgstr "切り取り" @@ -4681,7 +4681,7 @@ msgstr "現在のセル位置へ、クリップボードのセルを貼り付け #: common/grid_tricks.cpp:284 common/tool/actions.cpp:191 #: kicad/project_tree_pane.cpp:771 pcbnew/dialogs/panel_setup_rules.cpp:115 -#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2013 +#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2018 msgid "Delete" msgstr "削除" @@ -5264,8 +5264,8 @@ msgid "Invalid size %lld: too large" msgstr "不正なサイズ %lld: 大きすぎます" #: common/plugins/eagle/eagle_parser.cpp:281 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:373 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:389 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:366 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:382 #, c-format msgid "Invalid Arc with radius %f and angle %f" msgstr "不正な円弧 (半径 %f 、角度 %f )" @@ -16890,7 +16890,7 @@ msgstr "選択レイヤー: %s" #: pcbnew/fp_text_grid_table.cpp:109 pcbnew/pad.cpp:980 #: pcbnew/pcb_dimension.cpp:353 pcbnew/pcb_dimension.cpp:1087 #: pcbnew/pcb_shape.cpp:159 pcbnew/pcb_target.cpp:155 pcbnew/pcb_text.cpp:120 -#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1173 +#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1168 #: pcbnew/tools/board_inspection_tool.cpp:238 #: pcbnew/tools/board_inspection_tool.cpp:385 #: pcbnew/tools/board_inspection_tool.cpp:461 @@ -20877,13 +20877,13 @@ msgstr "その他" msgid "no layers" msgstr "レイヤーなし" -#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1134 -#: pcbnew/pcb_track.cpp:1151 +#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1129 +#: pcbnew/pcb_track.cpp:1146 msgid "Position X" msgstr "位置 X" -#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1137 -#: pcbnew/pcb_track.cpp:1154 +#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1132 +#: pcbnew/pcb_track.cpp:1149 msgid "Position Y" msgstr "位置 Y" @@ -24691,55 +24691,55 @@ msgstr "" msgid "Error loading footprint library table." msgstr "プロジェクトのフットプリント ライブラリー テーブルをロード中にエラー。" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:178 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:170 msgid "Circle Properties" msgstr "円のプロパティ" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:191 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:183 msgid "Arc Properties" msgstr "円弧のプロパティ" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:197 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:189 msgid "Polygon Properties" msgstr "ポリゴンのプロパティ" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:203 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:195 msgid "Rectangle Properties" msgstr "矩形のプロパティ" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:209 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:201 msgid "Line Segment Properties" msgstr "配線セグメントのプロパティ" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:343 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:336 msgid "Modify drawing properties" msgstr "図形のプロパティを変更" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:368 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:361 msgid "The arc angle cannot be zero." msgstr "円弧の角度は0にできません。" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:415 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:427 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:433 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:388 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:398 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:408 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:420 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:426 msgid "The item thickness must be greater than zero." msgstr "アイテムの太さは０より大きくなければなりません。" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:402 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 msgid "The radius must be greater than zero." msgstr "半径は０より大きくなければなりません。" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:412 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 msgid "The rectangle cannot be empty." msgstr "矩形は空にすることができません。" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:421 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:414 msgid "The polygon outline thickness must be >= 0." msgstr "ポリゴン外形線の太さは 0 以上にする必要があります。" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "エラー リスト" @@ -26908,17 +26908,17 @@ msgid "Via type:" msgstr "ビア タイプ:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "貫通" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "マイクロ" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "ブラインド/ベリード" @@ -28393,426 +28393,6 @@ msgstr "DRC ルール:" msgid "Check rule syntax" msgstr "ルールの文法をチェック" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" -"### トップレベルの句\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### ルール句\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### 制約タイプ\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### アイテムタイプ\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### 例\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### 注\n" -"\n" -"version句ははじめの句でなければなりません。 ファイルの文法のバージョンを示" -"し、\n" -"将来のルールパーサーが自動的なアップデートをできるようするためです。\n" -"ここには\"1\"を設定します。\n" -"\n" -"ルールは特異性の順に並べます。\n" -"後ろにあるルールは前にあるものより優先されます。\n" -"一度マッチするルールが見つかれば、他のルールはチェックされません。\n" -"\n" -"Ctrl+/ の操作で行をコメント化/非コメント化できます。\n" -"


\n" -"\n" -"### 式関数\n" -"\n" -"全ての関数のパラメーターは単純なワイルドカードをサポートします。 (`*` and `?" -"`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"`A`のいずれかの部分が与えられたフットプリントのコートヤードの中にある場合、真" -"になります。\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"`A`のいずれかの部分が与えられたフットプリントの表面のコートヤードの中にある場" -"合、真になります。\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"`A`のいずれかの部分が与えられたフットプリントの裏面のコートヤードの中にある場" -"合、真になります。\n" -"

\n" -"\n" -" A.insideArea('')\n" -"`A`のいずれかの部分が与えられたゾーンの中にある場合、真になります。\n" -"

\n" -"\n" -" A.isPlated()\n" -"`A`にメッキされた穴が含まれている場合、真になります。\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"`A`が与えられた差動ペアのネットに属する場合、真になります。\n" -"`` は差動ペアのベース名です。例えば、`inDiffPair('CLK')`は\n" -"`CKL_P`と`CLK_N`のネットにマッチします。\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"`A`と`B`が同じ差動ペアに属する場合、真になります。\n" -"

\n" -"\n" -" A.memberOf('')\n" -"`A`と`B`が与えられたグループに属する場合、真になります。ネストされたメンバー" -"関係も含みます。\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"`A`が与えられたレイヤー上にある場合、真になります。\n" -"レイヤー名は 基板の設定 > 基板編集レイヤー で指定された名前か、\n" -"正規化名(例: `F.Cu`)が使えます。\n" -"\n" -"注意: これは、ルールがそのレイヤーに対して評価されているかいないかにかかわら" -"ず\n" -"`A`がレイヤーにある場合に真を返します。\n" -"後者の場合、`(layer \"layer_name\")`の句をルールの中で使います。\n" -"


\n" -"\n" -"### 更なる例\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # テンティングされたビアにシルクがかかるのを防ぐ\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\" \n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\" \n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\" \n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" -" \n" -" (rule \"Pad to Track Clearance\" \n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\" \n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -" \n" -" (rule \"Max Drill Hole Size PTH\" \n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # 特定の差動ペアに最適なギャップを指定する\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" -"\n" -" # 差動ペアの周りにより大きなクリアランスを指定する\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "新しい寸法線オブジェクトのデフォルト値:" @@ -29410,13 +28990,13 @@ msgstr "ゾーンをチェック中..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29426,7 +29006,7 @@ msgstr "ゾーンをチェック中..." msgid "(%s clearance %s; actual %s)" msgstr "(%s クリアランス %s; 現状 %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(ネット %s と %s)" @@ -31141,7 +30721,7 @@ msgstr "ヒートシンク" msgid "Castellated" msgstr "端面スルーホール" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "直径" @@ -31479,7 +31059,7 @@ msgstr "ブラインド/ベリード ビア" msgid "Through Via" msgstr "貫通ビア" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "ドリル" @@ -31502,23 +31082,23 @@ msgstr "配線(円弧) %s ( %s 上、長さ: %s )" msgid "Track %s on %s, length %s" msgstr "配線 %s ( %s 上、長さ: %s )" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "原点 X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "原点 Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "レイヤー上面" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "レイヤー底面" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "ビア タイプ" @@ -34034,24 +33614,24 @@ msgstr "回転" msgid "Change Side / Flip" msgstr "配置面を変更/反転" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "数値を指定して移動" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "重複した %d アイテム" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "コピーの参照点を選択..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "選択対象をコピーしました" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "コピーはキャンセルされました" @@ -36246,39 +35826,39 @@ msgstr "他の全てのネットクラスを非表示" msgid "Presets (Ctrl+Tab):" msgstr "プリセット (Ctrl+Tab):" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "名前を付けてプリセットを保存..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "プリセットを削除..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "レイヤー プリセット名:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "レイヤー プリセットを保存" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "プリセット" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "プリセットを削除" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "プリセットを選択:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "設定を開く" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." @@ -36582,6 +36162,431 @@ msgstr "KiCad 回路図ファイル" msgid "KiCad Printed Circuit Board" msgstr "KiCad プリント基板ファイル" +#~ msgid "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('/CLK')`\n" +#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" +#~ msgstr "" +#~ "### トップレベルの句\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### ルール句\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### 制約タイプ\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### アイテムタイプ\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### 例\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### 注\n" +#~ "\n" +#~ "version句ははじめの句でなければなりません。 ファイルの文法のバージョンを" +#~ "示し、\n" +#~ "将来のルールパーサーが自動的なアップデートをできるようするためです。\n" +#~ "ここには\"1\"を設定します。\n" +#~ "\n" +#~ "ルールは特異性の順に並べます。\n" +#~ "後ろにあるルールは前にあるものより優先されます。\n" +#~ "一度マッチするルールが見つかれば、他のルールはチェックされません。\n" +#~ "\n" +#~ "Ctrl+/ の操作で行をコメント化/非コメント化できます。\n" +#~ "


\n" +#~ "\n" +#~ "### 式関数\n" +#~ "\n" +#~ "全ての関数のパラメーターは単純なワイルドカードをサポートします。 (`*` and " +#~ "`?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "`A`のいずれかの部分が与えられたフットプリントのコートヤードの中にある場" +#~ "合、真になります。\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "`A`のいずれかの部分が与えられたフットプリントの表面のコートヤードの中にあ" +#~ "る場合、真になります。\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "`A`のいずれかの部分が与えられたフットプリントの裏面のコートヤードの中にあ" +#~ "る場合、真になります。\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "`A`のいずれかの部分が与えられたゾーンの中にある場合、真になります。\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "`A`にメッキされた穴が含まれている場合、真になります。\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "`A`が与えられた差動ペアのネットに属する場合、真になります。\n" +#~ "`` は差動ペアのベース名です。例えば、`inDiffPair('CLK')`は\n" +#~ "`CKL_P`と`CLK_N`のネットにマッチします。\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "`A`と`B`が同じ差動ペアに属する場合、真になります。\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "`A`と`B`が与えられたグループに属する場合、真になります。ネストされたメン" +#~ "バー関係も含みます。\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "`A`が与えられたレイヤー上にある場合、真になります。\n" +#~ "レイヤー名は 基板の設定 > 基板編集レイヤー で指定された名前か、\n" +#~ "正規化名(例: `F.Cu`)が使えます。\n" +#~ "\n" +#~ "注意: これは、ルールがそのレイヤーに対して評価されているかいないかにかかわ" +#~ "らず\n" +#~ "`A`がレイヤーにある場合に真を返します。\n" +#~ "後者の場合、`(layer \"layer_name\")`の句をルールの中で使います。\n" +#~ "


\n" +#~ "\n" +#~ "### 更なる例\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # テンティングされたビアにシルクがかかるのを防ぐ\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\" \n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\" \n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\" \n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" +#~ " \n" +#~ " (rule \"Pad to Track Clearance\" \n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\" \n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ " \n" +#~ " (rule \"Max Drill Hole Size PTH\" \n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # 特定の差動ペアに最適なギャップを指定する\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" +#~ "\n" +#~ " # 差動ペアの周りにより大きなクリアランスを指定する\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" + #, fuzzy, c-format #~ msgid "Unable to locate padstack %s in file %s\n" #~ msgstr "アーカイブ ファイル '%s' を作成できません。\n" diff --git a/translation/pofiles/ko.po b/translation/pofiles/ko.po index 16b6716030..4893439327 100644 --- a/translation/pofiles/ko.po +++ b/translation/pofiles/ko.po @@ -14,7 +14,7 @@ msgid "" msgstr "" "Project-Id-Version: kicad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-08-15 01:21+0000\n" "Last-Translator: 김랑기 \n" "Language-Team: Korean \n" @@ -4188,7 +4188,7 @@ msgid "Shape" msgstr "형상" #: common/eda_shape.cpp:574 common/eda_shape.cpp:584 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:181 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:173 #: pcbnew/pcb_track.cpp:686 msgid "Radius" msgstr "반지름" @@ -4222,8 +4222,8 @@ msgstr "포인트" #: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:155 #: pcbnew/fp_text.cpp:305 pcbnew/fp_text_grid_table.cpp:105 pcbnew/pad.cpp:1008 #: pcbnew/pcb_target.cpp:158 pcbnew/pcb_target.cpp:204 pcbnew/pcb_text.cpp:127 -#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1132 pcbnew/pcb_track.cpp:1149 -#: pcbnew/pcb_track.cpp:1168 +#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1127 pcbnew/pcb_track.cpp:1144 +#: pcbnew/pcb_track.cpp:1163 msgid "Width" msgstr "두께" @@ -4271,13 +4271,13 @@ msgstr "시작 X" msgid "Start Y" msgstr "시작 Y" -#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1140 -#: pcbnew/pcb_track.cpp:1157 +#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1135 +#: pcbnew/pcb_track.cpp:1152 msgid "End X" msgstr "끝 X" -#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1142 -#: pcbnew/pcb_track.cpp:1159 +#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1137 +#: pcbnew/pcb_track.cpp:1154 msgid "End Y" msgstr "끝 Y" @@ -4363,7 +4363,7 @@ msgstr "왼쪽" #: pagelayout_editor/dialogs/properties_frame_base.cpp:89 #: pagelayout_editor/dialogs/properties_frame_base.cpp:105 #: pcbnew/dialogs/dialog_dimension_properties_base.cpp:315 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:179 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:171 #: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:117 #: pcbnew/dialogs/dialog_text_properties_base.cpp:145 msgid "Center" @@ -4641,7 +4641,7 @@ msgstr "파일 '%s'을(를) 복사할 수 없습니다." #: common/grid_tricks.cpp:278 common/tool/actions.cpp:153 #: eeschema/tools/ee_actions.cpp:148 pcbnew/dialogs/panel_setup_rules.cpp:112 -#: pcbnew/tools/edit_tool.cpp:2011 +#: pcbnew/tools/edit_tool.cpp:2016 msgid "Cut" msgstr "자르기" @@ -4669,7 +4669,7 @@ msgstr "현재 셀의 행렬에 클립보드 셀 붙여넣기" #: common/grid_tricks.cpp:284 common/tool/actions.cpp:191 #: kicad/project_tree_pane.cpp:771 pcbnew/dialogs/panel_setup_rules.cpp:115 -#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2013 +#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2018 msgid "Delete" msgstr "삭제" @@ -5250,8 +5250,8 @@ msgid "Invalid size %lld: too large" msgstr "잘못된 크기 %lld: 너무 큼" #: common/plugins/eagle/eagle_parser.cpp:281 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:373 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:389 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:366 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:382 #, c-format msgid "Invalid Arc with radius %f and angle %f" msgstr "반경이 %f이고 각도가 %f인 잘못된 호" @@ -16796,7 +16796,7 @@ msgstr "레이어 선택: %s" #: pcbnew/fp_text_grid_table.cpp:109 pcbnew/pad.cpp:980 #: pcbnew/pcb_dimension.cpp:353 pcbnew/pcb_dimension.cpp:1087 #: pcbnew/pcb_shape.cpp:159 pcbnew/pcb_target.cpp:155 pcbnew/pcb_text.cpp:120 -#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1173 +#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1168 #: pcbnew/tools/board_inspection_tool.cpp:238 #: pcbnew/tools/board_inspection_tool.cpp:385 #: pcbnew/tools/board_inspection_tool.cpp:461 @@ -20762,13 +20762,13 @@ msgstr "기타" msgid "no layers" msgstr "레이어 없음" -#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1134 -#: pcbnew/pcb_track.cpp:1151 +#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1129 +#: pcbnew/pcb_track.cpp:1146 msgid "Position X" msgstr "위치 X" -#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1137 -#: pcbnew/pcb_track.cpp:1154 +#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1132 +#: pcbnew/pcb_track.cpp:1149 msgid "Position Y" msgstr "위치 Y" @@ -24558,55 +24558,55 @@ msgstr "" msgid "Error loading footprint library table." msgstr "풋프린트 라이브러리 테이블을 불러오는 중에 오류가 발생했습니다." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:178 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:170 msgid "Circle Properties" msgstr "원 속성" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:191 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:183 msgid "Arc Properties" msgstr "호 속성" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:197 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:189 msgid "Polygon Properties" msgstr "다각형 속성" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:203 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:195 msgid "Rectangle Properties" msgstr "사각형 속성" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:209 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:201 msgid "Line Segment Properties" msgstr "도선 세그먼트 속성" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:343 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:336 msgid "Modify drawing properties" msgstr "그리기 속성 편집" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:368 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:361 msgid "The arc angle cannot be zero." msgstr "호의 각도는 0이 될 수 없습니다." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:415 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:427 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:433 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:388 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:398 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:408 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:420 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:426 msgid "The item thickness must be greater than zero." msgstr "아이템의 두께는 0보다 커야 합니다." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:402 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 msgid "The radius must be greater than zero." msgstr "반지름은 0보다 커야 합니다." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:412 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 msgid "The rectangle cannot be empty." msgstr "직사각형은 비어있을 수 없습니다." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:421 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:414 msgid "The polygon outline thickness must be >= 0." msgstr "다각형 윤곽선 두께는 >= 0이어야 합니다." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "오류 목록" @@ -26760,17 +26760,17 @@ msgid "Via type:" msgstr "비아 형식:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "스루" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "마이크로" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "블라인드/베리드" @@ -28234,419 +28234,6 @@ msgstr "DRC 규칙:" msgid "Check rule syntax" msgstr "규칙 문법을 체크" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" -"### 최상위 조항\n" -"\n" -" (version <번호>)\n" -"\n" -" (rule <규칙_이름> <규칙_절> ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### 규칙 조항\n" -"\n" -" (constraint <제약_형식> ...)\n" -"\n" -" (condition \"<표현식>\")\n" -"\n" -" (layer \"<레이어_이름>\")\n" -"\n" -"\n" -"

\n" -"\n" -"### 제약 형식\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### 개체 형식\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### 예시\n" -"\n" -" (버전 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # HV 트랙 사이의 더 넓은 간격\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### 참고\n" -"\n" -"버전 절이 첫 번째 절이 되어야 합니다. 이는 파일의 문법 버전을 알려주며, \n" -"향후 규칙 구문 분석기가 자동 업데이트를 진행하는 데 도움을 줍니다.\n" -"이는 \"1\" 로 설정되어야 합니다.\n" -"\n" -"규칙은 구체성에 따라 정렬되어야 하고,\n" -"이후의 규칙은 이전 규칙보다 우선하며,\n" -"일치하는 규칙이 발견되면 더 이상의 규칙은 확인하지 않습니다.\n" -"\n" -"Ctrl+/ 을 사용하여 줄에 주석을 달거나 주석을 해제합니다.\n" -"


\n" -"\n" -"### 표현식 함수\n" -"\n" -"모든 함수 매개변수는 간단한 와일드카드를 지원한다 (`*`와 `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"`A`의 일부가 지정된 풋프린트의 주요 코트야드 범위 내에 있을 경우 참이 된다.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"`A`의 일부가 지정된 풋프린트의 전면 코트야드 범위 내에 있을 경우 참이 된다.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"`A`의 일부가 지정된 풋프린트의 후면 코트야드 범위 내에 있을 경우 참이 된다.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"`A`의 일부가 제시된 영역의 테두리 내에 있을 경우 참이 된다.\n" -"

\n" -"\n" -" A.isPlated()\n" -"`A`가 도금된 홀을 포함할 때 참이 된다.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"`A`가 제시된 차동 쌍의 일부에 포함되는 네트를 가지고 있을 경우 참이 된다.\n" -"``은 차동 쌍의 기본 이름이다. 예를 들어, `inDiffPair('/CLK')`은\n" -"`/CLK_P` 와 `/CLK_N` 네트 안의 항목들과 대응됩니다.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"`A`와 `B`같은 차동 쌍의 멤버일 경우 참이 된다.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"`A`가 제시된 그룹의 멤버일 경우 참이 된다. 중첩된 구성원을 포함합니다.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"`A`가 제시된 레이어에 존재할 경우 참이 된다. 레이어 이름은\n" -"Board Setup > Board Editor Layers에서 할당된 이름 또는\n" -"정식 이름이 될 수 있다(예: `F.Cu`).\n" -"\n" -"주의: 규칙이 해당 레이어에 적용되는지 여부와 관계 없이,\n" -"`A`가 제시된 레이어에 있을 경우 참을 반환합니다.\n" -"후자의 경우 규칙에서`(layer \"layer_name\")` 절을 사용합니다.\n" -"


\n" -"\n" -"### 더 많은 예시\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # 천막 비아에 실크 방지\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # 특정 diff 쌍에 대한 최적의 간격을 지정함\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # diff 쌍 주변에 더 큰 간격을 지정함\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "새 치수 객체에 대한 기본 속성:" @@ -29243,13 +28830,13 @@ msgstr "영역 확인 중..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29259,7 +28846,7 @@ msgstr "영역 확인 중..." msgid "(%s clearance %s; actual %s)" msgstr "(%s 클리어런스 %s; 실제 값 %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(네트 %s 와 %s)" @@ -30959,7 +30546,7 @@ msgstr "히트 싱크" msgid "Castellated" msgstr "카스텔레이티드" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "직경" @@ -31297,7 +30884,7 @@ msgstr "숨겨진 비아" msgid "Through Via" msgstr "관통 비아" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "드릴" @@ -31320,23 +30907,23 @@ msgstr "배선 (호) %s on %s, 길이 %s" msgid "Track %s on %s, length %s" msgstr "배선 %s on %s, 길이 %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "원점 X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "원점 Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "레이어 상단" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "레이어 하단" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "비아 유형" @@ -33842,24 +33429,24 @@ msgstr "회전" msgid "Change Side / Flip" msgstr "배치면을 변경 / 반전" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "수치 지정 후 이동" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "중복된 %d개 항목" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "복사본에 대한 참조점 선택..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "선택 항목이 복사되었습니다" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "복사 취소됨" @@ -36049,39 +35636,39 @@ msgstr "다른 모든 네트클래스 숨기기" msgid "Presets (Ctrl+Tab):" msgstr "사전 설정 (Ctrl+Tab):" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "사전 설정 저장..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "사전 설정 삭제..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "레이어 사전 설정 이름:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "레이어 사전 설정을 저장" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "프리셋" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "사전 설정 삭제" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "프리셋 선택:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "설정 열기" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." @@ -36385,6 +35972,430 @@ msgstr "KiCad 회로도" msgid "KiCad Printed Circuit Board" msgstr "KiCad 인쇄 회로 기판" +#~ msgid "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('/CLK')`\n" +#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" +#~ msgstr "" +#~ "### 최상위 조항\n" +#~ "\n" +#~ " (version <번호>)\n" +#~ "\n" +#~ " (rule <규칙_이름> <규칙_절> ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### 규칙 조항\n" +#~ "\n" +#~ " (constraint <제약_형식> ...)\n" +#~ "\n" +#~ " (condition \"<표현식>\")\n" +#~ "\n" +#~ " (layer \"<레이어_이름>\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### 제약 형식\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### 개체 형식\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### 예시\n" +#~ "\n" +#~ " (버전 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # HV 트랙 사이의 더 넓은 간격\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### 참고\n" +#~ "\n" +#~ "버전 절이 첫 번째 절이 되어야 합니다. 이는 파일의 문법 버전을 알려주" +#~ "며, \n" +#~ "향후 규칙 구문 분석기가 자동 업데이트를 진행하는 데 도움을 줍니다.\n" +#~ "이는 \"1\" 로 설정되어야 합니다.\n" +#~ "\n" +#~ "규칙은 구체성에 따라 정렬되어야 하고,\n" +#~ "이후의 규칙은 이전 규칙보다 우선하며,\n" +#~ "일치하는 규칙이 발견되면 더 이상의 규칙은 확인하지 않습니다.\n" +#~ "\n" +#~ "Ctrl+/ 을 사용하여 줄에 주석을 달거나 주석을 해제합니다.\n" +#~ "


\n" +#~ "\n" +#~ "### 표현식 함수\n" +#~ "\n" +#~ "모든 함수 매개변수는 간단한 와일드카드를 지원한다 (`*`와 `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "`A`의 일부가 지정된 풋프린트의 주요 코트야드 범위 내에 있을 경우 참이 된" +#~ "다.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "`A`의 일부가 지정된 풋프린트의 전면 코트야드 범위 내에 있을 경우 참이 된" +#~ "다.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "`A`의 일부가 지정된 풋프린트의 후면 코트야드 범위 내에 있을 경우 참이 된" +#~ "다.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "`A`의 일부가 제시된 영역의 테두리 내에 있을 경우 참이 된다.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "`A`가 도금된 홀을 포함할 때 참이 된다.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "`A`가 제시된 차동 쌍의 일부에 포함되는 네트를 가지고 있을 경우 참이 된" +#~ "다.\n" +#~ "``은 차동 쌍의 기본 이름이다. 예를 들어, `inDiffPair('/CLK')`" +#~ "은\n" +#~ "`/CLK_P` 와 `/CLK_N` 네트 안의 항목들과 대응됩니다.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "`A`와 `B`같은 차동 쌍의 멤버일 경우 참이 된다.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "`A`가 제시된 그룹의 멤버일 경우 참이 된다. 중첩된 구성원을 포함합니다.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "`A`가 제시된 레이어에 존재할 경우 참이 된다. 레이어 이름은\n" +#~ "Board Setup > Board Editor Layers에서 할당된 이름 또는\n" +#~ "정식 이름이 될 수 있다(예: `F.Cu`).\n" +#~ "\n" +#~ "주의: 규칙이 해당 레이어에 적용되는지 여부와 관계 없이,\n" +#~ "`A`가 제시된 레이어에 있을 경우 참을 반환합니다.\n" +#~ "후자의 경우 규칙에서`(layer \"layer_name\")` 절을 사용합니다.\n" +#~ "


\n" +#~ "\n" +#~ "### 더 많은 예시\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # 천막 비아에 실크 방지\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # 특정 diff 쌍에 대한 최적의 간격을 지정함\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # diff 쌍 주변에 더 큰 간격을 지정함\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" + #, fuzzy, c-format #~ msgid "Unable to locate padstack %s in file %s\n" #~ msgstr "'%s' 보관 파일을 생성할 수 없음\n" diff --git a/translation/pofiles/lt.po b/translation/pofiles/lt.po index b1ac895504..56e838c57e 100644 --- a/translation/pofiles/lt.po +++ b/translation/pofiles/lt.po @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad 4.0\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2021-08-20 19:52+0000\n" "Last-Translator: Seth Hillbrand \n" "Language-Team: Lithuanian = 0." msgstr "Толщина элемента должна быть больше нуля." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Klaidų sąrašas" @@ -27594,17 +27594,17 @@ msgid "Via type:" msgstr "Perėjimo tipas:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "Ištisinis perėjimas" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "Mikro" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Aklas / palaidotas" @@ -29080,216 +29080,6 @@ msgstr "KDR taisyklės:" msgid "Check rule syntax" msgstr "Patikrinkite taisyklės sintaksę" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "Numatytosios naujų matmenų objektų ypatybės:" @@ -29913,13 +29703,13 @@ msgstr "Tikrinama zonos užpildymas ..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29929,7 +29719,7 @@ msgstr "Tikrinama zonos užpildymas ..." msgid "(%s clearance %s; actual %s)" msgstr "(%s leidimas %s; faktinis %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(tinklai %s ir %s)" @@ -31689,7 +31479,7 @@ msgstr "Radiatorius" msgid "Castellated" msgstr "Castellated" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Diametras" @@ -32038,7 +31828,7 @@ msgstr "Paslėptas perėjimas" msgid "Through Via" msgstr "Ištisinis perėjimas" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Grąžtas" @@ -32061,23 +31851,23 @@ msgstr "Takelis %s %s, ilgis %s" msgid "Track %s on %s, length %s" msgstr "Takelis %s %s, ilgis %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "Kilmė X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "Kilmė Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "Sluoksnio viršus" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "Sluoksnio apačia" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "„Via Type“" @@ -34661,24 +34451,24 @@ msgstr "Pasukti" msgid "Change Side / Flip" msgstr "Ppakeisti perėjimo ir grąžto dydį" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "Perkelti tiksliai" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "Kopijuojami %d elementai" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "Pasirinkite kopijos atskaitos tašką ..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "Pasirinkimas nukopijuotas" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 #, fuzzy msgid "Copy canceled" msgstr "Kopija atšaukta" @@ -36958,39 +36748,39 @@ msgstr "Slėpti visas kitas tinklo klases" msgid "Presets (Ctrl+Tab):" msgstr "(„Ctrl“ + tabuliavimo klavišas)" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "Išsaugoti iš anksto nustatytą ..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "Ištrinti iš anksto nustatytą ..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "Iš anksto nustatytas sluoksnio pavadinimas:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "Išsaugoti sluoksnio išankstinį nustatymą" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "Parinktys" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "Ištrinti iš anksto nustatytą" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "Pasirinkite išankstinį nustatymą:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "Atidarykite „Preferences“" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." diff --git a/translation/pofiles/lv.po b/translation/pofiles/lv.po index 092d6c373d..9519e03058 100644 --- a/translation/pofiles/lv.po +++ b/translation/pofiles/lv.po @@ -4,7 +4,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad 6.0\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2021-01-13 14:21+0000\n" "Last-Translator: Rihards Skuja \n" "Language-Team: Latvian = 0." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "" @@ -25542,17 +25542,17 @@ msgid "Via type:" msgstr "" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "" @@ -26931,216 +26931,6 @@ msgstr "" msgid "Check rule syntax" msgstr "" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "" @@ -27735,13 +27525,13 @@ msgstr "" #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -27751,7 +27541,7 @@ msgstr "" msgid "(%s clearance %s; actual %s)" msgstr "" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "" @@ -29390,7 +29180,7 @@ msgstr "" msgid "Castellated" msgstr "" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "" @@ -29723,7 +29513,7 @@ msgstr "" msgid "Through Via" msgstr "" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "" @@ -29746,23 +29536,23 @@ msgstr "" msgid "Track %s on %s, length %s" msgstr "" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "" @@ -32063,24 +31853,24 @@ msgstr "" msgid "Change Side / Flip" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "" -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "" @@ -34269,39 +34059,39 @@ msgstr "" msgid "Presets (Ctrl+Tab):" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." diff --git a/translation/pofiles/nl.po b/translation/pofiles/nl.po index b67c131d15..1ef58c6269 100644 --- a/translation/pofiles/nl.po +++ b/translation/pofiles/nl.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-04-13 14:13+0000\n" "Last-Translator: Bas Wijnen \n" "Language-Team: Dutch \n" @@ -4237,7 +4237,7 @@ msgid "Shape" msgstr "Vorm" #: common/eda_shape.cpp:574 common/eda_shape.cpp:584 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:181 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:173 #: pcbnew/pcb_track.cpp:686 msgid "Radius" msgstr "Straal" @@ -4271,8 +4271,8 @@ msgstr "Punten" #: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:155 #: pcbnew/fp_text.cpp:305 pcbnew/fp_text_grid_table.cpp:105 pcbnew/pad.cpp:1008 #: pcbnew/pcb_target.cpp:158 pcbnew/pcb_target.cpp:204 pcbnew/pcb_text.cpp:127 -#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1132 pcbnew/pcb_track.cpp:1149 -#: pcbnew/pcb_track.cpp:1168 +#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1127 pcbnew/pcb_track.cpp:1144 +#: pcbnew/pcb_track.cpp:1163 msgid "Width" msgstr "Breedte" @@ -4320,13 +4320,13 @@ msgstr "Start X" msgid "Start Y" msgstr "Start Y" -#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1140 -#: pcbnew/pcb_track.cpp:1157 +#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1135 +#: pcbnew/pcb_track.cpp:1152 msgid "End X" msgstr "Einde X" -#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1142 -#: pcbnew/pcb_track.cpp:1159 +#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1137 +#: pcbnew/pcb_track.cpp:1154 msgid "End Y" msgstr "Einde Y" @@ -4412,7 +4412,7 @@ msgstr "Links" #: pagelayout_editor/dialogs/properties_frame_base.cpp:89 #: pagelayout_editor/dialogs/properties_frame_base.cpp:105 #: pcbnew/dialogs/dialog_dimension_properties_base.cpp:315 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:179 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:171 #: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:117 #: pcbnew/dialogs/dialog_text_properties_base.cpp:145 msgid "Center" @@ -4697,7 +4697,7 @@ msgstr "Kan bestand '%s' niet kopiëren." #: common/grid_tricks.cpp:278 common/tool/actions.cpp:153 #: eeschema/tools/ee_actions.cpp:148 pcbnew/dialogs/panel_setup_rules.cpp:112 -#: pcbnew/tools/edit_tool.cpp:2011 +#: pcbnew/tools/edit_tool.cpp:2016 msgid "Cut" msgstr "Knip" @@ -4726,7 +4726,7 @@ msgstr "Plak klembordcellen in de matrix in de huidige cel" #: common/grid_tricks.cpp:284 common/tool/actions.cpp:191 #: kicad/project_tree_pane.cpp:771 pcbnew/dialogs/panel_setup_rules.cpp:115 -#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2013 +#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2018 msgid "Delete" msgstr "Verwijderen" @@ -5307,8 +5307,8 @@ msgid "Invalid size %lld: too large" msgstr "Ongeldige maat %lld: te groot" #: common/plugins/eagle/eagle_parser.cpp:281 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:373 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:389 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:366 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:382 #, c-format msgid "Invalid Arc with radius %f and angle %f" msgstr "Ongeldige boog met straal %f en hoek %f" @@ -17023,7 +17023,7 @@ msgstr "Selecteer laag: %s" #: pcbnew/fp_text_grid_table.cpp:109 pcbnew/pad.cpp:980 #: pcbnew/pcb_dimension.cpp:353 pcbnew/pcb_dimension.cpp:1087 #: pcbnew/pcb_shape.cpp:159 pcbnew/pcb_target.cpp:155 pcbnew/pcb_text.cpp:120 -#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1173 +#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1168 #: pcbnew/tools/board_inspection_tool.cpp:238 #: pcbnew/tools/board_inspection_tool.cpp:385 #: pcbnew/tools/board_inspection_tool.cpp:461 @@ -21036,13 +21036,13 @@ msgstr "en anderen" msgid "no layers" msgstr "geen lagen" -#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1134 -#: pcbnew/pcb_track.cpp:1151 +#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1129 +#: pcbnew/pcb_track.cpp:1146 msgid "Position X" msgstr "Positie X" -#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1137 -#: pcbnew/pcb_track.cpp:1154 +#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1132 +#: pcbnew/pcb_track.cpp:1149 msgid "Position Y" msgstr "Positie Y" @@ -24890,57 +24890,57 @@ msgstr "" msgid "Error loading footprint library table." msgstr "Fout bij het laden van de footprint-bibliotheek-tabel." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:178 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:170 msgid "Circle Properties" msgstr "Circle Eigenschappen" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:191 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:183 msgid "Arc Properties" msgstr "Arc-eigenschappen" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:197 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:189 msgid "Polygon Properties" msgstr "Polygoon-eigenschappen" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:203 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:195 msgid "Rectangle Properties" msgstr "Rechthoekige eigenschappen" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:209 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:201 msgid "Line Segment Properties" msgstr "Eigenschappen lijnsegment" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:343 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:336 msgid "Modify drawing properties" msgstr "Wijzig tekeningeigenschappen" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:368 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:361 msgid "The arc angle cannot be zero." msgstr "De booghoek mag niet nul zijn." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:415 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:427 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:433 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:388 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:398 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:408 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:420 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:426 #, fuzzy msgid "The item thickness must be greater than zero." msgstr "Traceerafstand moet groter zijn dan 0." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:402 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 #, fuzzy msgid "The radius must be greater than zero." msgstr "Traceerafstand moet groter zijn dan 0." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:412 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 msgid "The rectangle cannot be empty." msgstr "De rechthoek mag niet leeg zijn." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:421 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:414 msgid "The polygon outline thickness must be >= 0." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Foutenlijst" @@ -27147,17 +27147,17 @@ msgid "Via type:" msgstr "Via type:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "Door" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "Micro" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Blind / begraven" @@ -28655,216 +28655,6 @@ msgstr "DRC-regels:" msgid "Check rule syntax" msgstr "Controleer de syntaxis van de regel" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "Standaardeigenschappen voor nieuwe dimensieobjecten:" @@ -29472,13 +29262,13 @@ msgstr "Zones controleren ..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29488,7 +29278,7 @@ msgstr "Zones controleren ..." msgid "(%s clearance %s; actual %s)" msgstr "(%s vrije afstand %s; werkelijk %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(netten %s en %s)" @@ -31205,7 +30995,7 @@ msgstr "Koellichaam" msgid "Castellated" msgstr "Gekanteeld" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Diameter" @@ -31545,7 +31335,7 @@ msgstr "Blind/Onzichtbare Via" msgid "Through Via" msgstr "Through Via" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Boor" @@ -31568,23 +31358,23 @@ msgstr "Spoor (boog) %s op %s, lengte %s" msgid "Track %s on %s, length %s" msgstr "Spoor %s op %s, lengte %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "Nulpunt X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "Nulpunt Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "Laag boven" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "Laag onder" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "Via Type" @@ -34125,24 +33915,24 @@ msgstr "Roteren" msgid "Change Side / Flip" msgstr "Omdraaien" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "Verplaats exact" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "%d artikel(en) gedupliceerd" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "Selecteer referentiepunt voor de kopie ..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "Selectie gekopieerd" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "Kopiëren geannuleerd" @@ -36370,39 +36160,39 @@ msgstr "Verberg alle andere net-klassen" msgid "Presets (Ctrl+Tab):" msgstr "Voorvoegsel (Ctrl+Tab):" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "Instelling opslaan ..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "Instelling verwijderen ..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "Layer preset naam:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "Layer Preset opslaan" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "Instellingen" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "Instelling verwijderen" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "Selecteer preset:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "Open Voorkeuren" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." diff --git a/translation/pofiles/no.po b/translation/pofiles/no.po index 2722f5c6f6..a46ab29879 100644 --- a/translation/pofiles/no.po +++ b/translation/pofiles/no.po @@ -5,7 +5,7 @@ msgid "" msgstr "" "Project-Id-Version: 5.99\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-06-27 00:52+0000\n" "Last-Translator: Allan Nordhøy \n" "Language-Team: Norwegian Bokmål = 0." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Feilliste" @@ -27593,17 +27593,17 @@ msgid "Via type:" msgstr "Via-type:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "Gjennom" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "Mikro" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Blind / begravd" @@ -29079,216 +29079,6 @@ msgstr "DRC-regler:" msgid "Check rule syntax" msgstr "Kontroller regelsyntaks" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "Standardegenskaper for nye dimensjonsobjekter:" @@ -29917,13 +29707,13 @@ msgstr "Kontrollerer sonefyllinger ..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29933,7 +29723,7 @@ msgstr "Kontrollerer sonefyllinger ..." msgid "(%s clearance %s; actual %s)" msgstr "(%s klaring %s; faktisk %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(garn %s og %s)" @@ -31684,7 +31474,7 @@ msgstr "Kjøleribbe" msgid "Castellated" msgstr "Kastellert" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Diameter" @@ -32033,7 +31823,7 @@ msgstr "Blind / Begravet Via" msgid "Through Via" msgstr "Gjennom Via" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Bore" @@ -32056,23 +31846,23 @@ msgstr "Spor %s på %s, lengde %s" msgid "Track %s on %s, length %s" msgstr "Spor %s på %s, lengde %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "Opprinnelse X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "Opprinnelse Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "Layer Top" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "Lagbunn" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "Via-type" @@ -34651,24 +34441,24 @@ msgstr "Roter" msgid "Change Side / Flip" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "Gå nøyaktig" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "Duplisert %d vare (r)" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "Velg referansepunkt for kopien ..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "Valget ble kopiert" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 #, fuzzy msgid "Copy canceled" msgstr "Kopien avbrutt" @@ -36941,40 +36731,40 @@ msgstr "Skjul alle andre nettklasser" msgid "Presets (Ctrl+Tab):" msgstr "(Ctrl+Tab)" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "Lagre forhåndsinnstilling ..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "Slett forhåndsinnstilling ..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "Lagets forhåndsinnstilte navn:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "Lagre laginnstilling" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "Forhåndsinnstillinger" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "Slett forhåndsinnstilling" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "Velg forhåndsinnstilling:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 #, fuzzy msgid "Open Preferences" msgstr "&Innstillinger" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." diff --git a/translation/pofiles/pl.po b/translation/pofiles/pl.po index ab3369c86d..9ce0a23b00 100644 --- a/translation/pofiles/pl.po +++ b/translation/pofiles/pl.po @@ -5,7 +5,7 @@ msgid "" msgstr "" "Project-Id-Version: kicad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-09-27 07:22+0000\n" "Last-Translator: ZbeeGin \n" "Language-Team: Polish \n" @@ -4220,7 +4220,7 @@ msgid "Shape" msgstr "Kształt" #: common/eda_shape.cpp:574 common/eda_shape.cpp:584 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:181 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:173 #: pcbnew/pcb_track.cpp:686 msgid "Radius" msgstr "Promień" @@ -4254,8 +4254,8 @@ msgstr "Punkty" #: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:155 #: pcbnew/fp_text.cpp:305 pcbnew/fp_text_grid_table.cpp:105 pcbnew/pad.cpp:1008 #: pcbnew/pcb_target.cpp:158 pcbnew/pcb_target.cpp:204 pcbnew/pcb_text.cpp:127 -#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1132 pcbnew/pcb_track.cpp:1149 -#: pcbnew/pcb_track.cpp:1168 +#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1127 pcbnew/pcb_track.cpp:1144 +#: pcbnew/pcb_track.cpp:1163 msgid "Width" msgstr "Szerokość" @@ -4303,13 +4303,13 @@ msgstr "Początek X" msgid "Start Y" msgstr "Początek Y" -#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1140 -#: pcbnew/pcb_track.cpp:1157 +#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1135 +#: pcbnew/pcb_track.cpp:1152 msgid "End X" msgstr "Koniec X" -#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1142 -#: pcbnew/pcb_track.cpp:1159 +#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1137 +#: pcbnew/pcb_track.cpp:1154 msgid "End Y" msgstr "Koniec Y" @@ -4395,7 +4395,7 @@ msgstr "Lewo" #: pagelayout_editor/dialogs/properties_frame_base.cpp:89 #: pagelayout_editor/dialogs/properties_frame_base.cpp:105 #: pcbnew/dialogs/dialog_dimension_properties_base.cpp:315 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:179 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:171 #: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:117 #: pcbnew/dialogs/dialog_text_properties_base.cpp:145 msgid "Center" @@ -4681,7 +4681,7 @@ msgstr "Nie można skopiować '%s'." #: common/grid_tricks.cpp:278 common/tool/actions.cpp:153 #: eeschema/tools/ee_actions.cpp:148 pcbnew/dialogs/panel_setup_rules.cpp:112 -#: pcbnew/tools/edit_tool.cpp:2011 +#: pcbnew/tools/edit_tool.cpp:2016 msgid "Cut" msgstr "Wytnij" @@ -4709,7 +4709,7 @@ msgstr "Wklej komórki ze schowka do matrycy od bieżącej pozycji" #: common/grid_tricks.cpp:284 common/tool/actions.cpp:191 #: kicad/project_tree_pane.cpp:771 pcbnew/dialogs/panel_setup_rules.cpp:115 -#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2013 +#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2018 msgid "Delete" msgstr "Usuń" @@ -5291,8 +5291,8 @@ msgid "Invalid size %lld: too large" msgstr "Nieprawidłowy rozmiar %lld: za duży" #: common/plugins/eagle/eagle_parser.cpp:281 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:373 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:389 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:366 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:382 #, c-format msgid "Invalid Arc with radius %f and angle %f" msgstr "Nieprawidłowy łuk o promieniu %f i kącie %f" @@ -17002,7 +17002,7 @@ msgstr "Wybieram warstwę: %s" #: pcbnew/fp_text_grid_table.cpp:109 pcbnew/pad.cpp:980 #: pcbnew/pcb_dimension.cpp:353 pcbnew/pcb_dimension.cpp:1087 #: pcbnew/pcb_shape.cpp:159 pcbnew/pcb_target.cpp:155 pcbnew/pcb_text.cpp:120 -#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1173 +#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1168 #: pcbnew/tools/board_inspection_tool.cpp:238 #: pcbnew/tools/board_inspection_tool.cpp:385 #: pcbnew/tools/board_inspection_tool.cpp:461 @@ -20999,13 +20999,13 @@ msgstr "i pozostałe" msgid "no layers" msgstr "brak warstw" -#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1134 -#: pcbnew/pcb_track.cpp:1151 +#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1129 +#: pcbnew/pcb_track.cpp:1146 msgid "Position X" msgstr "Pozycja X" -#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1137 -#: pcbnew/pcb_track.cpp:1154 +#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1132 +#: pcbnew/pcb_track.cpp:1149 msgid "Position Y" msgstr "Pozycja Y" @@ -24852,55 +24852,55 @@ msgstr "" msgid "Error loading footprint library table." msgstr "Błąd podczas wczytywania tabeli bibliotek footprintów." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:178 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:170 msgid "Circle Properties" msgstr "Właściwości Okręgów" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:191 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:183 msgid "Arc Properties" msgstr "Właściwości Łuków" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:197 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:189 msgid "Polygon Properties" msgstr "Właściwości stref wypełnień" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:203 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:195 msgid "Rectangle Properties" msgstr "Właściwości prostokąta" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:209 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:201 msgid "Line Segment Properties" msgstr "Właściwości Segmentów" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:343 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:336 msgid "Modify drawing properties" msgstr "Modyfikuj właściwości rysunków" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:368 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:361 msgid "The arc angle cannot be zero." msgstr "Kąt łuku nie może być zerowy." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:415 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:427 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:433 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:388 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:398 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:408 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:420 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:426 msgid "The item thickness must be greater than zero." msgstr "Grubość musi być większa niż zero." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:402 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 msgid "The radius must be greater than zero." msgstr "Promień musi być większy niż zero." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:412 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 msgid "The rectangle cannot be empty." msgstr "Prostokąt nie może być pusty." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:421 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:414 msgid "The polygon outline thickness must be >= 0." msgstr "Grubość obrysu strefy musi być większa niż zero." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Lista błędów" @@ -27106,17 +27106,17 @@ msgid "Via type:" msgstr "Typ przelotki:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "Na wylot" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "Mikroprzelotka" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Ślepa/Zagrzebana" @@ -28617,430 +28617,6 @@ msgstr "Reguły DRC:" msgid "Check rule syntax" msgstr "Sprawdź składnię reguł" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" -"### Klauzule najwyższego poziomu\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Klauzule warunkowe\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Typy ograniczeń\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Typy elementów\n" -"\n" -"* buried_via\n" -"* graphic\n" -"* hole\n" -"* micro_via\n" -"* pad\n" -"* text\n" -"* track\n" -"* via\n" -"* zone\n" -"\n" -"
\n" -"\n" -"### Przykłady\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # szerszy prześwit pomiędzy ścieżkami HV\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Uwagi\n" -"\n" -"Klauzula wersji musi być pierwszą klauzulą. Oznacza ona wersję składni " -"zastosowanej w pliku, \n" -"wobec czego przyszłe parsery będą mogły przeprowadzać automatyczne " -"aktualizacje. Obecnie powinna \n" -"być ustawiona na \"1\".\n" -"\n" -"Reguły powinny być uporządkowane według szczegółowości. Dalsze reguły \n" -"mają pierwszeństwo nad regułami wcześniejszymi; jak tylko odnaleziona \n" -"będzie pasująca reguła dalsze reguły nie będą sprawdzane.\n" -"\n" -"Użyj Ctrl+/ by zakomentować lub odkomentować linię.\n" -"


\n" -"\n" -"### Funkcje wyrażeniowe\n" -"\n" -"Wszystkie parametry funkcji obsługują proste sybmole wieloznaczne (`*` oraz " -"`?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"Prawdziwe jeśli dowolna część `A` leży wewnątrz obszaru zajętości podanego " -"footprintu.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"Prawdziwe jeśli dowolna część `A` leży wewnątrz obszaru zajętości podanego " -"footprintu na stronie górnej.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"Prawdziwe jeśli dowolna część `A` leży wewnątrz obszaru zajętości podanego " -"footprintu na stronie dolnej.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"Prawdziwe jeśli dowolna część `A` leży w obrysie podanej strefy.\n" -"

\n" -"\n" -" A.isPlated()\n" -"Prawdziwe jeśli `A` posiada otwór, który jest metalizowany.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"Prawdziwe jeśli `A` posiada sieć, która jest składnikiem pary różnicowej.\n" -"`` to nazwa bazowa pary różnicowej. Na przykład " -"`inDiffPair('CLK')`\n" -"odnosi się do sieci zarówno `CLK_P` jak i `CLK_N`.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"Prawdziwe jeśli `A` i `B` są członkami tej samej pary różnicowej.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"Prawdziwe jeśli `A` jest członkiem podanej grupy. Nawet zagnieżdżonej w " -"innej grupie.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"Prawdziwe jeśli `A` istnieje na określonej warstwie. Nazwa warstwy może być " -"zarówno\n" -"nazwą przypisaną w oknie dialogowym Ustawienia Płytki > Ustawienia warstw " -"jak też\n" -"jej nazwą kanoniczną (na przykład: `F.Cu`).\n" -"\n" -"UWAGA: Zwraca prawdę, jeśli `A` znajduje się na danej warstwie, \n" -"niezależnie czy reguła jest oceniana dla tej warstwy.\n" -"W tym ostatnim przypadku użyj w regule klauzuli `(layer \"nazwa_warstwy" -"\")`.\n" -"


\n" -"\n" -"### Więcej przykładów\n" -"\n" -" (rule \"blokada strefy\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # zapobiega opisowi na przelotkach\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Odległość między przelotkami różnych sieci\" \n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Prześwit między polami różnych sieci\" \n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Prześwit między otworem a ścieżką\" \n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" -" \n" -" (rule \"Prześwit między polem a ścieżką\" \n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Maksymalny rozmiar otworu mechanicznego\" \n" -" (constraint hole (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -" \n" -" (rule \"Maksymalny rozmiar otworu przewlekanego\" \n" -" (constraint hole (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Określa optymalną przerwę dla konkretnej pary różnicowej\n" -" (rule \"prześwit dp dla lini zegarowej\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" -"\n" -" # Określa większy prześwit wokół dowolnej pary różnicowej\n" -" (rule \"prześwit dp\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "Domyślne ustawienia dla nowych wymiarowań:" @@ -29641,13 +29217,13 @@ msgstr "Sprawdzam wypełnione strefy..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29657,7 +29233,7 @@ msgstr "Sprawdzam wypełnione strefy..." msgid "(%s clearance %s; actual %s)" msgstr "(%s prześwit %s; obecnie %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(sieci %s oraz %s)" @@ -31376,7 +30952,7 @@ msgstr "Radiator" msgid "Castellated" msgstr "Kastelacja" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Średnica" @@ -31714,7 +31290,7 @@ msgstr "Przelotka ślepa/zagrzebana" msgid "Through Via" msgstr "Przelotka na wylot" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Wiercenie" @@ -31737,23 +31313,23 @@ msgstr "Ścieżka (łuk) %s na %s, długość %s" msgid "Track %s on %s, length %s" msgstr "Ścieżka %s na %s, długość %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "Punkt bazowy X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "Punkt bazowy Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "Warstwa górna" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "Warstwa dolna" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "Typ przelotki" @@ -34305,24 +33881,24 @@ msgstr "Obrót" msgid "Change Side / Flip" msgstr "Zmień stronę / obróć" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "Przesuń dokładnie" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "Powielono %d pozycji" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "Wybierz punkt odniesienia dla operacji kopiowania..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "Skopiowano zaznaczenie" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "Kopiowanie przerwane" @@ -36545,39 +36121,39 @@ msgstr "Ukryj wszystkie inne klasy sieci" msgid "Presets (Ctrl+Tab):" msgstr "Ustawienia wstępne (Ctrl+Tab):" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "Zapisz ustawienie..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "Usuń ustawienie..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "Nazwa ustawienia warstwy:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "Zapisuje ustawienia warstw" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "Ustawienia wstępne" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "Usuń ustawienie" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "Wybierz ustawienie:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "Otwórz okno ustawień" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." @@ -36887,6 +36463,436 @@ msgstr "Schemat KiCad" msgid "KiCad Printed Circuit Board" msgstr "Obwód drukowany KiCad" +#~ msgid "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('/CLK')`\n" +#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" +#~ msgstr "" +#~ "### Klauzule najwyższego poziomu\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Klauzule warunkowe\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Typy ograniczeń\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Typy elementów\n" +#~ "\n" +#~ "* buried_via\n" +#~ "* graphic\n" +#~ "* hole\n" +#~ "* micro_via\n" +#~ "* pad\n" +#~ "* text\n" +#~ "* track\n" +#~ "* via\n" +#~ "* zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Przykłady\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # szerszy prześwit pomiędzy ścieżkami HV\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Uwagi\n" +#~ "\n" +#~ "Klauzula wersji musi być pierwszą klauzulą. Oznacza ona wersję składni " +#~ "zastosowanej w pliku, \n" +#~ "wobec czego przyszłe parsery będą mogły przeprowadzać automatyczne " +#~ "aktualizacje. Obecnie powinna \n" +#~ "być ustawiona na \"1\".\n" +#~ "\n" +#~ "Reguły powinny być uporządkowane według szczegółowości. Dalsze reguły \n" +#~ "mają pierwszeństwo nad regułami wcześniejszymi; jak tylko odnaleziona \n" +#~ "będzie pasująca reguła dalsze reguły nie będą sprawdzane.\n" +#~ "\n" +#~ "Użyj Ctrl+/ by zakomentować lub odkomentować linię.\n" +#~ "


\n" +#~ "\n" +#~ "### Funkcje wyrażeniowe\n" +#~ "\n" +#~ "Wszystkie parametry funkcji obsługują proste sybmole wieloznaczne (`*` " +#~ "oraz `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "Prawdziwe jeśli dowolna część `A` leży wewnątrz obszaru zajętości " +#~ "podanego footprintu.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "Prawdziwe jeśli dowolna część `A` leży wewnątrz obszaru zajętości " +#~ "podanego footprintu na stronie górnej.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "Prawdziwe jeśli dowolna część `A` leży wewnątrz obszaru zajętości " +#~ "podanego footprintu na stronie dolnej.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "Prawdziwe jeśli dowolna część `A` leży w obrysie podanej strefy.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "Prawdziwe jeśli `A` posiada otwór, który jest metalizowany.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "Prawdziwe jeśli `A` posiada sieć, która jest składnikiem pary " +#~ "różnicowej.\n" +#~ "`` to nazwa bazowa pary różnicowej. Na przykład " +#~ "`inDiffPair('CLK')`\n" +#~ "odnosi się do sieci zarówno `CLK_P` jak i `CLK_N`.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "Prawdziwe jeśli `A` i `B` są członkami tej samej pary różnicowej.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "Prawdziwe jeśli `A` jest członkiem podanej grupy. Nawet zagnieżdżonej w " +#~ "innej grupie.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "Prawdziwe jeśli `A` istnieje na określonej warstwie. Nazwa warstwy może " +#~ "być zarówno\n" +#~ "nazwą przypisaną w oknie dialogowym Ustawienia Płytki > Ustawienia warstw " +#~ "jak też\n" +#~ "jej nazwą kanoniczną (na przykład: `F.Cu`).\n" +#~ "\n" +#~ "UWAGA: Zwraca prawdę, jeśli `A` znajduje się na danej warstwie, \n" +#~ "niezależnie czy reguła jest oceniana dla tej warstwy.\n" +#~ "W tym ostatnim przypadku użyj w regule klauzuli `(layer \"nazwa_warstwy" +#~ "\")`.\n" +#~ "


\n" +#~ "\n" +#~ "### Więcej przykładów\n" +#~ "\n" +#~ " (rule \"blokada strefy\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # zapobiega opisowi na przelotkach\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Odległość między przelotkami różnych sieci\" \n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Prześwit między polami różnych sieci\" \n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Prześwit między otworem a ścieżką\" \n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" +#~ " \n" +#~ " (rule \"Prześwit między polem a ścieżką\" \n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Maksymalny rozmiar otworu mechanicznego\" \n" +#~ " (constraint hole (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ " \n" +#~ " (rule \"Maksymalny rozmiar otworu przewlekanego\" \n" +#~ " (constraint hole (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Określa optymalną przerwę dla konkretnej pary różnicowej\n" +#~ " (rule \"prześwit dp dla lini zegarowej\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" +#~ "\n" +#~ " # Określa większy prześwit wokół dowolnej pary różnicowej\n" +#~ " (rule \"prześwit dp\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" + #, fuzzy, c-format #~ msgid "Unable to locate padstack %s in file %s\n" #~ msgstr "Nie można utworzyć pliku archiwum '%s'.\n" diff --git a/translation/pofiles/pt.po b/translation/pofiles/pt.po index 69ad6c5d00..3e900834c5 100644 --- a/translation/pofiles/pt.po +++ b/translation/pofiles/pt.po @@ -10,7 +10,7 @@ msgid "" msgstr "" "Project-Id-Version: kicad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-07-07 12:47+0000\n" "Last-Translator: leonardokr \n" "Language-Team: Portuguese = 0." msgstr "A espessura do contorno do polígono deve ser >= 0." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Lista de Erros" @@ -27137,17 +27137,17 @@ msgid "Via type:" msgstr "Tipo de Via:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "Através" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "Micro" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Cega/Encoberta" @@ -28644,423 +28644,6 @@ msgstr "Regras do DRC:" msgid "Check rule syntax" msgstr "Verifique a sintaxe da regra" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -#, fuzzy -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('CLK')`\n" -"matches items in the `CLK_P` and `CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\" \n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\" \n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\" \n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" -" \n" -" (rule \"Pad to Track Clearance\" \n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\" \n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -" \n" -" (rule \"Max Drill Hole Size PTH\" \n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "Propriedades padrão para os novos dimensionamentos dos objetos:" @@ -29667,13 +29250,13 @@ msgstr "A verificar as zonas..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29683,7 +29266,7 @@ msgstr "A verificar as zonas..." msgid "(%s clearance %s; actual %s)" msgstr "(%s isolamento %s; atual %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(redes %s e %s)" @@ -31415,7 +30998,7 @@ msgstr "Dissipador de calor" msgid "Castellated" msgstr "Castelado" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Diâmetro" @@ -31754,7 +31337,7 @@ msgstr "Via encoberta (interna)" msgid "Through Via" msgstr "Via Passante" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Furo" @@ -31777,23 +31360,23 @@ msgstr "Pista (arc) %s no %s, comprimento %s" msgid "Track %s on %s, length %s" msgstr "Pista %s no %s, comprimento %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "Origem X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "Origem Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "Camada cima" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "Camada baixo" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "Tipo via" @@ -34343,24 +33926,24 @@ msgstr "Vertical" msgid "Change Side / Flip" msgstr "Altere o lado/vira" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "Mover com exatidão" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "Item(s) %d duplicados" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "Selecione o ponto de referência para a cópia..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "Seleção copiada" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "Cópia cancelada" @@ -36600,39 +36183,39 @@ msgstr "Oculta todas as outras classes da rede" msgid "Presets (Ctrl+Tab):" msgstr "Predefinições (Ctrl+Tab):" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "Salva predefinição..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "Exclui predefinição..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "Nome da predefinição da camada:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "Salva predefinição da camada" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "Predefinições" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "Exclui predefinição" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "Selecione a predefinição:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "Abrir preferências" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." @@ -36941,6 +36524,430 @@ msgstr "Esquema KiCad" msgid "KiCad Printed Circuit Board" msgstr "Placa de circuito impresso KiCad" +#, fuzzy +#~ msgid "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('/CLK')`\n" +#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" +#~ msgstr "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('CLK')`\n" +#~ "matches items in the `CLK_P` and `CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\" \n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\" \n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\" \n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" +#~ " \n" +#~ " (rule \"Pad to Track Clearance\" \n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\" \n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ " \n" +#~ " (rule \"Max Drill Hole Size PTH\" \n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" + #, fuzzy, c-format #~ msgid "Unable to locate padstack %s in file %s\n" #~ msgstr "Não foi possível criar o ficheiro de arquivo zip \"%s\"\n" diff --git a/translation/pofiles/pt_br.po b/translation/pofiles/pt_br.po index ad958e85b9..c549773887 100644 --- a/translation/pofiles/pt_br.po +++ b/translation/pofiles/pt_br.po @@ -10,7 +10,7 @@ msgid "" msgstr "" "Project-Id-Version: kicad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-07-04 20:18+0000\n" "Last-Translator: Wellington Terumi Uemura \n" "Language-Team: Portuguese (Brazil) = 0." msgstr "A espessura do contorno do polígono deve ser >= 0." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Lista de erros" @@ -27192,17 +27192,17 @@ msgid "Via type:" msgstr "Tipo da via:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "Através" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "Micro" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Cega/Encoberta" @@ -28698,430 +28698,6 @@ msgstr "Regras do DRC:" msgid "Check rule syntax" msgstr "Verifique a sintaxe da regra" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" -"### Cláusulas de nível superior\n" -"\n" -" (versão )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Cláusulas da regra\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Tipos de restrição\n" -"\n" -" * annular\\_width\n" -" * isolamento\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * desaprovar\n" -" * edge\\_clearance\n" -" * comprimento\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * desvio\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Os tipos dos itens\n" -"\n" -" * buried_via\n" -" * gráfico\n" -" * furo\n" -" * micro_via\n" -" * ilha\n" -" * texto\n" -" * trilha\n" -" * via\n" -" * região\n" -"\n" -"
\n" -"\n" -"### Examplos\n" -"\n" -" (versão 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notas\n" -"\n" -"A versão da cláusula deve ser a primeira cláusula. Indica a versão da " -"sintaxe do arquivo para que\n" -"os futuros analisadores das regras possam realizar atualizações " -"automáticas. Deveria ser\n" -"definido como \"1\".\n" -"\n" -"As regras devem ser ordenadas por especificidade. Regras posteriores tomam\n" -"precedência sobre as regras anteriores; assim que uma regra correspondente " -"for encontrada\n" -"nenhuma regra adicional será verificada.\n" -"\n" -"Use Ctrl+/ para comentar ou remover o comantário da(s) linha(s).\n" -"


\n" -"\n" -"### Funções da expressão\n" -"\n" -"Todos os parâmetros de função suportam curingas simples (`*` e `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"Verdadeiro caso qualquer parte de `A` esteja dentro do pedaço principal do " -"footprint do componente informado.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"Verdadeiro caso qualquer parte de `A` esteja dentro do pedaço frontal do " -"footprint do componente informado.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"Verdadeiro caso qualquer parte de `A` esteja dentro do pedaço traseiro do " -"footprint do componente informado.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"Verdadeiro caso qualquer parte de `A` esteja dentro do contorno da zona " -"informada.\n" -"

\n" -"\n" -" A.isPlated()\n" -"Verdadeiro caso `A` tenha um furo que seja metalizado.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"Verdadeiro caso `A` tenha uma rede que faça parte do par diferencial " -"informado.\n" -"`` é a base do nome do par diferencial. Por exemplo, " -"`inDiffPair('CLK')`\n" -"corresponde aos itens dentro do `/CLK_P` e nas redes `/CLK_N`.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"Verdadeiro caso `A` e `B` sejam membros do mesmo par de diferencial.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"Verdadeiro caso `A` seja um membro de um determinado grupo. Inclui " -"associações aninhadas.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"Verdadeiro caso `A` exista na camada informada. O nome da camada pode ser\n" -"o nome atribuído na Configuração da placa > Camadas do editor da placa ou\n" -"o nome canônico (ou seja: `F.Cu`).\n" -"\n" -"Nota: isto retorna verdadeiro caso `A` esteja em determinada camada, " -"independentemente\n" -"da avaliação ou não da regra para essa camada.\n" -"Para o último, use uma cláusula `(layer \"nome_da_camada\")` na regra.\n" -"


\n" -"\n" -"### Mais exemplos\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # previne a serigrafia nas vias cobertas\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\" \n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Espaço entre as ilhas nas diferentes redes\" \n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (regra \"Através do furo para rastrear o isolamento\" \n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -" \n" -" (regra \"Ilha para rastrear o isolamento\" \n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (regra \"isolamento para o recorte de 1 mm\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Tamanho máximo do furo com perfuração mecânica\" \n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (regra \"Tamanho máximo da perfuração do furo PTH\" \n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Determina uma lacuna ideal para um par diferencial particular\n" -" (rule \"lacuna do relógio dp\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Especifica um isolamento maior em torno de qualquer par de diferenças\n" -" (regra \"isolamento dp\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "Propriedades padrão para os novos dimensionamentos dos objetos:" @@ -29724,13 +29300,13 @@ msgstr "Verificando as zonas..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29740,7 +29316,7 @@ msgstr "Verificando as zonas..." msgid "(%s clearance %s; actual %s)" msgstr "(%s isolamento %s; atual %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(redes %s e %s)" @@ -31474,7 +31050,7 @@ msgstr "Dissipador de calor" msgid "Castellated" msgstr "Castelado" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Diâmetro" @@ -31812,7 +31388,7 @@ msgstr "Via encoberta (interna)" msgid "Through Via" msgstr "Via passante" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Furo" @@ -31835,23 +31411,23 @@ msgstr "Trilha (arc) %s no %s, comprimento %s" msgid "Track %s on %s, length %s" msgstr "Trilha %s no %s, comprimento %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "Origem X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "Origem Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "Camada cima" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "Camada baixo" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "Tipo via" @@ -34397,24 +33973,24 @@ msgstr "Rotacione" msgid "Change Side / Flip" msgstr "Altere o lado/vira" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "Move com exatidão" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "%d Item(s) duplicados" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "Selecione o ponto de referência para a cópia..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "Seleção copiada" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "Cópia cancelada" @@ -36659,39 +36235,39 @@ msgstr "Oculta todas as outras classes da rede" msgid "Presets (Ctrl+Tab):" msgstr "Predefinições (Ctrl+Tab):" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "Salva predefinição..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "Exclui predefinição..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "Nome da predefinição da camada:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "Salva predefinição da camada" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "Predefinições" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "Exclui predefinição" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "Selecione a predefinição:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "Abrir preferências" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." @@ -37001,6 +36577,439 @@ msgstr "Esquema KiCad" msgid "KiCad Printed Circuit Board" msgstr "Placa de circuito impresso KiCad" +#~ msgid "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('/CLK')`\n" +#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" +#~ msgstr "" +#~ "### Cláusulas de nível superior\n" +#~ "\n" +#~ " (versão )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Cláusulas da regra\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Tipos de restrição\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * isolamento\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * desaprovar\n" +#~ " * edge\\_clearance\n" +#~ " * comprimento\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * desvio\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Os tipos dos itens\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * gráfico\n" +#~ " * furo\n" +#~ " * micro_via\n" +#~ " * ilha\n" +#~ " * texto\n" +#~ " * trilha\n" +#~ " * via\n" +#~ " * região\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examplos\n" +#~ "\n" +#~ " (versão 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notas\n" +#~ "\n" +#~ "A versão da cláusula deve ser a primeira cláusula. Indica a versão da " +#~ "sintaxe do arquivo para que\n" +#~ "os futuros analisadores das regras possam realizar atualizações " +#~ "automáticas. Deveria ser\n" +#~ "definido como \"1\".\n" +#~ "\n" +#~ "As regras devem ser ordenadas por especificidade. Regras posteriores " +#~ "tomam\n" +#~ "precedência sobre as regras anteriores; assim que uma regra " +#~ "correspondente for encontrada\n" +#~ "nenhuma regra adicional será verificada.\n" +#~ "\n" +#~ "Use Ctrl+/ para comentar ou remover o comantário da(s) linha(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Funções da expressão\n" +#~ "\n" +#~ "Todos os parâmetros de função suportam curingas simples (`*` e `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "Verdadeiro caso qualquer parte de `A` esteja dentro do pedaço principal " +#~ "do footprint do componente informado.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "Verdadeiro caso qualquer parte de `A` esteja dentro do pedaço frontal do " +#~ "footprint do componente informado.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "Verdadeiro caso qualquer parte de `A` esteja dentro do pedaço traseiro do " +#~ "footprint do componente informado.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "Verdadeiro caso qualquer parte de `A` esteja dentro do contorno da zona " +#~ "informada.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "Verdadeiro caso `A` tenha um furo que seja metalizado.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "Verdadeiro caso `A` tenha uma rede que faça parte do par diferencial " +#~ "informado.\n" +#~ "`` é a base do nome do par diferencial. Por exemplo, " +#~ "`inDiffPair('CLK')`\n" +#~ "corresponde aos itens dentro do `/CLK_P` e nas redes `/CLK_N`.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "Verdadeiro caso `A` e `B` sejam membros do mesmo par de diferencial.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "Verdadeiro caso `A` seja um membro de um determinado grupo. Inclui " +#~ "associações aninhadas.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "Verdadeiro caso `A` exista na camada informada. O nome da camada pode " +#~ "ser\n" +#~ "o nome atribuído na Configuração da placa > Camadas do editor da placa " +#~ "ou\n" +#~ "o nome canônico (ou seja: `F.Cu`).\n" +#~ "\n" +#~ "Nota: isto retorna verdadeiro caso `A` esteja em determinada camada, " +#~ "independentemente\n" +#~ "da avaliação ou não da regra para essa camada.\n" +#~ "Para o último, use uma cláusula `(layer \"nome_da_camada\")` na regra.\n" +#~ "


\n" +#~ "\n" +#~ "### Mais exemplos\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # previne a serigrafia nas vias cobertas\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\" \n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Espaço entre as ilhas nas diferentes redes\" \n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (regra \"Através do furo para rastrear o isolamento\" \n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ " \n" +#~ " (regra \"Ilha para rastrear o isolamento\" \n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (regra \"isolamento para o recorte de 1 mm\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Tamanho máximo do furo com perfuração mecânica\" \n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (regra \"Tamanho máximo da perfuração do furo PTH\" \n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Determina uma lacuna ideal para um par diferencial particular\n" +#~ " (rule \"lacuna do relógio dp\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Especifica um isolamento maior em torno de qualquer par de " +#~ "diferenças\n" +#~ " (regra \"isolamento dp\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" + #, fuzzy, c-format #~ msgid "Unable to locate padstack %s in file %s\n" #~ msgstr "Não foi possível criar o ficheiro de arquivo zip \"%s\"\n" diff --git a/translation/pofiles/ro.po b/translation/pofiles/ro.po index bcfcf02383..928d9c9bcf 100644 --- a/translation/pofiles/ro.po +++ b/translation/pofiles/ro.po @@ -4,7 +4,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-05-15 11:56+0000\n" "Last-Translator: Alex Gellen \n" "Language-Team: Romanian \n" @@ -4259,7 +4259,7 @@ msgid "Shape" msgstr "Formă" #: common/eda_shape.cpp:574 common/eda_shape.cpp:584 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:181 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:173 #: pcbnew/pcb_track.cpp:686 msgid "Radius" msgstr "Rază" @@ -4293,8 +4293,8 @@ msgstr "Puncte" #: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:155 #: pcbnew/fp_text.cpp:305 pcbnew/fp_text_grid_table.cpp:105 pcbnew/pad.cpp:1008 #: pcbnew/pcb_target.cpp:158 pcbnew/pcb_target.cpp:204 pcbnew/pcb_text.cpp:127 -#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1132 pcbnew/pcb_track.cpp:1149 -#: pcbnew/pcb_track.cpp:1168 +#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1127 pcbnew/pcb_track.cpp:1144 +#: pcbnew/pcb_track.cpp:1163 msgid "Width" msgstr "Lățime" @@ -4342,13 +4342,13 @@ msgstr "Începe X" msgid "Start Y" msgstr "Începe Y" -#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1140 -#: pcbnew/pcb_track.cpp:1157 +#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1135 +#: pcbnew/pcb_track.cpp:1152 msgid "End X" msgstr "Termină X" -#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1142 -#: pcbnew/pcb_track.cpp:1159 +#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1137 +#: pcbnew/pcb_track.cpp:1154 msgid "End Y" msgstr "Termină Y" @@ -4434,7 +4434,7 @@ msgstr "Stânga" #: pagelayout_editor/dialogs/properties_frame_base.cpp:89 #: pagelayout_editor/dialogs/properties_frame_base.cpp:105 #: pcbnew/dialogs/dialog_dimension_properties_base.cpp:315 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:179 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:171 #: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:117 #: pcbnew/dialogs/dialog_text_properties_base.cpp:145 msgid "Center" @@ -4724,7 +4724,7 @@ msgstr "Nu se poate copia fișierul '%s'." #: common/grid_tricks.cpp:278 common/tool/actions.cpp:153 #: eeschema/tools/ee_actions.cpp:148 pcbnew/dialogs/panel_setup_rules.cpp:112 -#: pcbnew/tools/edit_tool.cpp:2011 +#: pcbnew/tools/edit_tool.cpp:2016 msgid "Cut" msgstr "Decupează" @@ -4752,7 +4752,7 @@ msgstr "Lipiți celulele din mapă la matricea celulelor curentă" #: common/grid_tricks.cpp:284 common/tool/actions.cpp:191 #: kicad/project_tree_pane.cpp:771 pcbnew/dialogs/panel_setup_rules.cpp:115 -#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2013 +#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2018 msgid "Delete" msgstr "Ștergeți" @@ -5339,8 +5339,8 @@ msgid "Invalid size %lld: too large" msgstr "Dimensiune nevalabilă %lld: prea mare" #: common/plugins/eagle/eagle_parser.cpp:281 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:373 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:389 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:366 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:382 #, c-format msgid "Invalid Arc with radius %f and angle %f" msgstr "Arc nevalabil cu raza %f și unghiul %f" @@ -16727,7 +16727,7 @@ msgstr "" #: pcbnew/fp_text_grid_table.cpp:109 pcbnew/pad.cpp:980 #: pcbnew/pcb_dimension.cpp:353 pcbnew/pcb_dimension.cpp:1087 #: pcbnew/pcb_shape.cpp:159 pcbnew/pcb_target.cpp:155 pcbnew/pcb_text.cpp:120 -#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1173 +#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1168 #: pcbnew/tools/board_inspection_tool.cpp:238 #: pcbnew/tools/board_inspection_tool.cpp:385 #: pcbnew/tools/board_inspection_tool.cpp:461 @@ -20639,13 +20639,13 @@ msgstr "" msgid "no layers" msgstr "" -#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1134 -#: pcbnew/pcb_track.cpp:1151 +#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1129 +#: pcbnew/pcb_track.cpp:1146 msgid "Position X" msgstr "" -#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1137 -#: pcbnew/pcb_track.cpp:1154 +#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1132 +#: pcbnew/pcb_track.cpp:1149 msgid "Position Y" msgstr "" @@ -24274,55 +24274,55 @@ msgstr "" msgid "Error loading footprint library table." msgstr "Eroare la încărcarea tabelului bibliotecii de amprentă." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:178 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:170 msgid "Circle Properties" msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:191 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:183 msgid "Arc Properties" msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:197 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:189 msgid "Polygon Properties" msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:203 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:195 msgid "Rectangle Properties" msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:209 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:201 msgid "Line Segment Properties" msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:343 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:336 msgid "Modify drawing properties" msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:368 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:361 msgid "The arc angle cannot be zero." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:415 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:427 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:433 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:388 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:398 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:408 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:420 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:426 msgid "The item thickness must be greater than zero." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:402 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 msgid "The radius must be greater than zero." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:412 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 msgid "The rectangle cannot be empty." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:421 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:414 msgid "The polygon outline thickness must be >= 0." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "" @@ -26391,17 +26391,17 @@ msgid "Via type:" msgstr "" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "Prin" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "Micro" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Orb/îngropat" @@ -27798,435 +27798,6 @@ msgstr "" msgid "Check rule syntax" msgstr "" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -#, fuzzy -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" -"### Clauze de nivel superior\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Clauze de regulă\n" -"\n" -" (constraint ...)\n" -"\n" -" (condiție \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Tipuri de constrângeri\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diametru\n" -"\n" -"\n" -"

\n" -"\n" -"### Tipuri de articole\n" -"\n" -" * buried_via\n" -" * grafic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Exemple\n" -"\n" -" (versiunea 1)\n" -"\n" -" (regula HV\n" -" (constrângere spațiu liber (min 1,5 mm))\n" -" (condiție \"A.NetClass == 'HV'\")))\n" -"\n" -"\n" -" (regulă HV\n" -" (strat exterior)\n" -" (constrângere clearance (min 1,5 mm))\n" -" (condiție \"A.NetClass == 'HV'\")))\n" -"\n" -"\n" -" (regula HV_HV\n" -" # spațiu liber mai mare între liniile HV\n" -" (constraint clearance (min \"1.5mm + 2.0mm\")))\n" -" (condiție \"A.NetClass == 'HV' && B.NetClass == 'HV'\")))\n" -"\n" -"\n" -" (regula HV_unshielded\n" -" (constrângere clearance (min 2mm))\n" -" (condiție \"A.NetClass == 'HV' && ! A.insideArea('Shield*')\")))\n" -"

\n" -"\n" -"### Note\n" -"\n" -"Clauza Version trebuie să fie prima clauză. Aceasta indică versiunea de " -"sintaxă a fișierului, astfel încât\n" -"viitoarele analizoare de reguli să poată efectua actualizări automate. Ar " -"trebui să fie\n" -"setată la \"1\".\n" -"\n" -"Regulile ar trebui să fie ordonate în funcție de specificitate. Regulile " -"ulterioare iau\n" -"prioritate față de regulile anterioare; odată ce se găsește o regulă " -"corespunzătoare\n" -"nu se verifică alte reguli.\n" -"\n" -"Folosiți Ctrl+/ pentru a comenta sau decomenta linia (liniile).\n" -"


\n" -"\n" -"### Funcții de expresie\n" -"\n" -"Toți parametrii funcțiilor suportă wildcards simple (`*` și `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"Adevărat dacă orice parte din `A` se află în interiorul curții principale a " -"amprentei date's.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"Adevărat dacă orice parte a lui `A` se află în interiorul curții frontale a " -"amprentei date's.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"Adevărat dacă orice parte a lui `A` se află în interiorul curții din spate a " -"amprentei date's.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"Adevărat dacă orice parte din `A` se află în interiorul conturului zonei's " -"date.\n" -"

\n" -"\n" -" A.isPlated()\n" -"Adevărat dacă `A` are o gaură care este placată.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"Adevărat dacă `A` are o rețea care face parte din perechea diferențială " -"specificată.\n" -"`` este numele de bază al perechii diferențiale. De exemplu, " -"`inDiffPair('/CLK')`.\n" -"se potrivește cu elementele din rețelele `/CLK_P` și `/CLK_N`.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"Adevărat dacă `A` și `B` sunt membri ai aceleiași perechi dif.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"Adevărat dacă `A` este un membru al grupului dat. Include apartenența " -"imbricata.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"Adevărat dacă `A` există pe stratul dat. Numele stratului poate fi\n" -"fie numele atribuit în Board Setup > Board Editor Layers sau\n" -"numele canonic (de exemplu: `F.Cu`).\n" -"\n" -"NB: acest lucru returnează adevărat dacă `A` există pe stratul dat, " -"independent\n" -"indiferent dacă regula este sau nu evaluată pentru acel strat.\n" -"Pentru aceasta din urmă, utilizați o clauză `(layer \"layer_name\")` în " -"regulă.\n" -"


\n" -"\n" -"### Mai multe exemple\n" -"\n" -" (regula \"copper keepout\"\n" -" (constrângere disallow track via zone)\n" -" (condiție \"A.insideArea('zone3')\")))\n" -"\n" -"\n" -" (regula \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm)))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\")))\n" -"\n" -"\n" -" # previne ca mătasea să nu treacă peste pasajele de tip \"tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\")))\n" -"\n" -"\n" -" (regula \"Distanța dintre Vias de rețele diferite\"\n" -" (constrângere gaură_la_gaură (min 0,254mm))\n" -" (condiție \"A.Type =='Via' && B.Type =='Via' && A.Net ! = B.Net\"))\n" -"\n" -" (regula \"Clearance between Pads of Different Nets\"\n" -" (constrângere spațiu liber (min. 3,0 mm))\n" -" (condiție \"A.Type =='Pad' && B.Type =='Pad' && A.Net ! = B.Net" -"\")))\n" -"\n" -"\n" -" (regula \"Via Hole to Track Clearance\"\n" -" (constrângerea hole_clearance (min 0.254mm))\n" -" (condition \"A.Type = 'Via' && B.Type == 'Track'\")))\n" -"\n" -" (regula \"Pad to Track Clearance\"\n" -" (constrângere degajare (min. 0,2 mm))\n" -" (condiție \"A.Type =='Pad' && B.Type =='Track'\")))\n" -"\n" -"\n" -" (regula \"clearance-to-1mm-cutout\"\n" -" (constrângere clearance (min 0,8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\")))\n" -"\n" -"\n" -" (regula \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condiție \"A.Pad_Type == 'NPTH, mechanical'\")))\n" -"\n" -" (regula \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\")))\n" -"\n" -"\n" -" # Specifică o distanță optimă pentru o anumită pereche de perechi de " -"diferețe\n" -" (regula \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\")))\n" -" (condiție \"A.inDiffPair('/CLK')\")))\n" -"\n" -" # Specificați un joc mai mare în jurul oricărei perechi de diferențiale\n" -" (regula \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condiție \"A.inDiffPair('*') &&! AB.isCoupledDiffPair()\")))\n" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "" @@ -28832,13 +28403,13 @@ msgstr "" #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -28848,7 +28419,7 @@ msgstr "" msgid "(%s clearance %s; actual %s)" msgstr "" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "" @@ -30515,7 +30086,7 @@ msgstr "" msgid "Castellated" msgstr "" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Diametru" @@ -30852,7 +30423,7 @@ msgstr "" msgid "Through Via" msgstr "" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Foraj" @@ -30875,23 +30446,23 @@ msgstr "" msgid "Track %s on %s, length %s" msgstr "" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "" @@ -33261,24 +32832,24 @@ msgstr "Rotiți" msgid "Change Side / Flip" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "" -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 #, fuzzy msgid "Copy canceled" msgstr "Anulați" @@ -35495,39 +35066,39 @@ msgstr "Ascundeți toate celelalte netclasses" msgid "Presets (Ctrl+Tab):" msgstr "Prestabilite (Ctrl+Tab)" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "Presetări" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." @@ -35832,6 +35403,441 @@ msgstr "Schematică KiCad" msgid "KiCad Printed Circuit Board" msgstr "Placă de circuite imprimate KiCad" +#, fuzzy +#~ msgid "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('/CLK')`\n" +#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" +#~ msgstr "" +#~ "### Clauze de nivel superior\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Clauze de regulă\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condiție \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Tipuri de constrângeri\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diametru\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Tipuri de articole\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * grafic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Exemple\n" +#~ "\n" +#~ " (versiunea 1)\n" +#~ "\n" +#~ " (regula HV\n" +#~ " (constrângere spațiu liber (min 1,5 mm))\n" +#~ " (condiție \"A.NetClass == 'HV'\")))\n" +#~ "\n" +#~ "\n" +#~ " (regulă HV\n" +#~ " (strat exterior)\n" +#~ " (constrângere clearance (min 1,5 mm))\n" +#~ " (condiție \"A.NetClass == 'HV'\")))\n" +#~ "\n" +#~ "\n" +#~ " (regula HV_HV\n" +#~ " # spațiu liber mai mare între liniile HV\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\")))\n" +#~ " (condiție \"A.NetClass == 'HV' && B.NetClass == 'HV'\")))\n" +#~ "\n" +#~ "\n" +#~ " (regula HV_unshielded\n" +#~ " (constrângere clearance (min 2mm))\n" +#~ " (condiție \"A.NetClass == 'HV' && ! A.insideArea('Shield*')\")))\n" +#~ "

\n" +#~ "\n" +#~ "### Note\n" +#~ "\n" +#~ "Clauza Version trebuie să fie prima clauză. Aceasta indică versiunea de " +#~ "sintaxă a fișierului, astfel încât\n" +#~ "viitoarele analizoare de reguli să poată efectua actualizări automate. " +#~ "Ar trebui să fie\n" +#~ "setată la \"1\".\n" +#~ "\n" +#~ "Regulile ar trebui să fie ordonate în funcție de specificitate. Regulile " +#~ "ulterioare iau\n" +#~ "prioritate față de regulile anterioare; odată ce se găsește o regulă " +#~ "corespunzătoare\n" +#~ "nu se verifică alte reguli.\n" +#~ "\n" +#~ "Folosiți Ctrl+/ pentru a comenta sau decomenta linia (liniile).\n" +#~ "


\n" +#~ "\n" +#~ "### Funcții de expresie\n" +#~ "\n" +#~ "Toți parametrii funcțiilor suportă wildcards simple (`*` și `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "Adevărat dacă orice parte din `A` se află în interiorul curții principale " +#~ "a amprentei date's.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "Adevărat dacă orice parte a lui `A` se află în interiorul curții frontale " +#~ "a amprentei date's.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "Adevărat dacă orice parte a lui `A` se află în interiorul curții din " +#~ "spate a amprentei date's.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "Adevărat dacă orice parte din `A` se află în interiorul conturului " +#~ "zonei's date.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "Adevărat dacă `A` are o gaură care este placată.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "Adevărat dacă `A` are o rețea care face parte din perechea diferențială " +#~ "specificată.\n" +#~ "`` este numele de bază al perechii diferențiale. De exemplu, " +#~ "`inDiffPair('/CLK')`.\n" +#~ "se potrivește cu elementele din rețelele `/CLK_P` și `/CLK_N`.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "Adevărat dacă `A` și `B` sunt membri ai aceleiași perechi dif.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "Adevărat dacă `A` este un membru al grupului dat. Include apartenența " +#~ "imbricata.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "Adevărat dacă `A` există pe stratul dat. Numele stratului poate fi\n" +#~ "fie numele atribuit în Board Setup > Board Editor Layers sau\n" +#~ "numele canonic (de exemplu: `F.Cu`).\n" +#~ "\n" +#~ "NB: acest lucru returnează adevărat dacă `A` există pe stratul dat, " +#~ "independent\n" +#~ "indiferent dacă regula este sau nu evaluată pentru acel strat.\n" +#~ "Pentru aceasta din urmă, utilizați o clauză `(layer \"layer_name\")` în " +#~ "regulă.\n" +#~ "


\n" +#~ "\n" +#~ "### Mai multe exemple\n" +#~ "\n" +#~ " (regula \"copper keepout\"\n" +#~ " (constrângere disallow track via zone)\n" +#~ " (condiție \"A.insideArea('zone3')\")))\n" +#~ "\n" +#~ "\n" +#~ " (regula \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm)))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\")))\n" +#~ "\n" +#~ "\n" +#~ " # previne ca mătasea să nu treacă peste pasajele de tip \"tented " +#~ "vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\")))\n" +#~ "\n" +#~ "\n" +#~ " (regula \"Distanța dintre Vias de rețele diferite\"\n" +#~ " (constrângere gaură_la_gaură (min 0,254mm))\n" +#~ " (condiție \"A.Type =='Via' && B.Type =='Via' && A.Net ! = B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (regula \"Clearance between Pads of Different Nets\"\n" +#~ " (constrângere spațiu liber (min. 3,0 mm))\n" +#~ " (condiție \"A.Type =='Pad' && B.Type =='Pad' && A.Net ! = B.Net" +#~ "\")))\n" +#~ "\n" +#~ "\n" +#~ " (regula \"Via Hole to Track Clearance\"\n" +#~ " (constrângerea hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type = 'Via' && B.Type == 'Track'\")))\n" +#~ "\n" +#~ " (regula \"Pad to Track Clearance\"\n" +#~ " (constrângere degajare (min. 0,2 mm))\n" +#~ " (condiție \"A.Type =='Pad' && B.Type =='Track'\")))\n" +#~ "\n" +#~ "\n" +#~ " (regula \"clearance-to-1mm-cutout\"\n" +#~ " (constrângere clearance (min 0,8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\")))\n" +#~ "\n" +#~ "\n" +#~ " (regula \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condiție \"A.Pad_Type == 'NPTH, mechanical'\")))\n" +#~ "\n" +#~ " (regula \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\")))\n" +#~ "\n" +#~ "\n" +#~ " # Specifică o distanță optimă pentru o anumită pereche de perechi de " +#~ "diferețe\n" +#~ " (regula \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\")))\n" +#~ " (condiție \"A.inDiffPair('/CLK')\")))\n" +#~ "\n" +#~ " # Specificați un joc mai mare în jurul oricărei perechi de " +#~ "diferențiale\n" +#~ " (regula \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condiție \"A.inDiffPair('*') &&! AB.isCoupledDiffPair()\")))\n" + #, fuzzy, c-format #~ msgid "Unable to locate padstack %s in file %s\n" #~ msgstr "Nu se poate crea fișierul de arhivă \"%s\"\n" diff --git a/translation/pofiles/ru.po b/translation/pofiles/ru.po index a734ad9d2d..d982a04538 100644 --- a/translation/pofiles/ru.po +++ b/translation/pofiles/ru.po @@ -9,7 +9,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-08-28 17:17+0000\n" "Last-Translator: Konstantin Baranovskiy \n" "Language-Team: Russian \n" @@ -4247,7 +4247,7 @@ msgid "Shape" msgstr "Форма" #: common/eda_shape.cpp:574 common/eda_shape.cpp:584 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:181 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:173 #: pcbnew/pcb_track.cpp:686 msgid "Radius" msgstr "Радиус" @@ -4281,8 +4281,8 @@ msgstr "Точки" #: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:155 #: pcbnew/fp_text.cpp:305 pcbnew/fp_text_grid_table.cpp:105 pcbnew/pad.cpp:1008 #: pcbnew/pcb_target.cpp:158 pcbnew/pcb_target.cpp:204 pcbnew/pcb_text.cpp:127 -#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1132 pcbnew/pcb_track.cpp:1149 -#: pcbnew/pcb_track.cpp:1168 +#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1127 pcbnew/pcb_track.cpp:1144 +#: pcbnew/pcb_track.cpp:1163 msgid "Width" msgstr "Ширина" @@ -4330,13 +4330,13 @@ msgstr "Начало X" msgid "Start Y" msgstr "Начало Y" -#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1140 -#: pcbnew/pcb_track.cpp:1157 +#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1135 +#: pcbnew/pcb_track.cpp:1152 msgid "End X" msgstr "Конец X" -#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1142 -#: pcbnew/pcb_track.cpp:1159 +#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1137 +#: pcbnew/pcb_track.cpp:1154 msgid "End Y" msgstr "Конец Y" @@ -4422,7 +4422,7 @@ msgstr "Влево" #: pagelayout_editor/dialogs/properties_frame_base.cpp:89 #: pagelayout_editor/dialogs/properties_frame_base.cpp:105 #: pcbnew/dialogs/dialog_dimension_properties_base.cpp:315 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:179 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:171 #: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:117 #: pcbnew/dialogs/dialog_text_properties_base.cpp:145 msgid "Center" @@ -4704,7 +4704,7 @@ msgstr "Не удалось скопировать файл '%s'." #: common/grid_tricks.cpp:278 common/tool/actions.cpp:153 #: eeschema/tools/ee_actions.cpp:148 pcbnew/dialogs/panel_setup_rules.cpp:112 -#: pcbnew/tools/edit_tool.cpp:2011 +#: pcbnew/tools/edit_tool.cpp:2016 msgid "Cut" msgstr "Вырезать" @@ -4733,7 +4733,7 @@ msgstr "Вставить элементы из буфера обмена в те #: common/grid_tricks.cpp:284 common/tool/actions.cpp:191 #: kicad/project_tree_pane.cpp:771 pcbnew/dialogs/panel_setup_rules.cpp:115 -#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2013 +#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2018 msgid "Delete" msgstr "Удалить" @@ -5313,8 +5313,8 @@ msgid "Invalid size %lld: too large" msgstr "Неверный размер %lld: слишком большой" #: common/plugins/eagle/eagle_parser.cpp:281 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:373 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:389 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:366 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:382 #, c-format msgid "Invalid Arc with radius %f and angle %f" msgstr "Неверная дуга с радиусом %f и углом %f" @@ -16918,7 +16918,7 @@ msgstr "Выбор слоя: %s" #: pcbnew/fp_text_grid_table.cpp:109 pcbnew/pad.cpp:980 #: pcbnew/pcb_dimension.cpp:353 pcbnew/pcb_dimension.cpp:1087 #: pcbnew/pcb_shape.cpp:159 pcbnew/pcb_target.cpp:155 pcbnew/pcb_text.cpp:120 -#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1173 +#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1168 #: pcbnew/tools/board_inspection_tool.cpp:238 #: pcbnew/tools/board_inspection_tool.cpp:385 #: pcbnew/tools/board_inspection_tool.cpp:461 @@ -20897,13 +20897,13 @@ msgstr "и прочие" msgid "no layers" msgstr "без слоёв" -#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1134 -#: pcbnew/pcb_track.cpp:1151 +#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1129 +#: pcbnew/pcb_track.cpp:1146 msgid "Position X" msgstr "Позиция X" -#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1137 -#: pcbnew/pcb_track.cpp:1154 +#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1132 +#: pcbnew/pcb_track.cpp:1149 msgid "Position Y" msgstr "Позиция Y" @@ -24747,55 +24747,55 @@ msgstr "" msgid "Error loading footprint library table." msgstr "Ошибка загрузки таблицы библиотек посад.мест." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:178 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:170 msgid "Circle Properties" msgstr "Свойства окружности" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:191 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:183 msgid "Arc Properties" msgstr "Свойства дуги" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:197 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:189 msgid "Polygon Properties" msgstr "Свойства полигона" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:203 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:195 msgid "Rectangle Properties" msgstr "Свойства прямоугольника" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:209 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:201 msgid "Line Segment Properties" msgstr "Свойства сегмента линии" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:343 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:336 msgid "Modify drawing properties" msgstr "Изменение свойств рисунка" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:368 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:361 msgid "The arc angle cannot be zero." msgstr "Угол дуги не может быть нулевым." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:415 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:427 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:433 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:388 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:398 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:408 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:420 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:426 msgid "The item thickness must be greater than zero." msgstr "Толщина элемента должна быть больше нуля." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:402 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 msgid "The radius must be greater than zero." msgstr "Радиус должен быть больше нуля." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:412 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 msgid "The rectangle cannot be empty." msgstr "Прямоугольник не может быть пустым." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:421 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:414 msgid "The polygon outline thickness must be >= 0." msgstr "Толщина контура полигона должна быть >= 0." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Список ошибок" @@ -26982,17 +26982,17 @@ msgid "Via type:" msgstr "Тип перех.отв.:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "Сквозное" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "Микро" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Глухое/внутр." @@ -28480,427 +28480,6 @@ msgstr "Правила проектирования DRC:" msgid "Check rule syntax" msgstr "Проверить синтаксис правил" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" -"### Определения верхнего уровня\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Определения правил\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Типы ограничений\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Типы элементов\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Примеры\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # больший зазор между высоковольтными дорожками\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Примечания\n" -"\n" -"Определение версии должно быть первым. Этим обозначается версия синтаксиса " -"файла, так что\n" -"будущие подпрограммы разбора правил смогут применять автоматическое " -"обновление. Её следует\n" -"устанавливать равной \"1\".\n" -"\n" -"Правила должны следовать в определённом порядке. Более поздние правила\n" -"имеют преимущество над более ранними.\n" -"Как только подходящее правило найдено, остальные правила не проверяются.\n" -"\n" -"Используйте Ctrl+/ для комментирования строк.\n" -"


\n" -"\n" -"### Функции\n" -"\n" -"Параметры всех функций поддерживают простые шаблоны (`*` и `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('<обозначения_посад.мест>')\n" -"Истина если любая часть `A` лежит в главной области установки указанных " -"посад.мест.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('<обозначения_посад.мест>')\n" -"Истина если любая часть `A` лежит в области установки указанных посад.мест. " -"сверху.\n" -"

\n" -"\n" -" A.insideBackCourtyard('<обозначения_посад.мест>')\n" -"Истина если любая часть `A` лежит в области установки указанных посад.мест. " -"снизу.\n" -"

\n" -"\n" -" A.insideArea('<имя_зоны>')\n" -"Истина если любая часть `A` лежит внутри контура указанной зоны.\n" -"

\n" -"\n" -" A.isPlated()\n" -"Истина если `A` имеет металлизированные отверстия.\n" -"

\n" -"\n" -" A.inDiffPair('<имя_цепи>')\n" -"Истина если `A` имеет цепь, которая является частью указанной диф.пары.\n" -"`<имя_цепи>` - это база имени диф.пары. Например, `inDiffPair('CLK')`\n" -"соответствует цепям `CLK_P` и `CLK_N`.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"Истина если `A` и `B` являются членами одной диф.пары.\n" -"

\n" -"\n" -" A.memberOf('<имя_группы>')\n" -"Истина если `A` является членом указанной группы (включая вложенные " -"группы).\n" -"

\n" -"\n" -" A.existsOnLayer('<имя_слоя>')\n" -"Истина если `A` существует на указанном слое. Имя слоя может быть как\n" -"наименованием, указанным в Параметры платы > Слои редактора, так и\n" -"стандартным именем (например, `F.Cu`).\n" -"\n" -"Обратите внимание: эта функция вернёт истину если `A` лежит на указанном " -"слое,\n" -"независимо от того может ли правило быть применено к этому слою.\n" -"В таком случае лучше использовать определение `(layer \"имя_слоя\")` для " -"правила.\n" -"


\n" -"\n" -"### Ещё примеры\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # исключить шёлкографию из перех.отв. покрытых паяльной маской\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -" \n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -" \n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Задать особый зазор для отдельной диф.пары\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Задать больший зазор между слоями меди и всеми диф.парами\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "По умолчанию для новых размерных линий:" @@ -29499,13 +29078,13 @@ msgstr "Проверка зон..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29515,7 +29094,7 @@ msgstr "Проверка зон..." msgid "(%s clearance %s; actual %s)" msgstr "(%s зазор %s; текущий %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(цепи %s и %s)" @@ -31230,7 +30809,7 @@ msgstr "Для отвода тепла" msgid "Castellated" msgstr "Периферийное полу-отверстие" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Диаметр" @@ -31569,7 +31148,7 @@ msgstr "Глухие/внутр. перех.отв." msgid "Through Via" msgstr "Сквозное перех.отв." -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Сверло" @@ -31592,23 +31171,23 @@ msgstr "Дорожка (дуга) %s на %s, длина %s" msgid "Track %s on %s, length %s" msgstr "Дорожка %s на %s, длина %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "Начало X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "Начало Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "Верхний слой" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "Нижний слой" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "Тип перех.отв." @@ -34131,24 +33710,24 @@ msgstr "Повернуть" msgid "Change Side / Flip" msgstr "Сменить сторону/перевернуть" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "Переместить точно" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "Дублировано %d элемент(ов)" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "Выбор опорной точку для копии..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "Выделение скопировано" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "Копирование отменено" @@ -36359,39 +35938,39 @@ msgstr "Скрыть остальные классы цепей" msgid "Presets (Ctrl+Tab):" msgstr "Наборы (Ctrl+Tab):" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "Сохранить набор..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "Удалить набор..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "Имя нового набора слоёв:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "Сохранить набор слоёв" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "Наборы слоёв" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "Удалить набор" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "Выбор набора:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "Открыть настройки" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." @@ -36696,6 +36275,432 @@ msgstr "Схема KiCad" msgid "KiCad Printed Circuit Board" msgstr "Печатная плата KiCad" +#~ msgid "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('/CLK')`\n" +#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" +#~ msgstr "" +#~ "### Определения верхнего уровня\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Определения правил\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Типы ограничений\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Типы элементов\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Примеры\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # больший зазор между высоковольтными дорожками\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Примечания\n" +#~ "\n" +#~ "Определение версии должно быть первым. Этим обозначается версия " +#~ "синтаксиса файла, так что\n" +#~ "будущие подпрограммы разбора правил смогут применять автоматическое " +#~ "обновление. Её следует\n" +#~ "устанавливать равной \"1\".\n" +#~ "\n" +#~ "Правила должны следовать в определённом порядке. Более поздние правила\n" +#~ "имеют преимущество над более ранними.\n" +#~ "Как только подходящее правило найдено, остальные правила не проверяются.\n" +#~ "\n" +#~ "Используйте Ctrl+/ для комментирования строк.\n" +#~ "


\n" +#~ "\n" +#~ "### Функции\n" +#~ "\n" +#~ "Параметры всех функций поддерживают простые шаблоны (`*` и `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('<обозначения_посад.мест>')\n" +#~ "Истина если любая часть `A` лежит в главной области установки указанных " +#~ "посад.мест.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('<обозначения_посад.мест>')\n" +#~ "Истина если любая часть `A` лежит в области установки указанных посад." +#~ "мест. сверху.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('<обозначения_посад.мест>')\n" +#~ "Истина если любая часть `A` лежит в области установки указанных посад." +#~ "мест. снизу.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('<имя_зоны>')\n" +#~ "Истина если любая часть `A` лежит внутри контура указанной зоны.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "Истина если `A` имеет металлизированные отверстия.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('<имя_цепи>')\n" +#~ "Истина если `A` имеет цепь, которая является частью указанной диф.пары.\n" +#~ "`<имя_цепи>` - это база имени диф.пары. Например, `inDiffPair('CLK')`\n" +#~ "соответствует цепям `CLK_P` и `CLK_N`.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "Истина если `A` и `B` являются членами одной диф.пары.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('<имя_группы>')\n" +#~ "Истина если `A` является членом указанной группы (включая вложенные " +#~ "группы).\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('<имя_слоя>')\n" +#~ "Истина если `A` существует на указанном слое. Имя слоя может быть как\n" +#~ "наименованием, указанным в Параметры платы > Слои редактора, так и\n" +#~ "стандартным именем (например, `F.Cu`).\n" +#~ "\n" +#~ "Обратите внимание: эта функция вернёт истину если `A` лежит на указанном " +#~ "слое,\n" +#~ "независимо от того может ли правило быть применено к этому слою.\n" +#~ "В таком случае лучше использовать определение `(layer \"имя_слоя\")` для " +#~ "правила.\n" +#~ "


\n" +#~ "\n" +#~ "### Ещё примеры\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # исключить шёлкографию из перех.отв. покрытых паяльной маской\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ " \n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ " \n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Задать особый зазор для отдельной диф.пары\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Задать больший зазор между слоями меди и всеми диф.парами\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" + #, fuzzy, c-format #~ msgid "Unable to locate padstack %s in file %s\n" #~ msgstr "Не удаётся создать файл архива '%s'.\n" diff --git a/translation/pofiles/sk.po b/translation/pofiles/sk.po index d842c50081..2b28038b7b 100644 --- a/translation/pofiles/sk.po +++ b/translation/pofiles/sk.po @@ -5,7 +5,7 @@ msgid "" msgstr "" "Project-Id-Version: kicad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-07-07 12:47+0000\n" "Last-Translator: Marcel Hecko \n" "Language-Team: Slovak \n" @@ -4297,7 +4297,7 @@ msgid "Shape" msgstr "Tvar" #: common/eda_shape.cpp:574 common/eda_shape.cpp:584 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:181 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:173 #: pcbnew/pcb_track.cpp:686 msgid "Radius" msgstr "Polomer" @@ -4331,8 +4331,8 @@ msgstr "Body" #: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:155 #: pcbnew/fp_text.cpp:305 pcbnew/fp_text_grid_table.cpp:105 pcbnew/pad.cpp:1008 #: pcbnew/pcb_target.cpp:158 pcbnew/pcb_target.cpp:204 pcbnew/pcb_text.cpp:127 -#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1132 pcbnew/pcb_track.cpp:1149 -#: pcbnew/pcb_track.cpp:1168 +#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1127 pcbnew/pcb_track.cpp:1144 +#: pcbnew/pcb_track.cpp:1163 msgid "Width" msgstr "Šírka" @@ -4383,13 +4383,13 @@ msgstr "Spustiť DRC" msgid "Start Y" msgstr "Spustiť DRC" -#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1140 -#: pcbnew/pcb_track.cpp:1157 +#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1135 +#: pcbnew/pcb_track.cpp:1152 msgid "End X" msgstr "Koniec X" -#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1142 -#: pcbnew/pcb_track.cpp:1159 +#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1137 +#: pcbnew/pcb_track.cpp:1154 msgid "End Y" msgstr "Koniec Y" @@ -4475,7 +4475,7 @@ msgstr "Vľavo" #: pagelayout_editor/dialogs/properties_frame_base.cpp:89 #: pagelayout_editor/dialogs/properties_frame_base.cpp:105 #: pcbnew/dialogs/dialog_dimension_properties_base.cpp:315 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:179 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:171 #: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:117 #: pcbnew/dialogs/dialog_text_properties_base.cpp:145 msgid "Center" @@ -4768,7 +4768,7 @@ msgstr "Nemožno kopírovať súbor \"%s\"." #: common/grid_tricks.cpp:278 common/tool/actions.cpp:153 #: eeschema/tools/ee_actions.cpp:148 pcbnew/dialogs/panel_setup_rules.cpp:112 -#: pcbnew/tools/edit_tool.cpp:2011 +#: pcbnew/tools/edit_tool.cpp:2016 msgid "Cut" msgstr "Vystrihnúť" @@ -4796,7 +4796,7 @@ msgstr "Prilepte bunky schránky do matice v aktuálnej bunke" #: common/grid_tricks.cpp:284 common/tool/actions.cpp:191 #: kicad/project_tree_pane.cpp:771 pcbnew/dialogs/panel_setup_rules.cpp:115 -#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2013 +#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2018 msgid "Delete" msgstr "Odstrániť" @@ -5390,8 +5390,8 @@ msgid "Invalid size %lld: too large" msgstr "Neplatná veľkosť %ll d: príliš veľká" #: common/plugins/eagle/eagle_parser.cpp:281 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:373 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:389 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:366 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:382 #, c-format msgid "Invalid Arc with radius %f and angle %f" msgstr "Neplatný oblúk s polomerom %f a uhlom %f" @@ -17215,7 +17215,7 @@ msgstr "Vyberte vrstvu: %s" #: pcbnew/fp_text_grid_table.cpp:109 pcbnew/pad.cpp:980 #: pcbnew/pcb_dimension.cpp:353 pcbnew/pcb_dimension.cpp:1087 #: pcbnew/pcb_shape.cpp:159 pcbnew/pcb_target.cpp:155 pcbnew/pcb_text.cpp:120 -#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1173 +#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1168 #: pcbnew/tools/board_inspection_tool.cpp:238 #: pcbnew/tools/board_inspection_tool.cpp:385 #: pcbnew/tools/board_inspection_tool.cpp:461 @@ -21353,13 +21353,13 @@ msgstr "a ďalšie" msgid "no layers" msgstr "žiadne vrstvy" -#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1134 -#: pcbnew/pcb_track.cpp:1151 +#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1129 +#: pcbnew/pcb_track.cpp:1146 msgid "Position X" msgstr "Pozícia X" -#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1137 -#: pcbnew/pcb_track.cpp:1154 +#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1132 +#: pcbnew/pcb_track.cpp:1149 msgid "Position Y" msgstr "Pozícia Y" @@ -25231,58 +25231,58 @@ msgstr "" msgid "Error loading footprint library table." msgstr "Chyba načítania tabuľky z knižnice púzdier projektu" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:178 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:170 msgid "Circle Properties" msgstr "Vlastnosti kruhu" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:191 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:183 msgid "Arc Properties" msgstr "Vlastnosti oblúka" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:197 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:189 msgid "Polygon Properties" msgstr "Vlastnosti mnohouholníkov" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:203 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:195 msgid "Rectangle Properties" msgstr "Vlastnosti obdĺžnika" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:209 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:201 msgid "Line Segment Properties" msgstr "Vlastnosti segmentu čiary" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:343 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:336 msgid "Modify drawing properties" msgstr "Upravte vlastnosti výkresu" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:368 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:361 msgid "The arc angle cannot be zero." msgstr "Uhol oblúka nemôže byť nulový." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:415 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:427 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:433 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:388 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:398 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:408 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:420 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:426 #, fuzzy msgid "The item thickness must be greater than zero." msgstr " Uout musí byť väčšie ako Uref" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:402 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 #, fuzzy msgid "The radius must be greater than zero." msgstr " Uout musí byť väčšie ako Uref" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:412 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 msgid "The rectangle cannot be empty." msgstr "Obdĺžnik nemôže byť prázdny." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:421 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:414 #, fuzzy msgid "The polygon outline thickness must be >= 0." msgstr " Uout musí byť väčšie ako Uref" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Zoznam chýb" @@ -27498,17 +27498,17 @@ msgid "Via type:" msgstr "Typom:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "Skrz" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "Micro" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Slepý / pochovaný" @@ -28982,216 +28982,6 @@ msgstr "Pravidlá KDR:" msgid "Check rule syntax" msgstr "Skontrolujte syntax pravidla" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "Predvolené vlastnosti pre nové objekty dimenzie:" @@ -29819,13 +29609,13 @@ msgstr "Kontroluje sa plnenie zón ..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29835,7 +29625,7 @@ msgstr "Kontroluje sa plnenie zón ..." msgid "(%s clearance %s; actual %s)" msgstr "(%s klírens %s; skutočný %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(siete %s a %s)" @@ -31587,7 +31377,7 @@ msgstr "Chladič" msgid "Castellated" msgstr "Castellated" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Priemer" @@ -31935,7 +31725,7 @@ msgstr "Slepá/vnorená prechodka" msgid "Through Via" msgstr "Cez Via" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Vŕtačka" @@ -31958,23 +31748,23 @@ msgstr "Trať %s dňa %s, dĺžka %s" msgid "Track %s on %s, length %s" msgstr "Trať %s dňa %s, dĺžka %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "Pôvod X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "Pôvod Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "Vrchná vrstva" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "Dno vrstvy" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "Cez Type" @@ -34536,24 +34326,24 @@ msgstr "Otočiť" msgid "Change Side / Flip" msgstr "Zmeniť veľkosť via a vŕtanie" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "Posunúť presne" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "Duplikované %d položky" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "Vyberte referenčný bod pre kópiu ..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "Výber bol skopírovaný" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 #, fuzzy msgid "Copy canceled" msgstr "Kópia bola zrušená" @@ -36833,39 +36623,39 @@ msgstr "Skryť všetky ostatné netclassy" msgid "Presets (Ctrl+Tab):" msgstr "(Ctrl + Tab)" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "Uložiť predvoľbu ..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "Odstrániť predvoľbu ..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "Názov predvoľby vrstvy:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "Uložiť predvoľbu vrstvy" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "Predvoľby" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "Odstrániť predvoľbu" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "Vyberte predvoľbu:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "Otvoriť Nastavenia" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." diff --git a/translation/pofiles/sl.po b/translation/pofiles/sl.po index 9ee828b857..972419005f 100644 --- a/translation/pofiles/sl.po +++ b/translation/pofiles/sl.po @@ -4,7 +4,7 @@ msgid "" msgstr "" "Project-Id-Version: kicad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-08-28 17:17+0000\n" "Last-Translator: Vitan Košpenda \n" "Language-Team: Slovenian \n" @@ -4884,7 +4884,7 @@ msgid "Shape" msgstr "Oblika" #: common/eda_shape.cpp:574 common/eda_shape.cpp:584 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:181 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:173 #: pcbnew/pcb_track.cpp:686 #, fuzzy msgid "Radius" @@ -4923,8 +4923,8 @@ msgstr "Točke" #: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:155 #: pcbnew/fp_text.cpp:305 pcbnew/fp_text_grid_table.cpp:105 pcbnew/pad.cpp:1008 #: pcbnew/pcb_target.cpp:158 pcbnew/pcb_target.cpp:204 pcbnew/pcb_text.cpp:127 -#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1132 pcbnew/pcb_track.cpp:1149 -#: pcbnew/pcb_track.cpp:1168 +#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1127 pcbnew/pcb_track.cpp:1144 +#: pcbnew/pcb_track.cpp:1163 #, fuzzy msgid "Width" msgstr "Širina" @@ -4980,14 +4980,14 @@ msgstr "Začni sloj" msgid "Start Y" msgstr "Začni sloj" -#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1140 -#: pcbnew/pcb_track.cpp:1157 +#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1135 +#: pcbnew/pcb_track.cpp:1152 #, fuzzy msgid "End X" msgstr "Konec X" -#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1142 -#: pcbnew/pcb_track.cpp:1159 +#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1137 +#: pcbnew/pcb_track.cpp:1154 #, fuzzy msgid "End Y" msgstr "Konec Y" @@ -5080,7 +5080,7 @@ msgstr "Levo" #: pagelayout_editor/dialogs/properties_frame_base.cpp:89 #: pagelayout_editor/dialogs/properties_frame_base.cpp:105 #: pcbnew/dialogs/dialog_dimension_properties_base.cpp:315 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:179 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:171 #: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:117 #: pcbnew/dialogs/dialog_text_properties_base.cpp:145 #, fuzzy @@ -5397,7 +5397,7 @@ msgstr "Datoteke \"%s\" ni mogoče kopirati." #: common/grid_tricks.cpp:278 common/tool/actions.cpp:153 #: eeschema/tools/ee_actions.cpp:148 pcbnew/dialogs/panel_setup_rules.cpp:112 -#: pcbnew/tools/edit_tool.cpp:2011 +#: pcbnew/tools/edit_tool.cpp:2016 #, fuzzy msgid "Cut" msgstr "Izreži" @@ -5431,7 +5431,7 @@ msgstr "Celice odložišča prilepite v matrico v trenutni celici" #: common/grid_tricks.cpp:284 common/tool/actions.cpp:191 #: kicad/project_tree_pane.cpp:771 pcbnew/dialogs/panel_setup_rules.cpp:115 -#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2013 +#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2018 #, fuzzy msgid "Delete" msgstr "Briši" @@ -6107,8 +6107,8 @@ msgid "Invalid size %lld: too large" msgstr "Neveljavna velikost %ll d: prevelika" #: common/plugins/eagle/eagle_parser.cpp:281 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:373 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:389 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:366 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:382 #, fuzzy, c-format msgid "Invalid Arc with radius %f and angle %f" msgstr "Neveljaven lok s polmerom %f in kotom %f" @@ -19458,7 +19458,7 @@ msgstr "Izberite sloj: %s" #: pcbnew/fp_text_grid_table.cpp:109 pcbnew/pad.cpp:980 #: pcbnew/pcb_dimension.cpp:353 pcbnew/pcb_dimension.cpp:1087 #: pcbnew/pcb_shape.cpp:159 pcbnew/pcb_target.cpp:155 pcbnew/pcb_text.cpp:120 -#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1173 +#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1168 #: pcbnew/tools/board_inspection_tool.cpp:238 #: pcbnew/tools/board_inspection_tool.cpp:385 #: pcbnew/tools/board_inspection_tool.cpp:461 @@ -24099,14 +24099,14 @@ msgstr "in drugi" msgid "no layers" msgstr "brez plasti" -#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1134 -#: pcbnew/pcb_track.cpp:1151 +#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1129 +#: pcbnew/pcb_track.cpp:1146 #, fuzzy msgid "Position X" msgstr "Položaj X" -#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1137 -#: pcbnew/pcb_track.cpp:1154 +#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1132 +#: pcbnew/pcb_track.cpp:1149 #, fuzzy msgid "Position Y" msgstr "Položaj Y" @@ -28602,63 +28602,63 @@ msgstr "" msgid "Error loading footprint library table." msgstr "Napaka pri nalaganju tabele knjižnice odtisa projekta" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:178 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:170 #, fuzzy msgid "Circle Properties" msgstr "Lastnosti kroga" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:191 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:183 #, fuzzy msgid "Arc Properties" msgstr "Lastnosti obloka" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:197 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:189 #, fuzzy msgid "Polygon Properties" msgstr "Lastnosti mnogokotnika" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:203 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:195 #, fuzzy msgid "Rectangle Properties" msgstr "Lastnosti pravokotnika" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:209 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:201 #, fuzzy msgid "Line Segment Properties" msgstr "Lastnosti odseka vrstic" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:343 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:336 #, fuzzy msgid "Modify drawing properties" msgstr "Spreminjanje lastnosti risbe" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:368 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:361 msgid "The arc angle cannot be zero." msgstr "Kot loka ne sme biti enak nič." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:415 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:427 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:433 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:388 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:398 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:408 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:420 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:426 #, fuzzy msgid "The item thickness must be greater than zero." msgstr "Vrzel v sledovih mora biti večja od 0." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:402 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 #, fuzzy msgid "The radius must be greater than zero." msgstr "Vrzel v sledovih mora biti večja od 0." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:412 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 msgid "The rectangle cannot be empty." msgstr "Pravokotnik ne sme biti prazen." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:421 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:414 msgid "The polygon outline thickness must be >= 0." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 #, fuzzy msgid "Error List" msgstr "Seznam napak" @@ -31250,19 +31250,19 @@ msgid "Via type:" msgstr "Tip skoznika:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 #, fuzzy msgid "Through" msgstr "Skozi" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 #, fuzzy msgid "Micro" msgstr "Mikro" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 #, fuzzy msgid "Blind/buried" msgstr "Slep / pokopan" @@ -32929,216 +32929,6 @@ msgstr "Pravila DRK:" msgid "Check rule syntax" msgstr "Preverite skladnjo pravila" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 #, fuzzy msgid "Default properties for new dimension objects:" @@ -33842,13 +33632,13 @@ msgstr "Preverjanje zapolnitve območja ..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -33858,7 +33648,7 @@ msgstr "Preverjanje zapolnitve območja ..." msgid "(%s clearance %s; actual %s)" msgstr "(%s zračnost %s; dejanska %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, fuzzy, c-format msgid "(nets %s and %s)" msgstr "(mreže %s in %s)" @@ -35787,7 +35577,7 @@ msgstr "Hladilnik" msgid "Castellated" msgstr "Kastelasti" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 #, fuzzy msgid "Diameter" msgstr "Premer" @@ -36180,7 +35970,7 @@ msgstr "Slepa / zakopana Via" msgid "Through Via" msgstr "Skozi Via" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Vrtanje" @@ -36204,27 +35994,27 @@ msgstr "Skladba %s na %s, dolžina %s" msgid "Track %s on %s, length %s" msgstr "Skladba %s na %s, dolžina %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 #, fuzzy msgid "Origin X" msgstr "Izvor X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 #, fuzzy msgid "Origin Y" msgstr "Izvor Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 #, fuzzy msgid "Layer Top" msgstr "Vrh sloja" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 #, fuzzy msgid "Layer Bottom" msgstr "Dno sloja" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 #, fuzzy msgid "Via Type" msgstr "Preko tipa" @@ -38955,27 +38745,27 @@ msgstr "Zavrti" msgid "Change Side / Flip" msgstr "Zamenjaj vrtalnik" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 #, fuzzy msgid "Move exact" msgstr "Premakni se natančno" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, fuzzy, c-format msgid "Duplicated %d item(s)" msgstr "Podvojene postavke %d" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 #, fuzzy msgid "Select reference point for the copy..." msgstr "Izberite referenčno točko za kopijo ..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 #, fuzzy msgid "Selection copied" msgstr "Izbor je kopiran" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 #, fuzzy msgid "Copy canceled" msgstr "Kopija preklicana" @@ -41676,47 +41466,47 @@ msgstr "Skrij vse ostale mrežne razrede" msgid "Presets (Ctrl+Tab):" msgstr "(Ctrl + Tab)" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 #, fuzzy msgid "Save preset..." msgstr "Shrani prednastavitev ..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 #, fuzzy msgid "Delete preset..." msgstr "Izbriši prednastavljeno ..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 #, fuzzy msgid "Layer preset name:" msgstr "Ime prednastavljene plasti:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 #, fuzzy msgid "Save Layer Preset" msgstr "Shrani prednastavitev sloja" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 #, fuzzy msgid "Presets" msgstr "Prednastavljeni" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 #, fuzzy msgid "Delete Preset" msgstr "Izbriši prednastavitev" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 #, fuzzy msgid "Select preset:" msgstr "Izberite prednastavitev:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 #, fuzzy msgid "Open Preferences" msgstr "Odprite nastavitve" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 #, fuzzy msgid "" "The current color theme is read-only. Create a new theme in Preferences to " diff --git a/translation/pofiles/sr.po b/translation/pofiles/sr.po index 56e06d5a1e..1881354211 100644 --- a/translation/pofiles/sr.po +++ b/translation/pofiles/sr.po @@ -3,7 +3,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-09-05 11:13+0000\n" "Last-Translator: Zoran \n" "Language-Team: Serbian \n" @@ -4298,7 +4298,7 @@ msgid "Shape" msgstr "Облик" #: common/eda_shape.cpp:574 common/eda_shape.cpp:584 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:181 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:173 #: pcbnew/pcb_track.cpp:686 msgid "Radius" msgstr "Полупречник" @@ -4332,8 +4332,8 @@ msgstr "" #: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:155 #: pcbnew/fp_text.cpp:305 pcbnew/fp_text_grid_table.cpp:105 pcbnew/pad.cpp:1008 #: pcbnew/pcb_target.cpp:158 pcbnew/pcb_target.cpp:204 pcbnew/pcb_text.cpp:127 -#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1132 pcbnew/pcb_track.cpp:1149 -#: pcbnew/pcb_track.cpp:1168 +#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1127 pcbnew/pcb_track.cpp:1144 +#: pcbnew/pcb_track.cpp:1163 msgid "Width" msgstr "Дужина" @@ -4384,14 +4384,14 @@ msgstr "X:" msgid "Start Y" msgstr "Y:" -#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1140 -#: pcbnew/pcb_track.cpp:1157 +#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1135 +#: pcbnew/pcb_track.cpp:1152 #, fuzzy msgid "End X" msgstr "Крај X:" -#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1142 -#: pcbnew/pcb_track.cpp:1159 +#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1137 +#: pcbnew/pcb_track.cpp:1154 #, fuzzy msgid "End Y" msgstr "Крај Y:" @@ -4478,7 +4478,7 @@ msgstr "Лијево" #: pagelayout_editor/dialogs/properties_frame_base.cpp:89 #: pagelayout_editor/dialogs/properties_frame_base.cpp:105 #: pcbnew/dialogs/dialog_dimension_properties_base.cpp:315 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:179 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:171 #: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:117 #: pcbnew/dialogs/dialog_text_properties_base.cpp:145 msgid "Center" @@ -4751,7 +4751,7 @@ msgstr "Немогуће копирати датотеку \"%s\"." #: common/grid_tricks.cpp:278 common/tool/actions.cpp:153 #: eeschema/tools/ee_actions.cpp:148 pcbnew/dialogs/panel_setup_rules.cpp:112 -#: pcbnew/tools/edit_tool.cpp:2011 +#: pcbnew/tools/edit_tool.cpp:2016 msgid "Cut" msgstr "Исјеци" @@ -4779,7 +4779,7 @@ msgstr "" #: common/grid_tricks.cpp:284 common/tool/actions.cpp:191 #: kicad/project_tree_pane.cpp:771 pcbnew/dialogs/panel_setup_rules.cpp:115 -#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2013 +#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2018 msgid "Delete" msgstr "Избриши" @@ -5401,8 +5401,8 @@ msgid "Invalid size %lld: too large" msgstr "" #: common/plugins/eagle/eagle_parser.cpp:281 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:373 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:389 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:366 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:382 #, c-format msgid "Invalid Arc with radius %f and angle %f" msgstr "" @@ -16988,7 +16988,7 @@ msgstr "Изабери слој: %s" #: pcbnew/fp_text_grid_table.cpp:109 pcbnew/pad.cpp:980 #: pcbnew/pcb_dimension.cpp:353 pcbnew/pcb_dimension.cpp:1087 #: pcbnew/pcb_shape.cpp:159 pcbnew/pcb_target.cpp:155 pcbnew/pcb_text.cpp:120 -#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1173 +#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1168 #: pcbnew/tools/board_inspection_tool.cpp:238 #: pcbnew/tools/board_inspection_tool.cpp:385 #: pcbnew/tools/board_inspection_tool.cpp:461 @@ -21102,14 +21102,14 @@ msgstr " и остали" msgid "no layers" msgstr "" -#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1134 -#: pcbnew/pcb_track.cpp:1151 +#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1129 +#: pcbnew/pcb_track.cpp:1146 #, fuzzy msgid "Position X" msgstr "X позиција:" -#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1137 -#: pcbnew/pcb_track.cpp:1154 +#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1132 +#: pcbnew/pcb_track.cpp:1149 #, fuzzy msgid "Position Y" msgstr "Y позиција:" @@ -24965,60 +24965,60 @@ msgstr "" msgid "Error loading footprint library table." msgstr "Грешка: " -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:178 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:170 msgid "Circle Properties" msgstr "Својства круга" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:191 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:183 msgid "Arc Properties" msgstr "Својства лука" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:197 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:189 msgid "Polygon Properties" msgstr "Својства полигона" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:203 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:195 #, fuzzy msgid "Rectangle Properties" msgstr "Својства круга" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:209 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:201 #, fuzzy msgid "Line Segment Properties" msgstr "Стил линије" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:343 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:336 #, fuzzy msgid "Modify drawing properties" msgstr "Опције цртања" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:368 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:361 msgid "The arc angle cannot be zero." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:415 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:427 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:433 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:388 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:398 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:408 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:420 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:426 msgid "The item thickness must be greater than zero." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:402 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 #, fuzzy msgid "The radius must be greater than zero." msgstr "Попуњавање зона" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:412 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 #, fuzzy msgid "The rectangle cannot be empty." msgstr "Попуњавање зона" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:421 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:414 msgid "The polygon outline thickness must be >= 0." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Листа грешака" @@ -27184,17 +27184,17 @@ msgid "Via type:" msgstr "Тип:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "Кроз" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "" @@ -28639,216 +28639,6 @@ msgstr "" msgid "Check rule syntax" msgstr "" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "" @@ -29489,13 +29279,13 @@ msgstr "Попуњавање зона" #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29505,7 +29295,7 @@ msgstr "Попуњавање зона" msgid "(%s clearance %s; actual %s)" msgstr "" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, fuzzy, c-format msgid "(nets %s and %s)" msgstr " у јединицама%c и %c" @@ -31239,7 +31029,7 @@ msgstr "" msgid "Castellated" msgstr "" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "" @@ -31603,7 +31393,7 @@ msgstr "" msgid "Through Via" msgstr "" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "" @@ -31626,26 +31416,26 @@ msgstr "Попуњавање зона" msgid "Track %s on %s, length %s" msgstr "Попуњавање зона" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 #, fuzzy msgid "Origin X" msgstr "Почетак:" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 #, fuzzy msgid "Origin Y" msgstr "Почетак:" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 #, fuzzy msgid "Layer Top" msgstr "Слој" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 #, fuzzy msgid "Via Type" msgstr "Тип:" @@ -34022,26 +33812,26 @@ msgstr "Окрени" msgid "Change Side / Flip" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 #, fuzzy msgid "Move exact" msgstr "Помјери" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "" -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 #, fuzzy msgid "Selection copied" msgstr "Појасни избор" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 #, fuzzy msgid "Copy canceled" msgstr "Копирање прекинуто." @@ -36445,46 +36235,46 @@ msgstr "Сакриј све слојеве бакра" msgid "Presets (Ctrl+Tab):" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 #, fuzzy msgid "Save preset..." msgstr "Сачувај &Као..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 #, fuzzy msgid "Delete preset..." msgstr "Избриши мрежу" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 #, fuzzy msgid "Layer preset name:" msgstr "Избор слоја:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 #, fuzzy msgid "Save Layer Preset" msgstr "Изабери језик" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 #, fuzzy msgid "Delete Preset" msgstr "Избриши мрежу" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 #, fuzzy msgid "Select preset:" msgstr "Изабери" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 #, fuzzy msgid "Open Preferences" msgstr "&Преференце" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." diff --git a/translation/pofiles/sv.po b/translation/pofiles/sv.po index 211c83c59d..86853c4c45 100644 --- a/translation/pofiles/sv.po +++ b/translation/pofiles/sv.po @@ -7,7 +7,7 @@ msgid "" msgstr "" "Project-Id-Version: \n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-10-06 09:15+0000\n" "Last-Translator: Henrik Kauhanen \n" "Language-Team: Swedish \n" @@ -4213,7 +4213,7 @@ msgid "Shape" msgstr "Form" #: common/eda_shape.cpp:574 common/eda_shape.cpp:584 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:181 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:173 #: pcbnew/pcb_track.cpp:686 msgid "Radius" msgstr "Radie" @@ -4247,8 +4247,8 @@ msgstr "Punkter" #: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:155 #: pcbnew/fp_text.cpp:305 pcbnew/fp_text_grid_table.cpp:105 pcbnew/pad.cpp:1008 #: pcbnew/pcb_target.cpp:158 pcbnew/pcb_target.cpp:204 pcbnew/pcb_text.cpp:127 -#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1132 pcbnew/pcb_track.cpp:1149 -#: pcbnew/pcb_track.cpp:1168 +#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1127 pcbnew/pcb_track.cpp:1144 +#: pcbnew/pcb_track.cpp:1163 msgid "Width" msgstr "Bredd" @@ -4296,13 +4296,13 @@ msgstr "Start X" msgid "Start Y" msgstr "Start Y" -#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1140 -#: pcbnew/pcb_track.cpp:1157 +#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1135 +#: pcbnew/pcb_track.cpp:1152 msgid "End X" msgstr "Avsluta X" -#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1142 -#: pcbnew/pcb_track.cpp:1159 +#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1137 +#: pcbnew/pcb_track.cpp:1154 msgid "End Y" msgstr "Avsluta Y" @@ -4388,7 +4388,7 @@ msgstr "Vänster" #: pagelayout_editor/dialogs/properties_frame_base.cpp:89 #: pagelayout_editor/dialogs/properties_frame_base.cpp:105 #: pcbnew/dialogs/dialog_dimension_properties_base.cpp:315 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:179 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:171 #: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:117 #: pcbnew/dialogs/dialog_text_properties_base.cpp:145 msgid "Center" @@ -4673,7 +4673,7 @@ msgstr "Kan inte kopiera filen '%s'." #: common/grid_tricks.cpp:278 common/tool/actions.cpp:153 #: eeschema/tools/ee_actions.cpp:148 pcbnew/dialogs/panel_setup_rules.cpp:112 -#: pcbnew/tools/edit_tool.cpp:2011 +#: pcbnew/tools/edit_tool.cpp:2016 msgid "Cut" msgstr "Klipp ut" @@ -4701,7 +4701,7 @@ msgstr "Klistra in urklippsceller i matris vid aktuell cell" #: common/grid_tricks.cpp:284 common/tool/actions.cpp:191 #: kicad/project_tree_pane.cpp:771 pcbnew/dialogs/panel_setup_rules.cpp:115 -#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2013 +#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2018 msgid "Delete" msgstr "Radera" @@ -5281,8 +5281,8 @@ msgid "Invalid size %lld: too large" msgstr "Ogiltig storlek %lld: för stor" #: common/plugins/eagle/eagle_parser.cpp:281 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:373 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:389 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:366 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:382 #, c-format msgid "Invalid Arc with radius %f and angle %f" msgstr "Ogiltig båge med radie %f och vinkel %f" @@ -16921,7 +16921,7 @@ msgstr "Välj lager: %s" #: pcbnew/fp_text_grid_table.cpp:109 pcbnew/pad.cpp:980 #: pcbnew/pcb_dimension.cpp:353 pcbnew/pcb_dimension.cpp:1087 #: pcbnew/pcb_shape.cpp:159 pcbnew/pcb_target.cpp:155 pcbnew/pcb_text.cpp:120 -#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1173 +#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1168 #: pcbnew/tools/board_inspection_tool.cpp:238 #: pcbnew/tools/board_inspection_tool.cpp:385 #: pcbnew/tools/board_inspection_tool.cpp:461 @@ -20917,13 +20917,13 @@ msgstr "och andra" msgid "no layers" msgstr "inga lager" -#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1134 -#: pcbnew/pcb_track.cpp:1151 +#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1129 +#: pcbnew/pcb_track.cpp:1146 msgid "Position X" msgstr "Position X" -#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1137 -#: pcbnew/pcb_track.cpp:1154 +#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1132 +#: pcbnew/pcb_track.cpp:1149 msgid "Position Y" msgstr "Position Y" @@ -24744,55 +24744,55 @@ msgstr "" msgid "Error loading footprint library table." msgstr "Fel vid inläsning av fotavtrycksbibliotekstabell." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:178 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:170 msgid "Circle Properties" msgstr "Cirkelegenskaper" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:191 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:183 msgid "Arc Properties" msgstr "Båg-egenskaper" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:197 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:189 msgid "Polygon Properties" msgstr "Polygonegenskaper" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:203 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:195 msgid "Rectangle Properties" msgstr "Rektangelegenskaper" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:209 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:201 msgid "Line Segment Properties" msgstr "Egenskaper för linjesegment" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:343 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:336 msgid "Modify drawing properties" msgstr "Ändra ritningsegenskaper" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:368 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:361 msgid "The arc angle cannot be zero." msgstr "Bågvinkeln kan inte vara noll." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:415 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:427 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:433 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:388 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:398 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:408 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:420 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:426 msgid "The item thickness must be greater than zero." msgstr "Objektets tjocklek måste vara större än noll." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:402 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 msgid "The radius must be greater than zero." msgstr "Radien måste vara större än noll." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:412 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 msgid "The rectangle cannot be empty." msgstr "Rektangeln kan inte vara tom." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:421 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:414 msgid "The polygon outline thickness must be >= 0." msgstr "Polygonens konturtjocklek måste vara >=0." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "Fellista" @@ -26970,17 +26970,17 @@ msgid "Via type:" msgstr "Via typ:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "Genom" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "Mikro" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Blind / begravd" @@ -28459,216 +28459,6 @@ msgstr "DRC-regler:" msgid "Check rule syntax" msgstr "Kontrollera regelsyntax" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "Standardegenskaper för nya måttsättningsobjekt:" @@ -29269,13 +29059,13 @@ msgstr "Kontrollerar zoner..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29285,7 +29075,7 @@ msgstr "Kontrollerar zoner..." msgid "(%s clearance %s; actual %s)" msgstr "(%s clearance %s; faktisk %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(nät %s och %s)" @@ -30996,7 +30786,7 @@ msgstr "Kylfläns" msgid "Castellated" msgstr "Krenelerad" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Diameter" @@ -31334,7 +31124,7 @@ msgstr "Blind / begravd via" msgid "Through Via" msgstr "Genom Via" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Borra" @@ -31357,23 +31147,23 @@ msgstr "Ledare (båge) %s på %s, längd %s" msgid "Track %s on %s, length %s" msgstr "Ledare %s på %s, längd %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "Origo X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "Origo Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "Övre lager" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "Undre lager" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "Via typ" @@ -33881,24 +33671,24 @@ msgstr "Rotera" msgid "Change Side / Flip" msgstr "Byt sida / vänd" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "Flytta exakt" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "Duplicerade %d objekt" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "Välj referenspunkt för kopian ..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "Urvalet kopierades" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "Kopiering avbröts" @@ -36107,39 +35897,39 @@ msgstr "Dölj alla andra nätklasser" msgid "Presets (Ctrl+Tab):" msgstr "Förinställningar (Ctrl + Tab):" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "Spara förinställning ..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "Ta bort förinställning ..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "Lagrets förinställda namn:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "Spara lagringsförinställning" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "Förinställningar" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "Ta bort förinställning" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "Välj förinställning:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "Öppna inställningar" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." diff --git a/translation/pofiles/th.po b/translation/pofiles/th.po index c6b714c8ec..26979ac2ea 100644 --- a/translation/pofiles/th.po +++ b/translation/pofiles/th.po @@ -3,7 +3,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-09-29 15:54+0000\n" "Last-Translator: boonchai k. \n" "Language-Team: Thai \n" @@ -4137,7 +4137,7 @@ msgid "Shape" msgstr "รูปร่าง" #: common/eda_shape.cpp:574 common/eda_shape.cpp:584 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:181 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:173 #: pcbnew/pcb_track.cpp:686 msgid "Radius" msgstr "รัศมี" @@ -4171,8 +4171,8 @@ msgstr "คะแนน" #: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:155 #: pcbnew/fp_text.cpp:305 pcbnew/fp_text_grid_table.cpp:105 pcbnew/pad.cpp:1008 #: pcbnew/pcb_target.cpp:158 pcbnew/pcb_target.cpp:204 pcbnew/pcb_text.cpp:127 -#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1132 pcbnew/pcb_track.cpp:1149 -#: pcbnew/pcb_track.cpp:1168 +#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1127 pcbnew/pcb_track.cpp:1144 +#: pcbnew/pcb_track.cpp:1163 msgid "Width" msgstr "ความหนา" @@ -4220,13 +4220,13 @@ msgstr "เริ่ม X" msgid "Start Y" msgstr "เริ่ม Y" -#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1140 -#: pcbnew/pcb_track.cpp:1157 +#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1135 +#: pcbnew/pcb_track.cpp:1152 msgid "End X" msgstr "สิ้นสุด X" -#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1142 -#: pcbnew/pcb_track.cpp:1159 +#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1137 +#: pcbnew/pcb_track.cpp:1154 msgid "End Y" msgstr "สิ้นสุด Y" @@ -4312,7 +4312,7 @@ msgstr "ซ้าย" #: pagelayout_editor/dialogs/properties_frame_base.cpp:89 #: pagelayout_editor/dialogs/properties_frame_base.cpp:105 #: pcbnew/dialogs/dialog_dimension_properties_base.cpp:315 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:179 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:171 #: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:117 #: pcbnew/dialogs/dialog_text_properties_base.cpp:145 msgid "Center" @@ -4587,7 +4587,7 @@ msgstr "ไม่สามารถสำเนาไฟล์ '%s'" #: common/grid_tricks.cpp:278 common/tool/actions.cpp:153 #: eeschema/tools/ee_actions.cpp:148 pcbnew/dialogs/panel_setup_rules.cpp:112 -#: pcbnew/tools/edit_tool.cpp:2011 +#: pcbnew/tools/edit_tool.cpp:2016 msgid "Cut" msgstr "ตัด" @@ -4615,7 +4615,7 @@ msgstr "วางสำเนาจากเซลส์คลิปบอร์ #: common/grid_tricks.cpp:284 common/tool/actions.cpp:191 #: kicad/project_tree_pane.cpp:771 pcbnew/dialogs/panel_setup_rules.cpp:115 -#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2013 +#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2018 msgid "Delete" msgstr "ลบ" @@ -5192,8 +5192,8 @@ msgid "Invalid size %lld: too large" msgstr "ขนาดไม่ถูก %lld: ใหญ่เกินไป" #: common/plugins/eagle/eagle_parser.cpp:281 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:373 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:389 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:366 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:382 #, c-format msgid "Invalid Arc with radius %f and angle %f" msgstr "เส้นโค้งไม่ถูกต้อง รัศมี %f และมุม %f" @@ -16628,7 +16628,7 @@ msgstr "เลือกเลเยอร์: %s" #: pcbnew/fp_text_grid_table.cpp:109 pcbnew/pad.cpp:980 #: pcbnew/pcb_dimension.cpp:353 pcbnew/pcb_dimension.cpp:1087 #: pcbnew/pcb_shape.cpp:159 pcbnew/pcb_target.cpp:155 pcbnew/pcb_text.cpp:120 -#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1173 +#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1168 #: pcbnew/tools/board_inspection_tool.cpp:238 #: pcbnew/tools/board_inspection_tool.cpp:385 #: pcbnew/tools/board_inspection_tool.cpp:461 @@ -20576,13 +20576,13 @@ msgstr "และอื่น ๆ" msgid "no layers" msgstr "ไม่มีเลเยอร์" -#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1134 -#: pcbnew/pcb_track.cpp:1151 +#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1129 +#: pcbnew/pcb_track.cpp:1146 msgid "Position X" msgstr "ตำแหน่ง X" -#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1137 -#: pcbnew/pcb_track.cpp:1154 +#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1132 +#: pcbnew/pcb_track.cpp:1149 msgid "Position Y" msgstr "ตำแหน่ง Y" @@ -24337,57 +24337,57 @@ msgstr "" msgid "Error loading footprint library table." msgstr "ข้อผิดพลาดในการโหลดตารางฟุ้ทพรินท์ไลบรารี" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:178 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:170 msgid "Circle Properties" msgstr "คุณสมบัติของวงกลม" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:191 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:183 msgid "Arc Properties" msgstr "คุณสมบัติส่วนโค้ง" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:197 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:189 msgid "Polygon Properties" msgstr "คุณสมบัติรูปหลายเหลี่ยม" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:203 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:195 msgid "Rectangle Properties" msgstr "คุณสมบัติสี่เหลี่ยมผืนผ้า" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:209 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:201 msgid "Line Segment Properties" msgstr "คุณสมบัติส่วนเส้นตรง" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:343 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:336 msgid "Modify drawing properties" msgstr "แก้ไขคุณสมบัติเขียนแบบ" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:368 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:361 msgid "The arc angle cannot be zero." msgstr "มุมโค้งไม่สามารถเป็นศูนย์" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:415 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:427 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:433 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:388 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:398 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:408 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:420 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:426 #, fuzzy msgid "The item thickness must be greater than zero." msgstr "ช่องว่างการติดตามต้องมากกว่า 0" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:402 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 #, fuzzy msgid "The radius must be greater than zero." msgstr "ช่องว่างการติดตามต้องมากกว่า 0" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:412 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 msgid "The rectangle cannot be empty." msgstr "สี่เหลี่ยมต้องไม่ว่างเปล่า" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:421 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:414 msgid "The polygon outline thickness must be >= 0." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "รายการข้อผิดพลาด" @@ -26514,17 +26514,17 @@ msgid "Via type:" msgstr "ชนิดเวีย:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "ผ่าน" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "ไมโคร" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "ชนิดบอด/ฝัง" @@ -27965,422 +27965,6 @@ msgstr "กฎ DRC:" msgid "Check rule syntax" msgstr "ตรวจสอบไวยากรณ์ของกฎ" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -#, fuzzy -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge_clearance\n" -" * length\n" -" * hole\n" -" * hole_clearance\n" -" * silk_clearance\n" -" * skew\n" -" * track_width\n" -" * via_count\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### ตัวอย่าง\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('CLK')`\n" -"matches items in the `CLK_P` and `CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\" \n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\" \n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\" \n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" -" \n" -" (rule \"Pad to Track Clearance\" \n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\" \n" -" (constraint hole (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -" \n" -" (rule \"Max Drill Hole Size PTH\" \n" -" (constraint hole (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "ค่าคุณสมบัติปริยาย สําหรับวัตถุวัดขนาดใหม่:" @@ -28980,13 +28564,13 @@ msgstr "กำลังตรวจสอบโซน..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -28996,7 +28580,7 @@ msgstr "กำลังตรวจสอบโซน..." msgid "(%s clearance %s; actual %s)" msgstr "(%s ระยะห่าง %s ค่าจริง %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(เน็ต %s และ %s)" @@ -30684,7 +30268,7 @@ msgstr "ครีบระบายความร้อน" msgid "Castellated" msgstr "คาสเทลเลต" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "เส้นผ่าศูนย์กลาง" @@ -31021,7 +30605,7 @@ msgstr "เวียชนิด บอด/ฝัง" msgid "Through Via" msgstr "เวียเจาะทะลุ" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "เจาะ" @@ -31044,23 +30628,23 @@ msgstr "แทร็ก (ส่วนโค้ง) %s บน %s, ความย msgid "Track %s on %s, length %s" msgstr "แทร็ก %s บน %s, ความยาว %s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "จุดเริ่มต้น X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "จุดเริ่มต้น Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "เลเยอร์ด้านบน" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "เลเยอร์ด้านล่าง" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "ชนิดเวีย" @@ -33495,24 +33079,24 @@ msgstr "หมุน" msgid "Change Side / Flip" msgstr "เปลี่ยน ด้าน/พลิก" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "ย้ายที่แน่นอน" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "ซ้ำกัน %d ชิ้นส่วน" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "เลือกจุดอ้างอิงสําหรับสําเนา..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "สำเนาการเลือกแล้ว" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "ยกเลิกสำเนาแล้ว" @@ -35697,39 +35281,39 @@ msgstr "ซ่อนเน็ตคลาสอื่นๆทั้งหมด msgid "Presets (Ctrl+Tab):" msgstr "ตั้งค่าไว้ (Ctrl+Tab):" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "บันทึกค่าที่ตั้งไว้..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "ลบค่าที่ตั้งไว้..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "ชื่อเลเยอร์ตั้งล่วงหน้า:" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "บันทึกเลเยอร์ที่ตั้งไว้ล่วงหน้า" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "ค่าที่ตั้งไว้" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "ลบที่ตั้งไว้ล่วงหน้า" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "เลือกค่าที่ตั้งไว้ล่วงหน้า:" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "เปิดตั้งความชอบ" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." @@ -36031,6 +35615,429 @@ msgstr "แผนผังวงจร KiCad" msgid "KiCad Printed Circuit Board" msgstr "แผ่นวงจรพิมพ์ KiCad" +#, fuzzy +#~ msgid "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('/CLK')`\n" +#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" +#~ msgstr "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge_clearance\n" +#~ " * length\n" +#~ " * hole\n" +#~ " * hole_clearance\n" +#~ " * silk_clearance\n" +#~ " * skew\n" +#~ " * track_width\n" +#~ " * via_count\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### ตัวอย่าง\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('CLK')`\n" +#~ "matches items in the `CLK_P` and `CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\" \n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\" \n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\" \n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" +#~ " \n" +#~ " (rule \"Pad to Track Clearance\" \n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\" \n" +#~ " (constraint hole (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ " \n" +#~ " (rule \"Max Drill Hole Size PTH\" \n" +#~ " (constraint hole (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" + #, fuzzy, c-format #~ msgid "Unable to locate padstack %s in file %s\n" #~ msgstr "ไม่สามารถสร้างไฟล์คลัง '%s'\n" diff --git a/translation/pofiles/tr.po b/translation/pofiles/tr.po index c4ca51e1b5..329e25ffae 100644 --- a/translation/pofiles/tr.po +++ b/translation/pofiles/tr.po @@ -10,7 +10,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-07-04 20:18+0000\n" "Last-Translator: Mustafa Selçuk ÇAVDAR \n" "Language-Team: Turkish \n" @@ -4199,7 +4199,7 @@ msgid "Shape" msgstr "Şekil" #: common/eda_shape.cpp:574 common/eda_shape.cpp:584 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:181 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:173 #: pcbnew/pcb_track.cpp:686 msgid "Radius" msgstr "Yarıçap" @@ -4233,8 +4233,8 @@ msgstr "Noktalar" #: pcbnew/dialogs/panel_setup_tracks_and_vias_base.cpp:155 #: pcbnew/fp_text.cpp:305 pcbnew/fp_text_grid_table.cpp:105 pcbnew/pad.cpp:1008 #: pcbnew/pcb_target.cpp:158 pcbnew/pcb_target.cpp:204 pcbnew/pcb_text.cpp:127 -#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1132 pcbnew/pcb_track.cpp:1149 -#: pcbnew/pcb_track.cpp:1168 +#: pcbnew/pcb_track.cpp:681 pcbnew/pcb_track.cpp:1127 pcbnew/pcb_track.cpp:1144 +#: pcbnew/pcb_track.cpp:1163 msgid "Width" msgstr "Genişlik" @@ -4282,13 +4282,13 @@ msgstr "X'i Başlat" msgid "Start Y" msgstr "Y'yi başlat" -#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1140 -#: pcbnew/pcb_track.cpp:1157 +#: common/eda_shape.cpp:1652 pcbnew/pcb_shape.cpp:264 pcbnew/pcb_track.cpp:1135 +#: pcbnew/pcb_track.cpp:1152 msgid "End X" msgstr "X'i sonlandır" -#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1142 -#: pcbnew/pcb_track.cpp:1159 +#: common/eda_shape.cpp:1654 pcbnew/pcb_shape.cpp:266 pcbnew/pcb_track.cpp:1137 +#: pcbnew/pcb_track.cpp:1154 msgid "End Y" msgstr "Y'yi bitir" @@ -4374,7 +4374,7 @@ msgstr "Sol" #: pagelayout_editor/dialogs/properties_frame_base.cpp:89 #: pagelayout_editor/dialogs/properties_frame_base.cpp:105 #: pcbnew/dialogs/dialog_dimension_properties_base.cpp:315 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:179 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:171 #: pcbnew/dialogs/dialog_pad_basicshapes_properties.cpp:117 #: pcbnew/dialogs/dialog_text_properties_base.cpp:145 msgid "Center" @@ -4659,7 +4659,7 @@ msgstr "'%s' dosyası kopyalanamıyor." #: common/grid_tricks.cpp:278 common/tool/actions.cpp:153 #: eeschema/tools/ee_actions.cpp:148 pcbnew/dialogs/panel_setup_rules.cpp:112 -#: pcbnew/tools/edit_tool.cpp:2011 +#: pcbnew/tools/edit_tool.cpp:2016 msgid "Cut" msgstr "Kes" @@ -4687,7 +4687,7 @@ msgstr "Pano hücrelerini geçerli hücredeki matrise yapıştırın" #: common/grid_tricks.cpp:284 common/tool/actions.cpp:191 #: kicad/project_tree_pane.cpp:771 pcbnew/dialogs/panel_setup_rules.cpp:115 -#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2013 +#: pcbnew/plugins/kicad/pcb_parser.cpp:857 pcbnew/tools/edit_tool.cpp:2018 msgid "Delete" msgstr "Sil" @@ -5266,8 +5266,8 @@ msgid "Invalid size %lld: too large" msgstr "Geçersiz boyut %lld: çok büyük" #: common/plugins/eagle/eagle_parser.cpp:281 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:373 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:389 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:366 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:382 #, c-format msgid "Invalid Arc with radius %f and angle %f" msgstr "%f Yarıçaplı geçersiz Yay ve %f açı" @@ -16375,7 +16375,7 @@ msgstr "" #: pcbnew/fp_text_grid_table.cpp:109 pcbnew/pad.cpp:980 #: pcbnew/pcb_dimension.cpp:353 pcbnew/pcb_dimension.cpp:1087 #: pcbnew/pcb_shape.cpp:159 pcbnew/pcb_target.cpp:155 pcbnew/pcb_text.cpp:120 -#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1173 +#: pcbnew/pcb_track.cpp:679 pcbnew/pcb_track.cpp:738 pcbnew/pcb_track.cpp:1168 #: pcbnew/tools/board_inspection_tool.cpp:238 #: pcbnew/tools/board_inspection_tool.cpp:385 #: pcbnew/tools/board_inspection_tool.cpp:461 @@ -20178,13 +20178,13 @@ msgstr "ve diğerleri" msgid "no layers" msgstr "" -#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1134 -#: pcbnew/pcb_track.cpp:1151 +#: pcbnew/board_item.cpp:232 pcbnew/pcb_track.cpp:1129 +#: pcbnew/pcb_track.cpp:1146 msgid "Position X" msgstr "" -#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1137 -#: pcbnew/pcb_track.cpp:1154 +#: pcbnew/board_item.cpp:234 pcbnew/pcb_track.cpp:1132 +#: pcbnew/pcb_track.cpp:1149 msgid "Position Y" msgstr "" @@ -23784,55 +23784,55 @@ msgstr "" msgid "Error loading footprint library table." msgstr "Ayak izi kitaplığı tablosu yüklenirken hata oluştu." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:178 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:170 msgid "Circle Properties" msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:191 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:183 msgid "Arc Properties" msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:197 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:189 msgid "Polygon Properties" msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:203 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:195 msgid "Rectangle Properties" msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:209 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:201 msgid "Line Segment Properties" msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:343 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:336 msgid "Modify drawing properties" msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:368 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:361 msgid "The arc angle cannot be zero." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:415 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:427 -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:433 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:388 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:398 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:408 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:420 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:426 msgid "The item thickness must be greater than zero." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:402 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:395 msgid "The radius must be greater than zero." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:412 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:405 msgid "The rectangle cannot be empty." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:421 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:414 msgid "The polygon outline thickness must be >= 0." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "" @@ -25877,17 +25877,17 @@ msgid "Via type:" msgstr "Geçiş türü:" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "İçinden" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "Mikro" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "Kör/gömülü" @@ -27265,216 +27265,6 @@ msgstr "" msgid "Check rule syntax" msgstr "" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "" @@ -28073,13 +27863,13 @@ msgstr "" #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -28089,7 +27879,7 @@ msgstr "" msgid "(%s clearance %s; actual %s)" msgstr "" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "" @@ -29733,7 +29523,7 @@ msgstr "" msgid "Castellated" msgstr "Sıralanmış" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "Çap" @@ -30067,7 +29857,7 @@ msgstr "" msgid "Through Via" msgstr "Tam Geçiş(via)" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "Matkap" @@ -30090,23 +29880,23 @@ msgstr "" msgid "Track %s on %s, length %s" msgstr "" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "" @@ -32392,24 +32182,24 @@ msgstr "Döndür" msgid "Change Side / Flip" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "" -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "Kopya iptal edildi" @@ -34590,39 +34380,39 @@ msgstr "Diğer Tüm Netclass'ları Gizle" msgid "Presets (Ctrl+Tab):" msgstr "Hazır Ayarlar (Ctrl+Tab):" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "ön ayarlar" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "Tercihleri Aç" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." diff --git a/translation/pofiles/vi.po b/translation/pofiles/vi.po index e88cd70bbf..241b593c91 100644 --- a/translation/pofiles/vi.po +++ b/translation/pofiles/vi.po @@ -4,7 +4,7 @@ msgid "" msgstr "" "Project-Id-Version: Kicad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-09-07 20:50+0000\n" "Last-Translator: lê văn lập \n" "Language-Team: Vietnamese = 0." msgstr "" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "" @@ -26709,17 +26709,17 @@ msgid "Via type:" msgstr "" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "" @@ -28113,216 +28113,6 @@ msgstr "" msgid "Check rule syntax" msgstr "" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "" @@ -28925,13 +28715,13 @@ msgstr "" #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -28941,7 +28731,7 @@ msgstr "" msgid "(%s clearance %s; actual %s)" msgstr "" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "" @@ -30616,7 +30406,7 @@ msgstr "" msgid "Castellated" msgstr "" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "" @@ -30958,7 +30748,7 @@ msgstr "" msgid "Through Via" msgstr "Via xuyên lỗ" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "" @@ -30981,23 +30771,23 @@ msgstr "" msgid "Track %s on %s, length %s" msgstr "" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "" @@ -33336,24 +33126,24 @@ msgstr "" msgid "Change Side / Flip" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "" -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 #, fuzzy msgid "Copy canceled" msgstr "Hủy bỏ" @@ -35580,39 +35370,39 @@ msgstr "" msgid "Presets (Ctrl+Tab):" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." diff --git a/translation/pofiles/zh_CN.po b/translation/pofiles/zh_CN.po index 1e324f465e..8df0e448ef 100644 --- a/translation/pofiles/zh_CN.po +++ b/translation/pofiles/zh_CN.po @@ -16,7 +16,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad_zh_CN_Master_v0.0.32\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-09-29 08:15+0000\n" "Last-Translator: obit \n" "Language-Team: Chinese (Simplified) = 0." msgstr "多边形轮廓厚度必须 >= 0。" -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "错误列表" @@ -26483,17 +26483,17 @@ msgid "Via type:" msgstr "过孔类型：" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "通孔" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "微孔" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "盲孔/埋孔" @@ -27934,475 +27934,6 @@ msgstr "DRC 规则：" msgid "Check rule syntax" msgstr "检查规则语法" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" -"### Top-level Clauses\n" -"### 顶层语句\n" -"\n" -" (version )\n" -"# 版本语句：(version <版本号>)\n" -"\n" -"\n" -" (rule ...)\n" -"# 规则语句：(rule <规则名> <规则语句> ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"### 规则语句\n" -"\n" -" (constraint ...)\n" -"# 约束语句：(constraint <约束类型> ...)\n" -"\n" -" (condition \"\")\n" -"# 条件语句：(condition \"<条件表达式>\")\n" -"\n" -" (layer \"\")\n" -"# 层语句：(layer \"<层名>\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"### 约束类型\n" -"\n" -" * annular\\_width\n" -"# （孔铜环宽度）\n" -" * clearance\n" -"# （间隙）\n" -" * courtyard_clearance\n" -"# （封装外框之间的间隙）\n" -" * diff\\_pair\\_gap\n" -"# （差分对间隙）\n" -" * diff\\_pair\\_uncoupled\n" -"# （对布线从该对中的另一个极性布线解耦的距离）\n" -" * disallow\n" -"# （不允许）\n" -" * edge\\_clearance\n" -"# （与板边的间隙）\n" -" * length\n" -"# （长度）\n" -" * hole\n" -"# （通孔）\n" -" * hole\\_clearance\n" -"# （与通孔的间隙）\n" -" * silk\\_clearance\n" -"# （与丝印的间隙）\n" -" * skew\n" -"# （总偏差）\n" -" * track\\_width\n" -"# （布线线宽）\n" -" * via\\_count\n" -"# （过孔个数）\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"### 电路板元素类型\n" -"\n" -" * buried_via\n" -"# （埋孔）\n" -" * graphic\n" -"# （图形）\n" -" * hole\n" -"# （通孔）\n" -" * micro_via\n" -"# （微孔）\n" -" * pad\n" -"# （焊盘）\n" -" * text\n" -"# （文本）\n" -" * track\n" -"# （布线）\n" -" * via\n" -"# （过孔）\n" -" * zone\n" -"# （敷铜）\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"### 范例\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -"# (rule 高压间距\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -"# (rule 外层高压间距\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -"# (rule 高压之间间距\n" -" # wider clearance between HV tracks\n" -" # 高压线路之间间距应该更大\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -"# (rule 无护罩高压线路\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### \n" -"\n" -"版本语句标志着文件的语法版本，所以版本语句必须是第一个语句，\n" -"以便将来的 KiCad 解析新版本的规则文件。版本应设为“1”。\n" -"\n" -"规则应该以优先级排序。后面的规则优先于前面的规则；\n" -"且一旦检测到某个规则成功匹配，则其余的规则均被忽略。\n" -"\n" -"使用 Ctrl+/ 来对选中的行添加或取消注释。\n" -"


\n" -"\n" -"### Expression functions\n" -"### 表达式函数\n" -"\n" -"函数的参数均支持简单的通配符（`*` 和 `?`）。\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"# A.insideCourtyard('<封装位号>')\n" -"若 `A` 的任何部分落在指定封装的主要外框中，则为真。\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"若 `A` 的任何部分落在指定封装的顶层外框中，则为真。\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"若 `A` 的任何部分落在指定封装的底层外框中，则为真。\n" -"

\n" -"\n" -" A.insideArea('')\n" -"若 `A` 的任何部分落在指定区域中，则为真。\n" -"

\n" -"\n" -" A.isPlated()\n" -"若 `A` 含/是铜孔，则为真。\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"# A.inDiffPair('<网络名>')\n" -"若 `A` 含有指定差分对的网络，则为真。\n" -"`<网络名>` 是指定差分对的基础名称。例如， `inDiffPair('CLK')`\n" -"matches items in the `CLK_P` and `CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"若 `A` 和 `B` 分别具有同一差分对的两个网络，则为真。\n" -"

\n" -"\n" -" A.memberOf('')\n" -"# A.memberOf('<组名>')\n" -"若 `A` 是指定组中的成员，则为真。组内嵌套的组也包括在内。\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"# A.existsOnLayer('<层名>')\n" -"若 `A` 在指定的层中，则为真。层名可以是“电路板设置 >\n" -"电路板编辑图层”菜单中指定的名称，也可以是内部最简名称\n" -"（如 `F.Cu`）。\n" -"\n" -"注：不论是否正在检查指定的层，只要 `A` 在该层上，\n" -"此条件即为真。对这样的使用场景，请在规则中使用\n" -"`(layer \"层名\")`。\n" -"\n" -"


\n" -"\n" -"### 更多的范例\n" -"\n" -" (rule \"copper keepout\"\n" -"# (rule \"禁止铜区\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -"# (rule \"BGA 加粗\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" # 禁止盖油过孔上印字\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\" \n" -"# (rule \"不同网络的过孔的间距\" \n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\" \n" -"# (rule \"不同网络的焊盘的间距\" \n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\" \n" -"# (rule \"过孔到焊盘的间距\" \n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" -" \n" -" (rule \"Pad to Track Clearance\" \n" -"# (rule \"焊盘到导线的间距\" \n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -"# (rule \"1mm宽开槽周围的间距\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\" \n" -"# (rule \"最大机械孔孔径\" \n" -" (constraint hole (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -" \n" -" (rule \"Max Drill Hole Size PTH\" \n" -"# (rule \"最大铜孔孔径\" \n" -" (constraint hole (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" # 给单独的差分对设置最优（opt）间距\n" -" (rule \"dp clock gap\"\n" -"# (rule \"差分对信号间距\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" # 给任意差分对周围扩大间距\n" -" (rule \"dp clearance\"\n" -"# (rule \"差分对外间距\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "新标注对象的默认属性：" @@ -28998,13 +28529,13 @@ msgstr "正在检查敷铜..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -29014,7 +28545,7 @@ msgstr "正在检查敷铜..." msgid "(%s clearance %s; actual %s)" msgstr "(%s 间隙 %s; 实际 %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(网络 %s 和 %s)" @@ -30695,7 +30226,7 @@ msgstr "散热片" msgid "Castellated" msgstr "邮票孔" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "直径" @@ -31032,7 +30563,7 @@ msgstr "盲孔/埋孔" msgid "Through Via" msgstr "通孔" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "钻孔" @@ -31055,23 +30586,23 @@ msgstr "导线 (圆弧) %s 位于 %s，长度 %s" msgid "Track %s on %s, length %s" msgstr "布线 %s (%s), 长度：%s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "原点 X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "原点 Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "图层顶部" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "图层底部" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "过孔类型" @@ -33497,24 +33028,24 @@ msgstr "旋转" msgid "Change Side / Flip" msgstr "更改所在面 / 翻转" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "精确移动" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "复制 %d 项" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "为副本选择参考点..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "选择已复制" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "已取消复制" @@ -35704,39 +35235,39 @@ msgstr "隐藏所有其他网络类" msgid "Presets (Ctrl+Tab):" msgstr "预设 (Ctrl+Tab)：" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "保存预设..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "删除预设..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "层预设名称：" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "保存层预设" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "预设" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "删除预设" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "选择预设：" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "打开偏好设置" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." @@ -36036,6 +35567,480 @@ msgstr "KiCad 原理图" msgid "KiCad Printed Circuit Board" msgstr "KiCad 印刷电路板" +#~ msgid "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('/CLK')`\n" +#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" +#~ msgstr "" +#~ "### Top-level Clauses\n" +#~ "### 顶层语句\n" +#~ "\n" +#~ " (version )\n" +#~ "# 版本语句：(version <版本号>)\n" +#~ "\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "# 规则语句：(rule <规则名> <规则语句> ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "### 规则语句\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "# 约束语句：(constraint <约束类型> ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "# 条件语句：(condition \"<条件表达式>\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "# 层语句：(layer \"<层名>\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "### 约束类型\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ "# （孔铜环宽度）\n" +#~ " * clearance\n" +#~ "# （间隙）\n" +#~ " * courtyard_clearance\n" +#~ "# （封装外框之间的间隙）\n" +#~ " * diff\\_pair\\_gap\n" +#~ "# （差分对间隙）\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ "# （对布线从该对中的另一个极性布线解耦的距离）\n" +#~ " * disallow\n" +#~ "# （不允许）\n" +#~ " * edge\\_clearance\n" +#~ "# （与板边的间隙）\n" +#~ " * length\n" +#~ "# （长度）\n" +#~ " * hole\n" +#~ "# （通孔）\n" +#~ " * hole\\_clearance\n" +#~ "# （与通孔的间隙）\n" +#~ " * silk\\_clearance\n" +#~ "# （与丝印的间隙）\n" +#~ " * skew\n" +#~ "# （总偏差）\n" +#~ " * track\\_width\n" +#~ "# （布线线宽）\n" +#~ " * via\\_count\n" +#~ "# （过孔个数）\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "### 电路板元素类型\n" +#~ "\n" +#~ " * buried_via\n" +#~ "# （埋孔）\n" +#~ " * graphic\n" +#~ "# （图形）\n" +#~ " * hole\n" +#~ "# （通孔）\n" +#~ " * micro_via\n" +#~ "# （微孔）\n" +#~ " * pad\n" +#~ "# （焊盘）\n" +#~ " * text\n" +#~ "# （文本）\n" +#~ " * track\n" +#~ "# （布线）\n" +#~ " * via\n" +#~ "# （过孔）\n" +#~ " * zone\n" +#~ "# （敷铜）\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "### 范例\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ "# (rule 高压间距\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ "# (rule 外层高压间距\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ "# (rule 高压之间间距\n" +#~ " # wider clearance between HV tracks\n" +#~ " # 高压线路之间间距应该更大\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ "# (rule 无护罩高压线路\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### \n" +#~ "\n" +#~ "版本语句标志着文件的语法版本，所以版本语句必须是第一个语句，\n" +#~ "以便将来的 KiCad 解析新版本的规则文件。版本应设为“1”。\n" +#~ "\n" +#~ "规则应该以优先级排序。后面的规则优先于前面的规则；\n" +#~ "且一旦检测到某个规则成功匹配，则其余的规则均被忽略。\n" +#~ "\n" +#~ "使用 Ctrl+/ 来对选中的行添加或取消注释。\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "### 表达式函数\n" +#~ "\n" +#~ "函数的参数均支持简单的通配符（`*` 和 `?`）。\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "# A.insideCourtyard('<封装位号>')\n" +#~ "若 `A` 的任何部分落在指定封装的主要外框中，则为真。\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "若 `A` 的任何部分落在指定封装的顶层外框中，则为真。\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "若 `A` 的任何部分落在指定封装的底层外框中，则为真。\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "若 `A` 的任何部分落在指定区域中，则为真。\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "若 `A` 含/是铜孔，则为真。\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "# A.inDiffPair('<网络名>')\n" +#~ "若 `A` 含有指定差分对的网络，则为真。\n" +#~ "`<网络名>` 是指定差分对的基础名称。例如， `inDiffPair('CLK')`\n" +#~ "matches items in the `CLK_P` and `CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "若 `A` 和 `B` 分别具有同一差分对的两个网络，则为真。\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "# A.memberOf('<组名>')\n" +#~ "若 `A` 是指定组中的成员，则为真。组内嵌套的组也包括在内。\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "# A.existsOnLayer('<层名>')\n" +#~ "若 `A` 在指定的层中，则为真。层名可以是“电路板设置 >\n" +#~ "电路板编辑图层”菜单中指定的名称，也可以是内部最简名称\n" +#~ "（如 `F.Cu`）。\n" +#~ "\n" +#~ "注：不论是否正在检查指定的层，只要 `A` 在该层上，\n" +#~ "此条件即为真。对这样的使用场景，请在规则中使用\n" +#~ "`(layer \"层名\")`。\n" +#~ "\n" +#~ "


\n" +#~ "\n" +#~ "### 更多的范例\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ "# (rule \"禁止铜区\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ "# (rule \"BGA 加粗\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " # 禁止盖油过孔上印字\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\" \n" +#~ "# (rule \"不同网络的过孔的间距\" \n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\" \n" +#~ "# (rule \"不同网络的焊盘的间距\" \n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\" \n" +#~ "# (rule \"过孔到焊盘的间距\" \n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" +#~ " \n" +#~ " (rule \"Pad to Track Clearance\" \n" +#~ "# (rule \"焊盘到导线的间距\" \n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ "# (rule \"1mm宽开槽周围的间距\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\" \n" +#~ "# (rule \"最大机械孔孔径\" \n" +#~ " (constraint hole (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ " \n" +#~ " (rule \"Max Drill Hole Size PTH\" \n" +#~ "# (rule \"最大铜孔孔径\" \n" +#~ " (constraint hole (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " # 给单独的差分对设置最优（opt）间距\n" +#~ " (rule \"dp clock gap\"\n" +#~ "# (rule \"差分对信号间距\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " # 给任意差分对周围扩大间距\n" +#~ " (rule \"dp clearance\"\n" +#~ "# (rule \"差分对外间距\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" + #, fuzzy, c-format #~ msgid "Unable to locate padstack %s in file %s\n" #~ msgstr "无法创建压缩文件 \"%s\"。\n" diff --git a/translation/pofiles/zh_TW.po b/translation/pofiles/zh_TW.po index a602e2d03f..507558859b 100644 --- a/translation/pofiles/zh_TW.po +++ b/translation/pofiles/zh_TW.po @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2022-09-29 19:10-0700\n" +"POT-Creation-Date: 2022-10-07 11:37-0700\n" "PO-Revision-Date: 2022-03-25 21:11+0000\n" "Last-Translator: taotieren \n" "Language-Team: Chinese (Traditional) = 0." msgstr "多邊形輪廓厚度必須大於等於 0." -#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:444 +#: pcbnew/dialogs/dialog_graphic_item_properties.cpp:437 msgid "Error List" msgstr "錯誤列表" @@ -26463,17 +26463,17 @@ msgid "Via type:" msgstr "過孔型別：" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1112 +#: pcbnew/pcb_track.cpp:1107 msgid "Through" msgstr "通孔" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1114 +#: pcbnew/pcb_track.cpp:1109 msgid "Micro" msgstr "微孔" #: pcbnew/dialogs/dialog_track_via_properties_base.cpp:255 -#: pcbnew/pcb_track.cpp:1113 +#: pcbnew/pcb_track.cpp:1108 msgid "Blind/buried" msgstr "盲孔/埋孔" @@ -27913,475 +27913,6 @@ msgstr "DRC 規則：" msgid "Check rule syntax" msgstr "檢查規則語法" -#: pcbnew/dialogs/panel_setup_rules_help_md.h:2 -msgid "" -"### Top-level Clauses\n" -"\n" -" (version )\n" -"\n" -" (rule ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"\n" -" (constraint ...)\n" -"\n" -" (condition \"\")\n" -"\n" -" (layer \"\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"\n" -" * annular\\_width\n" -" * clearance\n" -" * courtyard_clearance\n" -" * diff\\_pair\\_gap\n" -" * diff\\_pair\\_uncoupled\n" -" * disallow\n" -" * edge\\_clearance\n" -" * length\n" -" * hole\\_clearance\n" -" * hole\\_size\n" -" * silk\\_clearance\n" -" * skew\n" -" * track\\_width\n" -" * via\\_count\n" -" * via\\_diameter\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"\n" -" * buried_via\n" -" * graphic\n" -" * hole\n" -" * micro_via\n" -" * pad\n" -" * text\n" -" * track\n" -" * via\n" -" * zone\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -" # wider clearance between HV tracks\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### Notes\n" -"\n" -"Version clause must be the first clause. It indicates the syntax version of " -"the file so that \n" -"future rules parsers can perform automatic updates. It should be\n" -"set to \"1\".\n" -"\n" -"Rules should be ordered by specificity. Later rules take\n" -"precedence over earlier rules; once a matching rule is found\n" -"no further rules will be checked.\n" -"\n" -"Use Ctrl+/ to comment or uncomment line(s).\n" -"


\n" -"\n" -"### Expression functions\n" -"\n" -"All function parameters support simple wildcards (`*` and `?`).\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"True if any part of `A` lies within the given footprint's principal " -"courtyard.\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"True if any part of `A` lies within the given footprint's front courtyard.\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"True if any part of `A` lies within the given footprint's back courtyard.\n" -"

\n" -"\n" -" A.insideArea('')\n" -"True if any part of `A` lies within the given zone's outline.\n" -"

\n" -"\n" -" A.isPlated()\n" -"True if `A` has a hole which is plated.\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"True if `A` has net that is part of the specified differential pair.\n" -"`` is the base name of the differential pair. For example, " -"`inDiffPair('/CLK')`\n" -"matches items in the `/CLK_P` and `/CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"True if `A` and `B` are members of the same diff pair.\n" -"

\n" -"\n" -" A.memberOf('')\n" -"True if `A` is a member of the given group. Includes nested membership.\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"True if `A` exists on the given layer. The layer name can be\n" -"either the name assigned in Board Setup > Board Editor Layers or\n" -"the canonical name (ie: `F.Cu`).\n" -"\n" -"NB: this returns true if `A` is on the given layer, independently\n" -"of whether or not the rule is being evaluated for that layer.\n" -"For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -"


\n" -"\n" -"### More Examples\n" -"\n" -" (rule \"copper keepout\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\"\n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\"\n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\"\n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -"\n" -" (rule \"Pad to Track Clearance\"\n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\"\n" -" (constraint hole_size (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -"\n" -" (rule \"Max Drill Hole Size PTH\"\n" -" (constraint hole_size (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" (rule \"dp clock gap\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('/CLK')\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" (rule \"dp clearance\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -msgstr "" -"### Top-level Clauses\n" -"### 頂層語句\n" -"\n" -" (version )\n" -"# 版本語句：(version <版本號>)\n" -"\n" -"\n" -" (rule ...)\n" -"# 規則語句：(rule <規則名> <規則語句> ...)\n" -"\n" -"\n" -"

\n" -"\n" -"### Rule Clauses\n" -"### 規則語句\n" -"\n" -" (constraint ...)\n" -"# 約束語句：(constraint <約束型別> ...)\n" -"\n" -" (condition \"\")\n" -"# 條件語句：(condition \"<條件表示式>\")\n" -"\n" -" (layer \"\")\n" -"# 層語句：(layer \"<層名>\")\n" -"\n" -"\n" -"

\n" -"\n" -"### Constraint Types\n" -"### 約束型別\n" -"\n" -" * annular\\_width\n" -"# （孔銅環寬度）\n" -" * clearance\n" -"# （間隙）\n" -" * courtyard_clearance\n" -"# （封裝外框之間的間隙）\n" -" * diff\\_pair\\_gap\n" -"# （差分對間隙）\n" -" * diff\\_pair\\_uncoupled\n" -"# （對佈線從該對中的另一個極性佈線解耦的距離）\n" -" * disallow\n" -"# （不允許）\n" -" * edge\\_clearance\n" -"# （與板邊的間隙）\n" -" * length\n" -"# （長度）\n" -" * hole\n" -"# （通孔）\n" -" * hole\\_clearance\n" -"# （與通孔的間隙）\n" -" * silk\\_clearance\n" -"# （與絲印的間隙）\n" -" * skew\n" -"# （總偏差）\n" -" * track\\_width\n" -"# （佈線線寬）\n" -" * via\\_count\n" -"# （過孔個數）\n" -"\n" -"\n" -"

\n" -"\n" -"### Item Types\n" -"### 電路板元素型別\n" -"\n" -" * buried_via\n" -"# （埋孔）\n" -" * graphic\n" -"# （圖形）\n" -" * hole\n" -"# （通孔）\n" -" * micro_via\n" -"# （微孔）\n" -" * pad\n" -"# （焊盤）\n" -" * text\n" -"# （文字）\n" -" * track\n" -"# （佈線）\n" -" * via\n" -"# （過孔）\n" -" * zone\n" -"# （敷銅）\n" -"\n" -"
\n" -"\n" -"### Examples\n" -"### 範例\n" -"\n" -" (version 1)\n" -"\n" -" (rule HV\n" -"# (rule 高壓間距\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV\n" -"# (rule 外層高壓間距\n" -" (layer outer)\n" -" (constraint clearance (min 1.5mm))\n" -" (condition \"A.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_HV\n" -"# (rule 高壓之間間距\n" -" # wider clearance between HV tracks\n" -" # 高壓線路之間間距應該更大\n" -" (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -" (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -"\n" -"\n" -" (rule HV_unshielded\n" -"# (rule 無護罩高壓線路\n" -" (constraint clearance (min 2mm))\n" -" (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" -"

\n" -"\n" -"### \n" -"\n" -"版本語句標誌著檔案的語法版本，所以版本語句必須是第一個語句，\n" -"以便將來的 KiCad 解析新版本的規則檔案。版本應設為“1”。\n" -"\n" -"規則應該以優先順序排序。後面的規則優先於前面的規則；\n" -"且一旦檢測到某個規則成功匹配，則其餘的規則均被忽略。\n" -"\n" -"使用 Ctrl+/ 來對選中的行新增或取消註釋。\n" -"


\n" -"\n" -"### Expression functions\n" -"### 表示式函式\n" -"\n" -"函式的引數均支援簡單的萬用字元（`*` 和 `?`）。\n" -"

\n" -"\n" -" A.insideCourtyard('')\n" -"# A.insideCourtyard('<封裝位號>')\n" -"若 `A` 的任何部分落在指定封裝的主要外框中，則為真。\n" -"

\n" -"\n" -" A.insideFrontCourtyard('')\n" -"若 `A` 的任何部分落在指定封裝的頂層外框中，則為真。\n" -"

\n" -"\n" -" A.insideBackCourtyard('')\n" -"若 `A` 的任何部分落在指定封裝的底層外框中，則為真。\n" -"

\n" -"\n" -" A.insideArea('')\n" -"若 `A` 的任何部分落在指定區域中，則為真。\n" -"

\n" -"\n" -" A.isPlated()\n" -"若 `A` 含/是銅孔，則為真。\n" -"

\n" -"\n" -" A.inDiffPair('')\n" -"# A.inDiffPair('<網路名>')\n" -"若 `A` 含有指定差分對的網路，則為真。\n" -"`<網路名>` 是指定差分對的基礎名稱。例如， `inDiffPair('CLK')`\n" -"matches items in the `CLK_P` and `CLK_N` nets.\n" -"

\n" -"\n" -" AB.isCoupledDiffPair()\n" -"若 `A` 和 `B` 分別具有同一差分對的兩個網路，則為真。\n" -"

\n" -"\n" -" A.memberOf('')\n" -"# A.memberOf('<組名>')\n" -"若 `A` 是指定組中的成員，則為真。組內巢狀的組也包括在內。\n" -"

\n" -"\n" -" A.existsOnLayer('')\n" -"# A.existsOnLayer('<層名>')\n" -"若 `A` 在指定的層中，則為真。層名可以是“電路板設定 >\n" -"電路板編輯圖層”選單中指定的名稱，也可以是內部最簡名稱\n" -"（如 `F.Cu`）。\n" -"\n" -"注：不論是否正在檢查指定的層，只要 `A` 在該層上，\n" -"此條件即為真。對這樣的使用場景，請在規則中使用\n" -"`(layer \"層名\")`。\n" -"\n" -"


\n" -"\n" -"### 更多的範例\n" -"\n" -" (rule \"copper keepout\"\n" -"# (rule \"禁止銅區\"\n" -" (constraint disallow track via zone)\n" -" (condition \"A.insideArea('zone3')\"))\n" -"\n" -"\n" -" (rule \"BGA neckdown\"\n" -"# (rule \"BGA 加粗\"\n" -" (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -" (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -" (condition \"A.insideCourtyard('U3')\"))\n" -"\n" -"\n" -" # prevent silk over tented vias\n" -" # 禁止蓋油過孔上印字\n" -" (rule silk_over_via\n" -" (constraint silk_clearance (min 0.2mm))\n" -" (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -"\n" -"\n" -" (rule \"Distance between Vias of Different Nets\" \n" -"# (rule \"不同網路的過孔的間距\" \n" -" (constraint hole_to_hole (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net\"))\n" -"\n" -" (rule \"Clearance between Pads of Different Nets\" \n" -"# (rule \"不同網路的焊盤的間距\" \n" -" (constraint clearance (min 3.0mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net\"))\n" -"\n" -"\n" -" (rule \"Via Hole to Track Clearance\" \n" -"# (rule \"過孔到焊盤的間距\" \n" -" (constraint hole_clearance (min 0.254mm))\n" -" (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" -" \n" -" (rule \"Pad to Track Clearance\" \n" -"# (rule \"焊盤到導線的間距\" \n" -" (constraint clearance (min 0.2mm))\n" -" (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" -"\n" -"\n" -" (rule \"clearance-to-1mm-cutout\"\n" -"# (rule \"1mm寬開槽周圍的間距\"\n" -" (constraint clearance (min 0.8mm))\n" -" (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -"\n" -"\n" -" (rule \"Max Drill Hole Size Mechanical\" \n" -"# (rule \"最大機械孔孔徑\" \n" -" (constraint hole (max 6.3mm))\n" -" (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -" \n" -" (rule \"Max Drill Hole Size PTH\" \n" -"# (rule \"最大銅孔孔徑\" \n" -" (constraint hole (max 6.35mm))\n" -" (condition \"A.Pad_Type == 'Through-hole'\"))\n" -"\n" -"\n" -" # Specify an optimal gap for a particular diff-pair\n" -" # 給單獨的差分對設定最優（opt）間距\n" -" (rule \"dp clock gap\"\n" -"# (rule \"差分對訊號間距\"\n" -" (constraint diff_pair_gap (opt \"0.8mm\"))\n" -" (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" -"\n" -" # Specify a larger clearance around any diff-pair\n" -" # 給任意差分對周圍擴大間距\n" -" (rule \"dp clearance\"\n" -"# (rule \"差分對外間距\"\n" -" (constraint clearance (min \"1.5mm\"))\n" -" (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" - #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:72 msgid "Default properties for new dimension objects:" msgstr "新標註物件的預設屬性：" @@ -28976,13 +28507,13 @@ msgstr "正在檢查敷銅..." #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:312 #: pcbnew/drc/drc_test_provider_copper_clearance.cpp:378 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:468 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:514 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:704 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:733 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:756 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:782 -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1020 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:463 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:509 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:699 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:728 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:751 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:777 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:1015 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:214 #: pcbnew/drc/drc_test_provider_courtyard_clearance.cpp:242 #: pcbnew/drc/drc_test_provider_edge_clearance.cpp:101 @@ -28992,7 +28523,7 @@ msgstr "正在檢查敷銅..." msgid "(%s clearance %s; actual %s)" msgstr "(%s 間隙 %s; 實際 %s)" -#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:679 +#: pcbnew/drc/drc_test_provider_copper_clearance.cpp:674 #, c-format msgid "(nets %s and %s)" msgstr "(網路 %s 和 %s)" @@ -30674,7 +30205,7 @@ msgstr "散熱片" msgid "Castellated" msgstr "郵票孔" -#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1169 +#: pcbnew/pad.cpp:1004 pcbnew/pcb_track.cpp:742 pcbnew/pcb_track.cpp:1164 msgid "Diameter" msgstr "直徑" @@ -31010,7 +30541,7 @@ msgstr "盲孔/埋孔" msgid "Through Via" msgstr "通孔" -#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1171 +#: pcbnew/pcb_track.cpp:746 pcbnew/pcb_track.cpp:1166 msgid "Drill" msgstr "鑽孔" @@ -31033,23 +30564,23 @@ msgstr "導線 (圓弧) %s 位於 %s，長度 %s" msgid "Track %s on %s, length %s" msgstr "佈線 %s (%s), 長度：%s" -#: pcbnew/pcb_track.cpp:1135 pcbnew/pcb_track.cpp:1152 +#: pcbnew/pcb_track.cpp:1130 pcbnew/pcb_track.cpp:1147 msgid "Origin X" msgstr "原點 X" -#: pcbnew/pcb_track.cpp:1138 pcbnew/pcb_track.cpp:1155 +#: pcbnew/pcb_track.cpp:1133 pcbnew/pcb_track.cpp:1150 msgid "Origin Y" msgstr "原點 Y" -#: pcbnew/pcb_track.cpp:1174 +#: pcbnew/pcb_track.cpp:1169 msgid "Layer Top" msgstr "圖層頂部" -#: pcbnew/pcb_track.cpp:1176 +#: pcbnew/pcb_track.cpp:1171 msgid "Layer Bottom" msgstr "圖層底部" -#: pcbnew/pcb_track.cpp:1178 +#: pcbnew/pcb_track.cpp:1173 msgid "Via Type" msgstr "過孔型別" @@ -33471,24 +33002,24 @@ msgstr "旋轉" msgid "Change Side / Flip" msgstr "更改所在面 / 翻轉" -#: pcbnew/tools/edit_tool.cpp:2107 +#: pcbnew/tools/edit_tool.cpp:2112 msgid "Move exact" msgstr "精確移動" -#: pcbnew/tools/edit_tool.cpp:2240 +#: pcbnew/tools/edit_tool.cpp:2245 #, c-format msgid "Duplicated %d item(s)" msgstr "複製 %d 項" -#: pcbnew/tools/edit_tool.cpp:2463 +#: pcbnew/tools/edit_tool.cpp:2468 msgid "Select reference point for the copy..." msgstr "為副本選擇參考點..." -#: pcbnew/tools/edit_tool.cpp:2464 pcbnew/tools/edit_tool.cpp:2481 +#: pcbnew/tools/edit_tool.cpp:2469 pcbnew/tools/edit_tool.cpp:2486 msgid "Selection copied" msgstr "選擇已複製" -#: pcbnew/tools/edit_tool.cpp:2465 +#: pcbnew/tools/edit_tool.cpp:2470 msgid "Copy canceled" msgstr "已取消複製" @@ -35678,39 +35209,39 @@ msgstr "隱藏所有其他網路類" msgid "Presets (Ctrl+Tab):" msgstr "預設 (Ctrl+Tab)：" -#: pcbnew/widgets/appearance_controls.cpp:2422 +#: pcbnew/widgets/appearance_controls.cpp:2432 msgid "Save preset..." msgstr "儲存預設..." -#: pcbnew/widgets/appearance_controls.cpp:2423 +#: pcbnew/widgets/appearance_controls.cpp:2433 msgid "Delete preset..." msgstr "刪除預設..." -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Layer preset name:" msgstr "層預設名稱：" -#: pcbnew/widgets/appearance_controls.cpp:2501 +#: pcbnew/widgets/appearance_controls.cpp:2534 msgid "Save Layer Preset" msgstr "儲存層預設" -#: pcbnew/widgets/appearance_controls.cpp:2545 +#: pcbnew/widgets/appearance_controls.cpp:2578 msgid "Presets" msgstr "預設" -#: pcbnew/widgets/appearance_controls.cpp:2557 +#: pcbnew/widgets/appearance_controls.cpp:2590 msgid "Delete Preset" msgstr "刪除預設" -#: pcbnew/widgets/appearance_controls.cpp:2558 +#: pcbnew/widgets/appearance_controls.cpp:2591 msgid "Select preset:" msgstr "選擇預設：" -#: pcbnew/widgets/appearance_controls.cpp:3033 +#: pcbnew/widgets/appearance_controls.cpp:3066 msgid "Open Preferences" msgstr "開啟偏好設定" -#: pcbnew/widgets/appearance_controls.cpp:3047 +#: pcbnew/widgets/appearance_controls.cpp:3080 msgid "" "The current color theme is read-only. Create a new theme in Preferences to " "enable color editing." @@ -36010,6 +35541,480 @@ msgstr "KiCad 原理圖" msgid "KiCad Printed Circuit Board" msgstr "KiCad 印刷電路板" +#~ msgid "" +#~ "### Top-level Clauses\n" +#~ "\n" +#~ " (version )\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ " * clearance\n" +#~ " * courtyard_clearance\n" +#~ " * diff\\_pair\\_gap\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ " * disallow\n" +#~ " * edge\\_clearance\n" +#~ " * length\n" +#~ " * hole\\_clearance\n" +#~ " * hole\\_size\n" +#~ " * silk\\_clearance\n" +#~ " * skew\n" +#~ " * track\\_width\n" +#~ " * via\\_count\n" +#~ " * via\\_diameter\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "\n" +#~ " * buried_via\n" +#~ " * graphic\n" +#~ " * hole\n" +#~ " * micro_via\n" +#~ " * pad\n" +#~ " * text\n" +#~ " * track\n" +#~ " * via\n" +#~ " * zone\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ " # wider clearance between HV tracks\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### Notes\n" +#~ "\n" +#~ "Version clause must be the first clause. It indicates the syntax version " +#~ "of the file so that \n" +#~ "future rules parsers can perform automatic updates. It should be\n" +#~ "set to \"1\".\n" +#~ "\n" +#~ "Rules should be ordered by specificity. Later rules take\n" +#~ "precedence over earlier rules; once a matching rule is found\n" +#~ "no further rules will be checked.\n" +#~ "\n" +#~ "Use Ctrl+/ to comment or uncomment line(s).\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "\n" +#~ "All function parameters support simple wildcards (`*` and `?`).\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's principal " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's front " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "True if any part of `A` lies within the given footprint's back " +#~ "courtyard.\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "True if any part of `A` lies within the given zone's outline.\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "True if `A` has a hole which is plated.\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "True if `A` has net that is part of the specified differential pair.\n" +#~ "`` is the base name of the differential pair. For example, " +#~ "`inDiffPair('/CLK')`\n" +#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "True if `A` and `B` are members of the same diff pair.\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "True if `A` is a member of the given group. Includes nested membership.\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "True if `A` exists on the given layer. The layer name can be\n" +#~ "either the name assigned in Board Setup > Board Editor Layers or\n" +#~ "the canonical name (ie: `F.Cu`).\n" +#~ "\n" +#~ "NB: this returns true if `A` is on the given layer, independently\n" +#~ "of whether or not the rule is being evaluated for that layer.\n" +#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" +#~ "


\n" +#~ "\n" +#~ "### More Examples\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\"\n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\"\n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\"\n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" +#~ "\n" +#~ " (rule \"Pad to Track Clearance\"\n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\"\n" +#~ " (constraint hole_size (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size PTH\"\n" +#~ " (constraint hole_size (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " (rule \"dp clock gap\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('/CLK')\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " (rule \"dp clearance\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" +#~ msgstr "" +#~ "### Top-level Clauses\n" +#~ "### 頂層語句\n" +#~ "\n" +#~ " (version )\n" +#~ "# 版本語句：(version <版本號>)\n" +#~ "\n" +#~ "\n" +#~ " (rule ...)\n" +#~ "# 規則語句：(rule <規則名> <規則語句> ...)\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Rule Clauses\n" +#~ "### 規則語句\n" +#~ "\n" +#~ " (constraint ...)\n" +#~ "# 約束語句：(constraint <約束型別> ...)\n" +#~ "\n" +#~ " (condition \"\")\n" +#~ "# 條件語句：(condition \"<條件表示式>\")\n" +#~ "\n" +#~ " (layer \"\")\n" +#~ "# 層語句：(layer \"<層名>\")\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Constraint Types\n" +#~ "### 約束型別\n" +#~ "\n" +#~ " * annular\\_width\n" +#~ "# （孔銅環寬度）\n" +#~ " * clearance\n" +#~ "# （間隙）\n" +#~ " * courtyard_clearance\n" +#~ "# （封裝外框之間的間隙）\n" +#~ " * diff\\_pair\\_gap\n" +#~ "# （差分對間隙）\n" +#~ " * diff\\_pair\\_uncoupled\n" +#~ "# （對佈線從該對中的另一個極性佈線解耦的距離）\n" +#~ " * disallow\n" +#~ "# （不允許）\n" +#~ " * edge\\_clearance\n" +#~ "# （與板邊的間隙）\n" +#~ " * length\n" +#~ "# （長度）\n" +#~ " * hole\n" +#~ "# （通孔）\n" +#~ " * hole\\_clearance\n" +#~ "# （與通孔的間隙）\n" +#~ " * silk\\_clearance\n" +#~ "# （與絲印的間隙）\n" +#~ " * skew\n" +#~ "# （總偏差）\n" +#~ " * track\\_width\n" +#~ "# （佈線線寬）\n" +#~ " * via\\_count\n" +#~ "# （過孔個數）\n" +#~ "\n" +#~ "\n" +#~ "

\n" +#~ "\n" +#~ "### Item Types\n" +#~ "### 電路板元素型別\n" +#~ "\n" +#~ " * buried_via\n" +#~ "# （埋孔）\n" +#~ " * graphic\n" +#~ "# （圖形）\n" +#~ " * hole\n" +#~ "# （通孔）\n" +#~ " * micro_via\n" +#~ "# （微孔）\n" +#~ " * pad\n" +#~ "# （焊盤）\n" +#~ " * text\n" +#~ "# （文字）\n" +#~ " * track\n" +#~ "# （佈線）\n" +#~ " * via\n" +#~ "# （過孔）\n" +#~ " * zone\n" +#~ "# （敷銅）\n" +#~ "\n" +#~ "
\n" +#~ "\n" +#~ "### Examples\n" +#~ "### 範例\n" +#~ "\n" +#~ " (version 1)\n" +#~ "\n" +#~ " (rule HV\n" +#~ "# (rule 高壓間距\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV\n" +#~ "# (rule 外層高壓間距\n" +#~ " (layer outer)\n" +#~ " (constraint clearance (min 1.5mm))\n" +#~ " (condition \"A.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_HV\n" +#~ "# (rule 高壓之間間距\n" +#~ " # wider clearance between HV tracks\n" +#~ " # 高壓線路之間間距應該更大\n" +#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" +#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule HV_unshielded\n" +#~ "# (rule 無護罩高壓線路\n" +#~ " (constraint clearance (min 2mm))\n" +#~ " (condition \"A.NetClass == 'HV' && !A.insideArea('Shield*')\"))\n" +#~ "

\n" +#~ "\n" +#~ "### \n" +#~ "\n" +#~ "版本語句標誌著檔案的語法版本，所以版本語句必須是第一個語句，\n" +#~ "以便將來的 KiCad 解析新版本的規則檔案。版本應設為“1”。\n" +#~ "\n" +#~ "規則應該以優先順序排序。後面的規則優先於前面的規則；\n" +#~ "且一旦檢測到某個規則成功匹配，則其餘的規則均被忽略。\n" +#~ "\n" +#~ "使用 Ctrl+/ 來對選中的行新增或取消註釋。\n" +#~ "


\n" +#~ "\n" +#~ "### Expression functions\n" +#~ "### 表示式函式\n" +#~ "\n" +#~ "函式的引數均支援簡單的萬用字元（`*` 和 `?`）。\n" +#~ "

\n" +#~ "\n" +#~ " A.insideCourtyard('')\n" +#~ "# A.insideCourtyard('<封裝位號>')\n" +#~ "若 `A` 的任何部分落在指定封裝的主要外框中，則為真。\n" +#~ "

\n" +#~ "\n" +#~ " A.insideFrontCourtyard('')\n" +#~ "若 `A` 的任何部分落在指定封裝的頂層外框中，則為真。\n" +#~ "

\n" +#~ "\n" +#~ " A.insideBackCourtyard('')\n" +#~ "若 `A` 的任何部分落在指定封裝的底層外框中，則為真。\n" +#~ "

\n" +#~ "\n" +#~ " A.insideArea('')\n" +#~ "若 `A` 的任何部分落在指定區域中，則為真。\n" +#~ "

\n" +#~ "\n" +#~ " A.isPlated()\n" +#~ "若 `A` 含/是銅孔，則為真。\n" +#~ "

\n" +#~ "\n" +#~ " A.inDiffPair('')\n" +#~ "# A.inDiffPair('<網路名>')\n" +#~ "若 `A` 含有指定差分對的網路，則為真。\n" +#~ "`<網路名>` 是指定差分對的基礎名稱。例如， `inDiffPair('CLK')`\n" +#~ "matches items in the `CLK_P` and `CLK_N` nets.\n" +#~ "

\n" +#~ "\n" +#~ " AB.isCoupledDiffPair()\n" +#~ "若 `A` 和 `B` 分別具有同一差分對的兩個網路，則為真。\n" +#~ "

\n" +#~ "\n" +#~ " A.memberOf('')\n" +#~ "# A.memberOf('<組名>')\n" +#~ "若 `A` 是指定組中的成員，則為真。組內巢狀的組也包括在內。\n" +#~ "

\n" +#~ "\n" +#~ " A.existsOnLayer('')\n" +#~ "# A.existsOnLayer('<層名>')\n" +#~ "若 `A` 在指定的層中，則為真。層名可以是“電路板設定 >\n" +#~ "電路板編輯圖層”選單中指定的名稱，也可以是內部最簡名稱\n" +#~ "（如 `F.Cu`）。\n" +#~ "\n" +#~ "注：不論是否正在檢查指定的層，只要 `A` 在該層上，\n" +#~ "此條件即為真。對這樣的使用場景，請在規則中使用\n" +#~ "`(layer \"層名\")`。\n" +#~ "\n" +#~ "


\n" +#~ "\n" +#~ "### 更多的範例\n" +#~ "\n" +#~ " (rule \"copper keepout\"\n" +#~ "# (rule \"禁止銅區\"\n" +#~ " (constraint disallow track via zone)\n" +#~ " (condition \"A.insideArea('zone3')\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"BGA neckdown\"\n" +#~ "# (rule \"BGA 加粗\"\n" +#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" +#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" +#~ " (condition \"A.insideCourtyard('U3')\"))\n" +#~ "\n" +#~ "\n" +#~ " # prevent silk over tented vias\n" +#~ " # 禁止蓋油過孔上印字\n" +#~ " (rule silk_over_via\n" +#~ " (constraint silk_clearance (min 0.2mm))\n" +#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Distance between Vias of Different Nets\" \n" +#~ "# (rule \"不同網路的過孔的間距\" \n" +#~ " (constraint hole_to_hole (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Via' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ " (rule \"Clearance between Pads of Different Nets\" \n" +#~ "# (rule \"不同網路的焊盤的間距\" \n" +#~ " (constraint clearance (min 3.0mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Pad' && A.Net != B.Net" +#~ "\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Via Hole to Track Clearance\" \n" +#~ "# (rule \"過孔到焊盤的間距\" \n" +#~ " (constraint hole_clearance (min 0.254mm))\n" +#~ " (condition \"A.Type =='Via' && B.Type =='Track'\"))\n" +#~ " \n" +#~ " (rule \"Pad to Track Clearance\" \n" +#~ "# (rule \"焊盤到導線的間距\" \n" +#~ " (constraint clearance (min 0.2mm))\n" +#~ " (condition \"A.Type =='Pad' && B.Type =='Track'\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"clearance-to-1mm-cutout\"\n" +#~ "# (rule \"1mm寬開槽周圍的間距\"\n" +#~ " (constraint clearance (min 0.8mm))\n" +#~ " (condition \"A.Layer=='Edge.Cuts' && A.Thickness == 1.0mm\"))\n" +#~ "\n" +#~ "\n" +#~ " (rule \"Max Drill Hole Size Mechanical\" \n" +#~ "# (rule \"最大機械孔孔徑\" \n" +#~ " (constraint hole (max 6.3mm))\n" +#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" +#~ " \n" +#~ " (rule \"Max Drill Hole Size PTH\" \n" +#~ "# (rule \"最大銅孔孔徑\" \n" +#~ " (constraint hole (max 6.35mm))\n" +#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" +#~ "\n" +#~ "\n" +#~ " # Specify an optimal gap for a particular diff-pair\n" +#~ " # 給單獨的差分對設定最優（opt）間距\n" +#~ " (rule \"dp clock gap\"\n" +#~ "# (rule \"差分對訊號間距\"\n" +#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" +#~ " (condition \"A.inDiffPair('CLK') && AB.isCoupledDiffPair()\"))\n" +#~ "\n" +#~ " # Specify a larger clearance around any diff-pair\n" +#~ " # 給任意差分對周圍擴大間距\n" +#~ " (rule \"dp clearance\"\n" +#~ "# (rule \"差分對外間距\"\n" +#~ " (constraint clearance (min \"1.5mm\"))\n" +#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" + #, fuzzy, c-format #~ msgid "Unable to locate padstack %s in file %s\n" #~ msgstr "無法建立壓縮檔案 \"%s\"\n"