diff --git a/pcbnew/class_drc_item.cpp b/pcbnew/class_drc_item.cpp
index 1ea794734d..cfd8d5cea9 100644
--- a/pcbnew/class_drc_item.cpp
+++ b/pcbnew/class_drc_item.cpp
@@ -71,6 +71,10 @@ wxString DRC_ITEM::GetErrorText() const
         return wxString( _( "Via hole > diameter" ) );
     case DRCE_MICRO_VIA_INCORRECT_LAYER_PAIR:
         return wxString( _( "Micro Via: incorrect layer pairs (not adjacent)" ) );
+    case DRCE_MICRO_VIA_NOT_ALLOWED:
+        return wxString( _( "Micro Via: not allowed" ) );
+    case DRCE_BURIED_VIA_NOT_ALLOWED:
+        return wxString( _( "Buried Via: not allowed" ) );
     case COPPERAREA_INSIDE_COPPERAREA:
         return wxString( _( "Copper area inside copper area" ) );
     case COPPERAREA_CLOSE_TO_COPPERAREA:
diff --git a/pcbnew/drc_clearance_test_functions.cpp b/pcbnew/drc_clearance_test_functions.cpp
index b397606f75..e395e7d517 100644
--- a/pcbnew/drc_clearance_test_functions.cpp
+++ b/pcbnew/drc_clearance_test_functions.cpp
@@ -202,11 +202,31 @@ bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads )
             return false;
         }
 
+        // test if the type of via is allowed due to design rules
+        if( ( refvia->GetViaType() == VIA_MICROVIA ) &&
+            ( m_pcb->GetDesignSettings().m_MicroViasAllowed == false ) )
+        {
+            m_currentMarker = fillMarker( refvia, NULL,
+                    DRCE_MICRO_VIA_NOT_ALLOWED, m_currentMarker );
+            return false;
+        }
+
+        // test if the type of via is allowed due to design rules
+        if( ( refvia->GetViaType() == VIA_BLIND_BURIED ) &&
+            ( m_pcb->GetDesignSettings().m_BlindBuriedViaAllowed == false ) )
+        {
+            m_currentMarker = fillMarker( refvia, NULL,
+                    DRCE_BURIED_VIA_NOT_ALLOWED, m_currentMarker );
+            return false;
+        }
+
         // For microvias: test if they are blind vias and only between 2 layers
         // because they are used for very small drill size and are drill by laser
         // and **only one layer** can be drilled
         if( refvia->GetViaType() == VIA_MICROVIA )
         {
+
+
             PCB_LAYER_ID    layer1, layer2;
             bool        err = true;
 
@@ -227,6 +247,7 @@ bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads )
                 return false;
             }
         }
+
     }
     else    // This is a track segment
     {
diff --git a/pcbnew/drc_stuff.h b/pcbnew/drc_stuff.h
index 85166e1030..c2792e7541 100644
--- a/pcbnew/drc_stuff.h
+++ b/pcbnew/drc_stuff.h
@@ -36,6 +36,10 @@
 #define BAD_DRC 1
 
 
+// DRC error codes could be defined by an enum.
+// however a #define is used because error code value is displayed in DRC messages,
+// and using #define that shows each numerical value helps for debug.
+
 /// DRC error codes:
 #define DRCE_                                  1    // not used yet
 #define DRCE_UNCONNECTED_ITEMS                 2    ///< items are unconnected
@@ -83,7 +87,9 @@
 #define DRCE_OVERLAPPING_FOOTPRINTS            44   ///< footprint courtyards overlap
 #define DRCE_MISSING_COURTYARD_IN_FOOTPRINT    45   ///< footprint has no courtyard defined
 #define DRCE_MALFORMED_COURTYARD_IN_FOOTPRINT  46   ///< footprint has a courtyard but malformed
-                                                    ///< (not convetrible to polygon)
+                                                    ///< (not convertible to a closed polygon with holes)
+#define DRCE_MICRO_VIA_NOT_ALLOWED             47   ///< micro vias are not allowed
+#define DRCE_BURIED_VIA_NOT_ALLOWED            48   ///< buried vias are not allowed
 
 
 class EDA_DRAW_PANEL;