From 9e48b388fe80881096cf06ba71184e25026a01ec Mon Sep 17 00:00:00 2001 From: Seth Hillbrand Date: Tue, 28 Nov 2023 16:01:11 -0800 Subject: [PATCH] Add additional QA sliver check --- qa/data/pcbnew/issue16182.kicad_dru | 52 + qa/data/pcbnew/issue16182.kicad_pcb | 3461 ++++++++++++++++++++++++++ qa/data/pcbnew/issue16182.kicad_pro | 271 ++ qa/tests/pcbnew/test_zone_filler.cpp | 48 + 4 files changed, 3832 insertions(+) create mode 100644 qa/data/pcbnew/issue16182.kicad_dru create mode 100644 qa/data/pcbnew/issue16182.kicad_pcb create mode 100644 qa/data/pcbnew/issue16182.kicad_pro diff --git a/qa/data/pcbnew/issue16182.kicad_dru b/qa/data/pcbnew/issue16182.kicad_dru new file mode 100644 index 0000000000..ab1c317149 --- /dev/null +++ b/qa/data/pcbnew/issue16182.kicad_dru @@ -0,0 +1,52 @@ +(version 1) + +#Clearance for U101 +(rule "U101 clearance" + (constraint clearance (min 0.127mm)) + (condition "A.insideCourtyard('U101')")) + +#Clearance for U102 +(rule "U102 clearance" + (constraint clearance (min 0.127mm)) + (condition "A.insideCourtyard('U102')")) + +#Clearance for U201 +(rule "U201 clearance" + (constraint clearance (min 0.127mm)) + (condition "A.insideCourtyard('U201')")) + +#Clearance for U601 +(rule "U601 clearance" + (constraint clearance (min 0.127mm)) + (condition "A.insideCourtyard('U601')")) + +#Clearance for J202 +(rule "J202 clearance" + (constraint clearance (min 0.127mm)) + (condition "A.insideBackCourtyard('J202')")) + +#Clearance for J501 +(rule "J501 clearance" + (constraint clearance (min 0.127mm)) + (condition "A.insideCourtyard('J501')")) + +#Clearance for TVS diode arrays +(rule "TVS_Array clearance" + (constraint clearance (min 0.127mm)) + (condition "A.insideCourtyard('D6*') ")) + +#Ignore silkscreen overlap violations in rule area(s) 'interlocking_terminals' +(rule allow_silk_clearance_violation + (constraint silk_clearance (min -1mm)) + (condition "A.insideArea('interlocking_terminals')")) + +#Ignore courtyard overlap violations in rule area(s) 'interlocking_terminals' +#Doesn't seem to work, just exclude the violations for now.. +(rule allow_court_clearance_violation + (constraint courtyard_clearance (min -2mm)) + (condition "A.insideArea('interlocking_terminals')")) + +#Maintain clearance for outer layer copper pours (else overriden by above) +(rule "outer_pour clearance" + (constraint clearance (min 0.4mm)) + (condition "A.Name == 'outer_pour'")) diff --git a/qa/data/pcbnew/issue16182.kicad_pcb b/qa/data/pcbnew/issue16182.kicad_pcb new file mode 100644 index 0000000000..80345526f2 --- /dev/null +++ b/qa/data/pcbnew/issue16182.kicad_pcb @@ -0,0 +1,3461 @@ +(kicad_pcb (version 20231007) (generator pcbnew) + + (general + (thickness 1.6062) + ) + + (paper "A4") + (title_block + (title "grblPANEL") + (date "2023-04-28") + (rev "B") + (company "dresco") + ) + + (layers + (0 "F.Cu" signal) + (1 "In1.Cu" power) + (2 "In2.Cu" power) + (31 "B.Cu" signal) + (32 "B.Adhes" user "B.Adhesive") + (33 "F.Adhes" user "F.Adhesive") + (34 "B.Paste" user) + (35 "F.Paste" user) + (36 "B.SilkS" user "B.Silkscreen") + (37 "F.SilkS" user "F.Silkscreen") + (38 "B.Mask" user) + (39 "F.Mask" user) + (40 "Dwgs.User" user "User.Drawings") + (41 "Cmts.User" user "User.Comments") + (42 "Eco1.User" user "User.Eco1") + (43 "Eco2.User" user "User.Eco2") + (44 "Edge.Cuts" user) + (45 "Margin" user) + (46 "B.CrtYd" user "B.Courtyard") + (47 "F.CrtYd" user "F.Courtyard") + (48 "B.Fab" user) + (49 "F.Fab" user) + (50 "User.1" user) + (51 "User.2" user) + (52 "User.3" user) + (53 "User.4" user) + (54 "User.5" user) + (55 "User.6" user) + (56 "User.7" user) + (57 "User.8" user) + (58 "User.9" user) + ) + + (setup + (stackup + (layer "F.SilkS" (type "Top Silk Screen")) + (layer "F.Paste" (type "Top Solder Paste")) + (layer "F.Mask" (type "Top Solder Mask") (color "Black") (thickness 0.01)) + (layer "F.Cu" (type "copper") (thickness 0.035)) + (layer "dielectric 1" (type "prepreg") (thickness 0.2104) (material "FR4") (epsilon_r 4.6) (loss_tangent 0.02)) + (layer "In1.Cu" (type "copper") (thickness 0.0152)) + (layer "dielectric 2" (type "core") (thickness 1.065) (material "FR4") (epsilon_r 4.6) (loss_tangent 0.02)) + (layer "In2.Cu" (type "copper") (thickness 0.0152)) + (layer "dielectric 3" (type "prepreg") (thickness 0.2104) (material "FR4") (epsilon_r 4.6) (loss_tangent 0.02)) + (layer "B.Cu" (type "copper") (thickness 0.035)) + (layer "B.Mask" (type "Bottom Solder Mask") (color "Black") (thickness 0.01)) + (layer "B.Paste" (type "Bottom Solder Paste")) + (layer "B.SilkS" (type "Bottom Silk Screen")) + (copper_finish "ENIG") + (dielectric_constraints yes) + ) + (pad_to_mask_clearance 0) + (pcbplotparams + (layerselection 0x00010fc_ffffffff) + (plot_on_all_layers_selection 0x0000000_00000000) + (disableapertmacros false) + (usegerberextensions true) + (usegerberattributes true) + (usegerberadvancedattributes false) + (creategerberjobfile false) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 6) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups true) + (pdf_back_fp_property_popups true) + (dxfpolygonmode true) + (dxfimperialunits true) + (dxfusepcbnewfont true) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue false) + (plotfptext true) + (plotinvisibletext false) + (sketchpadsonfab false) + (subtractmaskfromsilk true) + (outputformat 1) + (mirror false) + (drillshape 0) + (scaleselection 1) + (outputdirectory "manufacturing/") + ) + ) + + (net 0 "") + (net 1 "GND") + (net 2 "/Power/VIN_PI_OUT") + (net 3 "+3V3") + (net 4 "/MCU/~{RST}") + (net 5 "/Power/PWR_LED_K") + (net 6 "DISPLAY_D{slash}C") + (net 7 "DISPLAY_SDA") + (net 8 "Net-(JP401-B)") + (net 9 "Net-(R202-Pad1)") + (net 10 "/MCU/LED_K") + (net 11 "/MCU/SWCLK{slash}BOOT0") + (net 12 "MODBUS_RX") + (net 13 "MODBUS_TX") + (net 14 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164.5 112.4) + (xy 162.9 112.4) + (xy 162.9 111.3) + (xy 164.5 109.8) + (xy 167.8 109.8) + ) + ) + ) + (zone (net 0) (net_name "") (layer "B.SilkS") (tstamp 46ad1240-798c-4e4c-aa7b-61fb3df10f24) (name "interlocking_terminals") (hatch edge 0.508) + (connect_pads (clearance 0)) + (min_thickness 0.254) (filled_areas_thickness no) + (keepout (tracks allowed) (vias allowed) (pads allowed) (copperpour allowed) (footprints allowed)) + (fill (thermal_gap 0.508) (thermal_bridge_width 0.508)) + (polygon + (pts + (xy 162.5 130.5) + (xy 104.8 130.5) + (xy 104.8 121.2) + (xy 162.5 121.2) + ) + ) + ) +) diff --git a/qa/data/pcbnew/issue16182.kicad_pro b/qa/data/pcbnew/issue16182.kicad_pro new file mode 100644 index 0000000000..ac9239c115 --- /dev/null +++ b/qa/data/pcbnew/issue16182.kicad_pro @@ -0,0 +1,271 @@ +{ + "board": { + "3dviewports": [], + "design_settings": { + "defaults": { + "apply_defaults_to_fp_fields": false, + "apply_defaults_to_fp_shapes": false, + "apply_defaults_to_fp_text": false, + "board_outline_line_width": 0.049999999999999996, + "copper_line_width": 0.19999999999999998, + "copper_text_italic": false, + "copper_text_size_h": 1.5, + "copper_text_size_v": 1.5, + "copper_text_thickness": 0.3, + "copper_text_upright": false, + "courtyard_line_width": 0.049999999999999996, + "dimension_precision": 4, + "dimension_units": 3, + "dimensions": { + "arrow_length": 1270000, + "extension_offset": 500000, + "keep_text_aligned": true, + "suppress_zeroes": false, + "text_position": 0, + "units_format": 1 + }, + "fab_line_width": 0.09999999999999999, + "fab_text_italic": false, + "fab_text_size_h": 1.0, + "fab_text_size_v": 1.0, + "fab_text_thickness": 0.15, + "fab_text_upright": false, + "other_line_width": 0.09999999999999999, + "other_text_italic": false, + "other_text_size_h": 1.0, + "other_text_size_v": 1.0, + "other_text_thickness": 0.15, + "other_text_upright": false, + "pads": { + "drill": 0.762, + "height": 1.524, + "width": 1.524 + }, + "silk_line_width": 0.09999999999999999, + "silk_text_italic": false, + "silk_text_size_h": 1.0, + "silk_text_size_v": 1.0, + "silk_text_thickness": 0.09999999999999999, + "silk_text_upright": false, + "zones": { + "min_clearance": 0.508 + } + }, + "diff_pair_dimensions": [], + "drc_exclusions": [], + "meta": { + "version": 2 + }, + "rule_severities": { + "annular_width": "error", + "clearance": "error", + "connection_width": "warning", + "copper_edge_clearance": "error", + "copper_sliver": "warning", + "courtyards_overlap": "error", + "diff_pair_gap_out_of_range": "error", + "diff_pair_uncoupled_length_too_long": "error", + "drill_out_of_range": "error", + "duplicate_footprints": "warning", + "extra_footprint": "warning", + "footprint": "error", + "footprint_type_mismatch": "ignore", + "hole_clearance": "error", + "hole_near_hole": "error", + "invalid_outline": "error", + "isolated_copper": "warning", + "item_on_disabled_layer": "error", + "items_not_allowed": "error", + "length_out_of_range": "error", + "lib_footprint_issues": "warning", + "lib_footprint_mismatch": "warning", + "malformed_courtyard": "error", + "microvia_drill_out_of_range": "error", + "missing_courtyard": "ignore", + "missing_footprint": "warning", + "net_conflict": "warning", + "npth_inside_courtyard": "ignore", + "padstack": "warning", + "pth_inside_courtyard": "ignore", + "shorting_items": "error", + "silk_edge_clearance": "warning", + "silk_over_copper": "warning", + "silk_overlap": "warning", + "skew_out_of_range": "error", + "solder_mask_bridge": "error", + "starved_thermal": "error", + "text_height": "warning", + "text_thickness": "warning", + "through_hole_pad_without_hole": "error", + "too_many_vias": "error", + "track_dangling": "warning", + "track_width": "error", + "tracks_crossing": "error", + "unconnected_items": "error", + "unresolved_variable": "error", + "via_dangling": "warning", + "zones_intersect": "error" + }, + "rules": { + "max_error": 0.005, + "min_clearance": 0.0, + "min_connection": 0.0, + "min_copper_edge_clearance": 0.5, + "min_hole_clearance": 0.25, + "min_hole_to_hole": 0.25, + "min_microvia_diameter": 0.19999999999999998, + "min_microvia_drill": 0.09999999999999999, + "min_resolved_spokes": 2, + "min_silk_clearance": 0.0, + "min_text_height": 0.7999999999999999, + "min_text_thickness": 0.08, + "min_through_hole_diameter": 0.3, + "min_track_width": 0.0, + "min_via_annular_width": 0.09999999999999999, + "min_via_diameter": 0.5, + "solder_mask_to_copper_clearance": 0.0, + "use_height_for_length_calcs": true + }, + "teardrop_options": [ + { + "td_onpadsmd": true, + "td_onroundshapesonly": false, + "td_ontrackend": false, + "td_onviapad": true + } + ], + "teardrop_parameters": [ + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_round_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_rect_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_track_end", + "td_width_to_size_filter_ratio": 0.9 + } + ], + "track_widths": [], + "tuning_pattern_settings": { + "diff_pair_defaults": { + "corner_radius_percentage": 100, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.1, + "single_sided": false, + "spacing": 0.6 + }, + "diff_pair_skew_defaults": { + "corner_radius_percentage": 100, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.1, + "single_sided": false, + "spacing": 0.6 + }, + "single_track_defaults": { + "corner_radius_percentage": 100, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.1, + "single_sided": false, + "spacing": 0.6 + } + }, + "via_dimensions": [], + "zones_allow_external_fillets": false + }, + "ipc2581": { + "dist": "", + "distpn": "", + "internal_id": "", + "mfg": "", + "mpn": "" + }, + "layer_presets": [], + "viewports": [] + }, + "boards": [], + "cvpcb": { + "equivalence_files": [] + }, + "libraries": { + "pinned_footprint_libs": [], + "pinned_symbol_libs": [] + }, + "meta": { + "filename": "issue16182.kicad_pro", + "version": 1 + }, + "net_settings": { + "classes": [ + { + "bus_width": 12, + "clearance": 0.2, + "diff_pair_gap": 0.25, + "diff_pair_via_gap": 0.25, + "diff_pair_width": 0.2, + "line_style": 0, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "Default", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.2, + "via_diameter": 0.6, + "via_drill": 0.3, + "wire_width": 6 + } + ], + "meta": { + "version": 3 + }, + "net_colors": null, + "netclass_assignments": null, + "netclass_patterns": [] + }, + "pcbnew": { + "last_paths": { + "gencad": "", + "idf": "", + "netlist": "", + "plot": "", + "pos_files": "", + "specctra_dsn": "", + "step": "", + "svg": "", + "vrml": "" + }, + "page_layout_descr_file": "" + }, + "schematic": { + "legacy_lib_dir": "", + "legacy_lib_list": [] + }, + "sheets": [], + "text_variables": {} +} diff --git a/qa/tests/pcbnew/test_zone_filler.cpp b/qa/tests/pcbnew/test_zone_filler.cpp index 93641a13e0..0718baf619 100644 --- a/qa/tests/pcbnew/test_zone_filler.cpp +++ b/qa/tests/pcbnew/test_zone_filler.cpp @@ -222,3 +222,51 @@ BOOST_FIXTURE_TEST_CASE( RegressionZoneFillTests, ZONE_FILL_TEST_FIXTURE ) } } + +BOOST_FIXTURE_TEST_CASE( RegressionSliverZoneFillTests, ZONE_FILL_TEST_FIXTURE ) +{ + std::vector tests = { "issue16182" // Slivers + }; + + for( const wxString& relPath : tests ) + { + KI_TEST::LoadBoard( m_settingsManager, relPath, m_board ); + + BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings(); + + KI_TEST::FillZones( m_board.get() ); + + std::vector violations; + + bds.m_DRCEngine->SetViolationHandler( + [&]( const std::shared_ptr& aItem, VECTOR2I aPos, int aLayer ) + { + if( aItem->GetErrorCode() == DRCE_COPPER_SLIVER ) + violations.push_back( *aItem ); + } ); + + bds.m_DRCEngine->RunTests( EDA_UNITS::MILLIMETRES, true, false ); + + if( violations.empty() ) + { + BOOST_CHECK_EQUAL( 1, 1 ); // quiet "did not check any assertions" warning + BOOST_TEST_MESSAGE( (const char*)(wxString::Format( "Zone fill copper sliver regression: %s passed", relPath ).utf8_str()) ); + } + else + { + UNITS_PROVIDER unitsProvider( pcbIUScale, EDA_UNITS::INCHES ); + + std::map itemMap; + m_board->FillItemMap( itemMap ); + + for( const DRC_ITEM& item : violations ) + { + BOOST_TEST_MESSAGE( item.ShowReport( &unitsProvider, RPT_SEVERITY_ERROR, + itemMap ) ); + } + + BOOST_ERROR( (const char*)(wxString::Format( "Zone fill copper sliver regression: %s failed", relPath ).utf8_str()) ); + } + } +} +