diff --git a/pcbnew/drc/drc_test_provider_courtyard_clearance.cpp b/pcbnew/drc/drc_test_provider_courtyard_clearance.cpp index 2772d9f329..39cb51f830 100644 --- a/pcbnew/drc/drc_test_provider_courtyard_clearance.cpp +++ b/pcbnew/drc/drc_test_provider_courtyard_clearance.cpp @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include #include @@ -34,6 +36,8 @@ - DRCE_OVERLAPPING_FOOTPRINTS - DRCE_MISSING_COURTYARD - DRCE_MALFORMED_COURTYARD + - DRCE_PTH_IN_COURTYARD, + - DRCE_NPTH_IN_COURTYARD, TODO: do an actual clearance check instead of polygon intersection. Treat closed outlines as filled and allow open curves in the courtyard. @@ -145,9 +149,6 @@ bool DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testCourtyardClearances() { const int delta = 100; // This is the number of tests between 2 calls to the progress bar - if( m_drcEngine->IsErrorLimitExceeded( DRCE_OVERLAPPING_FOOTPRINTS) ) - return true; // continue with other tests - if( !reportPhase( _( "Checking footprints for overlapping courtyards..." ) ) ) return false; // DRC cancelled @@ -158,15 +159,24 @@ bool DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testCourtyardClearances() if( !reportProgress( ii++, m_board->Footprints().size(), delta ) ) return false; // DRC cancelled - if( m_drcEngine->IsErrorLimitExceeded( DRCE_OVERLAPPING_FOOTPRINTS) ) - break; + if( m_drcEngine->IsErrorLimitExceeded( DRCE_OVERLAPPING_FOOTPRINTS) + && m_drcEngine->IsErrorLimitExceeded( DRCE_PTH_IN_COURTYARD ) + && m_drcEngine->IsErrorLimitExceeded( DRCE_NPTH_IN_COURTYARD ) ) + { + return true; // continue with other tests + } FOOTPRINT* fpA = *itA; const SHAPE_POLY_SET& frontA = fpA->GetPolyCourtyard( F_CrtYd ); const SHAPE_POLY_SET& backA = fpA->GetPolyCourtyard( B_CrtYd ); - if( frontA.OutlineCount() == 0 && backA.OutlineCount() == 0 ) - continue; // No courtyards defined + if( frontA.OutlineCount() == 0 && backA.OutlineCount() == 0 + && m_drcEngine->IsErrorLimitExceeded( DRCE_PTH_IN_COURTYARD ) + && m_drcEngine->IsErrorLimitExceeded( DRCE_NPTH_IN_COURTYARD ) ) + { + // No courtyards defined and no hole testing against other footprint's courtyards + continue; + } BOX2I frontBBox = frontA.BBoxFromCaches(); BOX2I backBBox = backA.BBoxFromCaches(); @@ -174,9 +184,12 @@ bool DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testCourtyardClearances() frontBBox.Inflate( m_largestClearance ); backBBox.Inflate( m_largestClearance ); + EDA_RECT fpABBox = fpA->GetBoundingBox(); + for( auto itB = itA + 1; itB != m_board->Footprints().end(); itB++ ) { FOOTPRINT* fpB = *itB; + EDA_RECT fpBBBox = fpB->GetBoundingBox(); const SHAPE_POLY_SET& frontB = fpB->GetPolyCourtyard( F_CrtYd ); const SHAPE_POLY_SET& backB = fpB->GetPolyCourtyard( B_CrtYd ); DRC_CONSTRAINT constraint; @@ -237,6 +250,48 @@ bool DRC_TEST_PROVIDER_COURTYARD_CLEARANCE::testCourtyardClearances() reportViolation( drce, (wxPoint) pos ); } } + + auto testPadAgainstCourtyards = + [&]( const PAD* pad, const FOOTPRINT* footprint ) + { + int errorCode = 0; + + if( pad->GetAttribute() == PAD_ATTRIB::PTH ) + errorCode = DRCE_PTH_IN_COURTYARD; + else if( pad->GetAttribute() == PAD_ATTRIB::NPTH ) + errorCode = DRCE_NPTH_IN_COURTYARD; + else + return; + + if( m_drcEngine->IsErrorLimitExceeded( errorCode ) ) + return; + + const SHAPE_SEGMENT* hole = pad->GetEffectiveHoleShape(); + const SHAPE_POLY_SET& front = footprint->GetPolyCourtyard( F_CrtYd ); + const SHAPE_POLY_SET& back = footprint->GetPolyCourtyard( B_CrtYd ); + + if( ( front.OutlineCount() > 0 && front.Collide( hole, 0 ) ) + || ( back.OutlineCount() > 0 && back.Collide( hole, 0 ) ) ) + { + std::shared_ptr drce = DRC_ITEM::Create( errorCode ); + drce->SetItems( pad, footprint ); + reportViolation( drce, pad->GetPosition() ); + } + }; + + if( ( frontA.OutlineCount() > 0 && frontA.BBoxFromCaches().Intersects( fpBBBox ) ) + || ( backA.OutlineCount() > 0 && backA.BBoxFromCaches().Intersects( fpBBBox ) ) ) + { + for( const PAD* padB : fpB->Pads() ) + testPadAgainstCourtyards( padB, fpA ); + } + + if( ( frontB.OutlineCount() > 0 && frontB.BBoxFromCaches().Intersects( fpABBox ) ) + || ( backB.OutlineCount() > 0 && backB.BBoxFromCaches().Intersects( fpABBox ) ) ) + { + for( const PAD* padA : fpA->Pads() ) + testPadAgainstCourtyards( padA, fpB ); + } } } diff --git a/qa/data/issue9081.kicad_pcb b/qa/data/issue9081.kicad_pcb new file mode 100644 index 0000000000..6a6eb98980 --- /dev/null +++ b/qa/data/issue9081.kicad_pcb @@ -0,0 +1,215 @@ +(kicad_pcb (version 20210824) (generator pcbnew) + + (general + (thickness 1.6) + ) + + (paper "A4") + (layers + (0 "F.Cu" signal) + (31 "B.Cu" signal) + (32 "B.Adhes" user "B.Adhesive") + (33 "F.Adhes" user "F.Adhesive") + (34 "B.Paste" user) + (35 "F.Paste" user) + (36 "B.SilkS" user "B.Silkscreen") + (37 "F.SilkS" user "F.Silkscreen") + (38 "B.Mask" user) + (39 "F.Mask" user) + (40 "Dwgs.User" user "User.Drawings") + (41 "Cmts.User" user "User.Comments") + (42 "Eco1.User" user "User.Eco1") + (43 "Eco2.User" user "User.Eco2") + (44 "Edge.Cuts" user) + (45 "Margin" user) + (46 "B.CrtYd" user "B.Courtyard") + (47 "F.CrtYd" user "F.Courtyard") + (48 "B.Fab" user) + (49 "F.Fab" user) + (50 "User.1" user) + (51 "User.2" user) + (52 "User.3" user) + (53 "User.4" user) + (54 "User.5" user) + (55 "User.6" user) + (56 "User.7" user) + (57 "User.8" user) + (58 "User.9" user) + ) + + (setup + (stackup + (layer "F.SilkS" (type "Top Silk Screen")) + (layer "F.Paste" (type "Top Solder Paste")) + (layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01)) + (layer "F.Cu" (type "copper") (thickness 0.035)) + (layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02)) + (layer "B.Cu" (type "copper") (thickness 0.035)) + (layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01)) + (layer "B.Paste" (type "Bottom Solder Paste")) + (layer "B.SilkS" (type "Bottom Silk Screen")) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (pcbplotparams + (layerselection 0x00010fc_ffffffff) + (disableapertmacros false) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (svguseinch false) + (svgprecision 6) + (excludeedgelayer true) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (dxfpolygonmode true) + (dxfimperialunits true) + (dxfusepcbnewfont true) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + 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"board_outline_line_width": 0.09999999999999999, + "copper_line_width": 0.19999999999999998, + "copper_text_italic": false, + "copper_text_size_h": 1.5, + "copper_text_size_v": 1.5, + "copper_text_thickness": 0.3, + "copper_text_upright": false, + "courtyard_line_width": 0.049999999999999996, + "dimension_precision": 4, + "dimension_units": 3, + "dimensions": { + "arrow_length": 1270000, + "extension_offset": 500000, + "keep_text_aligned": true, + "suppress_zeroes": false, + "text_position": 0, + "units_format": 1 + }, + "fab_line_width": 0.09999999999999999, + "fab_text_italic": false, + "fab_text_size_h": 1.0, + "fab_text_size_v": 1.0, + "fab_text_thickness": 0.15, + "fab_text_upright": false, + "other_line_width": 0.15, + "other_text_italic": false, + "other_text_size_h": 1.0, + "other_text_size_v": 1.0, + "other_text_thickness": 0.15, + "other_text_upright": false, + "pads": { + "drill": 0.762, + "height": 1.524, + "width": 1.524 + }, + "silk_line_width": 0.15, + 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"error", + "pin_not_driven": "error", + "pin_to_pin": "warning", + "power_pin_not_driven": "error", + "similar_labels": "warning", + "unannotated": "error", + "unit_value_mismatch": "error", + "unresolved_variable": "error", + "wire_dangling": "error" + } + }, + "libraries": { + "pinned_footprint_libs": [], + "pinned_symbol_libs": [] + }, + "meta": { + "filename": "asdf_DRC_THThole_5.99.kicad_pro", + "version": 1 + }, + "net_settings": { + "classes": [ + { + "bus_width": 12.0, + "clearance": 0.2, + "diff_pair_gap": 0.25, + "diff_pair_via_gap": 0.25, + "diff_pair_width": 0.2, + "line_style": 0, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "Default", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.25, + "via_diameter": 0.8, + "via_drill": 0.4, + "wire_width": 6.0 + } + ], + "meta": { + "version": 0 + }, + "net_colors": null + }, + "pcbnew": { + "last_paths": { + "gencad": "", + "idf": "", + "netlist": "", + "specctra_dsn": "", + "step": "", + "vrml": "" + }, + "page_layout_descr_file": "" + }, + "schematic": { + "annotate_start_num": 0, + "drawing": { + "default_bus_thickness": 12.0, + "default_junction_size": 40.0, + "default_line_thickness": 6.0, + "default_text_size": 50.0, + "default_wire_thickness": 6.0, + "field_names": [], + "intersheets_ref_own_page": false, + "intersheets_ref_prefix": "", + "intersheets_ref_short": false, + "intersheets_ref_show": false, + "intersheets_ref_suffix": "", + "junction_size_choice": 3, + "label_size_ratio": 0.375, + "pin_symbol_size": 25.0, + "text_offset_ratio": 0.15 + }, + "legacy_lib_dir": "", + "legacy_lib_list": [], + "meta": { + "version": 1 + }, + "net_format_name": "", + "ngspice": { + "fix_include_paths": true, + "fix_passive_vals": false, + "meta": { + "version": 0 + }, + "model_mode": 0, + "workbook_filename": "" + }, + "page_layout_descr_file": "", + "plot_directory": "", + "spice_adjust_passive_values": false, + "spice_external_command": "spice \"%I\"", + "subpart_first_id": 65, + "subpart_id_separator": 0 + }, + "sheets": [ + [ + "f1329f92-898b-48fb-8d8c-becaafb4793f", + "" + ] + ], + "text_variables": {} +} diff --git a/qa/pcbnew/drc/test_drc_regressions.cpp b/qa/pcbnew/drc/test_drc_regressions.cpp index ed7e0b8f60..34bc5c5673 100644 --- a/qa/pcbnew/drc/test_drc_regressions.cpp +++ b/qa/pcbnew/drc/test_drc_regressions.cpp @@ -111,7 +111,8 @@ BOOST_FIXTURE_TEST_CASE( DRCFalseNegativeRegressions, DRC_REGRESSION_TEST_FIXTUR { "issue7241", 1 }, { "issue7267", 4 }, { "issue7325", 2 }, - { "issue8003", 2 } }; + { "issue8003", 2 }, + { "issue9081", 2 } }; for( const std::pair& entry : tests ) {