diff --git a/pcbnew/class_board.cpp b/pcbnew/class_board.cpp
index 09f008bc7b..6cc0803dc4 100644
--- a/pcbnew/class_board.cpp
+++ b/pcbnew/class_board.cpp
@@ -1335,40 +1335,40 @@ void BOARD::SynchronizeProperties()
 
 void BOARD::SynchronizeNetsAndNetClasses()
 {
-    if( m_project )
+    if( !m_project )
+        return;
+
+    NET_SETTINGS* netSettings     = m_project->GetProjectFile().m_NetSettings.get();
+    NETCLASSES&   netClasses      = netSettings->m_NetClasses;
+    NETCLASSPTR   defaultNetClass = netClasses.GetDefault();
+
+    for( NETINFO_ITEM* net : m_NetInfo )
     {
-        NET_SETTINGS* netSettings     = m_project->GetProjectFile().m_NetSettings.get();
-        NETCLASSES&   netClasses      = netSettings->m_NetClasses;
-        NETCLASSPTR   defaultNetClass = netClasses.GetDefault();
+        const wxString& netname = net->GetNetname();
 
-        for( NETINFO_ITEM* net : m_NetInfo )
+        if( netSettings->m_NetClassAssignments.count( netname ) )
         {
-            const wxString& netname = net->GetNetname();
-
-            if( netSettings->m_NetClassAssignments.count( netname ) )
-            {
-                const wxString& classname = netSettings->m_NetClassAssignments[ netname ];
-                net->SetClass( netClasses.Find( classname ) );
-            }
-            else
-            {
-                net->SetClass( defaultNetClass );
-            }
+            const wxString& classname = netSettings->m_NetClassAssignments[ netname ];
+            net->SetClass( netClasses.Find( classname ) );
+        }
+        else
+        {
+            net->SetClass( defaultNetClass );
         }
-
-        BOARD_DESIGN_SETTINGS& bds = GetDesignSettings();
-
-        // Set initial values for custom track width & via size to match the default
-        // netclass settings
-        bds.UseCustomTrackViaSize( false );
-        bds.SetCustomTrackWidth( defaultNetClass->GetTrackWidth() );
-        bds.SetCustomViaSize( defaultNetClass->GetViaDiameter() );
-        bds.SetCustomViaDrill( defaultNetClass->GetViaDrill() );
-        bds.SetCustomDiffPairWidth( defaultNetClass->GetDiffPairWidth() );
-        bds.SetCustomDiffPairGap( defaultNetClass->GetDiffPairGap() );
-        bds.SetCustomDiffPairViaGap( defaultNetClass->GetDiffPairViaGap() );
     }
 
+    BOARD_DESIGN_SETTINGS& bds = GetDesignSettings();
+
+    // Set initial values for custom track width & via size to match the default
+    // netclass settings
+    bds.UseCustomTrackViaSize( false );
+    bds.SetCustomTrackWidth( defaultNetClass->GetTrackWidth() );
+    bds.SetCustomViaSize( defaultNetClass->GetViaDiameter() );
+    bds.SetCustomViaDrill( defaultNetClass->GetViaDrill() );
+    bds.SetCustomDiffPairWidth( defaultNetClass->GetDiffPairWidth() );
+    bds.SetCustomDiffPairGap( defaultNetClass->GetDiffPairGap() );
+    bds.SetCustomDiffPairViaGap( defaultNetClass->GetDiffPairViaGap() );
+
     InvokeListeners( &BOARD_LISTENER::OnBoardNetSettingsChanged, *this );
 }
 
diff --git a/pcbnew/pcb_base_edit_frame.cpp b/pcbnew/pcb_base_edit_frame.cpp
index 209efaf1af..e59eb70969 100644
--- a/pcbnew/pcb_base_edit_frame.cpp
+++ b/pcbnew/pcb_base_edit_frame.cpp
@@ -142,22 +142,6 @@ void PCB_BASE_EDIT_FRAME::SetBoard( BOARD* aBoard )
 
     PCB_BASE_FRAME::SetBoard( aBoard );
 
-    if( new_board )
-    {
-        BOARD_DESIGN_SETTINGS& bds = aBoard->GetDesignSettings();
-        bds.m_DRCEngine = std::make_shared<DRC_ENGINE>( aBoard, &bds );
-
-        try
-        {
-            bds.m_DRCEngine->InitEngine( GetDesignRulesPath() );
-        }
-        catch( PARSE_ERROR& pe )
-        {
-            // TODO: We could redirect to Board Setup here and report the error.  Or we could
-            // wait till they run DRC or do an Inspect Clearance.  Not sure which is better....
-        }
-    }
-
     GetCanvas()->GetGAL()->SetGridOrigin( VECTOR2D( aBoard->GetDesignSettings().m_GridOrigin ) );
 
     // update the tool manager with the new board and its view.
@@ -170,7 +154,22 @@ void PCB_BASE_EDIT_FRAME::SetBoard( BOARD* aBoard )
                                        GetCanvas()->GetViewControls(), config(), this );
 
         if( new_board )
+        {
             m_toolManager->ResetTools( TOOL_BASE::MODEL_RELOAD );
+
+            BOARD_DESIGN_SETTINGS& bds = aBoard->GetDesignSettings();
+            bds.m_DRCEngine = std::make_shared<DRC_ENGINE>( aBoard, &bds );
+
+            try
+            {
+                bds.m_DRCEngine->InitEngine( GetDesignRulesPath() );
+            }
+            catch( PARSE_ERROR& pe )
+            {
+                // TODO: We could redirect to Board Setup here and report the error.  Or we could
+                // wait till they run DRC or do an Inspect Clearance.  Not sure which is better....
+            }
+        }
     }
 }
 
diff --git a/pcbnew/tools/drc_tool.cpp b/pcbnew/tools/drc_tool.cpp
index a09d7a60ae..3aa36de182 100644
--- a/pcbnew/tools/drc_tool.cpp
+++ b/pcbnew/tools/drc_tool.cpp
@@ -64,7 +64,7 @@ void DRC_TOOL::Reset( RESET_REASON aReason )
         m_drcEngine = m_pcb->GetDesignSettings().m_DRCEngine;
     }
 
-    if( aReason == MODEL_RELOAD )
+    if( aReason == MODEL_RELOAD && m_pcb->GetProject() )
     {
         try
         {
diff --git a/pcbnew/widgets/appearance_controls.cpp b/pcbnew/widgets/appearance_controls.cpp
index 0470c3c819..d495d5c603 100644
--- a/pcbnew/widgets/appearance_controls.cpp
+++ b/pcbnew/widgets/appearance_controls.cpp
@@ -1882,6 +1882,10 @@ void APPEARANCE_CONTROLS::rebuildNets()
     COLOR_SETTINGS* theme   = m_frame->GetColorSettings();
     COLOR4D         bgColor = theme->GetColor( LAYER_PCB_BACKGROUND );
 
+    // If the board isn't fully loaded, we can't yet rebuild
+    if( !board->GetProject() )
+        return;
+
     KIGFX::PCB_RENDER_SETTINGS* rs = static_cast<KIGFX::PCB_RENDER_SETTINGS*>(
             m_frame->GetCanvas()->GetView()->GetPainter()->GetSettings() );