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Support for a visibility flag and color selection to NPTH holes 

(when disabled they are shown as standard holes, a lot less distracting
than the previous fixed yellow color)
This commit is contained in:
Lorenzo Marcantonio 2013-04-07 18:20:46 +02:00
parent 204d085b64
commit b739b2b075
7 changed files with 38 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
common/class_colors_design_settings.cpp
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@ -40,6 +40,7 @@ static const EDA_COLOR_T default_items_color[LAYERSCOLORSBUFFERSIZE] =
CYAN, // VIA_MICROVIA_VISIBLE
BROWN, // VIA_BBLIND_VISIBLE
LIGHTGRAY, // VIA_THROUGH_VISIBLE
YELLOW, // NON_PLATED_VISIBLE
LIGHTGRAY, // MOD_TEXT_FR_VISIBLE
BLUE, // MOD_TEXT_BK_VISIBLE
DARKGRAY, // MOD_TEXT_INVISIBLE
@ -47,23 +48,15 @@ static const EDA_COLOR_T default_items_color[LAYERSCOLORSBUFFERSIZE] =
RED, // PAD_FR_VISIBLE
GREEN, // PAD_BK_VISIBLE
LIGHTGRAY, // RATSNEST_VISIBLE
DARKGRAY, //GRID_VISIBLE
DARKGRAY, // GRID_VISIBLE
LIGHTRED, LIGHTGRAY, LIGHTGRAY, LIGHTGRAY,
LIGHTGRAY, LIGHTGRAY,
LIGHTGRAY, LIGHTGRAY,
LIGHTGRAY, LIGHTGRAY,
LIGHTGRAY, LIGHTGRAY,
LIGHTGRAY,
LIGHTGRAY,
LIGHTGRAY,
LIGHTGRAY,
LIGHTGRAY,
LIGHTGRAY,
LIGHTGRAY,
LIGHTGRAY
LIGHTGRAY, LIGHTGRAY, LIGHTGRAY, LIGHTGRAY,
LIGHTGRAY, LIGHTGRAY, LIGHTGRAY, LIGHTGRAY,
LIGHTGRAY, LIGHTGRAY, LIGHTGRAY, LIGHTGRAY,
LIGHTGRAY, LIGHTGRAY, LIGHTGRAY
};
COLORS_DESIGN_SETTINGS:: COLORS_DESIGN_SETTINGS()
COLORS_DESIGN_SETTINGS::COLORS_DESIGN_SETTINGS()
{
for( unsigned ii = 0; ii < DIM(m_LayersColors); ii++ )
m_LayersColors[ii] = default_layer_color[ii];

1
include/layers_id_colors_and_visibility.h
View File

@ -196,6 +196,7 @@ enum PCB_VISIBLE
VIA_MICROVIA_VISIBLE,
VIA_BBLIND_VISIBLE,
VIA_THROUGH_VISIBLE,
NON_PLATED_VISIBLE,
MOD_TEXT_FR_VISIBLE,
MOD_TEXT_BK_VISIBLE,
MOD_TEXT_INVISIBLE, ///< text marked as invisible

2
pcbnew/class_board.cpp
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@ -637,6 +637,7 @@ EDA_COLOR_T BOARD::GetVisibleElementColor( int aPCB_VISIBLE )
switch( aPCB_VISIBLE )
{
case NON_PLATED_VISIBLE:
case VIA_THROUGH_VISIBLE:
case VIA_MICROVIA_VISIBLE:
case VIA_BBLIND_VISIBLE:
@ -663,6 +664,7 @@ void BOARD::SetVisibleElementColor( int aPCB_VISIBLE, EDA_COLOR_T aColor )
{
switch( aPCB_VISIBLE )
{
case NON_PLATED_VISIBLE:
case VIA_THROUGH_VISIBLE:
case VIA_MICROVIA_VISIBLE:
case VIA_BBLIND_VISIBLE:

2
pcbnew/class_pad.cpp
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@ -524,7 +524,7 @@ void D_PAD::GetMsgPanelInfo( std::vector< MSG_PANEL_ITEM>& aList )
wxString msg = module->GetReference();
aList.push_back( MSG_PANEL_ITEM( _( "Module" ), msg, DARKCYAN ) );
ReturnStringPadName( Line );
aList.push_back( MSG_PANEL_ITEM( _( "RefP" ), Line, BROWN ) );
aList.push_back( MSG_PANEL_ITEM( _( "Pad" ), Line, BROWN ) );
}
aList.push_back( MSG_PANEL_ITEM( _( "Net" ), m_Netname, DARKCYAN ) );

34
pcbnew/class_pad_draw_functions.cpp
View File

@ -79,7 +79,7 @@ void D_PAD::Draw( EDA_DRAW_PANEL* aPanel, wxDC* aDC, GR_DRAWMODE aDraw_mode,
#ifdef SHOW_PADMASK_REAL_SIZE_AND_COLOR
int showActualMaskSize = 0; /* Layer number if the actual pad size on mask layer can
* be displayed i.e. if only one layer is shown for this pad
* and this layer is a mask (solder mask or sloder paste
* and this layer is a mask (solder mask or solder paste
*/
#endif
@ -229,13 +229,13 @@ void D_PAD::Draw( EDA_DRAW_PANEL* aPanel, wxDC* aDC, GR_DRAWMODE aDraw_mode,
// layer so we can see pads on paste or solder layer and the size of the
// mask
if( ( aDraw_mode & GR_ALLOW_HIGHCONTRAST ) &&
DisplayOpt.ContrastModeDisplay && screen->m_Active_Layer > LAST_COPPER_LAYER )
DisplayOpt.ContrastModeDisplay && screen->m_Active_Layer >= FIRST_NON_COPPER_LAYER )
{
if( IsOnLayer( screen->m_Active_Layer ) )
{
color = brd->GetLayerColor( screen->m_Active_Layer );
// In hight contrast mode, and if the active layer is the mask
// In high contrast mode, and if the active layer is the mask
// layer shows the pad size with the mask clearance
switch( screen->m_Active_Layer )
{
@ -268,8 +268,12 @@ void D_PAD::Draw( EDA_DRAW_PANEL* aPanel, wxDC* aDC, GR_DRAWMODE aDraw_mode,
if( ( m_layerMask & ALL_CU_LAYERS ) == 0 )
DisplayIsol = false;
if( GetAttribute() == PAD_HOLE_NOT_PLATED )
if( ( GetAttribute() == PAD_HOLE_NOT_PLATED ) &&
brd->IsElementVisible( NON_PLATED_VISIBLE ) )
{
drawInfo.m_ShowNotPlatedHole = true;
drawInfo.m_NPHoleColor = brd->GetVisibleElementColor( NON_PLATED_VISIBLE );
}
drawInfo.m_DrawMode = aDraw_mode;
drawInfo.m_Color = color;
@ -286,7 +290,7 @@ void D_PAD::Draw( EDA_DRAW_PANEL* aPanel, wxDC* aDC, GR_DRAWMODE aDraw_mode,
*/
drawInfo.m_PadClearance = DisplayIsol ? GetClearance() : 0;
/* Draw the pad number */
// Draw the pad number
if( frame && !frame->m_DisplayPadNum )
drawInfo.m_Display_padnum = false;
@ -360,7 +364,7 @@ void D_PAD::DrawShape( EDA_RECT* aClipBox, wxDC* aDC, PAD_DRAWINFO& aDrawInfo )
seg_width, m_PadSketchModePenSize, aDrawInfo.m_Color );
}
/* Draw the isolation line. */
// Draw the clearance line
if( aDrawInfo.m_PadClearance )
{
seg_width += 2 * aDrawInfo.m_PadClearance;
@ -392,18 +396,17 @@ void D_PAD::DrawShape( EDA_RECT* aClipBox, wxDC* aDC, PAD_DRAWINFO& aDrawInfo )
}
break;
default:
break;
}
/* Draw the pad hole */
// Draw the pad hole
wxPoint holepos = m_Pos - aDrawInfo.m_Offset;
int hole = m_Drill.x >> 1;
bool drawhole = hole > 0;
if( !aDrawInfo.m_ShowPadFilled && !aDrawInfo. m_ShowNotPlatedHole )
if( !aDrawInfo.m_ShowPadFilled && !aDrawInfo.m_ShowNotPlatedHole )
drawhole = false;
if( drawhole )
@ -439,13 +442,13 @@ void D_PAD::DrawShape( EDA_RECT* aClipBox, wxDC* aDC, PAD_DRAWINFO& aDrawInfo )
halfsize.x = m_Drill.x >> 1;
halfsize.y = m_Drill.y >> 1;
if( m_Drill.x > m_Drill.y ) /* horizontal */
if( m_Drill.x > m_Drill.y ) // horizontal
{
delta_cx = halfsize.x - halfsize.y;
delta_cy = 0;
seg_width = m_Drill.y;
}
else /* vertical */
else // vertical
{
delta_cx = 0;
delta_cy = halfsize.y - halfsize.x;
@ -469,7 +472,7 @@ void D_PAD::DrawShape( EDA_RECT* aClipBox, wxDC* aDC, PAD_DRAWINFO& aDrawInfo )
GRSetDrawMode( aDC, aDrawInfo.m_DrawMode );
/* Draw "No connect" ( / or \ or cross X ) if necessary. : */
// Draw "No connect" ( / or \ or cross X ) if necessary
if( m_Netname.IsEmpty() && aDrawInfo.m_ShowNCMark )
{
int dx0 = std::min( halfsize.x, halfsize.y );
@ -479,12 +482,12 @@ void D_PAD::DrawShape( EDA_RECT* aClipBox, wxDC* aDC, PAD_DRAWINFO& aDrawInfo )
GRLine( aClipBox, aDC, holepos.x - dx0, holepos.y - dx0,
holepos.x + dx0, holepos.y + dx0, 0, nc_color );
if( m_layerMask & LAYER_BACK ) /* Draw / */
if( m_layerMask & LAYER_BACK ) // Draw /
GRLine( aClipBox, aDC, holepos.x + dx0, holepos.y - dx0,
holepos.x - dx0, holepos.y + dx0, 0, nc_color );
}
/* Draw the pad number */
// Draw the pad number
if( !aDrawInfo.m_Display_padnum && !aDrawInfo.m_Display_netname )
return;
@ -627,8 +630,7 @@ void D_PAD::BuildPadPolygon( wxPoint aCoord[4], wxSize aInflateValue, int aRotat
halfsize.x = m_Size.x >> 1;
halfsize.y = m_Size.y >> 1;
/* For rectangular shapes, inflate is easy
*/
// For rectangular shapes, inflate is easy
if( GetShape() == PAD_RECT )
{
halfsize += aInflateValue;

1
pcbnew/class_pcb_layer_widget.cpp
View File

@ -55,6 +55,7 @@ const LAYER_WIDGET::ROW PCB_LAYER_WIDGET::s_render_rows[] = {
RR( _( "Through Via" ), VIA_THROUGH_VISIBLE, WHITE, _( "Show through vias" ) ),
RR( _( "Bl/Buried Via" ), VIA_BBLIND_VISIBLE, WHITE, _( "Show blind or buried vias" ) ),
RR( _( "Micro Via" ), VIA_MICROVIA_VISIBLE, WHITE, _( "Show micro vias") ),
RR( _( "Non Plated" ), NON_PLATED_VISIBLE, WHITE, _( "Show non plated holes") ),
RR( _( "Ratsnest" ), RATSNEST_VISIBLE, WHITE, _( "Show unconnected nets as a ratsnest") ),
RR( _( "Pads Front" ), PAD_FR_VISIBLE, WHITE, _( "Show footprint pads on board's front" ) ),

3
pcbnew/pcbnew_config.cpp
View File

@ -439,6 +439,9 @@ PARAM_CFG_ARRAY& PCB_EDIT_FRAME::GetConfigurationSettings()
m_configSettings.push_back( new PARAM_CFG_SETCOLOR( true, wxT( "ColorViaMicroEx" ),
ITEM_COLOR( VIA_MICROVIA_VISIBLE ),
CYAN ) );
m_configSettings.push_back( new PARAM_CFG_SETCOLOR( true, wxT( "ColorNonPlatedEx" ),
ITEM_COLOR( NON_PLATED_VISIBLE ),
YELLOW ) );
m_configSettings.push_back( new PARAM_CFG_SETCOLOR( true, wxT( "ColorRatsEx" ),
ITEM_COLOR( RATSNEST_VISIBLE ),
WHITE ) );