Support for a visibility flag and color selection to NPTH holes
(when disabled they are shown as standard holes, a lot less distracting than the previous fixed yellow color)
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204d085b64
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b739b2b075
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@ -36,34 +36,27 @@ static const EDA_COLOR_T default_layer_color[LAYERSCOLORSBUFFERSIZE] =
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static const EDA_COLOR_T default_items_color[LAYERSCOLORSBUFFERSIZE] =
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{
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LIGHTGRAY, // unused
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CYAN, // VIA_MICROVIA_VISIBLE
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BROWN, // VIA_BBLIND_VISIBLE
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LIGHTGRAY, // VIA_THROUGH_VISIBLE
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LIGHTGRAY, // MOD_TEXT_FR_VISIBLE
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LIGHTGRAY, // unused
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CYAN, // VIA_MICROVIA_VISIBLE
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BROWN, // VIA_BBLIND_VISIBLE
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LIGHTGRAY, // VIA_THROUGH_VISIBLE
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YELLOW, // NON_PLATED_VISIBLE
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LIGHTGRAY, // MOD_TEXT_FR_VISIBLE
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BLUE, // MOD_TEXT_BK_VISIBLE
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DARKGRAY, // MOD_TEXT_INVISIBLE
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BLUE, // ANCHOR_VISIBLE
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RED, // PAD_FR_VISIBLE
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GREEN, // PAD_BK_VISIBLE
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LIGHTGRAY, // RATSNEST_VISIBLE
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DARKGRAY, //GRID_VISIBLE
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DARKGRAY, // GRID_VISIBLE
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LIGHTRED, LIGHTGRAY, LIGHTGRAY, LIGHTGRAY,
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LIGHTGRAY, LIGHTGRAY,
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LIGHTGRAY, LIGHTGRAY,
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LIGHTGRAY, LIGHTGRAY,
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LIGHTGRAY, LIGHTGRAY,
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LIGHTGRAY,
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LIGHTGRAY,
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LIGHTGRAY,
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LIGHTGRAY,
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LIGHTGRAY,
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LIGHTGRAY,
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LIGHTGRAY,
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LIGHTGRAY
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LIGHTGRAY, LIGHTGRAY, LIGHTGRAY, LIGHTGRAY,
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LIGHTGRAY, LIGHTGRAY, LIGHTGRAY, LIGHTGRAY,
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LIGHTGRAY, LIGHTGRAY, LIGHTGRAY, LIGHTGRAY,
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LIGHTGRAY, LIGHTGRAY, LIGHTGRAY
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};
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COLORS_DESIGN_SETTINGS:: COLORS_DESIGN_SETTINGS()
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COLORS_DESIGN_SETTINGS::COLORS_DESIGN_SETTINGS()
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{
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for( unsigned ii = 0; ii < DIM(m_LayersColors); ii++ )
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m_LayersColors[ii] = default_layer_color[ii];
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@ -196,6 +196,7 @@ enum PCB_VISIBLE
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VIA_MICROVIA_VISIBLE,
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VIA_BBLIND_VISIBLE,
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VIA_THROUGH_VISIBLE,
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NON_PLATED_VISIBLE,
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MOD_TEXT_FR_VISIBLE,
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MOD_TEXT_BK_VISIBLE,
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MOD_TEXT_INVISIBLE, ///< text marked as invisible
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@ -637,6 +637,7 @@ EDA_COLOR_T BOARD::GetVisibleElementColor( int aPCB_VISIBLE )
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switch( aPCB_VISIBLE )
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{
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case NON_PLATED_VISIBLE:
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case VIA_THROUGH_VISIBLE:
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case VIA_MICROVIA_VISIBLE:
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case VIA_BBLIND_VISIBLE:
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@ -663,6 +664,7 @@ void BOARD::SetVisibleElementColor( int aPCB_VISIBLE, EDA_COLOR_T aColor )
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{
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switch( aPCB_VISIBLE )
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{
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case NON_PLATED_VISIBLE:
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case VIA_THROUGH_VISIBLE:
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case VIA_MICROVIA_VISIBLE:
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case VIA_BBLIND_VISIBLE:
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@ -524,7 +524,7 @@ void D_PAD::GetMsgPanelInfo( std::vector< MSG_PANEL_ITEM>& aList )
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wxString msg = module->GetReference();
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aList.push_back( MSG_PANEL_ITEM( _( "Module" ), msg, DARKCYAN ) );
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ReturnStringPadName( Line );
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aList.push_back( MSG_PANEL_ITEM( _( "RefP" ), Line, BROWN ) );
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aList.push_back( MSG_PANEL_ITEM( _( "Pad" ), Line, BROWN ) );
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}
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aList.push_back( MSG_PANEL_ITEM( _( "Net" ), m_Netname, DARKCYAN ) );
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@ -79,7 +79,7 @@ void D_PAD::Draw( EDA_DRAW_PANEL* aPanel, wxDC* aDC, GR_DRAWMODE aDraw_mode,
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#ifdef SHOW_PADMASK_REAL_SIZE_AND_COLOR
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int showActualMaskSize = 0; /* Layer number if the actual pad size on mask layer can
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* be displayed i.e. if only one layer is shown for this pad
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* and this layer is a mask (solder mask or sloder paste
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* and this layer is a mask (solder mask or solder paste
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*/
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#endif
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@ -229,13 +229,13 @@ void D_PAD::Draw( EDA_DRAW_PANEL* aPanel, wxDC* aDC, GR_DRAWMODE aDraw_mode,
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// layer so we can see pads on paste or solder layer and the size of the
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// mask
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if( ( aDraw_mode & GR_ALLOW_HIGHCONTRAST ) &&
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DisplayOpt.ContrastModeDisplay && screen->m_Active_Layer > LAST_COPPER_LAYER )
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DisplayOpt.ContrastModeDisplay && screen->m_Active_Layer >= FIRST_NON_COPPER_LAYER )
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{
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if( IsOnLayer( screen->m_Active_Layer ) )
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{
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color = brd->GetLayerColor( screen->m_Active_Layer );
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// In hight contrast mode, and if the active layer is the mask
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// In high contrast mode, and if the active layer is the mask
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// layer shows the pad size with the mask clearance
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switch( screen->m_Active_Layer )
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{
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@ -268,8 +268,12 @@ void D_PAD::Draw( EDA_DRAW_PANEL* aPanel, wxDC* aDC, GR_DRAWMODE aDraw_mode,
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if( ( m_layerMask & ALL_CU_LAYERS ) == 0 )
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DisplayIsol = false;
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if( GetAttribute() == PAD_HOLE_NOT_PLATED )
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if( ( GetAttribute() == PAD_HOLE_NOT_PLATED ) &&
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brd->IsElementVisible( NON_PLATED_VISIBLE ) )
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{
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drawInfo.m_ShowNotPlatedHole = true;
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drawInfo.m_NPHoleColor = brd->GetVisibleElementColor( NON_PLATED_VISIBLE );
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}
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drawInfo.m_DrawMode = aDraw_mode;
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drawInfo.m_Color = color;
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@ -286,7 +290,7 @@ void D_PAD::Draw( EDA_DRAW_PANEL* aPanel, wxDC* aDC, GR_DRAWMODE aDraw_mode,
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*/
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drawInfo.m_PadClearance = DisplayIsol ? GetClearance() : 0;
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/* Draw the pad number */
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// Draw the pad number
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if( frame && !frame->m_DisplayPadNum )
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drawInfo.m_Display_padnum = false;
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@ -360,7 +364,7 @@ void D_PAD::DrawShape( EDA_RECT* aClipBox, wxDC* aDC, PAD_DRAWINFO& aDrawInfo )
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seg_width, m_PadSketchModePenSize, aDrawInfo.m_Color );
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}
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/* Draw the isolation line. */
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// Draw the clearance line
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if( aDrawInfo.m_PadClearance )
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{
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seg_width += 2 * aDrawInfo.m_PadClearance;
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@ -392,18 +396,17 @@ void D_PAD::DrawShape( EDA_RECT* aClipBox, wxDC* aDC, PAD_DRAWINFO& aDrawInfo )
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}
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break;
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default:
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break;
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}
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/* Draw the pad hole */
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// Draw the pad hole
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wxPoint holepos = m_Pos - aDrawInfo.m_Offset;
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int hole = m_Drill.x >> 1;
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bool drawhole = hole > 0;
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if( !aDrawInfo.m_ShowPadFilled && !aDrawInfo. m_ShowNotPlatedHole )
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if( !aDrawInfo.m_ShowPadFilled && !aDrawInfo.m_ShowNotPlatedHole )
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drawhole = false;
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if( drawhole )
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@ -439,13 +442,13 @@ void D_PAD::DrawShape( EDA_RECT* aClipBox, wxDC* aDC, PAD_DRAWINFO& aDrawInfo )
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halfsize.x = m_Drill.x >> 1;
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halfsize.y = m_Drill.y >> 1;
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if( m_Drill.x > m_Drill.y ) /* horizontal */
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if( m_Drill.x > m_Drill.y ) // horizontal
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{
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delta_cx = halfsize.x - halfsize.y;
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delta_cy = 0;
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seg_width = m_Drill.y;
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}
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else /* vertical */
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else // vertical
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{
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delta_cx = 0;
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delta_cy = halfsize.y - halfsize.x;
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@ -469,7 +472,7 @@ void D_PAD::DrawShape( EDA_RECT* aClipBox, wxDC* aDC, PAD_DRAWINFO& aDrawInfo )
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GRSetDrawMode( aDC, aDrawInfo.m_DrawMode );
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/* Draw "No connect" ( / or \ or cross X ) if necessary. : */
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// Draw "No connect" ( / or \ or cross X ) if necessary
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if( m_Netname.IsEmpty() && aDrawInfo.m_ShowNCMark )
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{
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int dx0 = std::min( halfsize.x, halfsize.y );
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@ -479,12 +482,12 @@ void D_PAD::DrawShape( EDA_RECT* aClipBox, wxDC* aDC, PAD_DRAWINFO& aDrawInfo )
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GRLine( aClipBox, aDC, holepos.x - dx0, holepos.y - dx0,
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holepos.x + dx0, holepos.y + dx0, 0, nc_color );
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if( m_layerMask & LAYER_BACK ) /* Draw / */
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if( m_layerMask & LAYER_BACK ) // Draw /
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GRLine( aClipBox, aDC, holepos.x + dx0, holepos.y - dx0,
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holepos.x - dx0, holepos.y + dx0, 0, nc_color );
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}
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/* Draw the pad number */
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// Draw the pad number
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if( !aDrawInfo.m_Display_padnum && !aDrawInfo.m_Display_netname )
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return;
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@ -627,8 +630,7 @@ void D_PAD::BuildPadPolygon( wxPoint aCoord[4], wxSize aInflateValue, int aRotat
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halfsize.x = m_Size.x >> 1;
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halfsize.y = m_Size.y >> 1;
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/* For rectangular shapes, inflate is easy
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*/
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// For rectangular shapes, inflate is easy
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if( GetShape() == PAD_RECT )
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{
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halfsize += aInflateValue;
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@ -55,6 +55,7 @@ const LAYER_WIDGET::ROW PCB_LAYER_WIDGET::s_render_rows[] = {
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RR( _( "Through Via" ), VIA_THROUGH_VISIBLE, WHITE, _( "Show through vias" ) ),
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RR( _( "Bl/Buried Via" ), VIA_BBLIND_VISIBLE, WHITE, _( "Show blind or buried vias" ) ),
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RR( _( "Micro Via" ), VIA_MICROVIA_VISIBLE, WHITE, _( "Show micro vias") ),
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RR( _( "Non Plated" ), NON_PLATED_VISIBLE, WHITE, _( "Show non plated holes") ),
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RR( _( "Ratsnest" ), RATSNEST_VISIBLE, WHITE, _( "Show unconnected nets as a ratsnest") ),
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RR( _( "Pads Front" ), PAD_FR_VISIBLE, WHITE, _( "Show footprint pads on board's front" ) ),
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@ -439,6 +439,9 @@ PARAM_CFG_ARRAY& PCB_EDIT_FRAME::GetConfigurationSettings()
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m_configSettings.push_back( new PARAM_CFG_SETCOLOR( true, wxT( "ColorViaMicroEx" ),
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ITEM_COLOR( VIA_MICROVIA_VISIBLE ),
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CYAN ) );
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m_configSettings.push_back( new PARAM_CFG_SETCOLOR( true, wxT( "ColorNonPlatedEx" ),
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ITEM_COLOR( NON_PLATED_VISIBLE ),
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YELLOW ) );
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m_configSettings.push_back( new PARAM_CFG_SETCOLOR( true, wxT( "ColorRatsEx" ),
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ITEM_COLOR( RATSNEST_VISIBLE ),
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WHITE ) );
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