diff --git a/pcbnew/class_track.cpp b/pcbnew/class_track.cpp
index cfae464319..630db23727 100644
--- a/pcbnew/class_track.cpp
+++ b/pcbnew/class_track.cpp
@@ -178,6 +178,7 @@ SEARCH_RESULT TRACK::Visit( INSPECTOR* inspector, const void* testData,
 // see class_track.h
 bool SEGVIA::IsOnLayer( int layer_number ) const
 {
+/* its the same logic, don't need this    
     int via_type = Shape();
 
     if( via_type == VIA_NORMALE )
@@ -189,12 +190,13 @@ bool SEGVIA::IsOnLayer( int layer_number ) const
     }
 
     // VIA_BORGNE ou  VIA_ENTERREE:
+*/    
 
     int bottom_layer, top_layer;
     
     ReturnLayerPair( &top_layer, &bottom_layer );
     
-    if( bottom_layer <= layer_number && top_layer >= layer_number )
+    if( bottom_layer <= layer_number &&  layer_number <= top_layer )
         return true;
     else
         return false;
@@ -242,7 +244,7 @@ void SEGVIA::SetLayerPair( int top_layer, int bottom_layer )
  *  m_Layer code les 2 couches limitant la via
  */
 {
-    int via_type = m_Shape & 255;
+    int via_type = Shape();
 
     if( via_type == VIA_NORMALE )
     {
@@ -252,6 +254,7 @@ void SEGVIA::SetLayerPair( int top_layer, int bottom_layer )
 
     if( bottom_layer > top_layer )
         EXCHG( bottom_layer, top_layer );
+    
     m_Layer = (top_layer & 15) + ( (bottom_layer & 15) << 4 );
 }
 
diff --git a/pcbnew/editrack-part2.cpp b/pcbnew/editrack-part2.cpp
index d6e9902075..c82b78692e 100644
--- a/pcbnew/editrack-part2.cpp
+++ b/pcbnew/editrack-part2.cpp
@@ -185,6 +185,7 @@ void WinEDA_PcbFrame::Other_Layer_Route( TRACK* track, wxDC* DC )
     /* Avoid more than one via on the current location: */
     if( Locate_Via( m_Pcb, g_CurrentTrackSegment->m_End, g_CurrentTrackSegment->GetLayer() ) )
         return;
+    
     pt_segm = g_FirstTrackSegment;
     for( ii = 0; ii < g_TrackSegmentCount - 1; ii++, pt_segm = (TRACK*) pt_segm->Pnext )
     {
@@ -229,18 +230,25 @@ void WinEDA_PcbFrame::Other_Layer_Route( TRACK* track, wxDC* DC )
     else
         GetScreen()->m_Active_Layer = GetScreen()->m_Route_Layer_BOTTOM;
 
+    
     /* Adjust the via layer pair */
-    if( (Via->m_Shape & 15) == VIA_ENTERREE )
+    if( Via->Shape() == VIA_ENTERREE )
     {
-        Via->SetLayer( old_layer | GetScreen()->m_Active_Layer << 4 );
+        Via->SetLayerPair( old_layer, GetScreen()->m_Active_Layer );
     }
-    else if( (Via->m_Shape & 15) == VIA_BORGNE )    //blind via
-    {                                               // A revoir! ( la via devrait deboucher sur 1 cote )
-        Via->SetLayer( old_layer | GetScreen()->m_Active_Layer << 4 );
+    
+    else if( Via->Shape() == VIA_BORGNE )    //blind via
+    {                                               
+        // A revoir! ( la via devrait deboucher sur 1 cote )
+        Via->SetLayerPair( old_layer, GetScreen()->m_Active_Layer );
     }
-    else
-        Via->SetLayer( 0x0F ); // Usual via is from copper to component; layer pair is 0 and 0x0F
-
+    
+    else    // @todo: why have this override behaviour?  why does the user even need to tell us what kind of via, when we know which two layers are in play?
+    {        
+        // Usual via is from copper to component; layer pair is 0 and 0x0F.
+        Via->SetLayerPair( LAYER_CUIVRE_N, LAYER_CMP_N );
+    }
+        
     if( Drc_On &&( Drc( this, DC, Via, m_Pcb->m_Track, 1 ) == BAD_DRC ) )
     {
         /* DRC fault: the Via cannot be placed here ... */
diff --git a/pcbnew/router.cpp b/pcbnew/router.cpp
index 7a0023556f..cfb02ba11e 100644
--- a/pcbnew/router.cpp
+++ b/pcbnew/router.cpp
@@ -607,6 +607,7 @@ void WinEDA_PcbFrame::ReadAutoroutedTracks( wxDC* DC )
                 NewVia->m_Shape = VIA_NORMALE;
             else
                 NewVia->m_Shape = VIA_ENTERREE;
+            
             NewVia->Insert( m_Pcb, NULL );
             NbTrack++;
             break;