From bd14224b420c71184efc121b3164467c9db715be Mon Sep 17 00:00:00 2001 From: Alex Shvartzkop Date: Mon, 1 Jul 2024 14:47:38 +0300 Subject: [PATCH] QA: remove 8.99 files for issue17967. --- .../pcbnew/issue17967/issue17967.kicad_dru | 28 - .../pcbnew/issue17967/issue17967.kicad_pcb | 1291 ----------------- .../pcbnew/issue17967/issue17967.kicad_pro | 702 --------- qa/tests/pcbnew/drc/test_drc_regressions.cpp | 3 +- 4 files changed, 1 insertion(+), 2023 deletions(-) delete mode 100644 qa/data/pcbnew/issue17967/issue17967.kicad_dru delete mode 100644 qa/data/pcbnew/issue17967/issue17967.kicad_pcb delete mode 100644 qa/data/pcbnew/issue17967/issue17967.kicad_pro diff --git a/qa/data/pcbnew/issue17967/issue17967.kicad_dru b/qa/data/pcbnew/issue17967/issue17967.kicad_dru deleted file mode 100644 index c2cf77f979..0000000000 --- a/qa/data/pcbnew/issue17967/issue17967.kicad_dru +++ /dev/null @@ -1,28 +0,0 @@ -(version 1) -(rule "csi_outer" - (layer outer) - (condition "(A.NetClass == 'csi_diff100R')") - (constraint track_width (opt 0.065mm)) - (constraint diff_pair_gap (min "0.065mm") (opt 0.15mm) (max "0.35mm")) - (constraint diff_pair_uncoupled (max 15mm)) -) -(rule "csi_clearance" - (layer outer) - (condition "(A.NetClass == 'csi_diff100R' && !AB.isCoupledDiffPair() && A.Type == 'Track' && B.Type == 'Track')") - (constraint clearance (min 0.3mm)) -) - -(rule "csi_GND_clearance" - (layer outer) - (condition "A.NetClass == 'csi_diff100R' && B.NetName == 'GND'") - (constraint clearance (min 0.15mm)) -) - -(rule "connector_clearance" - (condition "(A.Type == 'Pad' || A.Type == 'Via') && ( A.insideCourtyard('J1') || A.insideCourtyard('J2') || A.insideCourtyard('J3')) ") - (constraint clearance (min 0.15mm)) -) - - - - diff --git a/qa/data/pcbnew/issue17967/issue17967.kicad_pcb b/qa/data/pcbnew/issue17967/issue17967.kicad_pcb deleted file mode 100644 index d5b6964c49..0000000000 --- a/qa/data/pcbnew/issue17967/issue17967.kicad_pcb +++ /dev/null @@ -1,1291 +0,0 @@ -(kicad_pcb - (version 20240225) - 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"td_curve_segcount": 10, - "td_height_ratio": 1.0, - "td_length_ratio": 0.5, - "td_maxheight": 2.0, - "td_maxlen": 1.0, - "td_on_pad_in_zone": false, - "td_target_name": "td_round_shape", - "td_width_to_size_filter_ratio": 0.9 - }, - { - "td_allow_use_two_tracks": true, - "td_curve_segcount": 10, - "td_height_ratio": 1.0, - "td_length_ratio": 1.0, - "td_maxheight": 2.0, - "td_maxlen": 1.0, - "td_on_pad_in_zone": false, - "td_target_name": "td_rect_shape", - "td_width_to_size_filter_ratio": 0.9 - }, - { - "td_allow_use_two_tracks": true, - "td_curve_segcount": 0, - "td_height_ratio": 1.0, - "td_length_ratio": 0.5, - "td_maxheight": 2.0, - "td_maxlen": 1.0, - "td_on_pad_in_zone": false, - "td_target_name": "td_track_end", - "td_width_to_size_filter_ratio": 0.9 - } - ], - "track_widths": [ - 0.0, - 0.065, - 0.072, - 0.095, - 0.101, - 0.15, - 0.2, - 0.25, - 0.3, - 0.3556, - 0.38, - 0.4064, - 0.51, - 0.6, - 0.8, - 1.0, - 1.5, - 2.0 - ], - "tuning_pattern_settings": { - "diff_pair_defaults": { - "corner_radius_percentage": 100, - "corner_style": 1, - "max_amplitude": 1.0, - "min_amplitude": 0.1, - "single_sided": false, - "spacing": 0.6 - }, - "diff_pair_skew_defaults": { - "corner_radius_percentage": 100, - "corner_style": 1, - "max_amplitude": 1.0, - "min_amplitude": 0.1, - "single_sided": false, - "spacing": 0.6 - }, - "single_track_defaults": { - "corner_radius_percentage": 100, - "corner_style": 1, - "max_amplitude": 1.0, - "min_amplitude": 0.1, - "single_sided": false, - "spacing": 0.6 - } - }, - "via_dimensions": [ - { - "diameter": 0.0, - "drill": 0.0 - }, - { - "diameter": 0.35, - "drill": 0.15 - }, - { - "diameter": 0.4, - "drill": 0.2 - }, - { - "diameter": 0.45, - "drill": 0.25 - }, - { - "diameter": 0.55, - "drill": 0.3 - } - ], - "zones_allow_external_fillets": true, - "zones_use_no_outline": true - }, - "ipc2581": { - "dist": "", - "distpn": "", - "internal_id": "", - "mfg": "", - "mpn": "" - }, - "layer_presets": [], - "viewports": [] - }, - "boards": [], - "cvpcb": { - "equivalence_files": [] - }, - "erc": { - "erc_exclusions": [], - "meta": { - "version": 0 - }, - "pin_map": [ - [ - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 2 - ], - [ - 0, - 2, - 0, - 1, - 0, - 0, - 1, - 0, - 2, - 2, - 2, - 2 - ], - [ - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 1, - 0, - 1, - 2 - ], - [ - 0, - 1, - 0, - 0, - 0, - 0, - 1, - 1, - 2, - 1, - 1, - 2 - ], - [ - 0, - 0, - 0, - 0, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 2 - ], - [ - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 2 - ], - [ - 1, - 1, - 1, - 1, - 1, - 0, - 1, - 1, - 1, - 1, - 1, - 2 - ], - [ - 0, - 0, - 0, - 1, - 0, - 0, - 1, - 0, - 0, - 0, - 0, - 2 - ], - [ - 0, - 2, - 1, - 2, - 0, - 0, - 1, - 0, - 2, - 2, - 2, - 2 - ], - [ - 0, - 2, - 0, - 1, - 0, - 0, - 1, - 0, - 2, - 0, - 0, - 2 - ], - [ - 0, - 2, - 1, - 1, - 0, - 0, - 1, - 0, - 2, - 0, - 0, - 2 - ], - [ - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2, - 2 - ] - ], - "rule_severities": { - "bus_definition_conflict": "error", - "bus_entry_needed": "error", - "bus_to_bus_conflict": "error", - "bus_to_net_conflict": "error", - "conflicting_netclasses": "error", - "different_unit_footprint": "error", - "different_unit_net": "error", - "duplicate_reference": "error", - "duplicate_sheet_names": "error", - "endpoint_off_grid": "warning", - "extra_units": "error", - "global_label_dangling": "warning", - "hier_label_mismatch": "error", - "label_dangling": "error", - "lib_symbol_issues": "warning", - "missing_bidi_pin": "warning", - "missing_input_pin": "warning", - "missing_power_pin": "error", - "missing_unit": "warning", - "multiple_net_names": "warning", - "net_not_bus_member": "warning", - "no_connect_connected": "warning", - "no_connect_dangling": "warning", - "pin_not_connected": "error", - "pin_not_driven": "error", - "pin_to_pin": "warning", - "power_pin_not_driven": "error", - "similar_labels": "warning", - "simulation_model_issue": "ignore", - "unannotated": "error", - "unit_value_mismatch": "error", - "unresolved_variable": "error", - "wire_dangling": "error" - } - }, - "libraries": { - "pinned_footprint_libs": [], - "pinned_symbol_libs": [] - }, - "meta": { - "filename": "issue17967.kicad_pro", - "version": 1 - }, - "net_settings": { - "classes": [ - { - "bus_width": 12, - "clearance": 0.15, - "diff_pair_gap": 0.15, - "diff_pair_via_gap": 0.25, - "diff_pair_width": 0.072, - "line_style": 0, - "microvia_diameter": 0.3, - "microvia_drill": 0.1, - "name": "Default", - "pcb_color": "rgba(0, 0, 0, 0.000)", - "schematic_color": "rgba(0, 0, 0, 0.000)", - "track_width": 0.076, - "via_diameter": 0.4, - "via_drill": 0.2, - "wire_width": 6 - }, - { - "bus_width": 12, - "clearance": 0.15, - "diff_pair_gap": 0.15, - "diff_pair_via_gap": 0.25, - "diff_pair_width": 0.072, - "line_style": 0, - "microvia_diameter": 0.3, - "microvia_drill": 0.1, - "name": "PWR", - "pcb_color": "rgba(0, 0, 0, 0.000)", - "schematic_color": "rgba(0, 0, 0, 0.000)", - "track_width": 0.2, - "via_diameter": 0.5, - "via_drill": 0.3, - "wire_width": 6 - }, - { - "bus_width": 12, - "clearance": 0.15, - "diff_pair_gap": 0.15, - "diff_pair_via_gap": 0.25, - "diff_pair_width": 0.072, - "line_style": 0, - "microvia_diameter": 0.3, - "microvia_drill": 0.1, - "name": "Signal", - "pcb_color": "rgba(0, 0, 0, 0.000)", - "schematic_color": "rgba(0, 0, 0, 0.000)", - "track_width": 0.1, - "via_diameter": 0.45, - "via_drill": 0.25, - "wire_width": 6 - }, - { - "bus_width": 12, - "clearance": 0.15, - "diff_pair_gap": 0.15, - "diff_pair_via_gap": 0.25, - "diff_pair_width": 0.065, - "line_style": 0, - "microvia_diameter": 0.3, - "microvia_drill": 0.1, - "name": "csi_diff100R", - "pcb_color": "rgba(0, 0, 0, 0.000)", - "schematic_color": "rgba(0, 0, 0, 0.000)", - "track_width": 0.065, - "via_diameter": 0.45, - "via_drill": 0.25, - "wire_width": 6 - } - ], - "meta": { - "version": 3 - }, - "net_colors": null, - "netclass_assignments": null, - "netclass_patterns": [ - { - "netclass": "csi_diff100R", - "pattern": ".*_[PN]" - } - ] - }, - "pcbnew": { - "last_paths": { - "gencad": "", - "idf": "", - "netlist": "", - "plot": "", - "pos_files": "", - "specctra_dsn": "", - "step": "", - "svg": "", - "vrml": "" - }, - "page_layout_descr_file": "" - }, - "schematic": { - "annotate_start_num": 0, - "bom_fmt_presets": [], - "bom_fmt_settings": { - "field_delimiter": ",", - "keep_line_breaks": false, - "keep_tabs": false, - "name": "CSV", - "ref_delimiter": ",", - "ref_range_delimiter": "", - "string_delimiter": "\"" - }, - "bom_presets": [], - "bom_settings": { - "exclude_dnp": false, - "fields_ordered": [ - { - "group_by": false, - "label": "Reference", - "name": "Reference", - "show": true - }, - { - "group_by": true, - "label": "Value", - "name": "Value", - "show": true - }, - { - "group_by": false, - "label": "Datasheet", - "name": "Datasheet", - "show": true - }, - { - "group_by": false, - "label": "Footprint", - "name": "Footprint", - "show": true - }, - { - "group_by": false, - "label": "Qty", - "name": "${QUANTITY}", - "show": true - }, - { - "group_by": true, - "label": "DNP", - "name": "${DNP}", - "show": true - } - ], - "filter_string": "", - "group_symbols": true, - "name": "Grouped By Value", - "sort_asc": true, - "sort_field": "位号" - }, - "connection_grid_size": 50.0, - "drawing": { - "dashed_lines_dash_length_ratio": 12.0, - "dashed_lines_gap_length_ratio": 3.0, - "default_line_thickness": 6.0, - "default_text_size": 50.0, - "field_names": [], - "intersheets_ref_own_page": false, - "intersheets_ref_prefix": "", - "intersheets_ref_short": false, - "intersheets_ref_show": false, - "intersheets_ref_suffix": "", - "junction_size_choice": 3, - "label_size_ratio": 0.375, - "operating_point_overlay_i_precision": 3, - "operating_point_overlay_i_range": "~A", - "operating_point_overlay_v_precision": 3, - "operating_point_overlay_v_range": "~V", - "overbar_offset_ratio": 1.23, - "pin_symbol_size": 25.0, - "text_offset_ratio": 0.15 - }, - "legacy_lib_dir": "", - "legacy_lib_list": [], - "meta": { - "version": 1 - }, - "net_format_name": "", - "ngspice": { - "fix_include_paths": true, - "fix_passive_vals": false, - "meta": { - "version": 0 - }, - "model_mode": 0, - "workbook_filename": "" - }, - "page_layout_descr_file": "", - "plot_directory": "", - "spice_adjust_passive_values": false, - "spice_current_sheet_as_root": false, - "spice_external_command": "spice \"%I\"", - "spice_model_current_sheet_as_root": true, - "spice_save_all_currents": false, - "spice_save_all_dissipations": false, - "spice_save_all_voltages": false, - "subpart_first_id": 65, - "subpart_id_separator": 0 - }, - "sheets": [ - [ - "811c9aa7-2999-4b11-a823-3df1e2e79d8b", - "根目录" - ] - ], - "text_variables": {} -} diff --git a/qa/tests/pcbnew/drc/test_drc_regressions.cpp b/qa/tests/pcbnew/drc/test_drc_regressions.cpp index 34a7ed2bbf..31015a6652 100644 --- a/qa/tests/pcbnew/drc/test_drc_regressions.cpp +++ b/qa/tests/pcbnew/drc/test_drc_regressions.cpp @@ -141,8 +141,7 @@ BOOST_FIXTURE_TEST_CASE( DRCFalseNegativeRegressions, DRC_REGRESSION_TEST_FIXTUR { "issue16566", 6 }, // Pad_Shape vs Shape property { "reverse_via", 3 }, // Via/track ordering { "intersectingzones", 1 }, // zones are too close to each other - { "fill_bad", 1 }, // zone max BBox was too small - { "issue17967/issue17967", 1} // Arc dp coupling + { "fill_bad", 1 } // zone max BBox was too small }; for( const auto& [testName, expectedErrors] : tests )