From bea5914726847a57a62dbc2d1d2fa053f8d50a4e Mon Sep 17 00:00:00 2001 From: Jeff Young Date: Sat, 3 Oct 2020 14:19:42 +0100 Subject: [PATCH] Make sure all DRC paths check for via/pad being flashed on layer. Fixes https://gitlab.com/kicad/code/kicad/issues/5830 --- .../drc/drc_test_provider_copper_clearance.cpp | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/pcbnew/drc/drc_test_provider_copper_clearance.cpp b/pcbnew/drc/drc_test_provider_copper_clearance.cpp index 4dea6b04cd..d01778fef1 100644 --- a/pcbnew/drc/drc_test_provider_copper_clearance.cpp +++ b/pcbnew/drc/drc_test_provider_copper_clearance.cpp @@ -503,7 +503,10 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::doTrackDrc( TRACK* aRefSeg, PCB_LAYER_I /***************************************/ // Can be *very* time consuming. - if( m_drcEngine->GetTestTracksAgainstZones() ) + if( m_drcEngine->GetTestTracksAgainstZones() + && ( aRefSeg->Type() != PCB_VIA_T + || static_cast( aRefSeg )->FlashLayer( aLayer ) + || static_cast( aRefSeg )->GetDrill() > 0 ) ) { SEG testSeg( aRefSeg->GetStart(), aRefSeg->GetEnd() ); @@ -524,10 +527,19 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::doTrackDrc( TRACK* aRefSeg, PCB_LAYER_I if( !refSegInflatedBB.Intersects( zone->GetBoundingBox() ) ) continue; + int halfWidth = refSegWidth / 2; + + if( aRefSeg->Type() == PCB_VIA_T ) + { + VIA* refVia = static_cast( aRefSeg ); + + if( !refVia->FlashLayer( aLayer ) ) + halfWidth = refVia->GetDrill() / 2 + bds.GetHolePlatingThickness(); + } + auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_CLEARANCE, aRefSeg, zone, aLayer ); int minClearance = constraint.GetValue().Min(); - int halfWidth = refSegWidth / 2; int allowedDist = minClearance + halfWidth - bds.GetDRCEpsilon(); const SHAPE_POLY_SET& zonePoly = zone->GetFilledPolysList( aLayer );