From bf3cb0b1d08335df86f481f3eb6ee28a2c35850e Mon Sep 17 00:00:00 2001 From: Seth Hillbrand Date: Wed, 30 Sep 2020 08:38:35 -0700 Subject: [PATCH] Standardize pad type enums --- .../3d_canvas/create_3Dgraphic_brd_items.cpp | 2 +- 3d-viewer/3d_canvas/create_layer_items.cpp | 4 +- .../c3d_render_createscene_ogl_legacy.cpp | 2 +- .../c3d_render_createscene.cpp | 2 +- include/pad_shapes.h | 14 +++---- ...board_items_to_polygon_shape_transform.cpp | 2 +- pcbnew/class_module.cpp | 4 +- pcbnew/class_pad.cpp | 38 +++++++++---------- pcbnew/class_pad.h | 8 ++-- pcbnew/connectivity/connectivity_items.cpp | 2 +- pcbnew/dialogs/dialog_board_statistics.cpp | 6 +-- pcbnew/dialogs/dialog_gendrill.cpp | 4 +- pcbnew/dialogs/dialog_pad_properties.cpp | 36 +++++++++--------- .../drc_test_provider_copper_clearance.cpp | 8 ++-- pcbnew/eagle_plugin.cpp | 6 +-- pcbnew/exporters/export_d356.cpp | 2 +- pcbnew/exporters/export_hyperlynx.cpp | 6 +-- pcbnew/exporters/export_idf.cpp | 2 +- pcbnew/exporters/export_vrml.cpp | 2 +- .../exporters/gendrill_file_writer_base.cpp | 6 +-- pcbnew/kicad_plugin.cpp | 10 ++--- pcbnew/legacy_plugin.cpp | 4 +- pcbnew/pad_naming.cpp | 2 +- pcbnew/pcad2kicadpcb_plugin/pcb_pad.cpp | 6 +-- pcbnew/pcb_expr_evaluator.cpp | 2 +- pcbnew/pcb_parser.cpp | 4 +- pcbnew/plot_board_layers.cpp | 2 +- pcbnew/plot_brditems_plotter.cpp | 10 ++--- pcbnew/plugins/altium/altium_pcb.cpp | 6 +-- .../cadstar/cadstar_pcb_archive_loader.cpp | 6 +-- pcbnew/router/pns_kicad_iface.cpp | 16 ++++---- pcbnew/tools/pcb_inspection_tool.cpp | 2 +- pcbnew/tools/selection_tool.cpp | 4 +- pcbnew/zone_filler.cpp | 4 +- qa/pcbnew/test_pad_naming.cpp | 4 +- 35 files changed, 119 insertions(+), 119 deletions(-) diff --git a/3d-viewer/3d_canvas/create_3Dgraphic_brd_items.cpp b/3d-viewer/3d_canvas/create_3Dgraphic_brd_items.cpp index 58d5506688..ce5675e457 100644 --- a/3d-viewer/3d_canvas/create_3Dgraphic_brd_items.cpp +++ b/3d-viewer/3d_canvas/create_3Dgraphic_brd_items.cpp @@ -493,7 +493,7 @@ void BOARD_ADAPTER::AddPadsShapesWithClearanceToContainer( const MODULE* aModule // NPTH pads are not drawn on layers if the // shape size and pos is the same as their hole: - if( aSkipNPTHPadsWihNoCopper && (pad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED) ) + if( aSkipNPTHPadsWihNoCopper && ( pad->GetAttribute() == PAD_ATTRIB_NPTH ) ) { if( (pad->GetDrillSize() == pad->GetSize()) && (pad->GetOffset() == wxPoint( 0, 0 )) ) diff --git a/3d-viewer/3d_canvas/create_layer_items.cpp b/3d-viewer/3d_canvas/create_layer_items.cpp index c5b63f6d5a..00909efa92 100644 --- a/3d-viewer/3d_canvas/create_layer_items.cpp +++ b/3d-viewer/3d_canvas/create_layer_items.cpp @@ -471,7 +471,7 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter ) // The hole in the body is inflated by copper thickness, // if not plated, no copper - const int inflate = (pad->GetAttribute () != PAD_ATTRIB_HOLE_NOT_PLATED) ? + const int inflate = ( pad->GetAttribute () != PAD_ATTRIB_NPTH ) ? GetCopperThicknessBIU() : 0; m_stats_nr_holes++; @@ -506,7 +506,7 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter ) // The hole in the body is inflated by copper thickness. const int inflate = GetCopperThicknessBIU(); - if( pad->GetAttribute () != PAD_ATTRIB_HOLE_NOT_PLATED ) + if( pad->GetAttribute () != PAD_ATTRIB_NPTH ) { pad->TransformHoleWithClearanceToPolygon( m_through_outer_holes_poly, inflate ); } diff --git a/3d-viewer/3d_rendering/3d_render_ogl_legacy/c3d_render_createscene_ogl_legacy.cpp b/3d-viewer/3d_rendering/3d_render_ogl_legacy/c3d_render_createscene_ogl_legacy.cpp index ddd7bc2510..c4c2ef4bb0 100644 --- a/3d-viewer/3d_rendering/3d_render_ogl_legacy/c3d_render_createscene_ogl_legacy.cpp +++ b/3d-viewer/3d_rendering/3d_render_ogl_legacy/c3d_render_createscene_ogl_legacy.cpp @@ -794,7 +794,7 @@ void C3D_RENDER_OGL_LEGACY::generate_3D_Vias_and_Pads() { for( auto pad : module->Pads() ) { - if( pad->GetAttribute() != PAD_ATTRIB_HOLE_NOT_PLATED ) + if( pad->GetAttribute() != PAD_ATTRIB_NPTH ) { const wxSize drillsize = pad->GetDrillSize(); const bool hasHole = drillsize.x && drillsize.y; diff --git a/3d-viewer/3d_rendering/3d_render_raytracing/c3d_render_createscene.cpp b/3d-viewer/3d_rendering/3d_render_raytracing/c3d_render_createscene.cpp index c2635e9fae..1e90bcd64f 100644 --- a/3d-viewer/3d_rendering/3d_render_raytracing/c3d_render_createscene.cpp +++ b/3d-viewer/3d_rendering/3d_render_raytracing/c3d_render_createscene.cpp @@ -1258,7 +1258,7 @@ void C3D_RENDER_RAYTRACING::add_3D_vias_and_pads_to_container() for( auto module : m_boardAdapter.GetBoard()->Modules() ) { for( auto pad : module->Pads() ) - if( pad->GetAttribute () != PAD_ATTRIB_HOLE_NOT_PLATED ) + if( pad->GetAttribute () != PAD_ATTRIB_NPTH ) { insert3DPadHole( pad ); } diff --git a/include/pad_shapes.h b/include/pad_shapes.h index d39f1eb2bb..238503eda6 100644 --- a/include/pad_shapes.h +++ b/include/pad_shapes.h @@ -77,13 +77,13 @@ enum PAD_DRILL_SHAPE_T */ enum PAD_ATTR_T { - PAD_ATTRIB_STANDARD, ///< Usual pad - PAD_ATTRIB_SMD, ///< Smd pad, appears on the solder paste layer (default) - PAD_ATTRIB_CONN, ///< Like smd, does not appear on the solder paste layer (default) - ///< note also has a special attribute in Gerber X files - ///< Used for edgecard connectors for instance - PAD_ATTRIB_HOLE_NOT_PLATED, ///< like PAD_STANDARD, but not plated - ///< mechanical use only, no connection allowed + PAD_ATTRIB_PTH, ///< Plated through hole pad + PAD_ATTRIB_SMD, ///< Smd pad, appears on the solder paste layer (default) + PAD_ATTRIB_CONN, ///< Like smd, does not appear on the solder paste layer (default) + ///< note also has a special attribute in Gerber X files + ///< Used for edgecard connectors for instance + PAD_ATTRIB_NPTH, ///< like PAD_PTH, but not plated + ///< mechanical use only, no connection allowed }; diff --git a/pcbnew/board_items_to_polygon_shape_transform.cpp b/pcbnew/board_items_to_polygon_shape_transform.cpp index 207378bec7..4328e844f6 100644 --- a/pcbnew/board_items_to_polygon_shape_transform.cpp +++ b/pcbnew/board_items_to_polygon_shape_transform.cpp @@ -131,7 +131,7 @@ void MODULE::TransformPadsShapesWithClearanceToPolygon( PCB_LAYER_ID aLayer, // NPTH pads are not drawn on layers if the shape size and pos is the same // as their hole: - if( aSkipNPTHPadsWihNoCopper && pad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED ) + if( aSkipNPTHPadsWihNoCopper && pad->GetAttribute() == PAD_ATTRIB_NPTH ) { if( pad->GetDrillSize() == pad->GetSize() && pad->GetOffset() == wxPoint( 0, 0 ) ) { diff --git a/pcbnew/class_module.cpp b/pcbnew/class_module.cpp index ee4ebc973b..2e9fe27eb3 100644 --- a/pcbnew/class_module.cpp +++ b/pcbnew/class_module.cpp @@ -834,7 +834,7 @@ unsigned MODULE::GetPadCount( INCLUDE_NPTH_T aIncludeNPTH ) const for( D_PAD* pad : m_pads ) { - if( pad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED ) + if( pad->GetAttribute() == PAD_ATTRIB_NPTH ) continue; cnt++; @@ -864,7 +864,7 @@ unsigned MODULE::GetUniquePadCount( INCLUDE_NPTH_T aIncludeNPTH ) const if( !aIncludeNPTH ) { // skip NPTH - if( pad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED ) + if( pad->GetAttribute() == PAD_ATTRIB_NPTH ) { continue; } diff --git a/pcbnew/class_pad.cpp b/pcbnew/class_pad.cpp index 9f91840686..3086dcfb8b 100644 --- a/pcbnew/class_pad.cpp +++ b/pcbnew/class_pad.cpp @@ -70,16 +70,16 @@ D_PAD::D_PAD( MODULE* parent ) : SetAnchorPadShape( PAD_SHAPE_CIRCLE ); // Default shape for custom shaped pads // is PAD_CIRCLE. SetDrillShape( PAD_DRILL_SHAPE_CIRCLE ); // Default pad drill shape is a circle. - m_attribute = PAD_ATTRIB_STANDARD; // Default pad type is NORMAL (thru hole) + m_attribute = PAD_ATTRIB_PTH; // Default pad type is plated through hole SetProperty( PAD_PROP_NONE ); // no special fabrication property m_localClearance = 0; m_localSolderMaskMargin = 0; m_localSolderPasteMargin = 0; m_localSolderPasteMarginRatio = 0.0; // Parameters for round rect only: - m_roundedCornerScale = 0.25; // from IPC-7351C standard + m_roundedCornerScale = 0.25; // from IPC-7351C standard // Parameters for chamfered rect only: - m_chamferScale = 0.2; // Size of chamfer: ratio of smallest of X,Y size + m_chamferScale = 0.2; // Size of chamfer: ratio of smallest of X,Y size m_chamferPositions = RECT_NO_CHAMFER; // No chamfered corner m_zoneConnection = ZONE_CONNECTION::INHERITED; // Use parent setting by default @@ -89,7 +89,7 @@ D_PAD::D_PAD( MODULE* parent ) : m_customShapeClearanceArea = CUST_PAD_SHAPE_IN_ZONE_OUTLINE; // Set layers mask to default for a standard thru hole pad. - m_layerMask = StandardMask(); + m_layerMask = PTHMask(); SetSubRatsnest( 0 ); // used in ratsnest calculations @@ -138,7 +138,7 @@ D_PAD& D_PAD::operator=( const D_PAD &aOther ) } -LSET D_PAD::StandardMask() +LSET D_PAD::PTHMask() { static LSET saved = LSET::AllCuMask() | LSET( 2, F_Mask, B_Mask ); return saved; @@ -201,7 +201,7 @@ bool D_PAD::FlashLayer( int aLayer ) const return false; /// We don't remove the copper from non-PTH pads - if( GetAttribute() != PAD_ATTRIB_STANDARD ) + if( GetAttribute() != PAD_ATTRIB_PTH ) return IsOnLayer( static_cast( aLayer ) ); /// Heatsink pads always get copper @@ -1044,11 +1044,11 @@ wxString D_PAD::ShowPadAttr() const { switch( GetAttribute() ) { - case PAD_ATTRIB_STANDARD: return _( "Std" ); - case PAD_ATTRIB_SMD: return _( "SMD" ); - case PAD_ATTRIB_CONN: return _( "Conn" ); - case PAD_ATTRIB_HOLE_NOT_PLATED: return _( "Not Plated" ); - default: return wxT( "???" ); + case PAD_ATTRIB_PTH: return _( "PTH" ); + case PAD_ATTRIB_SMD: return _( "SMD" ); + case PAD_ATTRIB_CONN: return _( "Conn" ); + case PAD_ATTRIB_NPTH: return _( "NPTH" ); + default: return wxT( "???" ); } } @@ -1085,7 +1085,7 @@ EDA_ITEM* D_PAD::Clone() const bool D_PAD::PadShouldBeNPTH() const { - return( m_attribute == PAD_ATTRIB_STANDARD + return( m_attribute == PAD_ATTRIB_PTH && m_drill.x >= m_size.x && m_drill.y >= m_size.y ); } @@ -1095,10 +1095,10 @@ void D_PAD::ViewGetLayers( int aLayers[], int& aCount ) const aCount = 0; // These 2 types of pads contain a hole - if( m_attribute == PAD_ATTRIB_STANDARD ) + if( m_attribute == PAD_ATTRIB_PTH ) aLayers[aCount++] = LAYER_PADS_PLATEDHOLES; - if( m_attribute == PAD_ATTRIB_HOLE_NOT_PLATED ) + if( m_attribute == PAD_ATTRIB_NPTH ) aLayers[aCount++] = LAYER_NON_PLATEDHOLES; if( IsOnLayer( F_Cu ) && IsOnLayer( B_Cu ) ) @@ -1113,7 +1113,7 @@ void D_PAD::ViewGetLayers( int aLayers[], int& aCount ) const // Is this a PTH pad that has only front copper? If so, we need to also display the // net name on the PTH netname layer so that it isn't blocked by the drill hole. - if( m_attribute == PAD_ATTRIB_STANDARD ) + if( m_attribute == PAD_ATTRIB_PTH ) aLayers[aCount++] = LAYER_PADS_NETNAMES; else aLayers[aCount++] = LAYER_PAD_FR_NETNAMES; @@ -1124,7 +1124,7 @@ void D_PAD::ViewGetLayers( int aLayers[], int& aCount ) const // Is this a PTH pad that has only back copper? If so, we need to also display the // net name on the PTH netname layer so that it isn't blocked by the drill hole. - if( m_attribute == PAD_ATTRIB_STANDARD ) + if( m_attribute == PAD_ATTRIB_PTH ) aLayers[aCount++] = LAYER_PADS_NETNAMES; else aLayers[aCount++] = LAYER_PAD_BK_NETNAMES; @@ -1177,7 +1177,7 @@ double D_PAD::ViewGetLOD( int aLayer, KIGFX::VIEW* aView ) const return HIDE; // Handle Render tab switches - if( ( GetAttribute() == PAD_ATTRIB_STANDARD || GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED ) + if( ( GetAttribute() == PAD_ATTRIB_PTH || GetAttribute() == PAD_ATTRIB_NPTH ) && !aView->IsLayerVisible( LAYER_PADS_TH ) ) return HIDE; @@ -1329,10 +1329,10 @@ static struct PAD_DESC PAD_DESC() { ENUM_MAP::Instance() - .Map( PAD_ATTRIB_STANDARD, _( "Through-hole" ) ) + .Map( PAD_ATTRIB_PTH, _( "Through-hole" ) ) .Map( PAD_ATTRIB_SMD, _( "SMD" ) ) .Map( PAD_ATTRIB_CONN, _( "Edge connector" ) ) - .Map( PAD_ATTRIB_HOLE_NOT_PLATED, _( "NPTH, mechanical" ) ); + .Map( PAD_ATTRIB_NPTH, _( "NPTH, mechanical" ) ); ENUM_MAP::Instance() .Map( PAD_SHAPE_CIRCLE, _( "Circle" ) ) diff --git a/pcbnew/class_pad.h b/pcbnew/class_pad.h index 33942614c7..e6ba8130ca 100644 --- a/pcbnew/class_pad.h +++ b/pcbnew/class_pad.h @@ -75,7 +75,7 @@ public: * Default layers used for pads, according to the pad type. * this is default values only, they can be changed for a given pad */ - static LSET StandardMask(); ///< layer set for a through hole pad + static LSET PTHMask(); ///< layer set for a through hole pad static LSET SMDMask(); ///< layer set for a SMD pad on Front layer static LSET ConnSMDMask(); ///< layer set for a SMD pad on Front layer ///< used for edge board connectors @@ -98,9 +98,9 @@ public: { if( *p == PCB_LOCATE_HOLE_T ) return true; - else if( *p == PCB_LOCATE_PTH_T && m_attribute != PAD_ATTRIB_HOLE_NOT_PLATED ) + else if( *p == PCB_LOCATE_PTH_T && m_attribute != PAD_ATTRIB_NPTH ) return true; - else if( *p == PCB_LOCATE_NPTH_T && m_attribute == PAD_ATTRIB_HOLE_NOT_PLATED ) + else if( *p == PCB_LOCATE_NPTH_T && m_attribute == PAD_ATTRIB_NPTH ) return true; } } @@ -701,7 +701,7 @@ private: // module anchor, orientation 0) PAD_ATTR_T m_attribute; // PAD_ATTRIB_NORMAL, PAD_ATTRIB_SMD, PAD_ATTRIB_CONN, - // PAD_ATTRIB_HOLE_NOT_PLATED + // PAD_ATTRIB_NPTH PAD_PROP_T m_property; // Property in fab files (BGA, FIDUCIAL, TESTPOINT, etc.) double m_orient; // in 1/10 degrees diff --git a/pcbnew/connectivity/connectivity_items.cpp b/pcbnew/connectivity/connectivity_items.cpp index c6780cda17..89c6b1e57d 100644 --- a/pcbnew/connectivity/connectivity_items.cpp +++ b/pcbnew/connectivity/connectivity_items.cpp @@ -208,7 +208,7 @@ CN_ITEM* CN_LIST::Add( D_PAD* pad ) switch( pad->GetAttribute() ) { case PAD_ATTRIB_SMD: - case PAD_ATTRIB_HOLE_NOT_PLATED: + case PAD_ATTRIB_NPTH: case PAD_ATTRIB_CONN: { LSET lmsk = pad->GetLayerSet(); diff --git a/pcbnew/dialogs/dialog_board_statistics.cpp b/pcbnew/dialogs/dialog_board_statistics.cpp index 982cf05aec..310c6df4e7 100644 --- a/pcbnew/dialogs/dialog_board_statistics.cpp +++ b/pcbnew/dialogs/dialog_board_statistics.cpp @@ -136,10 +136,10 @@ void DIALOG_BOARD_STATISTICS::refreshItemsTypes() m_componentsTypes.push_back( componentsType_t( MOD_SMD, _( "SMD:" ) ) ); m_padsTypes.clear(); - m_padsTypes.push_back( padsType_t( PAD_ATTRIB_STANDARD, _( "Through hole:" ) ) ); + m_padsTypes.push_back( padsType_t( PAD_ATTRIB_PTH, _( "Through hole:" ) ) ); m_padsTypes.push_back( padsType_t( PAD_ATTRIB_SMD, _( "SMD:" ) ) ); m_padsTypes.push_back( padsType_t( PAD_ATTRIB_CONN, _( "Connector:" ) ) ); - m_padsTypes.push_back( padsType_t( PAD_ATTRIB_HOLE_NOT_PLATED, _( "NPTH:" ) ) ); + m_padsTypes.push_back( padsType_t( PAD_ATTRIB_NPTH, _( "NPTH:" ) ) ); m_viasTypes.clear(); m_viasTypes.push_back( viasType_t( VIATYPE::THROUGH, _( "Through vias:" ) ) ); @@ -227,7 +227,7 @@ void DIALOG_BOARD_STATISTICS::getDataFromPCB() } drillType_t drill( pad->GetDrillSize().x, pad->GetDrillSize().y, - pad->GetDrillShape(), pad->GetAttribute() != PAD_ATTRIB_HOLE_NOT_PLATED, + pad->GetDrillShape(), pad->GetAttribute() != PAD_ATTRIB_NPTH, true, top, bottom ); auto it = m_drillTypes.begin(); diff --git a/pcbnew/dialogs/dialog_gendrill.cpp b/pcbnew/dialogs/dialog_gendrill.cpp index 937165fd10..5ebbcacb33 100644 --- a/pcbnew/dialogs/dialog_gendrill.cpp +++ b/pcbnew/dialogs/dialog_gendrill.cpp @@ -148,7 +148,7 @@ void DIALOG_GENDRILL::InitDisplayParams() { if( pad->GetDrillSize().x != 0 ) { - if( pad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED ) + if( pad->GetAttribute() == PAD_ATTRIB_NPTH ) m_notplatedPadsHoleCount++; else m_platedPadsHoleCount++; @@ -158,7 +158,7 @@ void DIALOG_GENDRILL::InitDisplayParams() { if( pad->GetDrillSize().x != 0 && pad->GetDrillSize().y != 0 ) { - if( pad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED ) + if( pad->GetAttribute() == PAD_ATTRIB_NPTH ) m_notplatedPadsHoleCount++; else m_platedPadsHoleCount++; diff --git a/pcbnew/dialogs/dialog_pad_properties.cpp b/pcbnew/dialogs/dialog_pad_properties.cpp index 36429c996f..cb23068fb9 100644 --- a/pcbnew/dialogs/dialog_pad_properties.cpp +++ b/pcbnew/dialogs/dialog_pad_properties.cpp @@ -77,10 +77,10 @@ enum CODE_CHOICE static PAD_ATTR_T code_type[] = { - PAD_ATTRIB_STANDARD, + PAD_ATTRIB_PTH, PAD_ATTRIB_SMD, PAD_ATTRIB_CONN, - PAD_ATTRIB_HOLE_NOT_PLATED, + PAD_ATTRIB_NPTH, PAD_ATTRIB_SMD // Aperture pad :type SMD with no copper layers, // only on tech layers (usually only on paste layer }; @@ -88,10 +88,10 @@ static PAD_ATTR_T code_type[] = // Default mask layers setup for pads according to the pad type static const LSET std_pad_layers[] = { - D_PAD::StandardMask(), // PAD_ATTRIB_STANDARD: + D_PAD::StandardMask(), // PAD_ATTRIB_PTH: D_PAD::SMDMask(), // PAD_ATTRIB_SMD: D_PAD::ConnSMDMask(), // PAD_ATTRIB_CONN: - D_PAD::UnplatedHoleMask(), // PAD_ATTRIB_HOLE_NOT_PLATED: + D_PAD::UnplatedHoleMask(), // PAD_ATTRIB_NPTH: D_PAD::ApertureMask() }; @@ -630,10 +630,10 @@ void DIALOG_PAD_PROPERTIES::initValues() { switch( m_dummyPad->GetAttribute() ) { - case PAD_ATTRIB_STANDARD: m_PadType->SetSelection( 0 ); break; - case PAD_ATTRIB_SMD: m_PadType->SetSelection( 1 ); break; - case PAD_ATTRIB_CONN: m_PadType->SetSelection( 2 ); break; - case PAD_ATTRIB_HOLE_NOT_PLATED: m_PadType->SetSelection( 3 ); break; + case PAD_ATTRIB_PTH: m_PadType->SetSelection( 0 ); break; + case PAD_ATTRIB_SMD: m_PadType->SetSelection( 1 ); break; + case PAD_ATTRIB_CONN: m_PadType->SetSelection( 2 ); break; + case PAD_ATTRIB_NPTH: m_PadType->SetSelection( 3 ); break; } } @@ -649,7 +649,7 @@ void DIALOG_PAD_PROPERTIES::initValues() } // Ensure the pad property is compatible with the pad type - if( m_dummyPad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED ) + if( m_dummyPad->GetAttribute() == PAD_ATTRIB_NPTH ) { m_choiceFabProperty->SetSelection( 0 ); m_choiceFabProperty->Enable( false ); @@ -1219,7 +1219,7 @@ bool DIALOG_PAD_PROPERTIES::padValuesOK() if( !padlayers_mask[F_Cu] && !padlayers_mask[B_Cu] ) { if( ( m_dummyPad->GetDrillSize().x || m_dummyPad->GetDrillSize().y ) - && m_dummyPad->GetAttribute() != PAD_ATTRIB_HOLE_NOT_PLATED ) + && m_dummyPad->GetAttribute() != PAD_ATTRIB_NPTH ) { // Note: he message is shown in an HTML window msg = _( "Error: plated through holes must have a copper pad on at least one layer" ); @@ -1247,8 +1247,8 @@ bool DIALOG_PAD_PROPERTIES::padValuesOK() switch( m_dummyPad->GetAttribute() ) { - case PAD_ATTRIB_HOLE_NOT_PLATED: // Not plated, but through hole, a hole is expected - case PAD_ATTRIB_STANDARD : // Pad through hole, a hole is also expected + case PAD_ATTRIB_NPTH: // Not plated, but through hole, a hole is expected + case PAD_ATTRIB_PTH: // Pad through hole, a hole is also expected if( m_dummyPad->GetDrillSize().x <= 0 || ( m_dummyPad->GetDrillSize().y <= 0 && m_dummyPad->GetDrillShape() == PAD_DRILL_SHAPE_OBLONG ) ) error_msgs.Add( _( "Error: Through hole pad: drill diameter set to 0" ) ); @@ -1272,11 +1272,11 @@ bool DIALOG_PAD_PROPERTIES::padValuesOK() } if( m_dummyPad->GetProperty() != PAD_PROP_NONE && - m_dummyPad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED ) + m_dummyPad->GetAttribute() == PAD_ATTRIB_NPTH ) error_msgs.Add( _( "Property cannot be set for NPTH" ) ); if( m_dummyPad->GetProperty() == PAD_PROP_CASTELLATED && - m_dummyPad->GetAttribute() != PAD_ATTRIB_STANDARD ) + m_dummyPad->GetAttribute() != PAD_ATTRIB_PTH ) error_msgs.Add( _( "Castellated property can be set only for PTH" ) ); if( m_dummyPad->GetProperty() == PAD_PROP_BGA && @@ -1506,8 +1506,8 @@ bool DIALOG_PAD_PROPERTIES::TransferDataFromWindow() int padNetcode = NETINFO_LIST::UNCONNECTED; - // For PAD_ATTRIB_HOLE_NOT_PLATED, ensure there is no net name selected - if( m_padMaster->GetAttribute() != PAD_ATTRIB_HOLE_NOT_PLATED ) + // For PAD_ATTRIB_NPTH, ensure there is no net name selected + if( m_padMaster->GetAttribute() != PAD_ATTRIB_NPTH ) padNetcode = m_PadNetSelector->GetSelectedNetcode(); m_currentPad->SetNetCode( padNetcode ); @@ -1744,7 +1744,7 @@ bool DIALOG_PAD_PROPERTIES::transferDataToPad( D_PAD* aPad ) switch( aPad->GetAttribute() ) { - case PAD_ATTRIB_STANDARD: + case PAD_ATTRIB_PTH: break; case PAD_ATTRIB_CONN: @@ -1758,7 +1758,7 @@ bool DIALOG_PAD_PROPERTIES::transferDataToPad( D_PAD* aPad ) aPad->SetDrillSize( wxSize( 0, 0 ) ); break; - case PAD_ATTRIB_HOLE_NOT_PLATED: + case PAD_ATTRIB_NPTH: // Mechanical purpose only: // no net name, no pad name allowed aPad->SetName( wxEmptyString ); diff --git a/pcbnew/drc/drc_test_provider_copper_clearance.cpp b/pcbnew/drc/drc_test_provider_copper_clearance.cpp index 0dab2c3aca..4dea6b04cd 100644 --- a/pcbnew/drc/drc_test_provider_copper_clearance.cpp +++ b/pcbnew/drc/drc_test_provider_copper_clearance.cpp @@ -279,7 +279,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testCopperDrawItem( BOARD_ITEM* aItem ) { padShape = pad->GetEffectiveShape().get(); } - else if( pad->GetAttribute() == PAD_ATTRIB_STANDARD ) + else if( pad->GetAttribute() == PAD_ATTRIB_PTH ) { // Note: drill size represents finish size, which means the actual holes size is the // plating thickness larger. @@ -381,7 +381,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::doTrackDrc( TRACK* aRefSeg, PCB_LAYER_I { padShape = pad->GetEffectiveShape().get(); } - else if( pad->GetAttribute() == PAD_ATTRIB_STANDARD ) + else if( pad->GetAttribute() == PAD_ATTRIB_PTH ) { // Note: drill size represents finish size, which means the actual holes size is the // plating thickness larger. @@ -688,7 +688,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::doPadToPadsDrc( int aRefPadIdx, { refPadShape = refPad->GetEffectiveShape().get(); } - else if( refPad->GetAttribute() == PAD_ATTRIB_STANDARD ) + else if( refPad->GetAttribute() == PAD_ATTRIB_PTH ) { // Note: drill size represents finish size, which means the actual holes size is the // plating thickness larger. @@ -708,7 +708,7 @@ void DRC_TEST_PROVIDER_COPPER_CLEARANCE::doPadToPadsDrc( int aRefPadIdx, { padShape = pad->GetEffectiveShape().get(); } - else if( pad->GetAttribute() == PAD_ATTRIB_STANDARD ) + else if( pad->GetAttribute() == PAD_ATTRIB_PTH ) { // Note: drill size represents finish size, which means the actual holes size is the // plating thickness larger. diff --git a/pcbnew/eagle_plugin.cpp b/pcbnew/eagle_plugin.cpp index e268ed12c3..dbe6b55ca5 100644 --- a/pcbnew/eagle_plugin.cpp +++ b/pcbnew/eagle_plugin.cpp @@ -829,7 +829,7 @@ void EAGLE_PLUGIN::loadPlain( wxXmlNode* aGraphics ) { m_xpath->push( "hole" ); - // Fabricate a MODULE with a single PAD_ATTRIB_HOLE_NOT_PLATED pad. + // Fabricate a MODULE with a single PAD_ATTRIB_NPTH pad. // Use m_hole_count to gen up a unique name. MODULE* module = new MODULE( m_board ); @@ -2076,12 +2076,12 @@ void EAGLE_PLUGIN::packageHole( MODULE* aModule, wxXmlNode* aTree, bool aCenter { EHOLE e( aTree ); - // we add a PAD_ATTRIB_HOLE_NOT_PLATED pad to this module. + // we add a PAD_ATTRIB_NPTH pad to this module. D_PAD* pad = new D_PAD( aModule ); aModule->Add( pad ); pad->SetShape( PAD_SHAPE_CIRCLE ); - pad->SetAttribute( PAD_ATTRIB_HOLE_NOT_PLATED ); + pad->SetAttribute( PAD_ATTRIB_NPTH ); // Mechanical purpose only: // no offset, no net name, no pad name allowed diff --git a/pcbnew/exporters/export_d356.cpp b/pcbnew/exporters/export_d356.cpp index f4bb893ff8..848256cc10 100644 --- a/pcbnew/exporters/export_d356.cpp +++ b/pcbnew/exporters/export_d356.cpp @@ -113,7 +113,7 @@ static void build_pad_testpoints( BOARD *aPcb, std::vector & aRecor rk.drill = std::min( drill.x, drill.y ); rk.hole = (rk.drill != 0); rk.smd = pad->GetAttribute() == PAD_ATTRIB_SMD; - rk.mechanical = (pad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED); + rk.mechanical = ( pad->GetAttribute() == PAD_ATTRIB_NPTH ); rk.x_location = pad->GetPosition().x - origin.x; rk.y_location = origin.y - pad->GetPosition().y; rk.x_size = pad->GetSize().x; diff --git a/pcbnew/exporters/export_hyperlynx.cpp b/pcbnew/exporters/export_hyperlynx.cpp index 03923037da..ecba4af1de 100644 --- a/pcbnew/exporters/export_hyperlynx.cpp +++ b/pcbnew/exporters/export_hyperlynx.cpp @@ -55,7 +55,7 @@ public: bool isThrough() const { - return m_type == PAD_ATTRIB_HOLE_NOT_PLATED || m_type == PAD_ATTRIB_STANDARD; + return m_type == PAD_ATTRIB_NPTH || m_type == PAD_ATTRIB_PTH; } bool operator==( const HYPERLYNX_PAD_STACK& other ) const @@ -237,7 +237,7 @@ HYPERLYNX_PAD_STACK::HYPERLYNX_PAD_STACK( BOARD* aBoard, const D_PAD* aPad ) m_layers = aPad->GetLayerSet(); m_drill = aPad->GetDrillSize().x; m_shape = aPad->GetShape(); - m_type = PAD_ATTRIB_STANDARD; + m_type = PAD_ATTRIB_PTH; m_id = 0; } @@ -251,7 +251,7 @@ HYPERLYNX_PAD_STACK::HYPERLYNX_PAD_STACK( BOARD* aBoard, const VIA* aVia ) m_layers = LSET::AllCuMask(); m_drill = aVia->GetDrillValue(); m_shape = PAD_SHAPE_CIRCLE; - m_type = PAD_ATTRIB_STANDARD; + m_type = PAD_ATTRIB_PTH; m_id = 0; } diff --git a/pcbnew/exporters/export_idf.cpp b/pcbnew/exporters/export_idf.cpp index 600a3df3d5..941c1be157 100644 --- a/pcbnew/exporters/export_idf.cpp +++ b/pcbnew/exporters/export_idf.cpp @@ -321,7 +321,7 @@ static void idf_export_module( BOARD* aPcb, MODULE* aModule, if( drill > 0.0 ) { // plating - if( pad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED ) + if( pad->GetAttribute() == PAD_ATTRIB_NPTH ) kplate = IDF3::NPTH; else kplate = IDF3::PTH; diff --git a/pcbnew/exporters/export_vrml.cpp b/pcbnew/exporters/export_vrml.cpp index 8f01c925d3..48e7ecbb4a 100644 --- a/pcbnew/exporters/export_vrml.cpp +++ b/pcbnew/exporters/export_vrml.cpp @@ -1259,7 +1259,7 @@ static void export_vrml_pad( MODEL_VRML& aModel, BOARD* aPcb, D_PAD* aPad ) { bool pth = false; - if( ( aPad->GetAttribute() != PAD_ATTRIB_HOLE_NOT_PLATED ) + if( ( aPad->GetAttribute() != PAD_ATTRIB_NPTH ) && !aModel.m_plainPCB ) pth = true; diff --git a/pcbnew/exporters/gendrill_file_writer_base.cpp b/pcbnew/exporters/gendrill_file_writer_base.cpp index e33ce6bef1..4ed3703555 100644 --- a/pcbnew/exporters/gendrill_file_writer_base.cpp +++ b/pcbnew/exporters/gendrill_file_writer_base.cpp @@ -126,10 +126,10 @@ void GENDRILL_WRITER_BASE::buildHolesList( DRILL_LAYER_PAIR aLayerPair, { if( !m_merge_PTH_NPTH ) { - if( !aGenerateNPTH_list && pad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED ) + if( !aGenerateNPTH_list && pad->GetAttribute() == PAD_ATTRIB_NPTH ) continue; - if( aGenerateNPTH_list && pad->GetAttribute() != PAD_ATTRIB_HOLE_NOT_PLATED ) + if( aGenerateNPTH_list && pad->GetAttribute() != PAD_ATTRIB_NPTH ) continue; } @@ -137,7 +137,7 @@ void GENDRILL_WRITER_BASE::buildHolesList( DRILL_LAYER_PAIR aLayerPair, continue; new_hole.m_ItemParent = pad; - new_hole.m_Hole_NotPlated = (pad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED); + new_hole.m_Hole_NotPlated = (pad->GetAttribute() == PAD_ATTRIB_NPTH); new_hole.m_Tool_Reference = -1; // Flag is: Not initialized new_hole.m_Hole_Orient = pad->GetOrientation(); new_hole.m_Hole_Shape = 0; // hole shape: round diff --git a/pcbnew/kicad_plugin.cpp b/pcbnew/kicad_plugin.cpp index a5c46100d2..a20b6cc991 100644 --- a/pcbnew/kicad_plugin.cpp +++ b/pcbnew/kicad_plugin.cpp @@ -1246,10 +1246,10 @@ void PCB_IO::format( D_PAD* aPad, int aNestLevel ) const switch( aPad->GetAttribute() ) { - case PAD_ATTRIB_STANDARD: type = "thru_hole"; break; - case PAD_ATTRIB_SMD: type = "smd"; break; - case PAD_ATTRIB_CONN: type = "connect"; break; - case PAD_ATTRIB_HOLE_NOT_PLATED: type = "np_thru_hole"; break; + case PAD_ATTRIB_PTH: type = "thru_hole"; break; + case PAD_ATTRIB_SMD: type = "smd"; break; + case PAD_ATTRIB_CONN: type = "connect"; break; + case PAD_ATTRIB_NPTH: type = "np_thru_hole"; break; default: THROW_IO_ERROR( wxString::Format( "unknown pad attribute: %d", aPad->GetAttribute() ) ); @@ -1314,7 +1314,7 @@ void PCB_IO::format( D_PAD* aPad, int aNestLevel ) const formatLayers( aPad->GetLayerSet() ); - if( aPad->GetAttribute() == PAD_ATTRIB_STANDARD ) + if( aPad->GetAttribute() == PAD_ATTRIB_PTH ) { if( aPad->GetRemoveUnconnected() ) { diff --git a/pcbnew/legacy_plugin.cpp b/pcbnew/legacy_plugin.cpp index 981ae19c00..e45a3a1845 100644 --- a/pcbnew/legacy_plugin.cpp +++ b/pcbnew/legacy_plugin.cpp @@ -1524,9 +1524,9 @@ void LEGACY_PLUGIN::loadPAD( MODULE* aModule ) else if( !strcmp( data, "CONN" ) ) attribute = PAD_ATTRIB_CONN; else if( !strcmp( data, "HOLE" ) ) - attribute = PAD_ATTRIB_HOLE_NOT_PLATED; + attribute = PAD_ATTRIB_NPTH; else - attribute = PAD_ATTRIB_STANDARD; + attribute = PAD_ATTRIB_PTH; strtok_r( NULL, delims, &saveptr ); // skip unused prm data = strtok_r( NULL, delims, &saveptr ); diff --git a/pcbnew/pad_naming.cpp b/pcbnew/pad_naming.cpp index 8be04d4197..3577cbc112 100644 --- a/pcbnew/pad_naming.cpp +++ b/pcbnew/pad_naming.cpp @@ -30,7 +30,7 @@ bool PAD_NAMING::PadCanHaveName( const D_PAD& aPad ) return false; // NPTH pads don't get numbers - if( aPad.GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED ) + if( aPad.GetAttribute() == PAD_ATTRIB_NPTH ) return false; return true; diff --git a/pcbnew/pcad2kicadpcb_plugin/pcb_pad.cpp b/pcbnew/pcad2kicadpcb_plugin/pcb_pad.cpp index b1752d0144..1b5faf80b7 100644 --- a/pcbnew/pcad2kicadpcb_plugin/pcb_pad.cpp +++ b/pcbnew/pcad2kicadpcb_plugin/pcb_pad.cpp @@ -199,7 +199,7 @@ void PCB_PAD::AddToModule( MODULE* aModule, int aRotation, bool aEncapsulatedPad { // mechanical hole pad->SetShape( PAD_SHAPE_CIRCLE ); - pad->SetAttribute( PAD_ATTRIB_HOLE_NOT_PLATED ); + pad->SetAttribute( PAD_ATTRIB_NPTH ); pad->SetDrillShape( PAD_DRILL_SHAPE_CIRCLE ); pad->SetDrillSize( wxSize( m_hole, m_hole ) ); @@ -218,7 +218,7 @@ void PCB_PAD::AddToModule( MODULE* aModule, int aRotation, bool aEncapsulatedPad } else { - ( m_hole ) ? padType = PAD_ATTRIB_STANDARD : padType = PAD_ATTRIB_SMD; + ( m_hole ) ? padType = PAD_ATTRIB_PTH : padType = PAD_ATTRIB_SMD; // form layer mask for( i = 0; i < (int) m_shapes.GetCount(); i++ ) @@ -250,7 +250,7 @@ void PCB_PAD::AddToModule( MODULE* aModule, int aRotation, bool aEncapsulatedPad return; } - if( padType == PAD_ATTRIB_STANDARD ) + if( padType == PAD_ATTRIB_PTH ) // actually this is a thru-hole pad pad->SetLayerSet( LSET::AllCuMask() | LSET( 2, B_Mask, F_Mask ) ); diff --git a/pcbnew/pcb_expr_evaluator.cpp b/pcbnew/pcb_expr_evaluator.cpp index 9eb6712e19..e636a60bb7 100644 --- a/pcbnew/pcb_expr_evaluator.cpp +++ b/pcbnew/pcb_expr_evaluator.cpp @@ -134,7 +134,7 @@ static void isPlated( LIBEVAL::CONTEXT* aCtx, void* self ) BOARD_ITEM* item = vref ? vref->GetObject( aCtx ) : nullptr; D_PAD* pad = dynamic_cast( item ); - if( pad && pad->GetAttribute() == PAD_ATTRIB_STANDARD ) + if( pad && pad->GetAttribute() == PAD_ATTRIB_PTH ) result->Set( 1.0 ); } diff --git a/pcbnew/pcb_parser.cpp b/pcbnew/pcb_parser.cpp index 578326dd4d..e7aa3293a8 100644 --- a/pcbnew/pcb_parser.cpp +++ b/pcbnew/pcb_parser.cpp @@ -3424,7 +3424,7 @@ D_PAD* PCB_PARSER::parseD_PAD( MODULE* aParent ) switch( token ) { case T_thru_hole: - pad->SetAttribute( PAD_ATTRIB_STANDARD ); + pad->SetAttribute( PAD_ATTRIB_PTH ); break; case T_smd: @@ -3444,7 +3444,7 @@ D_PAD* PCB_PARSER::parseD_PAD( MODULE* aParent ) break; case T_np_thru_hole: - pad->SetAttribute( PAD_ATTRIB_HOLE_NOT_PLATED ); + pad->SetAttribute( PAD_ATTRIB_NPTH ); break; default: diff --git a/pcbnew/plot_board_layers.cpp b/pcbnew/plot_board_layers.cpp index 7efc10c1db..070a455adf 100644 --- a/pcbnew/plot_board_layers.cpp +++ b/pcbnew/plot_board_layers.cpp @@ -300,7 +300,7 @@ void PlotStandardLayer( BOARD *aBoard, PLOTTER* aPlotter, LSET aLayerMask, if( aPlotOpt.GetSkipPlotNPTH_Pads() && ( aPlotOpt.GetDrillMarksType() == PCB_PLOT_PARAMS::NO_DRILL_SHAPE ) && ( pad->GetSize() == pad->GetDrillSize() ) && - ( pad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED ) ) + ( pad->GetAttribute() == PAD_ATTRIB_NPTH ) ) break; itemplotter.PlotPad( pad, color, padPlotMode ); diff --git a/pcbnew/plot_brditems_plotter.cpp b/pcbnew/plot_brditems_plotter.cpp index 04a8c98d6e..016638f157 100644 --- a/pcbnew/plot_brditems_plotter.cpp +++ b/pcbnew/plot_brditems_plotter.cpp @@ -47,7 +47,7 @@ #include #include // for GBR_NETLIST_METADATA #include // for LSET, IsCopperLayer -#include // for PAD_ATTRIB_HOLE_NOT_PLATED +#include // for PAD_ATTRIB_NPTH #include #include // for PCB_PLOT_PARAMS, PCB_PL... @@ -122,7 +122,7 @@ void BRDITEMS_PLOTTER::PlotPad( D_PAD* aPad, COLOR4D aColor, EDA_DRAW_MODE_T aPl // Some pads are mechanical pads ( through hole or smd ) // when this is the case, they have no pad name and/or are not plated. // In this case gerber files have slightly different attributes. - if( aPad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED || aPad->GetName().IsEmpty() ) + if( aPad->GetAttribute() == PAD_ATTRIB_NPTH || aPad->GetName().IsEmpty() ) gbr_metadata.m_NetlistMetadata.m_NotInNet = true; if( !plotOnExternalCopperLayer ) @@ -145,11 +145,11 @@ void BRDITEMS_PLOTTER::PlotPad( D_PAD* aPad, COLOR4D aColor, EDA_DRAW_MODE_T aPl // has its aperture attribute set to GBR_APERTURE_ATTRIB_CONDUCTOR switch( aPad->GetAttribute() ) { - case PAD_ATTRIB_HOLE_NOT_PLATED: // Mechanical pad through hole + case PAD_ATTRIB_NPTH: // Mechanical pad through hole gbr_metadata.SetApertureAttrib( GBR_APERTURE_METADATA::GBR_APERTURE_ATTRIB_WASHERPAD ); break; - case PAD_ATTRIB_STANDARD : // Pad through hole, a hole is also expected + case PAD_ATTRIB_PTH : // Pad through hole, a hole is also expected gbr_metadata.SetApertureAttrib( GBR_APERTURE_METADATA::GBR_APERTURE_ATTRIB_COMPONENTPAD ); break; @@ -200,7 +200,7 @@ void BRDITEMS_PLOTTER::PlotPad( D_PAD* aPad, COLOR4D aColor, EDA_DRAW_MODE_T aPl } // Ensure NPTH pads have *always* the GBR_APERTURE_ATTRIB_WASHERPAD attribute - if( aPad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED ) + if( aPad->GetAttribute() == PAD_ATTRIB_NPTH ) gbr_metadata.SetApertureAttrib( GBR_APERTURE_METADATA::GBR_APERTURE_ATTRIB_WASHERPAD ); } else diff --git a/pcbnew/plugins/altium/altium_pcb.cpp b/pcbnew/plugins/altium/altium_pcb.cpp index 34400152e4..cfab2aacc6 100644 --- a/pcbnew/plugins/altium/altium_pcb.cpp +++ b/pcbnew/plugins/altium/altium_pcb.cpp @@ -1739,8 +1739,8 @@ void ALTIUM_PCB::ParsePads6Data( "Pad '%s' of Footprint %s is not marked as multilayer, but it is an THT pad", elem.name, module->GetReference() ) ); } - pad->SetAttribute( elem.plated ? PAD_ATTR_T::PAD_ATTRIB_STANDARD : - PAD_ATTR_T::PAD_ATTRIB_HOLE_NOT_PLATED ); + pad->SetAttribute( elem.plated ? PAD_ATTR_T::PAD_ATTRIB_PTH : + PAD_ATTR_T::PAD_ATTRIB_NPTH ); if( !elem.sizeAndShape || elem.sizeAndShape->holeshape == ALTIUM_PAD_HOLE_SHAPE::ROUND ) { pad->SetDrillShape( PAD_DRILL_SHAPE_T::PAD_DRILL_SHAPE_CIRCLE ); @@ -1855,7 +1855,7 @@ void ALTIUM_PCB::ParsePads6Data( pad->SetLayerSet( FlipLayerMask( D_PAD::SMDMask() ) ); break; case ALTIUM_LAYER::MULTI_LAYER: - pad->SetLayerSet( elem.plated ? D_PAD::StandardMask() : D_PAD::UnplatedHoleMask() ); + pad->SetLayerSet( elem.plated ? D_PAD::PTHMask() : D_PAD::UnplatedHoleMask() ); break; default: PCB_LAYER_ID klayer = GetKicadLayer( elem.layer ); diff --git a/pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp b/pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp index ecdd32ee8a..586209b802 100644 --- a/pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp +++ b/pcbnew/plugins/cadstar/cadstar_pcb_archive_loader.cpp @@ -582,11 +582,11 @@ void CADSTAR_PCB_ARCHIVE_LOADER::loadLibraryPads( const SYMDEF_PCB& aComponent, case PAD_SIDE::THROUGH_HOLE: if( csPadcode.Plated ) - pad->SetAttribute( PAD_ATTR_T::PAD_ATTRIB_STANDARD ); + pad->SetAttribute( PAD_ATTR_T::PAD_ATTRIB_PTH ); else - pad->SetAttribute( PAD_ATTR_T::PAD_ATTRIB_HOLE_NOT_PLATED ); + pad->SetAttribute( PAD_ATTR_T::PAD_ATTRIB_NPTH ); - pad->SetLayerSet( pad->StandardMask() ); // for now we will assume no paste layers + pad->SetLayerSet( pad->PTHMask() ); // for now we will assume no paste layers //TODO: We need to read the csPad->Reassigns vector to make sure no paste break; diff --git a/pcbnew/router/pns_kicad_iface.cpp b/pcbnew/router/pns_kicad_iface.cpp index 6581d52a05..a6b1211de7 100644 --- a/pcbnew/router/pns_kicad_iface.cpp +++ b/pcbnew/router/pns_kicad_iface.cpp @@ -583,15 +583,15 @@ std::unique_ptr PNS_KICAD_IFACE_BASE::syncPad( D_PAD* aPad ) // ignore non-copper pads except for those with holes if( ( aPad->GetLayerSet() & LSET::AllCuMask()).none() && - aPad->GetAttribute() != PAD_ATTRIB_HOLE_NOT_PLATED ) + aPad->GetAttribute() != PAD_ATTRIB_NPTH ) return NULL; switch( aPad->GetAttribute() ) { - case PAD_ATTRIB_STANDARD: + case PAD_ATTRIB_PTH: break; - case PAD_ATTRIB_HOLE_NOT_PLATED: + case PAD_ATTRIB_NPTH: case PAD_ATTRIB_CONN: case PAD_ATTRIB_SMD: { @@ -604,7 +604,7 @@ std::unique_ptr PNS_KICAD_IFACE_BASE::syncPad( D_PAD* aPad ) { is_copper = true; - if( aPad->GetAttribute() != PAD_ATTRIB_HOLE_NOT_PLATED ) + if( aPad->GetAttribute() != PAD_ATTRIB_NPTH ) layers = LAYER_RANGE( i ); break; @@ -612,7 +612,7 @@ std::unique_ptr PNS_KICAD_IFACE_BASE::syncPad( D_PAD* aPad ) } /// Keep the NPTH pads because we will use the drill as alternate shape - if( !is_copper && aPad->GetAttribute() != PAD_ATTRIB_HOLE_NOT_PLATED ) + if( !is_copper && aPad->GetAttribute() != PAD_ATTRIB_NPTH ) return NULL; } break; @@ -624,11 +624,11 @@ std::unique_ptr PNS_KICAD_IFACE_BASE::syncPad( D_PAD* aPad ) std::unique_ptr< PNS::SOLID > solid( new PNS::SOLID ); - if( aPad->GetAttribute() == PAD_ATTRIB_STANDARD || - aPad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED ) + if( aPad->GetAttribute() == PAD_ATTRIB_PTH || + aPad->GetAttribute() == PAD_ATTRIB_NPTH ) solid->SetAlternateShape( aPad->GetEffectiveHoleShape()->Clone() ); - if( aPad->GetAttribute() == PAD_ATTRIB_HOLE_NOT_PLATED ) + if( aPad->GetAttribute() == PAD_ATTRIB_NPTH ) solid->SetRoutable( false ); solid->SetLayers( layers ); diff --git a/pcbnew/tools/pcb_inspection_tool.cpp b/pcbnew/tools/pcb_inspection_tool.cpp index 350d0f2faf..a1e343bb22 100644 --- a/pcbnew/tools/pcb_inspection_tool.cpp +++ b/pcbnew/tools/pcb_inspection_tool.cpp @@ -124,7 +124,7 @@ void PCB_INSPECTION_TOOL::reportZoneConnection( ZONE_CONTAINER* aZone, D_PAD* aP // Resolve complex connection types into simple types if( connection == ZONE_CONNECTION::THT_THERMAL ) { - if( aPad->GetAttribute() == PAD_ATTRIB_STANDARD ) + if( aPad->GetAttribute() == PAD_ATTRIB_PTH ) { connection = ZONE_CONNECTION::THERMAL; } diff --git a/pcbnew/tools/selection_tool.cpp b/pcbnew/tools/selection_tool.cpp index ec78915d10..c6dba7b83a 100644 --- a/pcbnew/tools/selection_tool.cpp +++ b/pcbnew/tools/selection_tool.cpp @@ -1918,8 +1918,8 @@ bool SELECTION_TOOL::Selectable( const BOARD_ITEM* aItem, bool checkVisibilityOn // Check render mode (from the Items tab) first switch( pad->GetAttribute() ) { - case PAD_ATTRIB_STANDARD: - case PAD_ATTRIB_HOLE_NOT_PLATED: + case PAD_ATTRIB_PTH: + case PAD_ATTRIB_NPTH: if( !board()->IsElementVisible( LAYER_PADS_TH ) ) return false; break; diff --git a/pcbnew/zone_filler.cpp b/pcbnew/zone_filler.cpp index 7231dc85b8..236607d20f 100644 --- a/pcbnew/zone_filler.cpp +++ b/pcbnew/zone_filler.cpp @@ -505,7 +505,7 @@ bool hasThermalConnection( D_PAD* pad, const ZONE_CONTAINER* aZone ) { // Rejects non-standard pads with tht-only thermal reliefs if( aZone->GetPadConnection( pad ) == ZONE_CONNECTION::THT_THERMAL - && pad->GetAttribute() != PAD_ATTRIB_STANDARD ) + && pad->GetAttribute() != PAD_ATTRIB_PTH ) { return false; } @@ -556,7 +556,7 @@ static void setupDummyPadForHole( const D_PAD* aPad, D_PAD& aDummyPad ) // plating thickness larger. int platingThickness = 0; - if( aPad->GetAttribute() == PAD_ATTRIB_STANDARD ) + if( aPad->GetAttribute() == PAD_ATTRIB_PTH ) platingThickness = aPad->GetBoard()->GetDesignSettings().GetHolePlatingThickness(); aDummyPad.SetOffset( wxPoint( 0, 0 ) ); diff --git a/qa/pcbnew/test_pad_naming.cpp b/qa/pcbnew/test_pad_naming.cpp index 511eaf06e2..eb1c907438 100644 --- a/qa/pcbnew/test_pad_naming.cpp +++ b/qa/pcbnew/test_pad_naming.cpp @@ -37,7 +37,7 @@ struct PAD_FIXTURE { D_PAD pad( &m_module ); - pad.SetAttribute( PAD_ATTRIB_HOLE_NOT_PLATED ); + pad.SetAttribute( PAD_ATTRIB_NPTH ); pad.SetLayerSet( D_PAD::UnplatedHoleMask() ); return pad; @@ -47,7 +47,7 @@ struct PAD_FIXTURE { D_PAD pad( &m_module ); - pad.SetAttribute( PAD_ATTRIB_STANDARD ); + pad.SetAttribute( PAD_ATTRIB_PTH ); pad.SetLayerSet( D_PAD::ApertureMask() ); return pad;