diff --git a/translation/pofiles/ar.po b/translation/pofiles/ar.po index 6b2f3550c7..2347419d05 100644 --- a/translation/pofiles/ar.po +++ b/translation/pofiles/ar.po @@ -2,7 +2,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2023-02-10 14:35-0800\n" +"POT-Creation-Date: 2023-02-10 15:35-0800\n" "PO-Revision-Date: 2018-07-15 17:07+0200\n" "Language: ar\n" "MIME-Version: 1.0\n" @@ -14565,7 +14565,7 @@ msgid "Invalid Ramp" msgstr "" #: eeschema/sim/kibis/ibis_parser.cpp:613 -msgid "Checking Header... " +msgid "Checking Header..." msgstr "" #: eeschema/sim/kibis/ibis_parser.cpp:620 @@ -30088,12 +30088,7 @@ msgid "" " (rule high-current\n" " (constraint track_width (min 1.0mm))\n" " (constraint connection_width (min 0.8mm))\n" -" (condition \"A.NetClass == 'Power'\"))\n" -"\n" -"### Documentation\n" -"\n" -"For the full documentation see [https://docs.kicad.org](https://docs.kicad." -"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)." +" (condition \"A.NetClass == 'Power'\"))" msgstr "" #: pcbnew/dialogs/panel_setup_text_and_graphics_base.cpp:75 diff --git a/translation/pofiles/bg.po b/translation/pofiles/bg.po index d5b835294d..30f658a879 100644 --- a/translation/pofiles/bg.po +++ b/translation/pofiles/bg.po @@ -3,7 +3,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2023-02-10 14:35-0800\n" +"POT-Creation-Date: 2023-02-10 15:35-0800\n" "PO-Revision-Date: 2023-02-06 21:07+0000\n" "Last-Translator: Michał Radziejewicz \n" "Language-Team: Bulgarian \n" "Language-Team: Catalan \n" "Language-Team: Czech \n" "Language-Team: Danish \n" "Language-Team: German \n" "Language-Team: Greek \n" "Language-Team: Simon Richter \n" @@ -10419,8 +10419,8 @@ msgstr "Invalid GND clamp." msgid "Invalid Ramp" msgstr "Invalid Ramp" -msgid "Checking Header... " -msgstr "Checking Header... " +msgid "Checking Header..." +msgstr "Checking Header..." msgid "Missing [IBIS Ver]" msgstr "Missing [IBIS Ver]" @@ -22315,12 +22315,7 @@ msgid "" " (rule high-current\n" " (constraint track_width (min 1.0mm))\n" " (constraint connection_width (min 0.8mm))\n" -" (condition \"A.NetClass == 'Power'\"))\n" -"\n" -"### Documentation\n" -"\n" -"For the full documentation see [https://docs.kicad.org](https://docs.kicad." -"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)." +" (condition \"A.NetClass == 'Power'\"))" msgstr "" "### Top-level Clauses\n" "\n" @@ -22642,12 +22637,7 @@ msgstr "" " (rule high-current\n" " (constraint track_width (min 1.0mm))\n" " (constraint connection_width (min 0.8mm))\n" -" (condition \"A.NetClass == 'Power'\"))\n" -"\n" -"### Documentation\n" -"\n" -"For the full documentation see [https://docs.kicad.org](https://docs.kicad." -"org/GetMajorMinorVersion/pcbnew/#custom_design_rules)." +" (condition \"A.NetClass == 'Power'\"))" msgid "Default properties for new dimension objects:" msgstr "Default properties for new dimension objects:" @@ -29428,665 +29418,9 @@ msgstr "KiCad Schematic" msgid "KiCad Printed Circuit Board" msgstr "KiCad Printed Circuit Board" -#~ msgid "Checking Header..." -#~ msgstr "Checking Header..." - #~ msgid "Reading file " #~ msgstr "Reading file " -#~ msgid "" -#~ "### Top-level Clauses\n" -#~ "\n" -#~ " (version )\n" -#~ "\n" -#~ " (rule ...)\n" -#~ "\n" -#~ "\n" -#~ "
\n" -#~ "\n" -#~ "### Rule Clauses\n" -#~ "\n" -#~ " (constraint ...)\n" -#~ "\n" -#~ " (condition \"\")\n" -#~ "\n" -#~ " (layer \"\")\n" -#~ "\n" -#~ " (severity )\n" -#~ "\n" -#~ "\n" -#~ "
\n" -#~ "\n" -#~ "### Constraint Types\n" -#~ "\n" -#~ " * annular\\_width\n" -#~ " * assertion\n" -#~ " * clearance\n" -#~ " * connection\\_width\n" -#~ " * courtyard_clearance\n" -#~ " * diff\\_pair\\_gap\n" -#~ " * diff\\_pair\\_uncoupled\n" -#~ " * disallow\n" -#~ " * edge\\_clearance\n" -#~ " * length\n" -#~ " * hole\\_clearance\n" -#~ " * hole\\_size\n" -#~ " * min\\_resolved\\_spokes\n" -#~ " * physical\\_clearance\n" -#~ " * physical\\_hole\\_clearance\n" -#~ " * silk\\_clearance\n" -#~ " * skew\n" -#~ " * text\\_height\n" -#~ " * text\\_thickness\n" -#~ " * thermal\\_relief\\_gap\n" -#~ " * thermal\\_spoke\\_width\n" -#~ " * track\\_width\n" -#~ " * via\\_count\n" -#~ " * via\\_diameter\n" -#~ " * zone\\_connection\n" -#~ "\n" -#~ "Note: `clearance` and `hole_clearance` rules are not run against items of " -#~ "the same net; `physical_clearance` and `physical_hole_clearance` rules " -#~ "are.\n" -#~ "

\n" -#~ "\n" -#~ "### Items\n" -#~ "\n" -#~ " * `A`    _the first (or only) item under test_\n" -#~ " * `B`    _the second item under test (for binary tests)_\n" -#~ " * `L`    _the layer currently under test_\n" -#~ "\n" -#~ "
\n" -#~ "\n" -#~ "### Item Types\n" -#~ "\n" -#~ " * buried\\_via\n" -#~ " * graphic\n" -#~ " * hole\n" -#~ " * micro\\_via\n" -#~ " * pad\n" -#~ " * text\n" -#~ " * track\n" -#~ " * via\n" -#~ " * zone\n" -#~ "\n" -#~ "
\n" -#~ "\n" -#~ "### Zone Connections\n" -#~ "\n" -#~ " * solid\n" -#~ " * thermal\\_reliefs\n" -#~ " * none\n" -#~ "\n" -#~ "
\n" -#~ "\n" -#~ "### Severity Names\n" -#~ "\n" -#~ " * warning\n" -#~ " * error\n" -#~ " * exclusion\n" -#~ " * ignore\n" -#~ "\n" -#~ "
\n" -#~ "\n" -#~ "### Examples\n" -#~ "\n" -#~ " (version 1)\n" -#~ "\n" -#~ " (rule HV\n" -#~ " (constraint clearance (min 1.5mm))\n" -#~ " (condition \"A.NetClass == 'HV'\"))\n" -#~ "\n" -#~ "\n" -#~ " (rule HV\n" -#~ " (layer outer)\n" -#~ " (constraint clearance (min 1.5mm))\n" -#~ " (condition \"A.NetClass == 'HV'\"))\n" -#~ "\n" -#~ "\n" -#~ " (rule HV_HV\n" -#~ " # wider clearance between HV tracks\n" -#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -#~ "\n" -#~ "\n" -#~ " (rule HV_unshielded\n" -#~ " (constraint clearance (min 2mm))\n" -#~ " (condition \"A.NetClass == 'HV' && !A." -#~ "enclosedByArea('Shield*')\"))\n" -#~ "\n" -#~ "\n" -#~ " (rule heavy_thermals\n" -#~ " (constraint thermal_spoke_width (min 0.5mm))\n" -#~ " (condition \"A.NetClass == 'HV'\"))\n" -#~ "

\n" -#~ "\n" -#~ "### Notes\n" -#~ "\n" -#~ "Version clause must be the first clause. It indicates the syntax version " -#~ "of the file so that \n" -#~ "future rules parsers can perform automatic updates. It should be\n" -#~ "set to \"1\".\n" -#~ "\n" -#~ "Rules should be ordered by specificity. Later rules take\n" -#~ "precedence over earlier rules; once a matching rule is found\n" -#~ "no further rules will be checked.\n" -#~ "\n" -#~ "Use Ctrl+/ to comment or uncomment line(s).\n" -#~ "


\n" -#~ "\n" -#~ "### Expression functions\n" -#~ "\n" -#~ "All function parameters support simple wildcards (`*` and `?`).\n" -#~ "

\n" -#~ "\n" -#~ " A.intersectsCourtyard('')\n" -#~ "True if any part of `A` lies within the given footprint's principal " -#~ "courtyard.\n" -#~ "

\n" -#~ "\n" -#~ " A.intersectsFrontCourtyard('')\n" -#~ "True if any part of `A` lies within the given footprint's front " -#~ "courtyard.\n" -#~ "

\n" -#~ "\n" -#~ " A.intersectsBackCourtyard('')\n" -#~ "True if any part of `A` lies within the given footprint's back " -#~ "courtyard.\n" -#~ "

\n" -#~ "\n" -#~ " A.intersectsArea('')\n" -#~ "True if any part of `A` lies within the given zone's outline.\n" -#~ "

\n" -#~ "\n" -#~ " A.enclosedByArea('')\n" -#~ "True if all of `A` lies within the given zone's outline. \n" -#~ "\n" -#~ "NB: this is potentially a more expensive call than `intersectsArea()`. " -#~ "Use `intersectsArea()` \n" -#~ "where possible.\n" -#~ "

\n" -#~ "\n" -#~ " A.isPlated()\n" -#~ "True if `A` has a hole which is plated.\n" -#~ "

\n" -#~ "\n" -#~ " A.inDiffPair('')\n" -#~ "True if `A` has a net that is part of the specified differential pair.\n" -#~ "`` is the base name of the differential pair. For example, " -#~ "`inDiffPair('/CLK')`\n" -#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" -#~ "

\n" -#~ "\n" -#~ " AB.isCoupledDiffPair()\n" -#~ "True if `A` and `B` are members of the same diff pair.\n" -#~ "

\n" -#~ "\n" -#~ " A.memberOf('')\n" -#~ "True if `A` is a member of the given group. Includes nested membership.\n" -#~ "

\n" -#~ "\n" -#~ " A.existsOnLayer('')\n" -#~ "True if `A` exists on the given layer. The layer name can be\n" -#~ "either the name assigned in Board Setup > Board Editor Layers or\n" -#~ "the canonical name (ie: `F.Cu`).\n" -#~ "\n" -#~ "NB: this returns true if `A` is on the given layer, independently\n" -#~ "of whether or not the rule is being evaluated for that layer.\n" -#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -#~ "

\n" -#~ "\n" -#~ " !!! A.insideCourtyard('') !!!\n" -#~ "Deprecated; use `intersectsCourtyard()` instead.\n" -#~ "

\n" -#~ "\n" -#~ " !!! A.insideFrontCourtyard('') !!!\n" -#~ "Deprecated; use `intersectsFrontCourtyard()` instead.\n" -#~ "

\n" -#~ "\n" -#~ " !!! A.insideBackCourtyard('') !!!\n" -#~ "Deprecated; use `intersectsBackCourtyard()` instead.\n" -#~ "

\n" -#~ "\n" -#~ " !!! A.insideArea('') !!!\n" -#~ "Deprecated; use `intersectsArea()` instead.\n" -#~ "


\n" -#~ "\n" -#~ "### More Examples\n" -#~ "\n" -#~ " (rule \"copper keepout\"\n" -#~ " (constraint disallow track via zone)\n" -#~ " (condition \"A.intersectsArea('zone3')\"))\n" -#~ "\n" -#~ "\n" -#~ " (rule \"BGA neckdown\"\n" -#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -#~ " (condition \"A.intersectsCourtyard('U3')\"))\n" -#~ "\n" -#~ "\n" -#~ " # prevent silk over tented vias\n" -#~ " (rule silk_over_via\n" -#~ " (constraint silk_clearance (min 0.2mm))\n" -#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -#~ "\n" -#~ "\n" -#~ " (rule \"Distance between Vias of Different Nets\"\n" -#~ " (constraint hole_to_hole (min 0.254mm))\n" -#~ " (condition \"A.Type == 'Via' && B.Type == 'Via' && A.Net != B." -#~ "Net\"))\n" -#~ "\n" -#~ " (rule \"Clearance between Pads of Different Nets\"\n" -#~ " (constraint clearance (min 3.0mm))\n" -#~ " (condition \"A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B." -#~ "Net\"))\n" -#~ "\n" -#~ "\n" -#~ " (rule \"Via Hole to Track Clearance\"\n" -#~ " (constraint hole_clearance (min 0.254mm))\n" -#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -#~ "\n" -#~ " (rule \"Pad to Track Clearance\"\n" -#~ " (constraint clearance (min 0.2mm))\n" -#~ " (condition \"A.Type == 'Pad' && B.Type == 'Track'\"))\n" -#~ "\n" -#~ "\n" -#~ " (rule \"clearance-to-1mm-cutout\"\n" -#~ " (constraint clearance (min 0.8mm))\n" -#~ " (condition \"A.Layer == 'Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -#~ "\n" -#~ "\n" -#~ " (rule \"Max Drill Hole Size Mechanical\"\n" -#~ " (constraint hole_size (max 6.3mm))\n" -#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -#~ "\n" -#~ " (rule \"Max Drill Hole Size PTH\"\n" -#~ " (constraint hole_size (max 6.35mm))\n" -#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" -#~ "\n" -#~ "\n" -#~ " # Specify an optimal gap for a particular diff-pair\n" -#~ " (rule \"dp clock gap\"\n" -#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" -#~ " (condition \"A.inDiffPair('/CLK')\"))\n" -#~ "\n" -#~ " # Specify a larger clearance around any diff-pair\n" -#~ " (rule \"dp clearance\"\n" -#~ " (constraint clearance (min \"1.5mm\"))\n" -#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -#~ "\n" -#~ "\n" -#~ " # Don't use thermal reliefs on heatsink pads\n" -#~ " (rule heat_sink_pad\n" -#~ " (constraint zone_connection solid)\n" -#~ " (condition \"A.Fabrication_Property == 'Heatsink pad'\"))\n" -#~ "\n" -#~ " # Require all four thermal relief spokes to connect to parent zone\n" -#~ " (rule fully_spoked_pads\n" -#~ " (constraint min_resolved_spokes 4))\n" -#~ "\n" -#~ " # Set thermal relief gap & spoke width for all zones\n" -#~ " (rule defined_relief\n" -#~ " (constraint thermal_relief_gap (min 10mil))\n" -#~ " (constraint thermal_spoke_width (min 12mil)))\n" -#~ "\n" -#~ " # Override thermal relief gap & spoke width for GND and PWR zones\n" -#~ " (rule defined_relief_pwr\n" -#~ " (constraint thermal_relief_gap (min 10mil))\n" -#~ " (constraint thermal_spoke_width (min 12mil))\n" -#~ " (condition \"A.Name == 'zone_GND' || A.Name == 'zone_PWR'\"))\n" -#~ "\n" -#~ "\n" -#~ " # Prevent solder wicking from SMD pads\n" -#~ " (rule holes_in_pads\n" -#~ " (constraint physical_hole_clearance (min 0.2mm))\n" -#~ " (condition \"B.Pad_Type == 'SMD'\"))\n" -#~ "\n" -#~ " # Disallow solder mask margin overrides\n" -#~ " (rule \"disallow solder mask margin overrides\"\n" -#~ " (constraint assertion \"A.Soldermask_Margin_Override == 0mm\")\n" -#~ " (condition \"A.Type == 'Pad'\"))\n" -#~ "\n" -#~ "\n" -#~ " # Enforce a mechanical clearance between components and board edge\n" -#~ " (rule front_mechanical_board_edge_clearance\n" -#~ " (layer \"F.Courtyard\")\n" -#~ " (constraint physical_clearance (min 3mm))\n" -#~ " (condition \"B.Layer == 'Edge.Cuts'\"))\n" -#~ "\n" -#~ "\n" -#~ " # Check current-carrying capacity\n" -#~ " (rule high-current\n" -#~ " (constraint track_width (min 1.0mm))\n" -#~ " (constraint connection_width (min 0.8mm))\n" -#~ " (condition \"A.NetClass == 'Power'\"))" -#~ msgstr "" -#~ "### Top-level Clauses\n" -#~ "\n" -#~ " (version )\n" -#~ "\n" -#~ " (rule ...)\n" -#~ "\n" -#~ "\n" -#~ "
\n" -#~ "\n" -#~ "### Rule Clauses\n" -#~ "\n" -#~ " (constraint ...)\n" -#~ "\n" -#~ " (condition \"\")\n" -#~ "\n" -#~ " (layer \"\")\n" -#~ "\n" -#~ " (severity )\n" -#~ "\n" -#~ "\n" -#~ "
\n" -#~ "\n" -#~ "### Constraint Types\n" -#~ "\n" -#~ " * annular\\_width\n" -#~ " * assertion\n" -#~ " * clearance\n" -#~ " * connection\\_width\n" -#~ " * courtyard_clearance\n" -#~ " * diff\\_pair\\_gap\n" -#~ " * diff\\_pair\\_uncoupled\n" -#~ " * disallow\n" -#~ " * edge\\_clearance\n" -#~ " * length\n" -#~ " * hole\\_clearance\n" -#~ " * hole\\_size\n" -#~ " * min\\_resolved\\_spokes\n" -#~ " * physical\\_clearance\n" -#~ " * physical\\_hole\\_clearance\n" -#~ " * silk\\_clearance\n" -#~ " * skew\n" -#~ " * text\\_height\n" -#~ " * text\\_thickness\n" -#~ " * thermal\\_relief\\_gap\n" -#~ " * thermal\\_spoke\\_width\n" -#~ " * track\\_width\n" -#~ " * via\\_count\n" -#~ " * via\\_diameter\n" -#~ " * zone\\_connection\n" -#~ "\n" -#~ "Note: `clearance` and `hole_clearance` rules are not run against items of " -#~ "the same net; `physical_clearance` and `physical_hole_clearance` rules " -#~ "are.\n" -#~ "

\n" -#~ "\n" -#~ "### Items\n" -#~ "\n" -#~ " * `A`    _the first (or only) item under test_\n" -#~ " * `B`    _the second item under test (for binary tests)_\n" -#~ " * `L`    _the layer currently under test_\n" -#~ "\n" -#~ "
\n" -#~ "\n" -#~ "### Item Types\n" -#~ "\n" -#~ " * buried\\_via\n" -#~ " * graphic\n" -#~ " * hole\n" -#~ " * micro\\_via\n" -#~ " * pad\n" -#~ " * text\n" -#~ " * track\n" -#~ " * via\n" -#~ " * zone\n" -#~ "\n" -#~ "
\n" -#~ "\n" -#~ "### Zone Connections\n" -#~ "\n" -#~ " * solid\n" -#~ " * thermal\\_reliefs\n" -#~ " * none\n" -#~ "\n" -#~ "
\n" -#~ "\n" -#~ "### Severity Names\n" -#~ "\n" -#~ " * warning\n" -#~ " * error\n" -#~ " * exclusion\n" -#~ " * ignore\n" -#~ "\n" -#~ "
\n" -#~ "\n" -#~ "### Examples\n" -#~ "\n" -#~ " (version 1)\n" -#~ "\n" -#~ " (rule HV\n" -#~ " (constraint clearance (min 1.5mm))\n" -#~ " (condition \"A.NetClass == 'HV'\"))\n" -#~ "\n" -#~ "\n" -#~ " (rule HV\n" -#~ " (layer outer)\n" -#~ " (constraint clearance (min 1.5mm))\n" -#~ " (condition \"A.NetClass == 'HV'\"))\n" -#~ "\n" -#~ "\n" -#~ " (rule HV_HV\n" -#~ " # wider clearance between HV tracks\n" -#~ " (constraint clearance (min \"1.5mm + 2.0mm\"))\n" -#~ " (condition \"A.NetClass == 'HV' && B.NetClass == 'HV'\"))\n" -#~ "\n" -#~ "\n" -#~ " (rule HV_unshielded\n" -#~ " (constraint clearance (min 2mm))\n" -#~ " (condition \"A.NetClass == 'HV' && !A." -#~ "enclosedByArea('Shield*')\"))\n" -#~ "\n" -#~ "\n" -#~ " (rule heavy_thermals\n" -#~ " (constraint thermal_spoke_width (min 0.5mm))\n" -#~ " (condition \"A.NetClass == 'HV'\"))\n" -#~ "

\n" -#~ "\n" -#~ "### Notes\n" -#~ "\n" -#~ "Version clause must be the first clause. It indicates the syntax version " -#~ "of the file so that \n" -#~ "future rules parsers can perform automatic updates. It should be\n" -#~ "set to \"1\".\n" -#~ "\n" -#~ "Rules should be ordered by specificity. Later rules take\n" -#~ "precedence over earlier rules; once a matching rule is found\n" -#~ "no further rules will be checked.\n" -#~ "\n" -#~ "Use Ctrl+/ to comment or uncomment line(s).\n" -#~ "


\n" -#~ "\n" -#~ "### Expression functions\n" -#~ "\n" -#~ "All function parameters support simple wildcards (`*` and `?`).\n" -#~ "

\n" -#~ "\n" -#~ " A.intersectsCourtyard('')\n" -#~ "True if any part of `A` lies within the given footprint's principal " -#~ "courtyard.\n" -#~ "

\n" -#~ "\n" -#~ " A.intersectsFrontCourtyard('')\n" -#~ "True if any part of `A` lies within the given footprint's front " -#~ "courtyard.\n" -#~ "

\n" -#~ "\n" -#~ " A.intersectsBackCourtyard('')\n" -#~ "True if any part of `A` lies within the given footprint's back " -#~ "courtyard.\n" -#~ "

\n" -#~ "\n" -#~ " A.intersectsArea('')\n" -#~ "True if any part of `A` lies within the given zone's outline.\n" -#~ "

\n" -#~ "\n" -#~ " A.enclosedByArea('')\n" -#~ "True if all of `A` lies within the given zone's outline. \n" -#~ "\n" -#~ "NB: this is potentially a more expensive call than `intersectsArea()`. " -#~ "Use `intersectsArea()` \n" -#~ "where possible.\n" -#~ "

\n" -#~ "\n" -#~ " A.isPlated()\n" -#~ "True if `A` has a hole which is plated.\n" -#~ "

\n" -#~ "\n" -#~ " A.inDiffPair('')\n" -#~ "True if `A` has a net that is part of the specified differential pair.\n" -#~ "`` is the base name of the differential pair. For example, " -#~ "`inDiffPair('/CLK')`\n" -#~ "matches items in the `/CLK_P` and `/CLK_N` nets.\n" -#~ "

\n" -#~ "\n" -#~ " AB.isCoupledDiffPair()\n" -#~ "True if `A` and `B` are members of the same diff pair.\n" -#~ "

\n" -#~ "\n" -#~ " A.memberOf('')\n" -#~ "True if `A` is a member of the given group. Includes nested membership.\n" -#~ "

\n" -#~ "\n" -#~ " A.existsOnLayer('')\n" -#~ "True if `A` exists on the given layer. The layer name can be\n" -#~ "either the name assigned in Board Setup > Board Editor Layers or\n" -#~ "the canonical name (ie: `F.Cu`).\n" -#~ "\n" -#~ "NB: this returns true if `A` is on the given layer, independently\n" -#~ "of whether or not the rule is being evaluated for that layer.\n" -#~ "For the latter use a `(layer \"layer_name\")` clause in the rule.\n" -#~ "

\n" -#~ "\n" -#~ " !!! A.insideCourtyard('') !!!\n" -#~ "Deprecated; use `intersectsCourtyard()` instead.\n" -#~ "

\n" -#~ "\n" -#~ " !!! A.insideFrontCourtyard('') !!!\n" -#~ "Deprecated; use `intersectsFrontCourtyard()` instead.\n" -#~ "

\n" -#~ "\n" -#~ " !!! A.insideBackCourtyard('') !!!\n" -#~ "Deprecated; use `intersectsBackCourtyard()` instead.\n" -#~ "

\n" -#~ "\n" -#~ " !!! A.insideArea('') !!!\n" -#~ "Deprecated; use `intersectsArea()` instead.\n" -#~ "


\n" -#~ "\n" -#~ "### More Examples\n" -#~ "\n" -#~ " (rule \"copper keepout\"\n" -#~ " (constraint disallow track via zone)\n" -#~ " (condition \"A.intersectsArea('zone3')\"))\n" -#~ "\n" -#~ "\n" -#~ " (rule \"BGA neckdown\"\n" -#~ " (constraint track_width (min 0.2mm) (opt 0.25mm))\n" -#~ " (constraint clearance (min 0.05mm) (opt 0.08mm))\n" -#~ " (condition \"A.intersectsCourtyard('U3')\"))\n" -#~ "\n" -#~ "\n" -#~ " # prevent silk over tented vias\n" -#~ " (rule silk_over_via\n" -#~ " (constraint silk_clearance (min 0.2mm))\n" -#~ " (condition \"A.Type == '*Text' && B.Type == 'Via'\"))\n" -#~ "\n" -#~ "\n" -#~ " (rule \"Distance between Vias of Different Nets\"\n" -#~ " (constraint hole_to_hole (min 0.254mm))\n" -#~ " (condition \"A.Type == 'Via' && B.Type == 'Via' && A.Net != B." -#~ "Net\"))\n" -#~ "\n" -#~ " (rule \"Clearance between Pads of Different Nets\"\n" -#~ " (constraint clearance (min 3.0mm))\n" -#~ " (condition \"A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B." -#~ "Net\"))\n" -#~ "\n" -#~ "\n" -#~ " (rule \"Via Hole to Track Clearance\"\n" -#~ " (constraint hole_clearance (min 0.254mm))\n" -#~ " (condition \"A.Type == 'Via' && B.Type == 'Track'\"))\n" -#~ "\n" -#~ " (rule \"Pad to Track Clearance\"\n" -#~ " (constraint clearance (min 0.2mm))\n" -#~ " (condition \"A.Type == 'Pad' && B.Type == 'Track'\"))\n" -#~ "\n" -#~ "\n" -#~ " (rule \"clearance-to-1mm-cutout\"\n" -#~ " (constraint clearance (min 0.8mm))\n" -#~ " (condition \"A.Layer == 'Edge.Cuts' && A.Thickness == 1.0mm\"))\n" -#~ "\n" -#~ "\n" -#~ " (rule \"Max Drill Hole Size Mechanical\"\n" -#~ " (constraint hole_size (max 6.3mm))\n" -#~ " (condition \"A.Pad_Type == 'NPTH, mechanical'\"))\n" -#~ "\n" -#~ " (rule \"Max Drill Hole Size PTH\"\n" -#~ " (constraint hole_size (max 6.35mm))\n" -#~ " (condition \"A.Pad_Type == 'Through-hole'\"))\n" -#~ "\n" -#~ "\n" -#~ " # Specify an optimal gap for a particular diff-pair\n" -#~ " (rule \"dp clock gap\"\n" -#~ " (constraint diff_pair_gap (opt \"0.8mm\"))\n" -#~ " (condition \"A.inDiffPair('/CLK')\"))\n" -#~ "\n" -#~ " # Specify a larger clearance around any diff-pair\n" -#~ " (rule \"dp clearance\"\n" -#~ " (constraint clearance (min \"1.5mm\"))\n" -#~ " (condition \"A.inDiffPair('*') && !AB.isCoupledDiffPair()\"))\n" -#~ "\n" -#~ "\n" -#~ " # Don't use thermal reliefs on heatsink pads\n" -#~ " (rule heat_sink_pad\n" -#~ " (constraint zone_connection solid)\n" -#~ " (condition \"A.Fabrication_Property == 'Heatsink pad'\"))\n" -#~ "\n" -#~ " # Require all four thermal relief spokes to connect to parent zone\n" -#~ " (rule fully_spoked_pads\n" -#~ " (constraint min_resolved_spokes 4))\n" -#~ "\n" -#~ " # Set thermal relief gap & spoke width for all zones\n" -#~ " (rule defined_relief\n" -#~ " (constraint thermal_relief_gap (min 10mil))\n" -#~ " (constraint thermal_spoke_width (min 12mil)))\n" -#~ "\n" -#~ " # Override thermal relief gap & spoke width for GND and PWR zones\n" -#~ " (rule defined_relief_pwr\n" -#~ " (constraint thermal_relief_gap (min 10mil))\n" -#~ " (constraint thermal_spoke_width (min 12mil))\n" -#~ " (condition \"A.Name == 'zone_GND' || A.Name == 'zone_PWR'\"))\n" -#~ "\n" -#~ "\n" -#~ " # Prevent solder wicking from SMD pads\n" -#~ " (rule holes_in_pads\n" -#~ " (constraint physical_hole_clearance (min 0.2mm))\n" -#~ " (condition \"B.Pad_Type == 'SMD'\"))\n" -#~ "\n" -#~ " # Disallow solder mask margin overrides\n" -#~ " (rule \"disallow solder mask margin overrides\"\n" -#~ " (constraint assertion \"A.Soldermask_Margin_Override == 0mm\")\n" -#~ " (condition \"A.Type == 'Pad'\"))\n" -#~ "\n" -#~ "\n" -#~ " # Enforce a mechanical clearance between components and board edge\n" -#~ " (rule front_mechanical_board_edge_clearance\n" -#~ " (layer \"F.Courtyard\")\n" -#~ " (constraint physical_clearance (min 3mm))\n" -#~ " (condition \"B.Layer == 'Edge.Cuts'\"))\n" -#~ "\n" -#~ "\n" -#~ " # Check current-carrying capacity\n" -#~ " (rule high-current\n" -#~ " (constraint track_width (min 1.0mm))\n" -#~ " (constraint connection_width (min 0.8mm))\n" -#~ " (condition \"A.NetClass == 'Power'\"))" - #~ msgid "Filter other symbol fields by name:" #~ msgstr "Filter other symbol fields by name:" diff --git a/translation/pofiles/es.po b/translation/pofiles/es.po index c92a16e5b5..a222fb7f76 100644 --- a/translation/pofiles/es.po +++ b/translation/pofiles/es.po @@ -14,7 +14,7 @@ msgid "" msgstr "" "Project-Id-Version: KiCad Spanish Translation\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2023-02-10 14:35-0800\n" +"POT-Creation-Date: 2023-02-10 15:35-0800\n" "PO-Revision-Date: 2022-12-03 01:48+0000\n" "Last-Translator: VicSanRoPe \n" "Language-Team: Spanish \n" "Language-Team: Spanish (Mexico) \n" "Language-Team: Estonian \n" "Language-Team: Finnish \n" "Language-Team: Hungarian \n" "Language-Team: Indonesian \n" "Language-Team: Italian \n" "Language-Team: Japanese \n" "Language-Team: Korean \n" "Language-Team: Lithuanian \n" "Language-Team: Latvian \n" "Language-Team: Dutch \n" "Language-Team: Norwegian Bokmål \n" "Language-Team: Polish \n" "Language-Team: Portuguese \n" "Language-Team: Portuguese (Brazil) \n" "Language-Team: Romanian \n" "Language-Team: Russian \n" "Language-Team: Slovak \n" "Language-Team: Slovenian \n" "Language-Team: Serbian \n" "Language-Team: Swedish \n" "Language-Team: Thai \n" "Language-Team: Turkish \n" "Language-Team: Ukrainian \n" "Language-Team: Vietnamese \n" "Language-Team: Chinese (Simplified) \n" "Language-Team: Chinese (Traditional)