diff --git a/pcbnew/router/pns_diff_pair_placer.cpp b/pcbnew/router/pns_diff_pair_placer.cpp
index d17b2bf38d..7afd386270 100644
--- a/pcbnew/router/pns_diff_pair_placer.cpp
+++ b/pcbnew/router/pns_diff_pair_placer.cpp
@@ -535,7 +535,7 @@ bool DIFF_PAIR_PLACER::FindDpPrimitivePair( NODE* aWorld, const VECTOR2I& aP, IT
 int DIFF_PAIR_PLACER::viaGap() const
 {
     return std::max( m_sizes.DiffPairViaGap(),
-                     m_sizes.GetHoleToHole() + m_viaDrill - m_viaDiameter );
+                     m_sizes.GetHoleToHole() + m_sizes.ViaDrill() - m_sizes.ViaDiameter() );
 }
 
 
diff --git a/pcbnew/router/pns_kicad_iface.cpp b/pcbnew/router/pns_kicad_iface.cpp
index 3c7cdfdec7..d3fb9be864 100644
--- a/pcbnew/router/pns_kicad_iface.cpp
+++ b/pcbnew/router/pns_kicad_iface.cpp
@@ -485,7 +485,16 @@ bool PNS_KICAD_IFACE_BASE::ImportSizes( PNS::SIZES_SETTINGS& aSizes, PNS::ITEM*
     aSizes.SetDiffPairGap( diffPairGap );
     aSizes.SetDiffPairViaGap( diffPairViaGap );
 
-    aSizes.SetHoleToHole( bds.m_HoleToHoleMin );
+    int      holeToHoleMin = bds.m_HoleToHoleMin;
+    PNS::VIA dummyVia;
+
+    if( m_ruleResolver->QueryConstraint( PNS::CONSTRAINT_TYPE::CT_HOLE_TO_HOLE, &dummyVia,
+                                         &dummyVia, UNDEFINED_LAYER, &constraint ) )
+    {
+        holeToHoleMin = constraint.m_Value.Min();
+    }
+
+    aSizes.SetHoleToHole( holeToHoleMin );
 
     aSizes.ClearLayerPairs();